1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \ 3; RUN: -verify-machineinstrs -target-abi ilp32f | \ 4; RUN: FileCheck -check-prefix=RV32IZFH %s 5; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \ 6; RUN: -verify-machineinstrs -target-abi lp64f | \ 7; RUN: FileCheck -check-prefix=RV64IZFH %s 8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=zhinx \ 9; RUN: -verify-machineinstrs -target-abi ilp32 | \ 10; RUN: FileCheck -check-prefix=RV32IZHINX %s 11; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=zhinx \ 12; RUN: -verify-machineinstrs -target-abi lp64 | \ 13; RUN: FileCheck -check-prefix=RV64IZHINX %s 14; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ 15; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \ 16; RUN: FileCheck -check-prefix=RV32IDZFH %s 17; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ 18; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \ 19; RUN: FileCheck -check-prefix=RV64IDZFH %s 20; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \ 21; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \ 22; RUN: FileCheck -check-prefix=RV32IZDINXZHINX %s 23; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \ 24; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \ 25; RUN: FileCheck -check-prefix=RV64IZDINXZHINX %s 26 27; These intrinsics require half to be a legal type. 28 29declare iXLen @llvm.lrint.iXLen.f16(half) 30 31define iXLen @lrint_f16(half %a) nounwind { 32; RV32IZFH-LABEL: lrint_f16: 33; RV32IZFH: # %bb.0: 34; RV32IZFH-NEXT: fcvt.w.h a0, fa0 35; RV32IZFH-NEXT: ret 36; 37; RV64IZFH-LABEL: lrint_f16: 38; RV64IZFH: # %bb.0: 39; RV64IZFH-NEXT: fcvt.l.h a0, fa0 40; RV64IZFH-NEXT: ret 41; 42; RV32IZHINX-LABEL: lrint_f16: 43; RV32IZHINX: # %bb.0: 44; RV32IZHINX-NEXT: fcvt.w.h a0, a0 45; RV32IZHINX-NEXT: ret 46; 47; RV64IZHINX-LABEL: lrint_f16: 48; RV64IZHINX: # %bb.0: 49; RV64IZHINX-NEXT: fcvt.l.h a0, a0 50; RV64IZHINX-NEXT: ret 51; 52; RV32IDZFH-LABEL: lrint_f16: 53; RV32IDZFH: # %bb.0: 54; RV32IDZFH-NEXT: fcvt.w.h a0, fa0 55; RV32IDZFH-NEXT: ret 56; 57; RV64IDZFH-LABEL: lrint_f16: 58; RV64IDZFH: # %bb.0: 59; RV64IDZFH-NEXT: fcvt.l.h a0, fa0 60; RV64IDZFH-NEXT: ret 61; 62; RV32IZDINXZHINX-LABEL: lrint_f16: 63; RV32IZDINXZHINX: # %bb.0: 64; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0 65; RV32IZDINXZHINX-NEXT: ret 66; 67; RV64IZDINXZHINX-LABEL: lrint_f16: 68; RV64IZDINXZHINX: # %bb.0: 69; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0 70; RV64IZDINXZHINX-NEXT: ret 71 %1 = call iXLen @llvm.lrint.iXLen.f16(half %a) 72 ret iXLen %1 73} 74 75declare i32 @llvm.lround.i32.f16(half) 76declare i64 @llvm.lround.i64.f16(half) 77 78define iXLen @lround_f16(half %a) nounwind { 79; RV32IZFH-LABEL: lround_f16: 80; RV32IZFH: # %bb.0: 81; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm 82; RV32IZFH-NEXT: ret 83; 84; RV64IZFH-LABEL: lround_f16: 85; RV64IZFH: # %bb.0: 86; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm 87; RV64IZFH-NEXT: ret 88; 89; RV32IZHINX-LABEL: lround_f16: 90; RV32IZHINX: # %bb.0: 91; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm 92; RV32IZHINX-NEXT: ret 93; 94; RV64IZHINX-LABEL: lround_f16: 95; RV64IZHINX: # %bb.0: 96; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm 97; RV64IZHINX-NEXT: ret 98; 99; RV32IDZFH-LABEL: lround_f16: 100; RV32IDZFH: # %bb.0: 101; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm 102; RV32IDZFH-NEXT: ret 103; 104; RV64IDZFH-LABEL: lround_f16: 105; RV64IDZFH: # %bb.0: 106; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm 107; RV64IDZFH-NEXT: ret 108; 109; RV32IZDINXZHINX-LABEL: lround_f16: 110; RV32IZDINXZHINX: # %bb.0: 111; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm 112; RV32IZDINXZHINX-NEXT: ret 113; 114; RV64IZDINXZHINX-LABEL: lround_f16: 115; RV64IZDINXZHINX: # %bb.0: 116; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm 117; RV64IZDINXZHINX-NEXT: ret 118 %1 = call iXLen @llvm.lround.iXLen.f16(half %a) 119 ret iXLen %1 120} 121 122define i32 @lround_i32_f16(half %a) nounwind { 123; RV32IZFH-LABEL: lround_i32_f16: 124; RV32IZFH: # %bb.0: 125; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm 126; RV32IZFH-NEXT: ret 127; 128; RV64IZFH-LABEL: lround_i32_f16: 129; RV64IZFH: # %bb.0: 130; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rmm 131; RV64IZFH-NEXT: ret 132; 133; RV32IZHINX-LABEL: lround_i32_f16: 134; RV32IZHINX: # %bb.0: 135; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm 136; RV32IZHINX-NEXT: ret 137; 138; RV64IZHINX-LABEL: lround_i32_f16: 139; RV64IZHINX: # %bb.0: 140; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rmm 141; RV64IZHINX-NEXT: ret 142; 143; RV32IDZFH-LABEL: lround_i32_f16: 144; RV32IDZFH: # %bb.0: 145; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm 146; RV32IDZFH-NEXT: ret 147; 148; RV64IDZFH-LABEL: lround_i32_f16: 149; RV64IDZFH: # %bb.0: 150; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rmm 151; RV64IDZFH-NEXT: ret 152; 153; RV32IZDINXZHINX-LABEL: lround_i32_f16: 154; RV32IZDINXZHINX: # %bb.0: 155; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm 156; RV32IZDINXZHINX-NEXT: ret 157; 158; RV64IZDINXZHINX-LABEL: lround_i32_f16: 159; RV64IZDINXZHINX: # %bb.0: 160; RV64IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm 161; RV64IZDINXZHINX-NEXT: ret 162 %1 = call i32 @llvm.lround.i32.f16(half %a) 163 ret i32 %1 164} 165