1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2# RUN: llc %s -mtriple=riscv32 -mattr=+zdinx -start-before=prologepilog -o - | FileCheck %s 3 4# We want to make sure eliminateFrameIndex doesn't fold sp+2044 as an offset in 5# a GPR pair spill/reload instruction. When we split the pair spill, we would be 6# unable to add 4 to the immediate without overflowing simm12. 7 8--- | 9 define void @foo() { 10 ; CHECK-LABEL: foo: 11 ; CHECK: # %bb.0: 12 ; CHECK-NEXT: addi sp, sp, -2048 13 ; CHECK-NEXT: addi sp, sp, -16 14 ; CHECK-NEXT: .cfi_def_cfa_offset 2064 15 ; CHECK-NEXT: lui t0, 1 16 ; CHECK-NEXT: add t0, sp, t0 17 ; CHECK-NEXT: sw a0, -2040(t0) # 4-byte Folded Spill 18 ; CHECK-NEXT: sw a1, -2036(t0) # 4-byte Folded Spill 19 ; CHECK-NEXT: lui a0, 1 20 ; CHECK-NEXT: add a0, sp, a0 21 ; CHECK-NEXT: sw a2, -2048(a0) # 4-byte Folded Spill 22 ; CHECK-NEXT: sw a3, -2044(a0) # 4-byte Folded Spill 23 ; CHECK-NEXT: sw a4, 2040(sp) # 4-byte Folded Spill 24 ; CHECK-NEXT: sw a5, 2044(sp) # 4-byte Folded Spill 25 ; CHECK-NEXT: sw a6, 2032(sp) # 4-byte Folded Spill 26 ; CHECK-NEXT: sw a7, 2036(sp) # 4-byte Folded Spill 27 ; CHECK-NEXT: lui a0, 1 28 ; CHECK-NEXT: add a0, sp, a0 29 ; CHECK-NEXT: lw a1, -2036(a0) # 4-byte Folded Reload 30 ; CHECK-NEXT: lw a0, -2040(a0) # 4-byte Folded Reload 31 ; CHECK-NEXT: lui a0, 1 32 ; CHECK-NEXT: add a0, sp, a0 33 ; CHECK-NEXT: lw a2, -2048(a0) # 4-byte Folded Reload 34 ; CHECK-NEXT: lw a3, -2044(a0) # 4-byte Folded Reload 35 ; CHECK-NEXT: lw a4, 2040(sp) # 4-byte Folded Reload 36 ; CHECK-NEXT: lw a5, 2044(sp) # 4-byte Folded Reload 37 ; CHECK-NEXT: lw a6, 2032(sp) # 4-byte Folded Reload 38 ; CHECK-NEXT: lw a7, 2036(sp) # 4-byte Folded Reload 39 ; CHECK-NEXT: addi sp, sp, 2032 40 ; CHECK-NEXT: addi sp, sp, 32 41 ; CHECK-NEXT: .cfi_def_cfa_offset 0 42 ; CHECK-NEXT: ret 43 ret void 44 } 45... 46--- 47name: foo 48tracksRegLiveness: true 49tracksDebugUserValues: true 50frameInfo: 51 maxAlignment: 4 52stack: 53 - { id: 0, type: spill-slot, size: 8, alignment: 4 } 54 - { id: 1, type: spill-slot, size: 8, alignment: 4 } 55 - { id: 2, type: spill-slot, size: 8, alignment: 4 } 56 - { id: 3, type: spill-slot, size: 8, alignment: 4 } 57 - { id: 4, type: spill-slot, size: 2024, alignment: 4 } 58machineFunctionInfo: 59 varArgsFrameIndex: 0 60 varArgsSaveSize: 0 61body: | 62 bb.0: 63 liveins: $x10_x11, $x12_x13, $x14_x15, $x16_x17 64 65 PseudoRV32ZdinxSD killed renamable $x10_x11, %stack.0, 0 :: (store (s64) into %stack.0, align 4) 66 PseudoRV32ZdinxSD killed renamable $x12_x13, %stack.1, 0 :: (store (s64) into %stack.1, align 4) 67 PseudoRV32ZdinxSD killed renamable $x14_x15, %stack.2, 0 :: (store (s64) into %stack.2, align 4) 68 PseudoRV32ZdinxSD killed renamable $x16_x17, %stack.3, 0 :: (store (s64) into %stack.3, align 4) 69 renamable $x10_x11 = PseudoRV32ZdinxLD %stack.0, 0 :: (load (s64) from %stack.0, align 4) 70 renamable $x12_x13 = PseudoRV32ZdinxLD %stack.1, 0 :: (load (s64) from %stack.1, align 4) 71 renamable $x14_x15 = PseudoRV32ZdinxLD %stack.2, 0 :: (load (s64) from %stack.2, align 4) 72 renamable $x16_x17 = PseudoRV32ZdinxLD %stack.3, 0 :: (load (s64) from %stack.3, align 4) 73 PseudoRET 74 75... 76