1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d -mattr=+xtheadfmemidx -mattr=+m -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s -check-prefix=RV32XTHEADMEMIDX 4; RUN: llc -mtriple=riscv64 -mattr=+d -mattr=+xtheadfmemidx -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s -check-prefix=RV64XTHEADFMEMIDX 6 7define float @flrw(ptr %a, i64 %b) { 8; RV32XTHEADMEMIDX-LABEL: flrw: 9; RV32XTHEADMEMIDX: # %bb.0: 10; RV32XTHEADMEMIDX-NEXT: th.flrw fa5, a0, a1, 2 11; RV32XTHEADMEMIDX-NEXT: fadd.s fa0, fa5, fa5 12; RV32XTHEADMEMIDX-NEXT: ret 13; 14; RV64XTHEADFMEMIDX-LABEL: flrw: 15; RV64XTHEADFMEMIDX: # %bb.0: 16; RV64XTHEADFMEMIDX-NEXT: th.flrw fa5, a0, a1, 2 17; RV64XTHEADFMEMIDX-NEXT: fadd.s fa0, fa5, fa5 18; RV64XTHEADFMEMIDX-NEXT: ret 19 %1 = getelementptr float, ptr %a, i64 %b 20 %2 = load float, ptr %1, align 4 21 %3 = fadd float %2, %2 22 ret float %3 23} 24 25define float @flurw(ptr %a, i32 %b) { 26; RV32XTHEADMEMIDX-LABEL: flurw: 27; RV32XTHEADMEMIDX: # %bb.0: 28; RV32XTHEADMEMIDX-NEXT: th.flrw fa5, a0, a1, 2 29; RV32XTHEADMEMIDX-NEXT: fadd.s fa0, fa5, fa5 30; RV32XTHEADMEMIDX-NEXT: ret 31; 32; RV64XTHEADFMEMIDX-LABEL: flurw: 33; RV64XTHEADFMEMIDX: # %bb.0: 34; RV64XTHEADFMEMIDX-NEXT: th.flurw fa5, a0, a1, 2 35; RV64XTHEADFMEMIDX-NEXT: fadd.s fa0, fa5, fa5 36; RV64XTHEADFMEMIDX-NEXT: ret 37 %1 = zext i32 %b to i64 38 %2 = getelementptr float, ptr %a, i64 %1 39 %3 = load float, ptr %2, align 4 40 %4 = fadd float %3, %3 41 ret float %4 42} 43 44define void @fsrw(ptr %a, i64 %b, float %c) { 45; RV32XTHEADMEMIDX-LABEL: fsrw: 46; RV32XTHEADMEMIDX: # %bb.0: 47; RV32XTHEADMEMIDX-NEXT: fadd.s fa5, fa0, fa0 48; RV32XTHEADMEMIDX-NEXT: th.fsrw fa5, a0, a1, 2 49; RV32XTHEADMEMIDX-NEXT: ret 50; 51; RV64XTHEADFMEMIDX-LABEL: fsrw: 52; RV64XTHEADFMEMIDX: # %bb.0: 53; RV64XTHEADFMEMIDX-NEXT: fadd.s fa5, fa0, fa0 54; RV64XTHEADFMEMIDX-NEXT: th.fsrw fa5, a0, a1, 2 55; RV64XTHEADFMEMIDX-NEXT: ret 56 %1 = fadd float %c, %c 57 %2 = getelementptr float, ptr %a, i64 %b 58 store float %1, ptr %2, align 4 59 ret void 60} 61 62define void @fsurw(ptr %a, i32 %b, float %c) { 63; RV32XTHEADMEMIDX-LABEL: fsurw: 64; RV32XTHEADMEMIDX: # %bb.0: 65; RV32XTHEADMEMIDX-NEXT: fadd.s fa5, fa0, fa0 66; RV32XTHEADMEMIDX-NEXT: th.fsrw fa5, a0, a1, 2 67; RV32XTHEADMEMIDX-NEXT: ret 68; 69; RV64XTHEADFMEMIDX-LABEL: fsurw: 70; RV64XTHEADFMEMIDX: # %bb.0: 71; RV64XTHEADFMEMIDX-NEXT: fadd.s fa5, fa0, fa0 72; RV64XTHEADFMEMIDX-NEXT: th.fsurw fa5, a0, a1, 2 73; RV64XTHEADFMEMIDX-NEXT: ret 74 %1 = zext i32 %b to i64 75 %2 = fadd float %c, %c 76 %3 = getelementptr float, ptr %a, i64 %1 77 store float %2, ptr %3, align 4 78 ret void 79} 80 81define double @flrd(ptr %a, i64 %b) { 82; RV32XTHEADMEMIDX-LABEL: flrd: 83; RV32XTHEADMEMIDX: # %bb.0: 84; RV32XTHEADMEMIDX-NEXT: th.flrd fa5, a0, a1, 3 85; RV32XTHEADMEMIDX-NEXT: fadd.d fa0, fa5, fa5 86; RV32XTHEADMEMIDX-NEXT: ret 87; 88; RV64XTHEADFMEMIDX-LABEL: flrd: 89; RV64XTHEADFMEMIDX: # %bb.0: 90; RV64XTHEADFMEMIDX-NEXT: th.flrd fa5, a0, a1, 3 91; RV64XTHEADFMEMIDX-NEXT: fadd.d fa0, fa5, fa5 92; RV64XTHEADFMEMIDX-NEXT: ret 93 %1 = getelementptr double, ptr %a, i64 %b 94 %2 = load double, ptr %1, align 8 95 %3 = fadd double %2, %2 96 ret double %3 97} 98 99define double @flurd(ptr %a, i32 %b) { 100; RV32XTHEADMEMIDX-LABEL: flurd: 101; RV32XTHEADMEMIDX: # %bb.0: 102; RV32XTHEADMEMIDX-NEXT: th.flrd fa5, a0, a1, 3 103; RV32XTHEADMEMIDX-NEXT: fadd.d fa0, fa5, fa5 104; RV32XTHEADMEMIDX-NEXT: ret 105; 106; RV64XTHEADFMEMIDX-LABEL: flurd: 107; RV64XTHEADFMEMIDX: # %bb.0: 108; RV64XTHEADFMEMIDX-NEXT: th.flurd fa5, a0, a1, 3 109; RV64XTHEADFMEMIDX-NEXT: fadd.d fa0, fa5, fa5 110; RV64XTHEADFMEMIDX-NEXT: ret 111 %1 = zext i32 %b to i64 112 %2 = getelementptr double, ptr %a, i64 %1 113 %3 = load double, ptr %2, align 8 114 %4 = fadd double %3, %3 115 ret double %4 116} 117 118define void @fsrd(ptr %a, i64 %b, double %c) { 119; RV32XTHEADMEMIDX-LABEL: fsrd: 120; RV32XTHEADMEMIDX: # %bb.0: 121; RV32XTHEADMEMIDX-NEXT: fadd.d fa5, fa0, fa0 122; RV32XTHEADMEMIDX-NEXT: th.fsrd fa5, a0, a1, 3 123; RV32XTHEADMEMIDX-NEXT: ret 124; 125; RV64XTHEADFMEMIDX-LABEL: fsrd: 126; RV64XTHEADFMEMIDX: # %bb.0: 127; RV64XTHEADFMEMIDX-NEXT: fadd.d fa5, fa0, fa0 128; RV64XTHEADFMEMIDX-NEXT: th.fsrd fa5, a0, a1, 3 129; RV64XTHEADFMEMIDX-NEXT: ret 130 %1 = fadd double %c, %c 131 %2 = getelementptr double, ptr %a, i64 %b 132 store double %1, ptr %2, align 8 133 ret void 134} 135 136define void @fsurd(ptr %a, i32 %b, double %c) { 137; RV32XTHEADMEMIDX-LABEL: fsurd: 138; RV32XTHEADMEMIDX: # %bb.0: 139; RV32XTHEADMEMIDX-NEXT: fadd.d fa5, fa0, fa0 140; RV32XTHEADMEMIDX-NEXT: th.fsrd fa5, a0, a1, 3 141; RV32XTHEADMEMIDX-NEXT: ret 142; 143; RV64XTHEADFMEMIDX-LABEL: fsurd: 144; RV64XTHEADFMEMIDX: # %bb.0: 145; RV64XTHEADFMEMIDX-NEXT: fadd.d fa5, fa0, fa0 146; RV64XTHEADFMEMIDX-NEXT: th.fsurd fa5, a0, a1, 3 147; RV64XTHEADFMEMIDX-NEXT: ret 148 %1 = zext i32 %b to i64 149 %2 = fadd double %c, %c 150 %3 = getelementptr double, ptr %a, i64 %1 151 store double %2, ptr %3, align 8 152 ret void 153} 154