1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32 3 4define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 { 5; RISCV32-LABEL: muloti_test: 6; RISCV32: # %bb.0: # %start 7; RISCV32-NEXT: addi sp, sp, -32 8; RISCV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill 9; RISCV32-NEXT: sw s1, 24(sp) # 4-byte Folded Spill 10; RISCV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill 11; RISCV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill 12; RISCV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill 13; RISCV32-NEXT: sw s5, 8(sp) # 4-byte Folded Spill 14; RISCV32-NEXT: lw a4, 0(a1) 15; RISCV32-NEXT: lw t0, 4(a1) 16; RISCV32-NEXT: lw a3, 8(a1) 17; RISCV32-NEXT: lw a1, 12(a1) 18; RISCV32-NEXT: lw a6, 0(a2) 19; RISCV32-NEXT: lw a5, 4(a2) 20; RISCV32-NEXT: lw a7, 8(a2) 21; RISCV32-NEXT: lw a2, 12(a2) 22; RISCV32-NEXT: mulhu t1, a4, a6 23; RISCV32-NEXT: mul t2, t0, a6 24; RISCV32-NEXT: mulhu t3, t0, a6 25; RISCV32-NEXT: mul t4, a4, a5 26; RISCV32-NEXT: mulhu t5, a4, a5 27; RISCV32-NEXT: mul s2, t0, a5 28; RISCV32-NEXT: mul t6, a7, a4 29; RISCV32-NEXT: mul s3, a3, a6 30; RISCV32-NEXT: mul s0, t0, a7 31; RISCV32-NEXT: mul s1, a2, a4 32; RISCV32-NEXT: mul s4, a5, a3 33; RISCV32-NEXT: add s1, s1, s0 34; RISCV32-NEXT: mul s0, a1, a6 35; RISCV32-NEXT: add s4, s0, s4 36; RISCV32-NEXT: mulhu s5, t0, a5 37; RISCV32-NEXT: add t1, t2, t1 38; RISCV32-NEXT: sltu t2, t1, t2 39; RISCV32-NEXT: add t2, t3, t2 40; RISCV32-NEXT: mulhu s0, a7, a4 41; RISCV32-NEXT: add t1, t4, t1 42; RISCV32-NEXT: sltu t3, t1, t4 43; RISCV32-NEXT: add t3, t5, t3 44; RISCV32-NEXT: mulhu t5, a3, a6 45; RISCV32-NEXT: add t4, s3, t6 46; RISCV32-NEXT: add s1, s0, s1 47; RISCV32-NEXT: add t6, t5, s4 48; RISCV32-NEXT: sltu s3, t4, s3 49; RISCV32-NEXT: add t3, t2, t3 50; RISCV32-NEXT: sltu t2, t3, t2 51; RISCV32-NEXT: add s5, s5, t2 52; RISCV32-NEXT: add s4, t6, s1 53; RISCV32-NEXT: add t3, s2, t3 54; RISCV32-NEXT: add t2, t3, t4 55; RISCV32-NEXT: sltu s2, t3, s2 56; RISCV32-NEXT: sltu t4, t2, t3 57; RISCV32-NEXT: add s2, s5, s2 58; RISCV32-NEXT: add s3, s4, s3 59; RISCV32-NEXT: add t3, s2, s3 60; RISCV32-NEXT: add t3, t3, t4 61; RISCV32-NEXT: beq t3, s2, .LBB0_2 62; RISCV32-NEXT: # %bb.1: # %start 63; RISCV32-NEXT: sltu t4, t3, s2 64; RISCV32-NEXT: .LBB0_2: # %start 65; RISCV32-NEXT: sltu s0, s1, s0 66; RISCV32-NEXT: snez s1, t0 67; RISCV32-NEXT: snez s2, a2 68; RISCV32-NEXT: sltu t5, t6, t5 69; RISCV32-NEXT: mulhu t6, a2, a4 70; RISCV32-NEXT: mulhu t0, t0, a7 71; RISCV32-NEXT: or a2, a7, a2 72; RISCV32-NEXT: snez a7, a5 73; RISCV32-NEXT: mul a4, a4, a6 74; RISCV32-NEXT: mulhu a6, a1, a6 75; RISCV32-NEXT: mulhu a5, a5, a3 76; RISCV32-NEXT: or a3, a3, a1 77; RISCV32-NEXT: snez a1, a1 78; RISCV32-NEXT: and s1, s2, s1 79; RISCV32-NEXT: snez t6, t6 80; RISCV32-NEXT: snez t0, t0 81; RISCV32-NEXT: and a1, a1, a7 82; RISCV32-NEXT: snez a6, a6 83; RISCV32-NEXT: snez a5, a5 84; RISCV32-NEXT: snez a2, a2 85; RISCV32-NEXT: snez a3, a3 86; RISCV32-NEXT: or a7, s1, t6 87; RISCV32-NEXT: or a1, a1, a6 88; RISCV32-NEXT: and a2, a3, a2 89; RISCV32-NEXT: or a3, a7, t0 90; RISCV32-NEXT: or a1, a1, a5 91; RISCV32-NEXT: or a3, a3, s0 92; RISCV32-NEXT: or a1, a1, t5 93; RISCV32-NEXT: or a1, a2, a1 94; RISCV32-NEXT: or a1, a1, a3 95; RISCV32-NEXT: or a1, a1, t4 96; RISCV32-NEXT: andi a1, a1, 1 97; RISCV32-NEXT: sw a4, 0(a0) 98; RISCV32-NEXT: sw t1, 4(a0) 99; RISCV32-NEXT: sw t2, 8(a0) 100; RISCV32-NEXT: sw t3, 12(a0) 101; RISCV32-NEXT: sb a1, 16(a0) 102; RISCV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload 103; RISCV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload 104; RISCV32-NEXT: lw s2, 20(sp) # 4-byte Folded Reload 105; RISCV32-NEXT: lw s3, 16(sp) # 4-byte Folded Reload 106; RISCV32-NEXT: lw s4, 12(sp) # 4-byte Folded Reload 107; RISCV32-NEXT: lw s5, 8(sp) # 4-byte Folded Reload 108; RISCV32-NEXT: addi sp, sp, 32 109; RISCV32-NEXT: ret 110start: 111 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 112 %1 = extractvalue { i128, i1 } %0, 0 113 %2 = extractvalue { i128, i1 } %0, 1 114 %3 = zext i1 %2 to i8 115 %4 = insertvalue { i128, i8 } undef, i128 %1, 0 116 %5 = insertvalue { i128, i8 } %4, i8 %3, 1 117 ret { i128, i8 } %5 118} 119 120; Function Attrs: nounwind readnone speculatable 121declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1 122 123attributes #0 = { nounwind readnone } 124attributes #1 = { nounwind readnone speculatable } 125attributes #2 = { nounwind } 126