xref: /llvm-project/llvm/test/CodeGen/RISCV/stack-clash-prologue-nounwind.ll (revision c835b48a4d72227b174bcd86f071238a1583803a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m -O2 < %s -verify-machineinstrs \
3; RUN:   | FileCheck %s -check-prefix=RV64I
4; RUN: llc -mtriple=riscv32 -mattr=+m -O2 < %s -verify-machineinstrs \
5; RUN:   | FileCheck %s -check-prefix=RV32I
6
7; Tests copied from PowerPC.
8
9; Free probe
10define i8 @f0() #0 nounwind {
11; RV64I-LABEL: f0:
12; RV64I:       # %bb.0: # %entry
13; RV64I-NEXT:    addi sp, sp, -64
14; RV64I-NEXT:    li a0, 3
15; RV64I-NEXT:    sb a0, 0(sp)
16; RV64I-NEXT:    lbu a0, 0(sp)
17; RV64I-NEXT:    addi sp, sp, 64
18; RV64I-NEXT:    ret
19;
20; RV32I-LABEL: f0:
21; RV32I:       # %bb.0: # %entry
22; RV32I-NEXT:    addi sp, sp, -64
23; RV32I-NEXT:    li a0, 3
24; RV32I-NEXT:    sb a0, 0(sp)
25; RV32I-NEXT:    lbu a0, 0(sp)
26; RV32I-NEXT:    addi sp, sp, 64
27; RV32I-NEXT:    ret
28entry:
29  %a = alloca i8, i64 64
30  %b = getelementptr inbounds i8, ptr %a, i64 63
31  store volatile i8 3, ptr %a
32  %c = load volatile i8, ptr %a
33  ret i8 %c
34}
35
36define i8 @f1() #0 nounwind {
37; RV64I-LABEL: f1:
38; RV64I:       # %bb.0: # %entry
39; RV64I-NEXT:    lui a0, 1
40; RV64I-NEXT:    sub sp, sp, a0
41; RV64I-NEXT:    sd zero, 0(sp)
42; RV64I-NEXT:    addi sp, sp, -16
43; RV64I-NEXT:    li a0, 3
44; RV64I-NEXT:    sb a0, 16(sp)
45; RV64I-NEXT:    lbu a0, 16(sp)
46; RV64I-NEXT:    lui a1, 1
47; RV64I-NEXT:    addiw a1, a1, 16
48; RV64I-NEXT:    add sp, sp, a1
49; RV64I-NEXT:    ret
50;
51; RV32I-LABEL: f1:
52; RV32I:       # %bb.0: # %entry
53; RV32I-NEXT:    lui a0, 1
54; RV32I-NEXT:    sub sp, sp, a0
55; RV32I-NEXT:    sw zero, 0(sp)
56; RV32I-NEXT:    addi sp, sp, -16
57; RV32I-NEXT:    li a0, 3
58; RV32I-NEXT:    sb a0, 16(sp)
59; RV32I-NEXT:    lbu a0, 16(sp)
60; RV32I-NEXT:    lui a1, 1
61; RV32I-NEXT:    addi a1, a1, 16
62; RV32I-NEXT:    add sp, sp, a1
63; RV32I-NEXT:    ret
64entry:
65  %a = alloca i8, i64 4096
66  %b = getelementptr inbounds i8, ptr %a, i64 63
67  store volatile i8 3, ptr %a
68  %c = load volatile i8, ptr %a
69  ret i8 %c
70}
71
72define i8 @f2() #0 nounwind {
73; RV64I-LABEL: f2:
74; RV64I:       # %bb.0: # %entry
75; RV64I-NEXT:    lui a0, 16
76; RV64I-NEXT:    sub t1, sp, a0
77; RV64I-NEXT:    lui t2, 1
78; RV64I-NEXT:  .LBB2_1: # %entry
79; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
80; RV64I-NEXT:    sub sp, sp, t2
81; RV64I-NEXT:    sd zero, 0(sp)
82; RV64I-NEXT:    bne sp, t1, .LBB2_1
83; RV64I-NEXT:  # %bb.2: # %entry
84; RV64I-NEXT:    addi sp, sp, -16
85; RV64I-NEXT:    li a0, 3
86; RV64I-NEXT:    sb a0, 16(sp)
87; RV64I-NEXT:    lbu a0, 16(sp)
88; RV64I-NEXT:    lui a1, 16
89; RV64I-NEXT:    addiw a1, a1, 16
90; RV64I-NEXT:    add sp, sp, a1
91; RV64I-NEXT:    ret
92;
93; RV32I-LABEL: f2:
94; RV32I:       # %bb.0: # %entry
95; RV32I-NEXT:    lui a0, 16
96; RV32I-NEXT:    sub t1, sp, a0
97; RV32I-NEXT:    lui t2, 1
98; RV32I-NEXT:  .LBB2_1: # %entry
99; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
100; RV32I-NEXT:    sub sp, sp, t2
101; RV32I-NEXT:    sw zero, 0(sp)
102; RV32I-NEXT:    bne sp, t1, .LBB2_1
103; RV32I-NEXT:  # %bb.2: # %entry
104; RV32I-NEXT:    addi sp, sp, -16
105; RV32I-NEXT:    li a0, 3
106; RV32I-NEXT:    sb a0, 16(sp)
107; RV32I-NEXT:    lbu a0, 16(sp)
108; RV32I-NEXT:    lui a1, 16
109; RV32I-NEXT:    addi a1, a1, 16
110; RV32I-NEXT:    add sp, sp, a1
111; RV32I-NEXT:    ret
112entry:
113  %a = alloca i8, i64 65536
114  %b = getelementptr inbounds i8, ptr %a, i64 63
115  store volatile i8 3, ptr %a
116  %c = load volatile i8, ptr %a
117  ret i8 %c
118}
119
120define i8 @f3() #0 "stack-probe-size"="32768" nounwind {
121; RV64I-LABEL: f3:
122; RV64I:       # %bb.0: # %entry
123; RV64I-NEXT:    lui a0, 8
124; RV64I-NEXT:    sub sp, sp, a0
125; RV64I-NEXT:    sd zero, 0(sp)
126; RV64I-NEXT:    lui a0, 8
127; RV64I-NEXT:    sub sp, sp, a0
128; RV64I-NEXT:    sd zero, 0(sp)
129; RV64I-NEXT:    addi sp, sp, -16
130; RV64I-NEXT:    li a0, 3
131; RV64I-NEXT:    sb a0, 16(sp)
132; RV64I-NEXT:    lbu a0, 16(sp)
133; RV64I-NEXT:    lui a1, 16
134; RV64I-NEXT:    addiw a1, a1, 16
135; RV64I-NEXT:    add sp, sp, a1
136; RV64I-NEXT:    ret
137;
138; RV32I-LABEL: f3:
139; RV32I:       # %bb.0: # %entry
140; RV32I-NEXT:    lui a0, 8
141; RV32I-NEXT:    sub sp, sp, a0
142; RV32I-NEXT:    sw zero, 0(sp)
143; RV32I-NEXT:    lui a0, 8
144; RV32I-NEXT:    sub sp, sp, a0
145; RV32I-NEXT:    sw zero, 0(sp)
146; RV32I-NEXT:    addi sp, sp, -16
147; RV32I-NEXT:    li a0, 3
148; RV32I-NEXT:    sb a0, 16(sp)
149; RV32I-NEXT:    lbu a0, 16(sp)
150; RV32I-NEXT:    lui a1, 16
151; RV32I-NEXT:    addi a1, a1, 16
152; RV32I-NEXT:    add sp, sp, a1
153; RV32I-NEXT:    ret
154entry:
155  %a = alloca i8, i64 65536
156  %b = getelementptr inbounds i8, ptr %a, i64 63
157  store volatile i8 3, ptr %a
158  %c = load volatile i8, ptr %a
159  ret i8 %c
160}
161
162; Same as f2, but without protection.
163define i8 @f4() nounwind {
164; RV64I-LABEL: f4:
165; RV64I:       # %bb.0: # %entry
166; RV64I-NEXT:    lui a0, 16
167; RV64I-NEXT:    addiw a0, a0, 16
168; RV64I-NEXT:    sub sp, sp, a0
169; RV64I-NEXT:    li a0, 3
170; RV64I-NEXT:    sb a0, 16(sp)
171; RV64I-NEXT:    lbu a0, 16(sp)
172; RV64I-NEXT:    lui a1, 16
173; RV64I-NEXT:    addiw a1, a1, 16
174; RV64I-NEXT:    add sp, sp, a1
175; RV64I-NEXT:    ret
176;
177; RV32I-LABEL: f4:
178; RV32I:       # %bb.0: # %entry
179; RV32I-NEXT:    lui a0, 16
180; RV32I-NEXT:    addi a0, a0, 16
181; RV32I-NEXT:    sub sp, sp, a0
182; RV32I-NEXT:    li a0, 3
183; RV32I-NEXT:    sb a0, 16(sp)
184; RV32I-NEXT:    lbu a0, 16(sp)
185; RV32I-NEXT:    lui a1, 16
186; RV32I-NEXT:    addi a1, a1, 16
187; RV32I-NEXT:    add sp, sp, a1
188; RV32I-NEXT:    ret
189entry:
190  %a = alloca i8, i64 65536
191  %b = getelementptr inbounds i8, ptr %a, i64 63
192  store volatile i8 3, ptr %a
193  %c = load volatile i8, ptr %a
194  ret i8 %c
195}
196
197define i8 @f5() #0 "stack-probe-size"="65536" nounwind {
198; RV64I-LABEL: f5:
199; RV64I:       # %bb.0: # %entry
200; RV64I-NEXT:    lui a0, 256
201; RV64I-NEXT:    sub t1, sp, a0
202; RV64I-NEXT:    lui t2, 16
203; RV64I-NEXT:  .LBB5_1: # %entry
204; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
205; RV64I-NEXT:    sub sp, sp, t2
206; RV64I-NEXT:    sd zero, 0(sp)
207; RV64I-NEXT:    bne sp, t1, .LBB5_1
208; RV64I-NEXT:  # %bb.2: # %entry
209; RV64I-NEXT:    addi sp, sp, -16
210; RV64I-NEXT:    li a0, 3
211; RV64I-NEXT:    sb a0, 16(sp)
212; RV64I-NEXT:    lbu a0, 16(sp)
213; RV64I-NEXT:    lui a1, 256
214; RV64I-NEXT:    addiw a1, a1, 16
215; RV64I-NEXT:    add sp, sp, a1
216; RV64I-NEXT:    ret
217;
218; RV32I-LABEL: f5:
219; RV32I:       # %bb.0: # %entry
220; RV32I-NEXT:    lui a0, 256
221; RV32I-NEXT:    sub t1, sp, a0
222; RV32I-NEXT:    lui t2, 16
223; RV32I-NEXT:  .LBB5_1: # %entry
224; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
225; RV32I-NEXT:    sub sp, sp, t2
226; RV32I-NEXT:    sw zero, 0(sp)
227; RV32I-NEXT:    bne sp, t1, .LBB5_1
228; RV32I-NEXT:  # %bb.2: # %entry
229; RV32I-NEXT:    addi sp, sp, -16
230; RV32I-NEXT:    li a0, 3
231; RV32I-NEXT:    sb a0, 16(sp)
232; RV32I-NEXT:    lbu a0, 16(sp)
233; RV32I-NEXT:    lui a1, 256
234; RV32I-NEXT:    addi a1, a1, 16
235; RV32I-NEXT:    add sp, sp, a1
236; RV32I-NEXT:    ret
237entry:
238  %a = alloca i8, i64 1048576
239  %b = getelementptr inbounds i8, ptr %a, i64 63
240  store volatile i8 3, ptr %a
241  %c = load volatile i8, ptr %a
242  ret i8 %c
243}
244
245define i8 @f6() #0 nounwind {
246; RV64I-LABEL: f6:
247; RV64I:       # %bb.0: # %entry
248; RV64I-NEXT:    lui a0, 262144
249; RV64I-NEXT:    sub t1, sp, a0
250; RV64I-NEXT:    lui t2, 1
251; RV64I-NEXT:  .LBB6_1: # %entry
252; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
253; RV64I-NEXT:    sub sp, sp, t2
254; RV64I-NEXT:    sd zero, 0(sp)
255; RV64I-NEXT:    bne sp, t1, .LBB6_1
256; RV64I-NEXT:  # %bb.2: # %entry
257; RV64I-NEXT:    addi sp, sp, -16
258; RV64I-NEXT:    li a0, 3
259; RV64I-NEXT:    sb a0, 16(sp)
260; RV64I-NEXT:    lbu a0, 16(sp)
261; RV64I-NEXT:    lui a1, 262144
262; RV64I-NEXT:    addiw a1, a1, 16
263; RV64I-NEXT:    add sp, sp, a1
264; RV64I-NEXT:    ret
265;
266; RV32I-LABEL: f6:
267; RV32I:       # %bb.0: # %entry
268; RV32I-NEXT:    lui a0, 262144
269; RV32I-NEXT:    sub t1, sp, a0
270; RV32I-NEXT:    lui t2, 1
271; RV32I-NEXT:  .LBB6_1: # %entry
272; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
273; RV32I-NEXT:    sub sp, sp, t2
274; RV32I-NEXT:    sw zero, 0(sp)
275; RV32I-NEXT:    bne sp, t1, .LBB6_1
276; RV32I-NEXT:  # %bb.2: # %entry
277; RV32I-NEXT:    addi sp, sp, -16
278; RV32I-NEXT:    li a0, 3
279; RV32I-NEXT:    sb a0, 16(sp)
280; RV32I-NEXT:    lbu a0, 16(sp)
281; RV32I-NEXT:    lui a1, 262144
282; RV32I-NEXT:    addi a1, a1, 16
283; RV32I-NEXT:    add sp, sp, a1
284; RV32I-NEXT:    ret
285entry:
286  %a = alloca i8, i64 1073741824
287  %b = getelementptr inbounds i8, ptr %a, i64 63
288  store volatile i8 3, ptr %a
289  %c = load volatile i8, ptr %a
290  ret i8 %c
291}
292
293define i8 @f7() #0 "stack-probe-size"="65536" nounwind {
294; RV64I-LABEL: f7:
295; RV64I:       # %bb.0: # %entry
296; RV64I-NEXT:    lui a0, 244128
297; RV64I-NEXT:    sub t1, sp, a0
298; RV64I-NEXT:    lui t2, 16
299; RV64I-NEXT:  .LBB7_1: # %entry
300; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
301; RV64I-NEXT:    sub sp, sp, t2
302; RV64I-NEXT:    sd zero, 0(sp)
303; RV64I-NEXT:    bne sp, t1, .LBB7_1
304; RV64I-NEXT:  # %bb.2: # %entry
305; RV64I-NEXT:    lui a0, 13
306; RV64I-NEXT:    addiw a0, a0, -1520
307; RV64I-NEXT:    sub sp, sp, a0
308; RV64I-NEXT:    li a0, 3
309; RV64I-NEXT:    sb a0, 9(sp)
310; RV64I-NEXT:    lbu a0, 9(sp)
311; RV64I-NEXT:    lui a1, 244141
312; RV64I-NEXT:    addiw a1, a1, -1520
313; RV64I-NEXT:    add sp, sp, a1
314; RV64I-NEXT:    ret
315;
316; RV32I-LABEL: f7:
317; RV32I:       # %bb.0: # %entry
318; RV32I-NEXT:    lui a0, 244128
319; RV32I-NEXT:    sub t1, sp, a0
320; RV32I-NEXT:    lui t2, 16
321; RV32I-NEXT:  .LBB7_1: # %entry
322; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
323; RV32I-NEXT:    sub sp, sp, t2
324; RV32I-NEXT:    sw zero, 0(sp)
325; RV32I-NEXT:    bne sp, t1, .LBB7_1
326; RV32I-NEXT:  # %bb.2: # %entry
327; RV32I-NEXT:    lui a0, 13
328; RV32I-NEXT:    addi a0, a0, -1520
329; RV32I-NEXT:    sub sp, sp, a0
330; RV32I-NEXT:    li a0, 3
331; RV32I-NEXT:    sb a0, 9(sp)
332; RV32I-NEXT:    lbu a0, 9(sp)
333; RV32I-NEXT:    lui a1, 244141
334; RV32I-NEXT:    addi a1, a1, -1520
335; RV32I-NEXT:    add sp, sp, a1
336; RV32I-NEXT:    ret
337entry:
338  %a = alloca i8, i64 1000000007
339  %b = getelementptr inbounds i8, ptr %a, i64 101
340  store volatile i8 3, ptr %a
341  %c = load volatile i8, ptr %a
342  ret i8 %c
343}
344
345attributes #0 = { "probe-stack"="inline-asm" }
346