xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vsub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vsub_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
9; CHECK-NEXT:    vsub.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %vc = sub <vscale x 1 x i8> %va, %vb
12  ret <vscale x 1 x i8> %vc
13}
14
15define <vscale x 1 x i8> @vsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
16; CHECK-LABEL: vsub_vx_nxv1i8:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
19; CHECK-NEXT:    vsub.vx v8, v8, a0
20; CHECK-NEXT:    ret
21  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
22  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
23  %vc = sub <vscale x 1 x i8> %va, %splat
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 1 x i8> @vsub_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
28; CHECK-LABEL: vsub_vx_nxv1i8_0:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    li a0, 1
31; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
32; CHECK-NEXT:    vsub.vx v8, v8, a0
33; CHECK-NEXT:    ret
34  %vc = sub <vscale x 1 x i8> %va, splat (i8 1)
35  ret <vscale x 1 x i8> %vc
36}
37
38; Test constant subs to see if we can optimize them away for scalable vectors.
39define <vscale x 1 x i8> @vsub_ii_nxv1i8_1() {
40; CHECK-LABEL: vsub_ii_nxv1i8_1:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
43; CHECK-NEXT:    vmv.v.i v8, -1
44; CHECK-NEXT:    ret
45  %vc = sub <vscale x 1 x i8> splat (i8 2), splat (i8 3)
46  ret <vscale x 1 x i8> %vc
47}
48
49define <vscale x 2 x i8> @vsub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
50; CHECK-LABEL: vsub_vv_nxv2i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
53; CHECK-NEXT:    vsub.vv v8, v8, v9
54; CHECK-NEXT:    ret
55  %vc = sub <vscale x 2 x i8> %va, %vb
56  ret <vscale x 2 x i8> %vc
57}
58
59define <vscale x 2 x i8> @vsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
60; CHECK-LABEL: vsub_vx_nxv2i8:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
63; CHECK-NEXT:    vsub.vx v8, v8, a0
64; CHECK-NEXT:    ret
65  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
66  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
67  %vc = sub <vscale x 2 x i8> %va, %splat
68  ret <vscale x 2 x i8> %vc
69}
70
71define <vscale x 2 x i8> @vsub_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
72; CHECK-LABEL: vsub_vx_nxv2i8_0:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    li a0, 1
75; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
76; CHECK-NEXT:    vsub.vx v8, v8, a0
77; CHECK-NEXT:    ret
78  %vc = sub <vscale x 2 x i8> %va, splat (i8 1)
79  ret <vscale x 2 x i8> %vc
80}
81
82define <vscale x 4 x i8> @vsub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
83; CHECK-LABEL: vsub_vv_nxv4i8:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
86; CHECK-NEXT:    vsub.vv v8, v8, v9
87; CHECK-NEXT:    ret
88  %vc = sub <vscale x 4 x i8> %va, %vb
89  ret <vscale x 4 x i8> %vc
90}
91
92define <vscale x 4 x i8> @vsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
93; CHECK-LABEL: vsub_vx_nxv4i8:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
96; CHECK-NEXT:    vsub.vx v8, v8, a0
97; CHECK-NEXT:    ret
98  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
99  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
100  %vc = sub <vscale x 4 x i8> %va, %splat
101  ret <vscale x 4 x i8> %vc
102}
103
104define <vscale x 4 x i8> @vsub_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
105; CHECK-LABEL: vsub_vx_nxv4i8_0:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    li a0, 1
108; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
109; CHECK-NEXT:    vsub.vx v8, v8, a0
110; CHECK-NEXT:    ret
111  %vc = sub <vscale x 4 x i8> %va, splat (i8 1)
112  ret <vscale x 4 x i8> %vc
113}
114
115define <vscale x 8 x i8> @vsub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
116; CHECK-LABEL: vsub_vv_nxv8i8:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
119; CHECK-NEXT:    vsub.vv v8, v8, v9
120; CHECK-NEXT:    ret
121  %vc = sub <vscale x 8 x i8> %va, %vb
122  ret <vscale x 8 x i8> %vc
123}
124
125define <vscale x 8 x i8> @vsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
126; CHECK-LABEL: vsub_vx_nxv8i8:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
129; CHECK-NEXT:    vsub.vx v8, v8, a0
130; CHECK-NEXT:    ret
131  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
132  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
133  %vc = sub <vscale x 8 x i8> %va, %splat
134  ret <vscale x 8 x i8> %vc
135}
136
137define <vscale x 8 x i8> @vsub_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
138; CHECK-LABEL: vsub_vx_nxv8i8_0:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    li a0, 1
141; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
142; CHECK-NEXT:    vsub.vx v8, v8, a0
143; CHECK-NEXT:    ret
144  %vc = sub <vscale x 8 x i8> %va, splat (i8 1)
145  ret <vscale x 8 x i8> %vc
146}
147
148define <vscale x 16 x i8> @vsub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
149; CHECK-LABEL: vsub_vv_nxv16i8:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
152; CHECK-NEXT:    vsub.vv v8, v8, v10
153; CHECK-NEXT:    ret
154  %vc = sub <vscale x 16 x i8> %va, %vb
155  ret <vscale x 16 x i8> %vc
156}
157
158define <vscale x 16 x i8> @vsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
159; CHECK-LABEL: vsub_vx_nxv16i8:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
162; CHECK-NEXT:    vsub.vx v8, v8, a0
163; CHECK-NEXT:    ret
164  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
165  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
166  %vc = sub <vscale x 16 x i8> %va, %splat
167  ret <vscale x 16 x i8> %vc
168}
169
170define <vscale x 16 x i8> @vsub_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
171; CHECK-LABEL: vsub_vx_nxv16i8_0:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    li a0, 1
174; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
175; CHECK-NEXT:    vsub.vx v8, v8, a0
176; CHECK-NEXT:    ret
177  %vc = sub <vscale x 16 x i8> %va, splat (i8 1)
178  ret <vscale x 16 x i8> %vc
179}
180
181define <vscale x 32 x i8> @vsub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
182; CHECK-LABEL: vsub_vv_nxv32i8:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
185; CHECK-NEXT:    vsub.vv v8, v8, v12
186; CHECK-NEXT:    ret
187  %vc = sub <vscale x 32 x i8> %va, %vb
188  ret <vscale x 32 x i8> %vc
189}
190
191define <vscale x 32 x i8> @vsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
192; CHECK-LABEL: vsub_vx_nxv32i8:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
195; CHECK-NEXT:    vsub.vx v8, v8, a0
196; CHECK-NEXT:    ret
197  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
198  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
199  %vc = sub <vscale x 32 x i8> %va, %splat
200  ret <vscale x 32 x i8> %vc
201}
202
203define <vscale x 32 x i8> @vsub_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
204; CHECK-LABEL: vsub_vx_nxv32i8_0:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    li a0, 1
207; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
208; CHECK-NEXT:    vsub.vx v8, v8, a0
209; CHECK-NEXT:    ret
210  %vc = sub <vscale x 32 x i8> %va, splat (i8 1)
211  ret <vscale x 32 x i8> %vc
212}
213
214define <vscale x 64 x i8> @vsub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
215; CHECK-LABEL: vsub_vv_nxv64i8:
216; CHECK:       # %bb.0:
217; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
218; CHECK-NEXT:    vsub.vv v8, v8, v16
219; CHECK-NEXT:    ret
220  %vc = sub <vscale x 64 x i8> %va, %vb
221  ret <vscale x 64 x i8> %vc
222}
223
224define <vscale x 64 x i8> @vsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
225; CHECK-LABEL: vsub_vx_nxv64i8:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
228; CHECK-NEXT:    vsub.vx v8, v8, a0
229; CHECK-NEXT:    ret
230  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
231  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
232  %vc = sub <vscale x 64 x i8> %va, %splat
233  ret <vscale x 64 x i8> %vc
234}
235
236define <vscale x 64 x i8> @vsub_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
237; CHECK-LABEL: vsub_vx_nxv64i8_0:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    li a0, 1
240; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
241; CHECK-NEXT:    vsub.vx v8, v8, a0
242; CHECK-NEXT:    ret
243  %vc = sub <vscale x 64 x i8> %va, splat (i8 1)
244  ret <vscale x 64 x i8> %vc
245}
246
247define <vscale x 1 x i16> @vsub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
248; CHECK-LABEL: vsub_vv_nxv1i16:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
251; CHECK-NEXT:    vsub.vv v8, v8, v9
252; CHECK-NEXT:    ret
253  %vc = sub <vscale x 1 x i16> %va, %vb
254  ret <vscale x 1 x i16> %vc
255}
256
257define <vscale x 1 x i16> @vsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
258; CHECK-LABEL: vsub_vx_nxv1i16:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
261; CHECK-NEXT:    vsub.vx v8, v8, a0
262; CHECK-NEXT:    ret
263  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
264  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
265  %vc = sub <vscale x 1 x i16> %va, %splat
266  ret <vscale x 1 x i16> %vc
267}
268
269define <vscale x 1 x i16> @vsub_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
270; CHECK-LABEL: vsub_vx_nxv1i16_0:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    li a0, 1
273; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
274; CHECK-NEXT:    vsub.vx v8, v8, a0
275; CHECK-NEXT:    ret
276  %vc = sub <vscale x 1 x i16> %va, splat (i16 1)
277  ret <vscale x 1 x i16> %vc
278}
279
280define <vscale x 2 x i16> @vsub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
281; CHECK-LABEL: vsub_vv_nxv2i16:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
284; CHECK-NEXT:    vsub.vv v8, v8, v9
285; CHECK-NEXT:    ret
286  %vc = sub <vscale x 2 x i16> %va, %vb
287  ret <vscale x 2 x i16> %vc
288}
289
290define <vscale x 2 x i16> @vsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
291; CHECK-LABEL: vsub_vx_nxv2i16:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
294; CHECK-NEXT:    vsub.vx v8, v8, a0
295; CHECK-NEXT:    ret
296  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
297  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
298  %vc = sub <vscale x 2 x i16> %va, %splat
299  ret <vscale x 2 x i16> %vc
300}
301
302define <vscale x 2 x i16> @vsub_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
303; CHECK-LABEL: vsub_vx_nxv2i16_0:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    li a0, 1
306; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
307; CHECK-NEXT:    vsub.vx v8, v8, a0
308; CHECK-NEXT:    ret
309  %vc = sub <vscale x 2 x i16> %va, splat (i16 1)
310  ret <vscale x 2 x i16> %vc
311}
312
313define <vscale x 4 x i16> @vsub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
314; CHECK-LABEL: vsub_vv_nxv4i16:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
317; CHECK-NEXT:    vsub.vv v8, v8, v9
318; CHECK-NEXT:    ret
319  %vc = sub <vscale x 4 x i16> %va, %vb
320  ret <vscale x 4 x i16> %vc
321}
322
323define <vscale x 4 x i16> @vsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
324; CHECK-LABEL: vsub_vx_nxv4i16:
325; CHECK:       # %bb.0:
326; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
327; CHECK-NEXT:    vsub.vx v8, v8, a0
328; CHECK-NEXT:    ret
329  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
330  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
331  %vc = sub <vscale x 4 x i16> %va, %splat
332  ret <vscale x 4 x i16> %vc
333}
334
335define <vscale x 4 x i16> @vsub_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
336; CHECK-LABEL: vsub_vx_nxv4i16_0:
337; CHECK:       # %bb.0:
338; CHECK-NEXT:    li a0, 1
339; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
340; CHECK-NEXT:    vsub.vx v8, v8, a0
341; CHECK-NEXT:    ret
342  %vc = sub <vscale x 4 x i16> %va, splat (i16 1)
343  ret <vscale x 4 x i16> %vc
344}
345
346define <vscale x 8 x i16> @vsub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
347; CHECK-LABEL: vsub_vv_nxv8i16:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
350; CHECK-NEXT:    vsub.vv v8, v8, v10
351; CHECK-NEXT:    ret
352  %vc = sub <vscale x 8 x i16> %va, %vb
353  ret <vscale x 8 x i16> %vc
354}
355
356define <vscale x 8 x i16> @vsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
357; CHECK-LABEL: vsub_vx_nxv8i16:
358; CHECK:       # %bb.0:
359; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
360; CHECK-NEXT:    vsub.vx v8, v8, a0
361; CHECK-NEXT:    ret
362  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
363  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
364  %vc = sub <vscale x 8 x i16> %va, %splat
365  ret <vscale x 8 x i16> %vc
366}
367
368define <vscale x 8 x i16> @vsub_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
369; CHECK-LABEL: vsub_vx_nxv8i16_0:
370; CHECK:       # %bb.0:
371; CHECK-NEXT:    li a0, 1
372; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
373; CHECK-NEXT:    vsub.vx v8, v8, a0
374; CHECK-NEXT:    ret
375  %vc = sub <vscale x 8 x i16> %va, splat (i16 1)
376  ret <vscale x 8 x i16> %vc
377}
378
379define <vscale x 16 x i16> @vsub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
380; CHECK-LABEL: vsub_vv_nxv16i16:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
383; CHECK-NEXT:    vsub.vv v8, v8, v12
384; CHECK-NEXT:    ret
385  %vc = sub <vscale x 16 x i16> %va, %vb
386  ret <vscale x 16 x i16> %vc
387}
388
389define <vscale x 16 x i16> @vsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
390; CHECK-LABEL: vsub_vx_nxv16i16:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
393; CHECK-NEXT:    vsub.vx v8, v8, a0
394; CHECK-NEXT:    ret
395  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
396  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
397  %vc = sub <vscale x 16 x i16> %va, %splat
398  ret <vscale x 16 x i16> %vc
399}
400
401define <vscale x 16 x i16> @vsub_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
402; CHECK-LABEL: vsub_vx_nxv16i16_0:
403; CHECK:       # %bb.0:
404; CHECK-NEXT:    li a0, 1
405; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
406; CHECK-NEXT:    vsub.vx v8, v8, a0
407; CHECK-NEXT:    ret
408  %vc = sub <vscale x 16 x i16> %va, splat (i16 1)
409  ret <vscale x 16 x i16> %vc
410}
411
412define <vscale x 32 x i16> @vsub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
413; CHECK-LABEL: vsub_vv_nxv32i16:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
416; CHECK-NEXT:    vsub.vv v8, v8, v16
417; CHECK-NEXT:    ret
418  %vc = sub <vscale x 32 x i16> %va, %vb
419  ret <vscale x 32 x i16> %vc
420}
421
422define <vscale x 32 x i16> @vsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
423; CHECK-LABEL: vsub_vx_nxv32i16:
424; CHECK:       # %bb.0:
425; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
426; CHECK-NEXT:    vsub.vx v8, v8, a0
427; CHECK-NEXT:    ret
428  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
429  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
430  %vc = sub <vscale x 32 x i16> %va, %splat
431  ret <vscale x 32 x i16> %vc
432}
433
434define <vscale x 32 x i16> @vsub_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
435; CHECK-LABEL: vsub_vx_nxv32i16_0:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    li a0, 1
438; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
439; CHECK-NEXT:    vsub.vx v8, v8, a0
440; CHECK-NEXT:    ret
441  %vc = sub <vscale x 32 x i16> %va, splat (i16 1)
442  ret <vscale x 32 x i16> %vc
443}
444
445define <vscale x 1 x i32> @vsub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
446; CHECK-LABEL: vsub_vv_nxv1i32:
447; CHECK:       # %bb.0:
448; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
449; CHECK-NEXT:    vsub.vv v8, v8, v9
450; CHECK-NEXT:    ret
451  %vc = sub <vscale x 1 x i32> %va, %vb
452  ret <vscale x 1 x i32> %vc
453}
454
455define <vscale x 1 x i32> @vsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
456; CHECK-LABEL: vsub_vx_nxv1i32:
457; CHECK:       # %bb.0:
458; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
459; CHECK-NEXT:    vsub.vx v8, v8, a0
460; CHECK-NEXT:    ret
461  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
462  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
463  %vc = sub <vscale x 1 x i32> %va, %splat
464  ret <vscale x 1 x i32> %vc
465}
466
467define <vscale x 1 x i32> @vsub_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
468; CHECK-LABEL: vsub_vx_nxv1i32_0:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    li a0, 1
471; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
472; CHECK-NEXT:    vsub.vx v8, v8, a0
473; CHECK-NEXT:    ret
474  %vc = sub <vscale x 1 x i32> %va, splat (i32 1)
475  ret <vscale x 1 x i32> %vc
476}
477
478define <vscale x 2 x i32> @vsub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
479; CHECK-LABEL: vsub_vv_nxv2i32:
480; CHECK:       # %bb.0:
481; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
482; CHECK-NEXT:    vsub.vv v8, v8, v9
483; CHECK-NEXT:    ret
484  %vc = sub <vscale x 2 x i32> %va, %vb
485  ret <vscale x 2 x i32> %vc
486}
487
488define <vscale x 2 x i32> @vsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
489; CHECK-LABEL: vsub_vx_nxv2i32:
490; CHECK:       # %bb.0:
491; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
492; CHECK-NEXT:    vsub.vx v8, v8, a0
493; CHECK-NEXT:    ret
494  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
495  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
496  %vc = sub <vscale x 2 x i32> %va, %splat
497  ret <vscale x 2 x i32> %vc
498}
499
500define <vscale x 2 x i32> @vsub_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
501; CHECK-LABEL: vsub_vx_nxv2i32_0:
502; CHECK:       # %bb.0:
503; CHECK-NEXT:    li a0, 1
504; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
505; CHECK-NEXT:    vsub.vx v8, v8, a0
506; CHECK-NEXT:    ret
507  %vc = sub <vscale x 2 x i32> %va, splat (i32 1)
508  ret <vscale x 2 x i32> %vc
509}
510
511define <vscale x 4 x i32> @vsub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
512; CHECK-LABEL: vsub_vv_nxv4i32:
513; CHECK:       # %bb.0:
514; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
515; CHECK-NEXT:    vsub.vv v8, v8, v10
516; CHECK-NEXT:    ret
517  %vc = sub <vscale x 4 x i32> %va, %vb
518  ret <vscale x 4 x i32> %vc
519}
520
521define <vscale x 4 x i32> @vsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
522; CHECK-LABEL: vsub_vx_nxv4i32:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
525; CHECK-NEXT:    vsub.vx v8, v8, a0
526; CHECK-NEXT:    ret
527  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
528  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
529  %vc = sub <vscale x 4 x i32> %va, %splat
530  ret <vscale x 4 x i32> %vc
531}
532
533define <vscale x 4 x i32> @vsub_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
534; CHECK-LABEL: vsub_vx_nxv4i32_0:
535; CHECK:       # %bb.0:
536; CHECK-NEXT:    li a0, 1
537; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
538; CHECK-NEXT:    vsub.vx v8, v8, a0
539; CHECK-NEXT:    ret
540  %vc = sub <vscale x 4 x i32> %va, splat (i32 1)
541  ret <vscale x 4 x i32> %vc
542}
543
544define <vscale x 8 x i32> @vsub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
545; CHECK-LABEL: vsub_vv_nxv8i32:
546; CHECK:       # %bb.0:
547; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
548; CHECK-NEXT:    vsub.vv v8, v8, v12
549; CHECK-NEXT:    ret
550  %vc = sub <vscale x 8 x i32> %va, %vb
551  ret <vscale x 8 x i32> %vc
552}
553
554define <vscale x 8 x i32> @vsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
555; CHECK-LABEL: vsub_vx_nxv8i32:
556; CHECK:       # %bb.0:
557; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
558; CHECK-NEXT:    vsub.vx v8, v8, a0
559; CHECK-NEXT:    ret
560  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
561  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
562  %vc = sub <vscale x 8 x i32> %va, %splat
563  ret <vscale x 8 x i32> %vc
564}
565
566define <vscale x 8 x i32> @vsub_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
567; CHECK-LABEL: vsub_vx_nxv8i32_0:
568; CHECK:       # %bb.0:
569; CHECK-NEXT:    li a0, 1
570; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
571; CHECK-NEXT:    vsub.vx v8, v8, a0
572; CHECK-NEXT:    ret
573  %vc = sub <vscale x 8 x i32> %va, splat (i32 1)
574  ret <vscale x 8 x i32> %vc
575}
576
577define <vscale x 16 x i32> @vsub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
578; CHECK-LABEL: vsub_vv_nxv16i32:
579; CHECK:       # %bb.0:
580; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
581; CHECK-NEXT:    vsub.vv v8, v8, v16
582; CHECK-NEXT:    ret
583  %vc = sub <vscale x 16 x i32> %va, %vb
584  ret <vscale x 16 x i32> %vc
585}
586
587define <vscale x 16 x i32> @vsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
588; CHECK-LABEL: vsub_vx_nxv16i32:
589; CHECK:       # %bb.0:
590; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
591; CHECK-NEXT:    vsub.vx v8, v8, a0
592; CHECK-NEXT:    ret
593  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
594  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
595  %vc = sub <vscale x 16 x i32> %va, %splat
596  ret <vscale x 16 x i32> %vc
597}
598
599define <vscale x 16 x i32> @vsub_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
600; CHECK-LABEL: vsub_vx_nxv16i32_0:
601; CHECK:       # %bb.0:
602; CHECK-NEXT:    li a0, 1
603; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
604; CHECK-NEXT:    vsub.vx v8, v8, a0
605; CHECK-NEXT:    ret
606  %vc = sub <vscale x 16 x i32> %va, splat (i32 1)
607  ret <vscale x 16 x i32> %vc
608}
609
610define <vscale x 1 x i64> @vsub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
611; CHECK-LABEL: vsub_vv_nxv1i64:
612; CHECK:       # %bb.0:
613; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
614; CHECK-NEXT:    vsub.vv v8, v8, v9
615; CHECK-NEXT:    ret
616  %vc = sub <vscale x 1 x i64> %va, %vb
617  ret <vscale x 1 x i64> %vc
618}
619
620define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
621; RV32-LABEL: vsub_vx_nxv1i64:
622; RV32:       # %bb.0:
623; RV32-NEXT:    addi sp, sp, -16
624; RV32-NEXT:    .cfi_def_cfa_offset 16
625; RV32-NEXT:    sw a0, 8(sp)
626; RV32-NEXT:    sw a1, 12(sp)
627; RV32-NEXT:    addi a0, sp, 8
628; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
629; RV32-NEXT:    vlse64.v v9, (a0), zero
630; RV32-NEXT:    vsub.vv v8, v8, v9
631; RV32-NEXT:    addi sp, sp, 16
632; RV32-NEXT:    .cfi_def_cfa_offset 0
633; RV32-NEXT:    ret
634;
635; RV64-LABEL: vsub_vx_nxv1i64:
636; RV64:       # %bb.0:
637; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
638; RV64-NEXT:    vsub.vx v8, v8, a0
639; RV64-NEXT:    ret
640  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
641  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
642  %vc = sub <vscale x 1 x i64> %va, %splat
643  ret <vscale x 1 x i64> %vc
644}
645
646define <vscale x 1 x i64> @vsub_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
647; CHECK-LABEL: vsub_vx_nxv1i64_0:
648; CHECK:       # %bb.0:
649; CHECK-NEXT:    li a0, 1
650; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
651; CHECK-NEXT:    vsub.vx v8, v8, a0
652; CHECK-NEXT:    ret
653  %vc = sub <vscale x 1 x i64> %va, splat (i64 1)
654  ret <vscale x 1 x i64> %vc
655}
656
657define <vscale x 2 x i64> @vsub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
658; CHECK-LABEL: vsub_vv_nxv2i64:
659; CHECK:       # %bb.0:
660; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
661; CHECK-NEXT:    vsub.vv v8, v8, v10
662; CHECK-NEXT:    ret
663  %vc = sub <vscale x 2 x i64> %va, %vb
664  ret <vscale x 2 x i64> %vc
665}
666
667define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
668; RV32-LABEL: vsub_vx_nxv2i64:
669; RV32:       # %bb.0:
670; RV32-NEXT:    addi sp, sp, -16
671; RV32-NEXT:    .cfi_def_cfa_offset 16
672; RV32-NEXT:    sw a0, 8(sp)
673; RV32-NEXT:    sw a1, 12(sp)
674; RV32-NEXT:    addi a0, sp, 8
675; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
676; RV32-NEXT:    vlse64.v v10, (a0), zero
677; RV32-NEXT:    vsub.vv v8, v8, v10
678; RV32-NEXT:    addi sp, sp, 16
679; RV32-NEXT:    .cfi_def_cfa_offset 0
680; RV32-NEXT:    ret
681;
682; RV64-LABEL: vsub_vx_nxv2i64:
683; RV64:       # %bb.0:
684; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
685; RV64-NEXT:    vsub.vx v8, v8, a0
686; RV64-NEXT:    ret
687  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
688  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
689  %vc = sub <vscale x 2 x i64> %va, %splat
690  ret <vscale x 2 x i64> %vc
691}
692
693define <vscale x 2 x i64> @vsub_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
694; CHECK-LABEL: vsub_vx_nxv2i64_0:
695; CHECK:       # %bb.0:
696; CHECK-NEXT:    li a0, 1
697; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
698; CHECK-NEXT:    vsub.vx v8, v8, a0
699; CHECK-NEXT:    ret
700  %vc = sub <vscale x 2 x i64> %va, splat (i64 1)
701  ret <vscale x 2 x i64> %vc
702}
703
704define <vscale x 4 x i64> @vsub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
705; CHECK-LABEL: vsub_vv_nxv4i64:
706; CHECK:       # %bb.0:
707; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
708; CHECK-NEXT:    vsub.vv v8, v8, v12
709; CHECK-NEXT:    ret
710  %vc = sub <vscale x 4 x i64> %va, %vb
711  ret <vscale x 4 x i64> %vc
712}
713
714define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
715; RV32-LABEL: vsub_vx_nxv4i64:
716; RV32:       # %bb.0:
717; RV32-NEXT:    addi sp, sp, -16
718; RV32-NEXT:    .cfi_def_cfa_offset 16
719; RV32-NEXT:    sw a0, 8(sp)
720; RV32-NEXT:    sw a1, 12(sp)
721; RV32-NEXT:    addi a0, sp, 8
722; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
723; RV32-NEXT:    vlse64.v v12, (a0), zero
724; RV32-NEXT:    vsub.vv v8, v8, v12
725; RV32-NEXT:    addi sp, sp, 16
726; RV32-NEXT:    .cfi_def_cfa_offset 0
727; RV32-NEXT:    ret
728;
729; RV64-LABEL: vsub_vx_nxv4i64:
730; RV64:       # %bb.0:
731; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
732; RV64-NEXT:    vsub.vx v8, v8, a0
733; RV64-NEXT:    ret
734  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
735  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
736  %vc = sub <vscale x 4 x i64> %va, %splat
737  ret <vscale x 4 x i64> %vc
738}
739
740define <vscale x 4 x i64> @vsub_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
741; CHECK-LABEL: vsub_vx_nxv4i64_0:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    li a0, 1
744; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
745; CHECK-NEXT:    vsub.vx v8, v8, a0
746; CHECK-NEXT:    ret
747  %vc = sub <vscale x 4 x i64> %va, splat (i64 1)
748  ret <vscale x 4 x i64> %vc
749}
750
751define <vscale x 8 x i64> @vsub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
752; CHECK-LABEL: vsub_vv_nxv8i64:
753; CHECK:       # %bb.0:
754; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
755; CHECK-NEXT:    vsub.vv v8, v8, v16
756; CHECK-NEXT:    ret
757  %vc = sub <vscale x 8 x i64> %va, %vb
758  ret <vscale x 8 x i64> %vc
759}
760
761define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
762; RV32-LABEL: vsub_vx_nxv8i64:
763; RV32:       # %bb.0:
764; RV32-NEXT:    addi sp, sp, -16
765; RV32-NEXT:    .cfi_def_cfa_offset 16
766; RV32-NEXT:    sw a0, 8(sp)
767; RV32-NEXT:    sw a1, 12(sp)
768; RV32-NEXT:    addi a0, sp, 8
769; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
770; RV32-NEXT:    vlse64.v v16, (a0), zero
771; RV32-NEXT:    vsub.vv v8, v8, v16
772; RV32-NEXT:    addi sp, sp, 16
773; RV32-NEXT:    .cfi_def_cfa_offset 0
774; RV32-NEXT:    ret
775;
776; RV64-LABEL: vsub_vx_nxv8i64:
777; RV64:       # %bb.0:
778; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
779; RV64-NEXT:    vsub.vx v8, v8, a0
780; RV64-NEXT:    ret
781  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
782  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
783  %vc = sub <vscale x 8 x i64> %va, %splat
784  ret <vscale x 8 x i64> %vc
785}
786
787define <vscale x 8 x i64> @vsub_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
788; CHECK-LABEL: vsub_vx_nxv8i64_0:
789; CHECK:       # %bb.0:
790; CHECK-NEXT:    li a0, 1
791; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
792; CHECK-NEXT:    vsub.vx v8, v8, a0
793; CHECK-NEXT:    ret
794  %vc = sub <vscale x 8 x i64> %va, splat (i64 1)
795  ret <vscale x 8 x i64> %vc
796}
797
798define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
799; RV32-LABEL: vsub_xx_nxv8i64:
800; RV32:       # %bb.0:
801; RV32-NEXT:    addi sp, sp, -16
802; RV32-NEXT:    sub a4, a0, a2
803; RV32-NEXT:    sltu a0, a0, a2
804; RV32-NEXT:    sub a1, a1, a3
805; RV32-NEXT:    sub a1, a1, a0
806; RV32-NEXT:    sw a4, 8(sp)
807; RV32-NEXT:    sw a1, 12(sp)
808; RV32-NEXT:    addi a0, sp, 8
809; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
810; RV32-NEXT:    vlse64.v v8, (a0), zero
811; RV32-NEXT:    addi sp, sp, 16
812; RV32-NEXT:    ret
813;
814; RV64-LABEL: vsub_xx_nxv8i64:
815; RV64:       # %bb.0:
816; RV64-NEXT:    sub a0, a0, a1
817; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
818; RV64-NEXT:    vmv.v.x v8, a0
819; RV64-NEXT:    ret
820  %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
821  %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
822  %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
823  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
824  %v = sub <vscale x 8 x i64> %splat1, %splat2
825  ret <vscale x 8 x i64> %v
826}
827
828define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
829; CHECK-LABEL: vsub_vv_mask_nxv8i32:
830; CHECK:       # %bb.0:
831; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
832; CHECK-NEXT:    vsub.vv v8, v8, v12, v0.t
833; CHECK-NEXT:    ret
834
835  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
836  %vc = sub <vscale x 8 x i32> %va, %vs
837  ret <vscale x 8 x i32> %vc
838}
839
840define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
841; CHECK-LABEL: vsub_vx_mask_nxv8i32:
842; CHECK:       # %bb.0:
843; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
844; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
845; CHECK-NEXT:    ret
846  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
847  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
848  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
849  %vc = sub <vscale x 8 x i32> %va, %vs
850  ret <vscale x 8 x i32> %vc
851}
852
853define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
854; CHECK-LABEL: vsub_vi_mask_nxv8i32:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    li a0, 7
857; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
858; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
859; CHECK-NEXT:    ret
860  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> zeroinitializer
861  %vc = sub <vscale x 8 x i32> %va, %vs
862  ret <vscale x 8 x i32> %vc
863}
864