xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4
5declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr, <vscale x 1 x i8>, i32, i32)
6declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
7
8define void @test_vsoxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9; CHECK-LABEL: test_vsoxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8:
10; CHECK:       # %bb.0: # %entry
11; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
12; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
13; CHECK-NEXT:    ret
14entry:
15  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
16  ret void
17}
18
19define void @test_vsoxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
20; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8:
21; CHECK:       # %bb.0: # %entry
22; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
23; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
24; CHECK-NEXT:    ret
25entry:
26  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
27  ret void
28}
29
30declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr, <vscale x 1 x i16>, i32, i32)
31declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
32
33define void @test_vsoxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
34; CHECK-LABEL: test_vsoxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16:
35; CHECK:       # %bb.0: # %entry
36; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
37; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
38; CHECK-NEXT:    ret
39entry:
40  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
41  ret void
42}
43
44define void @test_vsoxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
45; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16:
46; CHECK:       # %bb.0: # %entry
47; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
48; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
49; CHECK-NEXT:    ret
50entry:
51  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
52  ret void
53}
54
55declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr, <vscale x 1 x i32>, i32, i32)
56declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
57
58define void @test_vsoxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
59; CHECK-LABEL: test_vsoxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
62; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
63; CHECK-NEXT:    ret
64entry:
65  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
66  ret void
67}
68
69define void @test_vsoxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
70; CHECK-LABEL: test_vsoxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32:
71; CHECK:       # %bb.0: # %entry
72; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
73; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
74; CHECK-NEXT:    ret
75entry:
76  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
77  ret void
78}
79
80declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i8>, i32, i32)
81declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
82
83define void @test_vsoxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
84; CHECK-LABEL: test_vsoxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8:
85; CHECK:       # %bb.0: # %entry
86; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
87; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
88; CHECK-NEXT:    ret
89entry:
90  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
91  ret void
92}
93
94define void @test_vsoxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
95; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8:
96; CHECK:       # %bb.0: # %entry
97; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
98; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
99; CHECK-NEXT:    ret
100entry:
101  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
102  ret void
103}
104
105declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i16>, i32, i32)
106declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
107
108define void @test_vsoxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
109; CHECK-LABEL: test_vsoxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16:
110; CHECK:       # %bb.0: # %entry
111; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
112; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
113; CHECK-NEXT:    ret
114entry:
115  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
116  ret void
117}
118
119define void @test_vsoxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
120; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16:
121; CHECK:       # %bb.0: # %entry
122; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
123; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
124; CHECK-NEXT:    ret
125entry:
126  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
127  ret void
128}
129
130declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i32>, i32, i32)
131declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
132
133define void @test_vsoxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
134; CHECK-LABEL: test_vsoxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32:
135; CHECK:       # %bb.0: # %entry
136; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
137; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
138; CHECK-NEXT:    ret
139entry:
140  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
141  ret void
142}
143
144define void @test_vsoxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
145; CHECK-LABEL: test_vsoxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32:
146; CHECK:       # %bb.0: # %entry
147; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
148; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
149; CHECK-NEXT:    ret
150entry:
151  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
152  ret void
153}
154
155declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i8>, i32, i32)
156declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
157
158define void @test_vsoxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
159; CHECK-LABEL: test_vsoxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8:
160; CHECK:       # %bb.0: # %entry
161; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
162; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
163; CHECK-NEXT:    ret
164entry:
165  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
166  ret void
167}
168
169define void @test_vsoxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
170; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8:
171; CHECK:       # %bb.0: # %entry
172; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
173; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
174; CHECK-NEXT:    ret
175entry:
176  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
177  ret void
178}
179
180declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i16>, i32, i32)
181declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
182
183define void @test_vsoxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
184; CHECK-LABEL: test_vsoxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16:
185; CHECK:       # %bb.0: # %entry
186; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
187; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
188; CHECK-NEXT:    ret
189entry:
190  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
191  ret void
192}
193
194define void @test_vsoxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
195; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16:
196; CHECK:       # %bb.0: # %entry
197; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
198; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
199; CHECK-NEXT:    ret
200entry:
201  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
202  ret void
203}
204
205declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i32>, i32, i32)
206declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
207
208define void @test_vsoxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
209; CHECK-LABEL: test_vsoxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32:
210; CHECK:       # %bb.0: # %entry
211; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
212; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
213; CHECK-NEXT:    ret
214entry:
215  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
216  ret void
217}
218
219define void @test_vsoxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
220; CHECK-LABEL: test_vsoxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32:
221; CHECK:       # %bb.0: # %entry
222; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
223; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
224; CHECK-NEXT:    ret
225entry:
226  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
227  ret void
228}
229
230declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 8 x i8>, i32, i32)
231declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
232
233define void @test_vsoxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
234; CHECK-LABEL: test_vsoxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8:
235; CHECK:       # %bb.0: # %entry
236; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
237; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
238; CHECK-NEXT:    ret
239entry:
240  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
241  ret void
242}
243
244define void @test_vsoxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
245; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8:
246; CHECK:       # %bb.0: # %entry
247; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
248; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
249; CHECK-NEXT:    ret
250entry:
251  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
252  ret void
253}
254
255declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 8 x i16>, i32, i32)
256declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
257
258define void @test_vsoxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
259; CHECK-LABEL: test_vsoxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16:
260; CHECK:       # %bb.0: # %entry
261; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
262; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
263; CHECK-NEXT:    ret
264entry:
265  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
266  ret void
267}
268
269define void @test_vsoxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
270; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16:
271; CHECK:       # %bb.0: # %entry
272; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
273; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
274; CHECK-NEXT:    ret
275entry:
276  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
277  ret void
278}
279
280declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 8 x i32>, i32, i32)
281declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
282
283define void @test_vsoxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
284; CHECK-LABEL: test_vsoxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32:
285; CHECK:       # %bb.0: # %entry
286; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
287; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
288; CHECK-NEXT:    ret
289entry:
290  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
291  ret void
292}
293
294define void @test_vsoxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
295; CHECK-LABEL: test_vsoxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32:
296; CHECK:       # %bb.0: # %entry
297; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
298; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
299; CHECK-NEXT:    ret
300entry:
301  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
302  ret void
303}
304
305declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 16 x i8>, i32, i32)
306declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i32, i32)
307
308define void @test_vsoxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl) {
309; CHECK-LABEL: test_vsoxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8:
310; CHECK:       # %bb.0: # %entry
311; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
312; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
313; CHECK-NEXT:    ret
314entry:
315  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, i32 3)
316  ret void
317}
318
319define void @test_vsoxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 16 x i1> %mask) {
320; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8:
321; CHECK:       # %bb.0: # %entry
322; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
323; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
324; CHECK-NEXT:    ret
325entry:
326  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
327  ret void
328}
329
330declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 16 x i16>, i32, i32)
331declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i32, i32)
332
333define void @test_vsoxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl) {
334; CHECK-LABEL: test_vsoxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16:
335; CHECK:       # %bb.0: # %entry
336; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
337; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
338; CHECK-NEXT:    ret
339entry:
340  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, i32 3)
341  ret void
342}
343
344define void @test_vsoxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 16 x i1> %mask) {
345; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16:
346; CHECK:       # %bb.0: # %entry
347; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
348; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
349; CHECK-NEXT:    ret
350entry:
351  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
352  ret void
353}
354
355declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 16 x i32>, i32, i32)
356declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i32, i32)
357
358define void @test_vsoxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl) {
359; CHECK-LABEL: test_vsoxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32:
360; CHECK:       # %bb.0: # %entry
361; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
362; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
363; CHECK-NEXT:    ret
364entry:
365  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, i32 3)
366  ret void
367}
368
369define void @test_vsoxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 16 x i1> %mask) {
370; CHECK-LABEL: test_vsoxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32:
371; CHECK:       # %bb.0: # %entry
372; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
373; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
374; CHECK-NEXT:    ret
375entry:
376  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
377  ret void
378}
379
380declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 32 x i8>, i32, i32)
381declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv32i8.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 32 x i8>, <vscale x 32 x i1>, i32, i32)
382
383define void @test_vsoxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, i32 %vl) {
384; CHECK-LABEL: test_vsoxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8:
385; CHECK:       # %bb.0: # %entry
386; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
387; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
388; CHECK-NEXT:    ret
389entry:
390  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, i32 %vl, i32 3)
391  ret void
392}
393
394define void @test_vsoxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, i32 %vl, <vscale x 32 x i1> %mask) {
395; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8:
396; CHECK:       # %bb.0: # %entry
397; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
398; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
399; CHECK-NEXT:    ret
400entry:
401  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv32i8.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i32 %vl, i32 3)
402  ret void
403}
404
405declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 32 x i16>, i32, i32)
406declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv32i16.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 32 x i16>, <vscale x 32 x i1>, i32, i32)
407
408define void @test_vsoxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, i32 %vl) {
409; CHECK-LABEL: test_vsoxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16:
410; CHECK:       # %bb.0: # %entry
411; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
412; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
413; CHECK-NEXT:    ret
414entry:
415  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, i32 %vl, i32 3)
416  ret void
417}
418
419define void @test_vsoxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, i32 %vl, <vscale x 32 x i1> %mask) {
420; CHECK-LABEL: test_vsoxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16:
421; CHECK:       # %bb.0: # %entry
422; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
423; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
424; CHECK-NEXT:    ret
425entry:
426  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv32i16.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i32 %vl, i32 3)
427  ret void
428}
429
430declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr, <vscale x 1 x i8>, i32, i32)
431declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
432
433define void @test_vsoxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
434; CHECK-LABEL: test_vsoxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8:
435; CHECK:       # %bb.0: # %entry
436; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
437; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
438; CHECK-NEXT:    ret
439entry:
440  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
441  ret void
442}
443
444define void @test_vsoxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
445; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8:
446; CHECK:       # %bb.0: # %entry
447; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
448; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
449; CHECK-NEXT:    ret
450entry:
451  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
452  ret void
453}
454
455declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr, <vscale x 1 x i16>, i32, i32)
456declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
457
458define void @test_vsoxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
459; CHECK-LABEL: test_vsoxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16:
460; CHECK:       # %bb.0: # %entry
461; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
462; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
463; CHECK-NEXT:    ret
464entry:
465  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
466  ret void
467}
468
469define void @test_vsoxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
470; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16:
471; CHECK:       # %bb.0: # %entry
472; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
473; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
474; CHECK-NEXT:    ret
475entry:
476  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
477  ret void
478}
479
480declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr, <vscale x 1 x i32>, i32, i32)
481declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
482
483define void @test_vsoxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
484; CHECK-LABEL: test_vsoxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32:
485; CHECK:       # %bb.0: # %entry
486; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
487; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
488; CHECK-NEXT:    ret
489entry:
490  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
491  ret void
492}
493
494define void @test_vsoxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
495; CHECK-LABEL: test_vsoxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32:
496; CHECK:       # %bb.0: # %entry
497; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
498; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
499; CHECK-NEXT:    ret
500entry:
501  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
502  ret void
503}
504
505declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i8>, i32, i32)
506declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
507
508define void @test_vsoxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
509; CHECK-LABEL: test_vsoxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8:
510; CHECK:       # %bb.0: # %entry
511; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
512; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
513; CHECK-NEXT:    ret
514entry:
515  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
516  ret void
517}
518
519define void @test_vsoxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
520; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8:
521; CHECK:       # %bb.0: # %entry
522; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
523; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
524; CHECK-NEXT:    ret
525entry:
526  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
527  ret void
528}
529
530declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i16>, i32, i32)
531declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
532
533define void @test_vsoxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
534; CHECK-LABEL: test_vsoxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16:
535; CHECK:       # %bb.0: # %entry
536; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
537; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
538; CHECK-NEXT:    ret
539entry:
540  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
541  ret void
542}
543
544define void @test_vsoxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
545; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16:
546; CHECK:       # %bb.0: # %entry
547; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
548; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
549; CHECK-NEXT:    ret
550entry:
551  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
552  ret void
553}
554
555declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i32>, i32, i32)
556declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
557
558define void @test_vsoxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
559; CHECK-LABEL: test_vsoxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32:
560; CHECK:       # %bb.0: # %entry
561; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
562; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
563; CHECK-NEXT:    ret
564entry:
565  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
566  ret void
567}
568
569define void @test_vsoxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
570; CHECK-LABEL: test_vsoxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32:
571; CHECK:       # %bb.0: # %entry
572; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
573; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
574; CHECK-NEXT:    ret
575entry:
576  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
577  ret void
578}
579
580declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i8>, i32, i32)
581declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
582
583define void @test_vsoxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
584; CHECK-LABEL: test_vsoxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8:
585; CHECK:       # %bb.0: # %entry
586; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
587; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
588; CHECK-NEXT:    ret
589entry:
590  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
591  ret void
592}
593
594define void @test_vsoxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
595; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8:
596; CHECK:       # %bb.0: # %entry
597; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
598; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
599; CHECK-NEXT:    ret
600entry:
601  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
602  ret void
603}
604
605declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i16>, i32, i32)
606declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
607
608define void @test_vsoxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
609; CHECK-LABEL: test_vsoxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16:
610; CHECK:       # %bb.0: # %entry
611; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
612; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
613; CHECK-NEXT:    ret
614entry:
615  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
616  ret void
617}
618
619define void @test_vsoxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
620; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16:
621; CHECK:       # %bb.0: # %entry
622; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
623; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
624; CHECK-NEXT:    ret
625entry:
626  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
627  ret void
628}
629
630declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i32>, i32, i32)
631declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
632
633define void @test_vsoxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
634; CHECK-LABEL: test_vsoxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32:
635; CHECK:       # %bb.0: # %entry
636; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
637; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12
638; CHECK-NEXT:    ret
639entry:
640  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
641  ret void
642}
643
644define void @test_vsoxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
645; CHECK-LABEL: test_vsoxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32:
646; CHECK:       # %bb.0: # %entry
647; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
648; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12, v0.t
649; CHECK-NEXT:    ret
650entry:
651  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
652  ret void
653}
654
655declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 8 x i8>, i32, i32)
656declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
657
658define void @test_vsoxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
659; CHECK-LABEL: test_vsoxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8:
660; CHECK:       # %bb.0: # %entry
661; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
662; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
663; CHECK-NEXT:    ret
664entry:
665  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
666  ret void
667}
668
669define void @test_vsoxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
670; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8:
671; CHECK:       # %bb.0: # %entry
672; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
673; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
674; CHECK-NEXT:    ret
675entry:
676  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
677  ret void
678}
679
680declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 8 x i16>, i32, i32)
681declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
682
683define void @test_vsoxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
684; CHECK-LABEL: test_vsoxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16:
685; CHECK:       # %bb.0: # %entry
686; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
687; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v12
688; CHECK-NEXT:    ret
689entry:
690  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
691  ret void
692}
693
694define void @test_vsoxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
695; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16:
696; CHECK:       # %bb.0: # %entry
697; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
698; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v12, v0.t
699; CHECK-NEXT:    ret
700entry:
701  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
702  ret void
703}
704
705declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 8 x i32>, i32, i32)
706declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
707
708define void @test_vsoxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
709; CHECK-LABEL: test_vsoxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32:
710; CHECK:       # %bb.0: # %entry
711; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
712; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12
713; CHECK-NEXT:    ret
714entry:
715  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
716  ret void
717}
718
719define void @test_vsoxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
720; CHECK-LABEL: test_vsoxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32:
721; CHECK:       # %bb.0: # %entry
722; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
723; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12, v0.t
724; CHECK-NEXT:    ret
725entry:
726  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
727  ret void
728}
729
730declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 16 x i8>, i32, i32)
731declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i32, i32)
732
733define void @test_vsoxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl) {
734; CHECK-LABEL: test_vsoxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8:
735; CHECK:       # %bb.0: # %entry
736; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
737; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
738; CHECK-NEXT:    ret
739entry:
740  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, i32 3)
741  ret void
742}
743
744define void @test_vsoxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 16 x i1> %mask) {
745; CHECK-LABEL: test_vsoxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8:
746; CHECK:       # %bb.0: # %entry
747; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
748; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
749; CHECK-NEXT:    ret
750entry:
751  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
752  ret void
753}
754
755declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 16 x i16>, i32, i32)
756declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i32, i32)
757
758define void @test_vsoxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl) {
759; CHECK-LABEL: test_vsoxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16:
760; CHECK:       # %bb.0: # %entry
761; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
762; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v16
763; CHECK-NEXT:    ret
764entry:
765  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, i32 3)
766  ret void
767}
768
769define void @test_vsoxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 16 x i1> %mask) {
770; CHECK-LABEL: test_vsoxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16:
771; CHECK:       # %bb.0: # %entry
772; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
773; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v16, v0.t
774; CHECK-NEXT:    ret
775entry:
776  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
777  ret void
778}
779
780declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 16 x i32>, i32, i32)
781declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i32, i32)
782
783define void @test_vsoxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl) {
784; CHECK-LABEL: test_vsoxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32:
785; CHECK:       # %bb.0: # %entry
786; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
787; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16
788; CHECK-NEXT:    ret
789entry:
790  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, i32 3)
791  ret void
792}
793
794define void @test_vsoxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 16 x i1> %mask) {
795; CHECK-LABEL: test_vsoxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32:
796; CHECK:       # %bb.0: # %entry
797; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
798; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16, v0.t
799; CHECK-NEXT:    ret
800entry:
801  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
802  ret void
803}
804
805declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr, <vscale x 1 x i8>, i32, i32)
806declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
807
808define void @test_vsoxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
809; CHECK-LABEL: test_vsoxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8:
810; CHECK:       # %bb.0: # %entry
811; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
812; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
813; CHECK-NEXT:    ret
814entry:
815  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
816  ret void
817}
818
819define void @test_vsoxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
820; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8:
821; CHECK:       # %bb.0: # %entry
822; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
823; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
824; CHECK-NEXT:    ret
825entry:
826  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
827  ret void
828}
829
830declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr, <vscale x 1 x i16>, i32, i32)
831declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
832
833define void @test_vsoxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
834; CHECK-LABEL: test_vsoxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16:
835; CHECK:       # %bb.0: # %entry
836; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
837; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
838; CHECK-NEXT:    ret
839entry:
840  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
841  ret void
842}
843
844define void @test_vsoxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
845; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16:
846; CHECK:       # %bb.0: # %entry
847; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
848; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
849; CHECK-NEXT:    ret
850entry:
851  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
852  ret void
853}
854
855declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr, <vscale x 1 x i32>, i32, i32)
856declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
857
858define void @test_vsoxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
859; CHECK-LABEL: test_vsoxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32:
860; CHECK:       # %bb.0: # %entry
861; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
862; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
863; CHECK-NEXT:    ret
864entry:
865  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
866  ret void
867}
868
869define void @test_vsoxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
870; CHECK-LABEL: test_vsoxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32:
871; CHECK:       # %bb.0: # %entry
872; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
873; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
874; CHECK-NEXT:    ret
875entry:
876  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
877  ret void
878}
879
880declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i8>, i32, i32)
881declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
882
883define void @test_vsoxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
884; CHECK-LABEL: test_vsoxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8:
885; CHECK:       # %bb.0: # %entry
886; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
887; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
888; CHECK-NEXT:    ret
889entry:
890  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
891  ret void
892}
893
894define void @test_vsoxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
895; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8:
896; CHECK:       # %bb.0: # %entry
897; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
898; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
899; CHECK-NEXT:    ret
900entry:
901  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
902  ret void
903}
904
905declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i16>, i32, i32)
906declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
907
908define void @test_vsoxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
909; CHECK-LABEL: test_vsoxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16:
910; CHECK:       # %bb.0: # %entry
911; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
912; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
913; CHECK-NEXT:    ret
914entry:
915  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
916  ret void
917}
918
919define void @test_vsoxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
920; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16:
921; CHECK:       # %bb.0: # %entry
922; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
923; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
924; CHECK-NEXT:    ret
925entry:
926  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
927  ret void
928}
929
930declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i32>, i32, i32)
931declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
932
933define void @test_vsoxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
934; CHECK-LABEL: test_vsoxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32:
935; CHECK:       # %bb.0: # %entry
936; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
937; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
938; CHECK-NEXT:    ret
939entry:
940  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
941  ret void
942}
943
944define void @test_vsoxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
945; CHECK-LABEL: test_vsoxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32:
946; CHECK:       # %bb.0: # %entry
947; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
948; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
949; CHECK-NEXT:    ret
950entry:
951  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
952  ret void
953}
954
955declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i8>, i32, i32)
956declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
957
958define void @test_vsoxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
959; CHECK-LABEL: test_vsoxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8:
960; CHECK:       # %bb.0: # %entry
961; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
962; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
963; CHECK-NEXT:    ret
964entry:
965  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
966  ret void
967}
968
969define void @test_vsoxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
970; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8:
971; CHECK:       # %bb.0: # %entry
972; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
973; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
974; CHECK-NEXT:    ret
975entry:
976  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
977  ret void
978}
979
980declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i16>, i32, i32)
981declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
982
983define void @test_vsoxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
984; CHECK-LABEL: test_vsoxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16:
985; CHECK:       # %bb.0: # %entry
986; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
987; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
988; CHECK-NEXT:    ret
989entry:
990  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
991  ret void
992}
993
994define void @test_vsoxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
995; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16:
996; CHECK:       # %bb.0: # %entry
997; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
998; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
999; CHECK-NEXT:    ret
1000entry:
1001  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1002  ret void
1003}
1004
1005declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i32>, i32, i32)
1006declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
1007
1008define void @test_vsoxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
1009; CHECK-LABEL: test_vsoxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32:
1010; CHECK:       # %bb.0: # %entry
1011; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1012; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
1013; CHECK-NEXT:    ret
1014entry:
1015  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
1016  ret void
1017}
1018
1019define void @test_vsoxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1020; CHECK-LABEL: test_vsoxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32:
1021; CHECK:       # %bb.0: # %entry
1022; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1023; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
1024; CHECK-NEXT:    ret
1025entry:
1026  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1027  ret void
1028}
1029
1030declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 8 x i8>, i32, i32)
1031declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
1032
1033define void @test_vsoxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
1034; CHECK-LABEL: test_vsoxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8:
1035; CHECK:       # %bb.0: # %entry
1036; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1037; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
1038; CHECK-NEXT:    ret
1039entry:
1040  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
1041  ret void
1042}
1043
1044define void @test_vsoxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1045; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8:
1046; CHECK:       # %bb.0: # %entry
1047; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1048; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
1049; CHECK-NEXT:    ret
1050entry:
1051  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1052  ret void
1053}
1054
1055declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 8 x i16>, i32, i32)
1056declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
1057
1058define void @test_vsoxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
1059; CHECK-LABEL: test_vsoxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16:
1060; CHECK:       # %bb.0: # %entry
1061; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1062; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
1063; CHECK-NEXT:    ret
1064entry:
1065  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
1066  ret void
1067}
1068
1069define void @test_vsoxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1070; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16:
1071; CHECK:       # %bb.0: # %entry
1072; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1073; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
1074; CHECK-NEXT:    ret
1075entry:
1076  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1077  ret void
1078}
1079
1080declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 8 x i32>, i32, i32)
1081declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
1082
1083define void @test_vsoxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
1084; CHECK-LABEL: test_vsoxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32:
1085; CHECK:       # %bb.0: # %entry
1086; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1087; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
1088; CHECK-NEXT:    ret
1089entry:
1090  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
1091  ret void
1092}
1093
1094define void @test_vsoxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1095; CHECK-LABEL: test_vsoxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32:
1096; CHECK:       # %bb.0: # %entry
1097; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1098; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
1099; CHECK-NEXT:    ret
1100entry:
1101  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1102  ret void
1103}
1104
1105declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 16 x i8>, i32, i32)
1106declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i32, i32)
1107
1108define void @test_vsoxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl) {
1109; CHECK-LABEL: test_vsoxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8:
1110; CHECK:       # %bb.0: # %entry
1111; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
1112; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
1113; CHECK-NEXT:    ret
1114entry:
1115  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, i32 3)
1116  ret void
1117}
1118
1119define void @test_vsoxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 16 x i1> %mask) {
1120; CHECK-LABEL: test_vsoxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8:
1121; CHECK:       # %bb.0: # %entry
1122; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
1123; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
1124; CHECK-NEXT:    ret
1125entry:
1126  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
1127  ret void
1128}
1129
1130declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 16 x i16>, i32, i32)
1131declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i32, i32)
1132
1133define void @test_vsoxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl) {
1134; CHECK-LABEL: test_vsoxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16:
1135; CHECK:       # %bb.0: # %entry
1136; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
1137; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
1138; CHECK-NEXT:    ret
1139entry:
1140  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, i32 3)
1141  ret void
1142}
1143
1144define void @test_vsoxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 16 x i1> %mask) {
1145; CHECK-LABEL: test_vsoxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16:
1146; CHECK:       # %bb.0: # %entry
1147; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
1148; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
1149; CHECK-NEXT:    ret
1150entry:
1151  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
1152  ret void
1153}
1154
1155declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 16 x i32>, i32, i32)
1156declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i32, i32)
1157
1158define void @test_vsoxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl) {
1159; CHECK-LABEL: test_vsoxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32:
1160; CHECK:       # %bb.0: # %entry
1161; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
1162; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
1163; CHECK-NEXT:    ret
1164entry:
1165  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, i32 3)
1166  ret void
1167}
1168
1169define void @test_vsoxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 16 x i1> %mask) {
1170; CHECK-LABEL: test_vsoxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32:
1171; CHECK:       # %bb.0: # %entry
1172; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
1173; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
1174; CHECK-NEXT:    ret
1175entry:
1176  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 3)
1177  ret void
1178}
1179
1180declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr, <vscale x 1 x i8>, i32, i32)
1181declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
1182
1183define void @test_vsoxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
1184; CHECK-LABEL: test_vsoxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8:
1185; CHECK:       # %bb.0: # %entry
1186; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1187; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
1188; CHECK-NEXT:    ret
1189entry:
1190  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
1191  ret void
1192}
1193
1194define void @test_vsoxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1195; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8:
1196; CHECK:       # %bb.0: # %entry
1197; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1198; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
1199; CHECK-NEXT:    ret
1200entry:
1201  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1202  ret void
1203}
1204
1205declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr, <vscale x 1 x i16>, i32, i32)
1206declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
1207
1208define void @test_vsoxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
1209; CHECK-LABEL: test_vsoxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16:
1210; CHECK:       # %bb.0: # %entry
1211; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1212; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
1213; CHECK-NEXT:    ret
1214entry:
1215  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
1216  ret void
1217}
1218
1219define void @test_vsoxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1220; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16:
1221; CHECK:       # %bb.0: # %entry
1222; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1223; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
1224; CHECK-NEXT:    ret
1225entry:
1226  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1227  ret void
1228}
1229
1230declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr, <vscale x 1 x i32>, i32, i32)
1231declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
1232
1233define void @test_vsoxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
1234; CHECK-LABEL: test_vsoxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32:
1235; CHECK:       # %bb.0: # %entry
1236; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1237; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
1238; CHECK-NEXT:    ret
1239entry:
1240  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
1241  ret void
1242}
1243
1244define void @test_vsoxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1245; CHECK-LABEL: test_vsoxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32:
1246; CHECK:       # %bb.0: # %entry
1247; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1248; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
1249; CHECK-NEXT:    ret
1250entry:
1251  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1252  ret void
1253}
1254
1255declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i8>, i32, i32)
1256declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
1257
1258define void @test_vsoxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
1259; CHECK-LABEL: test_vsoxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8:
1260; CHECK:       # %bb.0: # %entry
1261; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1262; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
1263; CHECK-NEXT:    ret
1264entry:
1265  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
1266  ret void
1267}
1268
1269define void @test_vsoxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1270; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8:
1271; CHECK:       # %bb.0: # %entry
1272; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1273; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
1274; CHECK-NEXT:    ret
1275entry:
1276  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1277  ret void
1278}
1279
1280declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i16>, i32, i32)
1281declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
1282
1283define void @test_vsoxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
1284; CHECK-LABEL: test_vsoxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16:
1285; CHECK:       # %bb.0: # %entry
1286; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1287; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
1288; CHECK-NEXT:    ret
1289entry:
1290  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
1291  ret void
1292}
1293
1294define void @test_vsoxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1295; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16:
1296; CHECK:       # %bb.0: # %entry
1297; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1298; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
1299; CHECK-NEXT:    ret
1300entry:
1301  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1302  ret void
1303}
1304
1305declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i32>, i32, i32)
1306declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
1307
1308define void @test_vsoxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
1309; CHECK-LABEL: test_vsoxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32:
1310; CHECK:       # %bb.0: # %entry
1311; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1312; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
1313; CHECK-NEXT:    ret
1314entry:
1315  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
1316  ret void
1317}
1318
1319define void @test_vsoxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1320; CHECK-LABEL: test_vsoxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32:
1321; CHECK:       # %bb.0: # %entry
1322; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1323; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
1324; CHECK-NEXT:    ret
1325entry:
1326  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1327  ret void
1328}
1329
1330declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i8>, i32, i32)
1331declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
1332
1333define void @test_vsoxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
1334; CHECK-LABEL: test_vsoxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8:
1335; CHECK:       # %bb.0: # %entry
1336; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1337; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
1338; CHECK-NEXT:    ret
1339entry:
1340  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
1341  ret void
1342}
1343
1344define void @test_vsoxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1345; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8:
1346; CHECK:       # %bb.0: # %entry
1347; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1348; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
1349; CHECK-NEXT:    ret
1350entry:
1351  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1352  ret void
1353}
1354
1355declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i16>, i32, i32)
1356declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
1357
1358define void @test_vsoxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
1359; CHECK-LABEL: test_vsoxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16:
1360; CHECK:       # %bb.0: # %entry
1361; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1362; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
1363; CHECK-NEXT:    ret
1364entry:
1365  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
1366  ret void
1367}
1368
1369define void @test_vsoxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1370; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16:
1371; CHECK:       # %bb.0: # %entry
1372; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1373; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
1374; CHECK-NEXT:    ret
1375entry:
1376  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1377  ret void
1378}
1379
1380declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i32>, i32, i32)
1381declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
1382
1383define void @test_vsoxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
1384; CHECK-LABEL: test_vsoxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32:
1385; CHECK:       # %bb.0: # %entry
1386; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1387; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14
1388; CHECK-NEXT:    ret
1389entry:
1390  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
1391  ret void
1392}
1393
1394define void @test_vsoxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1395; CHECK-LABEL: test_vsoxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32:
1396; CHECK:       # %bb.0: # %entry
1397; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1398; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14, v0.t
1399; CHECK-NEXT:    ret
1400entry:
1401  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1402  ret void
1403}
1404
1405declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 8 x i8>, i32, i32)
1406declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
1407
1408define void @test_vsoxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
1409; CHECK-LABEL: test_vsoxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8:
1410; CHECK:       # %bb.0: # %entry
1411; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1412; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
1413; CHECK-NEXT:    ret
1414entry:
1415  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
1416  ret void
1417}
1418
1419define void @test_vsoxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1420; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8:
1421; CHECK:       # %bb.0: # %entry
1422; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1423; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
1424; CHECK-NEXT:    ret
1425entry:
1426  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1427  ret void
1428}
1429
1430declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 8 x i16>, i32, i32)
1431declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
1432
1433define void @test_vsoxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
1434; CHECK-LABEL: test_vsoxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16:
1435; CHECK:       # %bb.0: # %entry
1436; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1437; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v14
1438; CHECK-NEXT:    ret
1439entry:
1440  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
1441  ret void
1442}
1443
1444define void @test_vsoxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1445; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16:
1446; CHECK:       # %bb.0: # %entry
1447; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1448; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v14, v0.t
1449; CHECK-NEXT:    ret
1450entry:
1451  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1452  ret void
1453}
1454
1455declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 8 x i32>, i32, i32)
1456declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
1457
1458define void @test_vsoxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
1459; CHECK-LABEL: test_vsoxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32:
1460; CHECK:       # %bb.0: # %entry
1461; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1462; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v16
1463; CHECK-NEXT:    ret
1464entry:
1465  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
1466  ret void
1467}
1468
1469define void @test_vsoxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1470; CHECK-LABEL: test_vsoxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32:
1471; CHECK:       # %bb.0: # %entry
1472; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1473; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v16, v0.t
1474; CHECK-NEXT:    ret
1475entry:
1476  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1477  ret void
1478}
1479
1480declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr, <vscale x 1 x i8>, i32, i32)
1481declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
1482
1483define void @test_vsoxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
1484; CHECK-LABEL: test_vsoxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8:
1485; CHECK:       # %bb.0: # %entry
1486; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1487; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
1488; CHECK-NEXT:    ret
1489entry:
1490  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
1491  ret void
1492}
1493
1494define void @test_vsoxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1495; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8:
1496; CHECK:       # %bb.0: # %entry
1497; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1498; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
1499; CHECK-NEXT:    ret
1500entry:
1501  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1502  ret void
1503}
1504
1505declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr, <vscale x 1 x i16>, i32, i32)
1506declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
1507
1508define void @test_vsoxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
1509; CHECK-LABEL: test_vsoxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16:
1510; CHECK:       # %bb.0: # %entry
1511; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1512; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
1513; CHECK-NEXT:    ret
1514entry:
1515  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
1516  ret void
1517}
1518
1519define void @test_vsoxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1520; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16:
1521; CHECK:       # %bb.0: # %entry
1522; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1523; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
1524; CHECK-NEXT:    ret
1525entry:
1526  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1527  ret void
1528}
1529
1530declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr, <vscale x 1 x i32>, i32, i32)
1531declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
1532
1533define void @test_vsoxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
1534; CHECK-LABEL: test_vsoxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32:
1535; CHECK:       # %bb.0: # %entry
1536; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1537; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
1538; CHECK-NEXT:    ret
1539entry:
1540  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
1541  ret void
1542}
1543
1544define void @test_vsoxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1545; CHECK-LABEL: test_vsoxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32:
1546; CHECK:       # %bb.0: # %entry
1547; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1548; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
1549; CHECK-NEXT:    ret
1550entry:
1551  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1552  ret void
1553}
1554
1555declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i8>, i32, i32)
1556declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
1557
1558define void @test_vsoxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
1559; CHECK-LABEL: test_vsoxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8:
1560; CHECK:       # %bb.0: # %entry
1561; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1562; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
1563; CHECK-NEXT:    ret
1564entry:
1565  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
1566  ret void
1567}
1568
1569define void @test_vsoxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1570; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8:
1571; CHECK:       # %bb.0: # %entry
1572; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1573; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
1574; CHECK-NEXT:    ret
1575entry:
1576  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1577  ret void
1578}
1579
1580declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i16>, i32, i32)
1581declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
1582
1583define void @test_vsoxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
1584; CHECK-LABEL: test_vsoxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16:
1585; CHECK:       # %bb.0: # %entry
1586; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1587; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
1588; CHECK-NEXT:    ret
1589entry:
1590  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
1591  ret void
1592}
1593
1594define void @test_vsoxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1595; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16:
1596; CHECK:       # %bb.0: # %entry
1597; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1598; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
1599; CHECK-NEXT:    ret
1600entry:
1601  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1602  ret void
1603}
1604
1605declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i32>, i32, i32)
1606declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
1607
1608define void @test_vsoxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
1609; CHECK-LABEL: test_vsoxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32:
1610; CHECK:       # %bb.0: # %entry
1611; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1612; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
1613; CHECK-NEXT:    ret
1614entry:
1615  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
1616  ret void
1617}
1618
1619define void @test_vsoxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1620; CHECK-LABEL: test_vsoxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32:
1621; CHECK:       # %bb.0: # %entry
1622; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1623; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
1624; CHECK-NEXT:    ret
1625entry:
1626  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1627  ret void
1628}
1629
1630declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i8>, i32, i32)
1631declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
1632
1633define void @test_vsoxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
1634; CHECK-LABEL: test_vsoxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8:
1635; CHECK:       # %bb.0: # %entry
1636; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1637; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
1638; CHECK-NEXT:    ret
1639entry:
1640  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
1641  ret void
1642}
1643
1644define void @test_vsoxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1645; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8:
1646; CHECK:       # %bb.0: # %entry
1647; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1648; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
1649; CHECK-NEXT:    ret
1650entry:
1651  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1652  ret void
1653}
1654
1655declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i16>, i32, i32)
1656declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
1657
1658define void @test_vsoxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
1659; CHECK-LABEL: test_vsoxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16:
1660; CHECK:       # %bb.0: # %entry
1661; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1662; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
1663; CHECK-NEXT:    ret
1664entry:
1665  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
1666  ret void
1667}
1668
1669define void @test_vsoxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1670; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16:
1671; CHECK:       # %bb.0: # %entry
1672; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1673; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
1674; CHECK-NEXT:    ret
1675entry:
1676  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1677  ret void
1678}
1679
1680declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i32>, i32, i32)
1681declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
1682
1683define void @test_vsoxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
1684; CHECK-LABEL: test_vsoxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32:
1685; CHECK:       # %bb.0: # %entry
1686; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1687; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
1688; CHECK-NEXT:    ret
1689entry:
1690  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
1691  ret void
1692}
1693
1694define void @test_vsoxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1695; CHECK-LABEL: test_vsoxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32:
1696; CHECK:       # %bb.0: # %entry
1697; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1698; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
1699; CHECK-NEXT:    ret
1700entry:
1701  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1702  ret void
1703}
1704
1705declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 8 x i8>, i32, i32)
1706declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
1707
1708define void @test_vsoxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
1709; CHECK-LABEL: test_vsoxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8:
1710; CHECK:       # %bb.0: # %entry
1711; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1712; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
1713; CHECK-NEXT:    ret
1714entry:
1715  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
1716  ret void
1717}
1718
1719define void @test_vsoxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1720; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8:
1721; CHECK:       # %bb.0: # %entry
1722; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1723; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
1724; CHECK-NEXT:    ret
1725entry:
1726  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1727  ret void
1728}
1729
1730declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 8 x i16>, i32, i32)
1731declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
1732
1733define void @test_vsoxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
1734; CHECK-LABEL: test_vsoxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16:
1735; CHECK:       # %bb.0: # %entry
1736; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1737; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
1738; CHECK-NEXT:    ret
1739entry:
1740  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
1741  ret void
1742}
1743
1744define void @test_vsoxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1745; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16:
1746; CHECK:       # %bb.0: # %entry
1747; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1748; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
1749; CHECK-NEXT:    ret
1750entry:
1751  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1752  ret void
1753}
1754
1755declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 8 x i32>, i32, i32)
1756declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
1757
1758define void @test_vsoxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
1759; CHECK-LABEL: test_vsoxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32:
1760; CHECK:       # %bb.0: # %entry
1761; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1762; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v16
1763; CHECK-NEXT:    ret
1764entry:
1765  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
1766  ret void
1767}
1768
1769define void @test_vsoxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
1770; CHECK-LABEL: test_vsoxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32:
1771; CHECK:       # %bb.0: # %entry
1772; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
1773; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v16, v0.t
1774; CHECK-NEXT:    ret
1775entry:
1776  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
1777  ret void
1778}
1779
1780declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr, <vscale x 1 x i8>, i32, i32)
1781declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
1782
1783define void @test_vsoxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
1784; CHECK-LABEL: test_vsoxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8:
1785; CHECK:       # %bb.0: # %entry
1786; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1787; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
1788; CHECK-NEXT:    ret
1789entry:
1790  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
1791  ret void
1792}
1793
1794define void @test_vsoxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1795; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8:
1796; CHECK:       # %bb.0: # %entry
1797; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1798; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
1799; CHECK-NEXT:    ret
1800entry:
1801  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1802  ret void
1803}
1804
1805declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr, <vscale x 1 x i16>, i32, i32)
1806declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
1807
1808define void @test_vsoxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
1809; CHECK-LABEL: test_vsoxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16:
1810; CHECK:       # %bb.0: # %entry
1811; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1812; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
1813; CHECK-NEXT:    ret
1814entry:
1815  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
1816  ret void
1817}
1818
1819define void @test_vsoxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1820; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16:
1821; CHECK:       # %bb.0: # %entry
1822; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1823; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
1824; CHECK-NEXT:    ret
1825entry:
1826  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1827  ret void
1828}
1829
1830declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr, <vscale x 1 x i32>, i32, i32)
1831declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
1832
1833define void @test_vsoxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
1834; CHECK-LABEL: test_vsoxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32:
1835; CHECK:       # %bb.0: # %entry
1836; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1837; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
1838; CHECK-NEXT:    ret
1839entry:
1840  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
1841  ret void
1842}
1843
1844define void @test_vsoxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
1845; CHECK-LABEL: test_vsoxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32:
1846; CHECK:       # %bb.0: # %entry
1847; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
1848; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
1849; CHECK-NEXT:    ret
1850entry:
1851  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
1852  ret void
1853}
1854
1855declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i8>, i32, i32)
1856declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
1857
1858define void @test_vsoxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
1859; CHECK-LABEL: test_vsoxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8:
1860; CHECK:       # %bb.0: # %entry
1861; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1862; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
1863; CHECK-NEXT:    ret
1864entry:
1865  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
1866  ret void
1867}
1868
1869define void @test_vsoxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1870; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8:
1871; CHECK:       # %bb.0: # %entry
1872; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1873; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
1874; CHECK-NEXT:    ret
1875entry:
1876  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1877  ret void
1878}
1879
1880declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i16>, i32, i32)
1881declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
1882
1883define void @test_vsoxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
1884; CHECK-LABEL: test_vsoxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16:
1885; CHECK:       # %bb.0: # %entry
1886; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1887; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
1888; CHECK-NEXT:    ret
1889entry:
1890  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
1891  ret void
1892}
1893
1894define void @test_vsoxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1895; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16:
1896; CHECK:       # %bb.0: # %entry
1897; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1898; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
1899; CHECK-NEXT:    ret
1900entry:
1901  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1902  ret void
1903}
1904
1905declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i32>, i32, i32)
1906declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
1907
1908define void @test_vsoxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
1909; CHECK-LABEL: test_vsoxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32:
1910; CHECK:       # %bb.0: # %entry
1911; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1912; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
1913; CHECK-NEXT:    ret
1914entry:
1915  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
1916  ret void
1917}
1918
1919define void @test_vsoxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
1920; CHECK-LABEL: test_vsoxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32:
1921; CHECK:       # %bb.0: # %entry
1922; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
1923; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
1924; CHECK-NEXT:    ret
1925entry:
1926  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
1927  ret void
1928}
1929
1930declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i8>, i32, i32)
1931declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
1932
1933define void @test_vsoxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
1934; CHECK-LABEL: test_vsoxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8:
1935; CHECK:       # %bb.0: # %entry
1936; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1937; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
1938; CHECK-NEXT:    ret
1939entry:
1940  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
1941  ret void
1942}
1943
1944define void @test_vsoxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1945; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8:
1946; CHECK:       # %bb.0: # %entry
1947; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1948; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
1949; CHECK-NEXT:    ret
1950entry:
1951  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1952  ret void
1953}
1954
1955declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i16>, i32, i32)
1956declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
1957
1958define void @test_vsoxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
1959; CHECK-LABEL: test_vsoxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16:
1960; CHECK:       # %bb.0: # %entry
1961; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1962; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
1963; CHECK-NEXT:    ret
1964entry:
1965  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
1966  ret void
1967}
1968
1969define void @test_vsoxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1970; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16:
1971; CHECK:       # %bb.0: # %entry
1972; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1973; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
1974; CHECK-NEXT:    ret
1975entry:
1976  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
1977  ret void
1978}
1979
1980declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i32>, i32, i32)
1981declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
1982
1983define void @test_vsoxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
1984; CHECK-LABEL: test_vsoxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32:
1985; CHECK:       # %bb.0: # %entry
1986; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1987; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16
1988; CHECK-NEXT:    ret
1989entry:
1990  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
1991  ret void
1992}
1993
1994define void @test_vsoxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
1995; CHECK-LABEL: test_vsoxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32:
1996; CHECK:       # %bb.0: # %entry
1997; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
1998; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16, v0.t
1999; CHECK-NEXT:    ret
2000entry:
2001  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
2002  ret void
2003}
2004
2005declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 8 x i8>, i32, i32)
2006declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
2007
2008define void @test_vsoxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
2009; CHECK-LABEL: test_vsoxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8:
2010; CHECK:       # %bb.0: # %entry
2011; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2012; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
2013; CHECK-NEXT:    ret
2014entry:
2015  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
2016  ret void
2017}
2018
2019define void @test_vsoxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2020; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8:
2021; CHECK:       # %bb.0: # %entry
2022; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2023; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
2024; CHECK-NEXT:    ret
2025entry:
2026  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
2027  ret void
2028}
2029
2030declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 8 x i16>, i32, i32)
2031declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
2032
2033define void @test_vsoxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
2034; CHECK-LABEL: test_vsoxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16:
2035; CHECK:       # %bb.0: # %entry
2036; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2037; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v16
2038; CHECK-NEXT:    ret
2039entry:
2040  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
2041  ret void
2042}
2043
2044define void @test_vsoxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2045; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16:
2046; CHECK:       # %bb.0: # %entry
2047; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2048; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v16, v0.t
2049; CHECK-NEXT:    ret
2050entry:
2051  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
2052  ret void
2053}
2054
2055declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 8 x i32>, i32, i32)
2056declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
2057
2058define void @test_vsoxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
2059; CHECK-LABEL: test_vsoxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32:
2060; CHECK:       # %bb.0: # %entry
2061; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2062; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16
2063; CHECK-NEXT:    ret
2064entry:
2065  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
2066  ret void
2067}
2068
2069define void @test_vsoxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2070; CHECK-LABEL: test_vsoxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32:
2071; CHECK:       # %bb.0: # %entry
2072; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2073; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16, v0.t
2074; CHECK-NEXT:    ret
2075entry:
2076  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
2077  ret void
2078}
2079
2080declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr, <vscale x 1 x i8>, i32, i32)
2081declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
2082
2083define void @test_vsoxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
2084; CHECK-LABEL: test_vsoxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8:
2085; CHECK:       # %bb.0: # %entry
2086; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
2087; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
2088; CHECK-NEXT:    ret
2089entry:
2090  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 3)
2091  ret void
2092}
2093
2094define void @test_vsoxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2095; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8:
2096; CHECK:       # %bb.0: # %entry
2097; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
2098; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
2099; CHECK-NEXT:    ret
2100entry:
2101  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
2102  ret void
2103}
2104
2105declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr, <vscale x 1 x i16>, i32, i32)
2106declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
2107
2108define void @test_vsoxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
2109; CHECK-LABEL: test_vsoxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16:
2110; CHECK:       # %bb.0: # %entry
2111; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
2112; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
2113; CHECK-NEXT:    ret
2114entry:
2115  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 3)
2116  ret void
2117}
2118
2119define void @test_vsoxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2120; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16:
2121; CHECK:       # %bb.0: # %entry
2122; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
2123; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
2124; CHECK-NEXT:    ret
2125entry:
2126  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
2127  ret void
2128}
2129
2130declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr, <vscale x 1 x i32>, i32, i32)
2131declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
2132
2133define void @test_vsoxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
2134; CHECK-LABEL: test_vsoxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32:
2135; CHECK:       # %bb.0: # %entry
2136; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
2137; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
2138; CHECK-NEXT:    ret
2139entry:
2140  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 3)
2141  ret void
2142}
2143
2144define void @test_vsoxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2145; CHECK-LABEL: test_vsoxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32:
2146; CHECK:       # %bb.0: # %entry
2147; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
2148; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
2149; CHECK-NEXT:    ret
2150entry:
2151  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 3)
2152  ret void
2153}
2154
2155declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i8>, i32, i32)
2156declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
2157
2158define void @test_vsoxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
2159; CHECK-LABEL: test_vsoxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8:
2160; CHECK:       # %bb.0: # %entry
2161; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
2162; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
2163; CHECK-NEXT:    ret
2164entry:
2165  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 3)
2166  ret void
2167}
2168
2169define void @test_vsoxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2170; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8:
2171; CHECK:       # %bb.0: # %entry
2172; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
2173; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
2174; CHECK-NEXT:    ret
2175entry:
2176  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
2177  ret void
2178}
2179
2180declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i16>, i32, i32)
2181declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
2182
2183define void @test_vsoxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
2184; CHECK-LABEL: test_vsoxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16:
2185; CHECK:       # %bb.0: # %entry
2186; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
2187; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
2188; CHECK-NEXT:    ret
2189entry:
2190  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 3)
2191  ret void
2192}
2193
2194define void @test_vsoxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2195; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16:
2196; CHECK:       # %bb.0: # %entry
2197; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
2198; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
2199; CHECK-NEXT:    ret
2200entry:
2201  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
2202  ret void
2203}
2204
2205declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i32>, i32, i32)
2206declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
2207
2208define void @test_vsoxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
2209; CHECK-LABEL: test_vsoxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32:
2210; CHECK:       # %bb.0: # %entry
2211; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
2212; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
2213; CHECK-NEXT:    ret
2214entry:
2215  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 3)
2216  ret void
2217}
2218
2219define void @test_vsoxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2220; CHECK-LABEL: test_vsoxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32:
2221; CHECK:       # %bb.0: # %entry
2222; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
2223; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
2224; CHECK-NEXT:    ret
2225entry:
2226  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 3)
2227  ret void
2228}
2229
2230declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i8>, i32, i32)
2231declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
2232
2233define void @test_vsoxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
2234; CHECK-LABEL: test_vsoxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8:
2235; CHECK:       # %bb.0: # %entry
2236; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
2237; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
2238; CHECK-NEXT:    ret
2239entry:
2240  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 3)
2241  ret void
2242}
2243
2244define void @test_vsoxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2245; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8:
2246; CHECK:       # %bb.0: # %entry
2247; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
2248; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
2249; CHECK-NEXT:    ret
2250entry:
2251  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
2252  ret void
2253}
2254
2255declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i16>, i32, i32)
2256declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
2257
2258define void @test_vsoxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
2259; CHECK-LABEL: test_vsoxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16:
2260; CHECK:       # %bb.0: # %entry
2261; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
2262; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
2263; CHECK-NEXT:    ret
2264entry:
2265  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 3)
2266  ret void
2267}
2268
2269define void @test_vsoxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2270; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16:
2271; CHECK:       # %bb.0: # %entry
2272; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
2273; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
2274; CHECK-NEXT:    ret
2275entry:
2276  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
2277  ret void
2278}
2279
2280declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i32>, i32, i32)
2281declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
2282
2283define void @test_vsoxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
2284; CHECK-LABEL: test_vsoxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32:
2285; CHECK:       # %bb.0: # %entry
2286; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
2287; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
2288; CHECK-NEXT:    ret
2289entry:
2290  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 3)
2291  ret void
2292}
2293
2294define void @test_vsoxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2295; CHECK-LABEL: test_vsoxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32:
2296; CHECK:       # %bb.0: # %entry
2297; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
2298; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
2299; CHECK-NEXT:    ret
2300entry:
2301  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 3)
2302  ret void
2303}
2304
2305declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 8 x i8>, i32, i32)
2306declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
2307
2308define void @test_vsoxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
2309; CHECK-LABEL: test_vsoxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8:
2310; CHECK:       # %bb.0: # %entry
2311; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2312; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
2313; CHECK-NEXT:    ret
2314entry:
2315  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 3)
2316  ret void
2317}
2318
2319define void @test_vsoxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2320; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8:
2321; CHECK:       # %bb.0: # %entry
2322; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2323; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
2324; CHECK-NEXT:    ret
2325entry:
2326  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
2327  ret void
2328}
2329
2330declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 8 x i16>, i32, i32)
2331declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
2332
2333define void @test_vsoxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
2334; CHECK-LABEL: test_vsoxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16:
2335; CHECK:       # %bb.0: # %entry
2336; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2337; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
2338; CHECK-NEXT:    ret
2339entry:
2340  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 3)
2341  ret void
2342}
2343
2344define void @test_vsoxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2345; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16:
2346; CHECK:       # %bb.0: # %entry
2347; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2348; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
2349; CHECK-NEXT:    ret
2350entry:
2351  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
2352  ret void
2353}
2354
2355declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 8 x i32>, i32, i32)
2356declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
2357
2358define void @test_vsoxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
2359; CHECK-LABEL: test_vsoxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32:
2360; CHECK:       # %bb.0: # %entry
2361; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2362; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
2363; CHECK-NEXT:    ret
2364entry:
2365  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 3)
2366  ret void
2367}
2368
2369define void @test_vsoxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2370; CHECK-LABEL: test_vsoxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32:
2371; CHECK:       # %bb.0: # %entry
2372; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
2373; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
2374; CHECK-NEXT:    ret
2375entry:
2376  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 3)
2377  ret void
2378}
2379
2380declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 1 x i8>, i32, i32)
2381declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
2382
2383define void @test_vsoxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
2384; CHECK-LABEL: test_vsoxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:
2385; CHECK:       # %bb.0: # %entry
2386; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2387; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
2388; CHECK-NEXT:    ret
2389entry:
2390  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
2391  ret void
2392}
2393
2394define void @test_vsoxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2395; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:
2396; CHECK:       # %bb.0: # %entry
2397; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2398; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
2399; CHECK-NEXT:    ret
2400entry:
2401  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
2402  ret void
2403}
2404
2405declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 1 x i16>, i32, i32)
2406declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
2407
2408define void @test_vsoxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
2409; CHECK-LABEL: test_vsoxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:
2410; CHECK:       # %bb.0: # %entry
2411; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2412; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
2413; CHECK-NEXT:    ret
2414entry:
2415  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
2416  ret void
2417}
2418
2419define void @test_vsoxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2420; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:
2421; CHECK:       # %bb.0: # %entry
2422; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2423; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
2424; CHECK-NEXT:    ret
2425entry:
2426  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
2427  ret void
2428}
2429
2430declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 1 x i32>, i32, i32)
2431declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
2432
2433define void @test_vsoxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
2434; CHECK-LABEL: test_vsoxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:
2435; CHECK:       # %bb.0: # %entry
2436; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2437; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
2438; CHECK-NEXT:    ret
2439entry:
2440  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
2441  ret void
2442}
2443
2444define void @test_vsoxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2445; CHECK-LABEL: test_vsoxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:
2446; CHECK:       # %bb.0: # %entry
2447; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2448; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
2449; CHECK-NEXT:    ret
2450entry:
2451  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
2452  ret void
2453}
2454
2455declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 2 x i8>, i32, i32)
2456declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
2457
2458define void @test_vsoxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
2459; CHECK-LABEL: test_vsoxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:
2460; CHECK:       # %bb.0: # %entry
2461; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2462; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
2463; CHECK-NEXT:    ret
2464entry:
2465  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
2466  ret void
2467}
2468
2469define void @test_vsoxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2470; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:
2471; CHECK:       # %bb.0: # %entry
2472; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2473; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
2474; CHECK-NEXT:    ret
2475entry:
2476  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
2477  ret void
2478}
2479
2480declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 2 x i16>, i32, i32)
2481declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
2482
2483define void @test_vsoxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
2484; CHECK-LABEL: test_vsoxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:
2485; CHECK:       # %bb.0: # %entry
2486; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2487; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
2488; CHECK-NEXT:    ret
2489entry:
2490  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
2491  ret void
2492}
2493
2494define void @test_vsoxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2495; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:
2496; CHECK:       # %bb.0: # %entry
2497; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2498; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
2499; CHECK-NEXT:    ret
2500entry:
2501  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
2502  ret void
2503}
2504
2505declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 2 x i32>, i32, i32)
2506declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
2507
2508define void @test_vsoxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
2509; CHECK-LABEL: test_vsoxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:
2510; CHECK:       # %bb.0: # %entry
2511; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2512; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
2513; CHECK-NEXT:    ret
2514entry:
2515  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
2516  ret void
2517}
2518
2519define void @test_vsoxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2520; CHECK-LABEL: test_vsoxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:
2521; CHECK:       # %bb.0: # %entry
2522; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2523; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
2524; CHECK-NEXT:    ret
2525entry:
2526  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
2527  ret void
2528}
2529
2530declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 4 x i8>, i32, i32)
2531declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
2532
2533define void @test_vsoxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
2534; CHECK-LABEL: test_vsoxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:
2535; CHECK:       # %bb.0: # %entry
2536; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2537; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
2538; CHECK-NEXT:    ret
2539entry:
2540  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
2541  ret void
2542}
2543
2544define void @test_vsoxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2545; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:
2546; CHECK:       # %bb.0: # %entry
2547; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2548; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
2549; CHECK-NEXT:    ret
2550entry:
2551  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
2552  ret void
2553}
2554
2555declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 4 x i16>, i32, i32)
2556declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
2557
2558define void @test_vsoxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
2559; CHECK-LABEL: test_vsoxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:
2560; CHECK:       # %bb.0: # %entry
2561; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2562; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
2563; CHECK-NEXT:    ret
2564entry:
2565  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
2566  ret void
2567}
2568
2569define void @test_vsoxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2570; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:
2571; CHECK:       # %bb.0: # %entry
2572; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2573; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
2574; CHECK-NEXT:    ret
2575entry:
2576  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
2577  ret void
2578}
2579
2580declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 4 x i32>, i32, i32)
2581declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
2582
2583define void @test_vsoxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
2584; CHECK-LABEL: test_vsoxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:
2585; CHECK:       # %bb.0: # %entry
2586; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2587; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
2588; CHECK-NEXT:    ret
2589entry:
2590  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
2591  ret void
2592}
2593
2594define void @test_vsoxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2595; CHECK-LABEL: test_vsoxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:
2596; CHECK:       # %bb.0: # %entry
2597; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2598; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
2599; CHECK-NEXT:    ret
2600entry:
2601  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
2602  ret void
2603}
2604
2605declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 8 x i8>, i32, i32)
2606declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
2607
2608define void @test_vsoxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
2609; CHECK-LABEL: test_vsoxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:
2610; CHECK:       # %bb.0: # %entry
2611; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2612; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
2613; CHECK-NEXT:    ret
2614entry:
2615  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
2616  ret void
2617}
2618
2619define void @test_vsoxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2620; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:
2621; CHECK:       # %bb.0: # %entry
2622; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2623; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
2624; CHECK-NEXT:    ret
2625entry:
2626  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
2627  ret void
2628}
2629
2630declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 8 x i16>, i32, i32)
2631declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
2632
2633define void @test_vsoxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
2634; CHECK-LABEL: test_vsoxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:
2635; CHECK:       # %bb.0: # %entry
2636; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2637; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
2638; CHECK-NEXT:    ret
2639entry:
2640  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
2641  ret void
2642}
2643
2644define void @test_vsoxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2645; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:
2646; CHECK:       # %bb.0: # %entry
2647; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2648; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
2649; CHECK-NEXT:    ret
2650entry:
2651  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
2652  ret void
2653}
2654
2655declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 8 x i32>, i32, i32)
2656declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
2657
2658define void @test_vsoxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
2659; CHECK-LABEL: test_vsoxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:
2660; CHECK:       # %bb.0: # %entry
2661; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2662; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
2663; CHECK-NEXT:    ret
2664entry:
2665  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
2666  ret void
2667}
2668
2669define void @test_vsoxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2670; CHECK-LABEL: test_vsoxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:
2671; CHECK:       # %bb.0: # %entry
2672; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2673; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
2674; CHECK-NEXT:    ret
2675entry:
2676  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
2677  ret void
2678}
2679
2680declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i8>, i32, i32)
2681declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i8>, <vscale x 16 x i1>, i32, i32)
2682
2683define void @test_vsoxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl) {
2684; CHECK-LABEL: test_vsoxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:
2685; CHECK:       # %bb.0: # %entry
2686; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2687; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
2688; CHECK-NEXT:    ret
2689entry:
2690  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, i32 4)
2691  ret void
2692}
2693
2694define void @test_vsoxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 16 x i1> %mask) {
2695; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:
2696; CHECK:       # %bb.0: # %entry
2697; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2698; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
2699; CHECK-NEXT:    ret
2700entry:
2701  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
2702  ret void
2703}
2704
2705declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i16>, i32, i32)
2706declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i16>, <vscale x 16 x i1>, i32, i32)
2707
2708define void @test_vsoxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl) {
2709; CHECK-LABEL: test_vsoxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:
2710; CHECK:       # %bb.0: # %entry
2711; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2712; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
2713; CHECK-NEXT:    ret
2714entry:
2715  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, i32 4)
2716  ret void
2717}
2718
2719define void @test_vsoxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 16 x i1> %mask) {
2720; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:
2721; CHECK:       # %bb.0: # %entry
2722; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2723; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
2724; CHECK-NEXT:    ret
2725entry:
2726  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
2727  ret void
2728}
2729
2730declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i32>, i32, i32)
2731declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 16 x i32>, <vscale x 16 x i1>, i32, i32)
2732
2733define void @test_vsoxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl) {
2734; CHECK-LABEL: test_vsoxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:
2735; CHECK:       # %bb.0: # %entry
2736; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2737; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
2738; CHECK-NEXT:    ret
2739entry:
2740  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, i32 4)
2741  ret void
2742}
2743
2744define void @test_vsoxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 16 x i1> %mask) {
2745; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:
2746; CHECK:       # %bb.0: # %entry
2747; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2748; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
2749; CHECK-NEXT:    ret
2750entry:
2751  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
2752  ret void
2753}
2754
2755declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 1 x i8>, i32, i32)
2756declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
2757
2758define void @test_vsoxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
2759; CHECK-LABEL: test_vsoxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:
2760; CHECK:       # %bb.0: # %entry
2761; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2762; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
2763; CHECK-NEXT:    ret
2764entry:
2765  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
2766  ret void
2767}
2768
2769define void @test_vsoxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2770; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:
2771; CHECK:       # %bb.0: # %entry
2772; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2773; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
2774; CHECK-NEXT:    ret
2775entry:
2776  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
2777  ret void
2778}
2779
2780declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 1 x i16>, i32, i32)
2781declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
2782
2783define void @test_vsoxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
2784; CHECK-LABEL: test_vsoxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:
2785; CHECK:       # %bb.0: # %entry
2786; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2787; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
2788; CHECK-NEXT:    ret
2789entry:
2790  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
2791  ret void
2792}
2793
2794define void @test_vsoxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2795; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:
2796; CHECK:       # %bb.0: # %entry
2797; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2798; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
2799; CHECK-NEXT:    ret
2800entry:
2801  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
2802  ret void
2803}
2804
2805declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 1 x i32>, i32, i32)
2806declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
2807
2808define void @test_vsoxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
2809; CHECK-LABEL: test_vsoxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:
2810; CHECK:       # %bb.0: # %entry
2811; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2812; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
2813; CHECK-NEXT:    ret
2814entry:
2815  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
2816  ret void
2817}
2818
2819define void @test_vsoxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
2820; CHECK-LABEL: test_vsoxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:
2821; CHECK:       # %bb.0: # %entry
2822; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
2823; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
2824; CHECK-NEXT:    ret
2825entry:
2826  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
2827  ret void
2828}
2829
2830declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 2 x i8>, i32, i32)
2831declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
2832
2833define void @test_vsoxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
2834; CHECK-LABEL: test_vsoxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:
2835; CHECK:       # %bb.0: # %entry
2836; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2837; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
2838; CHECK-NEXT:    ret
2839entry:
2840  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
2841  ret void
2842}
2843
2844define void @test_vsoxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2845; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:
2846; CHECK:       # %bb.0: # %entry
2847; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2848; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
2849; CHECK-NEXT:    ret
2850entry:
2851  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
2852  ret void
2853}
2854
2855declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 2 x i16>, i32, i32)
2856declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
2857
2858define void @test_vsoxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
2859; CHECK-LABEL: test_vsoxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:
2860; CHECK:       # %bb.0: # %entry
2861; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2862; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
2863; CHECK-NEXT:    ret
2864entry:
2865  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
2866  ret void
2867}
2868
2869define void @test_vsoxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2870; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:
2871; CHECK:       # %bb.0: # %entry
2872; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2873; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
2874; CHECK-NEXT:    ret
2875entry:
2876  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
2877  ret void
2878}
2879
2880declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 2 x i32>, i32, i32)
2881declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
2882
2883define void @test_vsoxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
2884; CHECK-LABEL: test_vsoxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:
2885; CHECK:       # %bb.0: # %entry
2886; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2887; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
2888; CHECK-NEXT:    ret
2889entry:
2890  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
2891  ret void
2892}
2893
2894define void @test_vsoxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
2895; CHECK-LABEL: test_vsoxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:
2896; CHECK:       # %bb.0: # %entry
2897; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
2898; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
2899; CHECK-NEXT:    ret
2900entry:
2901  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
2902  ret void
2903}
2904
2905declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 4 x i8>, i32, i32)
2906declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
2907
2908define void @test_vsoxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
2909; CHECK-LABEL: test_vsoxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:
2910; CHECK:       # %bb.0: # %entry
2911; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2912; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
2913; CHECK-NEXT:    ret
2914entry:
2915  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
2916  ret void
2917}
2918
2919define void @test_vsoxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2920; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:
2921; CHECK:       # %bb.0: # %entry
2922; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2923; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
2924; CHECK-NEXT:    ret
2925entry:
2926  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
2927  ret void
2928}
2929
2930declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 4 x i16>, i32, i32)
2931declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
2932
2933define void @test_vsoxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
2934; CHECK-LABEL: test_vsoxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:
2935; CHECK:       # %bb.0: # %entry
2936; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2937; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
2938; CHECK-NEXT:    ret
2939entry:
2940  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
2941  ret void
2942}
2943
2944define void @test_vsoxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2945; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:
2946; CHECK:       # %bb.0: # %entry
2947; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2948; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
2949; CHECK-NEXT:    ret
2950entry:
2951  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
2952  ret void
2953}
2954
2955declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 4 x i32>, i32, i32)
2956declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
2957
2958define void @test_vsoxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
2959; CHECK-LABEL: test_vsoxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:
2960; CHECK:       # %bb.0: # %entry
2961; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2962; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12
2963; CHECK-NEXT:    ret
2964entry:
2965  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
2966  ret void
2967}
2968
2969define void @test_vsoxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
2970; CHECK-LABEL: test_vsoxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:
2971; CHECK:       # %bb.0: # %entry
2972; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
2973; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12, v0.t
2974; CHECK-NEXT:    ret
2975entry:
2976  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
2977  ret void
2978}
2979
2980declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 8 x i8>, i32, i32)
2981declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
2982
2983define void @test_vsoxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
2984; CHECK-LABEL: test_vsoxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:
2985; CHECK:       # %bb.0: # %entry
2986; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2987; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
2988; CHECK-NEXT:    ret
2989entry:
2990  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
2991  ret void
2992}
2993
2994define void @test_vsoxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
2995; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:
2996; CHECK:       # %bb.0: # %entry
2997; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
2998; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
2999; CHECK-NEXT:    ret
3000entry:
3001  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
3002  ret void
3003}
3004
3005declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 8 x i16>, i32, i32)
3006declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
3007
3008define void @test_vsoxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
3009; CHECK-LABEL: test_vsoxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:
3010; CHECK:       # %bb.0: # %entry
3011; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3012; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
3013; CHECK-NEXT:    ret
3014entry:
3015  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
3016  ret void
3017}
3018
3019define void @test_vsoxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
3020; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:
3021; CHECK:       # %bb.0: # %entry
3022; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3023; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
3024; CHECK-NEXT:    ret
3025entry:
3026  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
3027  ret void
3028}
3029
3030declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 8 x i32>, i32, i32)
3031declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
3032
3033define void @test_vsoxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
3034; CHECK-LABEL: test_vsoxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:
3035; CHECK:       # %bb.0: # %entry
3036; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3037; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16
3038; CHECK-NEXT:    ret
3039entry:
3040  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
3041  ret void
3042}
3043
3044define void @test_vsoxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
3045; CHECK-LABEL: test_vsoxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:
3046; CHECK:       # %bb.0: # %entry
3047; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3048; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16, v0.t
3049; CHECK-NEXT:    ret
3050entry:
3051  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
3052  ret void
3053}
3054
3055declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 1 x i8>, i32, i32)
3056declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
3057
3058define void @test_vsoxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
3059; CHECK-LABEL: test_vsoxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:
3060; CHECK:       # %bb.0: # %entry
3061; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3062; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
3063; CHECK-NEXT:    ret
3064entry:
3065  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
3066  ret void
3067}
3068
3069define void @test_vsoxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3070; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:
3071; CHECK:       # %bb.0: # %entry
3072; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3073; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
3074; CHECK-NEXT:    ret
3075entry:
3076  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3077  ret void
3078}
3079
3080declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 1 x i16>, i32, i32)
3081declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
3082
3083define void @test_vsoxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
3084; CHECK-LABEL: test_vsoxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:
3085; CHECK:       # %bb.0: # %entry
3086; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3087; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
3088; CHECK-NEXT:    ret
3089entry:
3090  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
3091  ret void
3092}
3093
3094define void @test_vsoxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3095; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:
3096; CHECK:       # %bb.0: # %entry
3097; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3098; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
3099; CHECK-NEXT:    ret
3100entry:
3101  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3102  ret void
3103}
3104
3105declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 1 x i32>, i32, i32)
3106declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
3107
3108define void @test_vsoxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
3109; CHECK-LABEL: test_vsoxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:
3110; CHECK:       # %bb.0: # %entry
3111; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3112; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
3113; CHECK-NEXT:    ret
3114entry:
3115  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
3116  ret void
3117}
3118
3119define void @test_vsoxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3120; CHECK-LABEL: test_vsoxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:
3121; CHECK:       # %bb.0: # %entry
3122; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3123; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
3124; CHECK-NEXT:    ret
3125entry:
3126  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3127  ret void
3128}
3129
3130declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 2 x i8>, i32, i32)
3131declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
3132
3133define void @test_vsoxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
3134; CHECK-LABEL: test_vsoxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:
3135; CHECK:       # %bb.0: # %entry
3136; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3137; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
3138; CHECK-NEXT:    ret
3139entry:
3140  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
3141  ret void
3142}
3143
3144define void @test_vsoxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3145; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:
3146; CHECK:       # %bb.0: # %entry
3147; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3148; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
3149; CHECK-NEXT:    ret
3150entry:
3151  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3152  ret void
3153}
3154
3155declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 2 x i16>, i32, i32)
3156declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
3157
3158define void @test_vsoxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
3159; CHECK-LABEL: test_vsoxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:
3160; CHECK:       # %bb.0: # %entry
3161; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3162; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
3163; CHECK-NEXT:    ret
3164entry:
3165  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
3166  ret void
3167}
3168
3169define void @test_vsoxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3170; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:
3171; CHECK:       # %bb.0: # %entry
3172; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3173; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
3174; CHECK-NEXT:    ret
3175entry:
3176  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3177  ret void
3178}
3179
3180declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 2 x i32>, i32, i32)
3181declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
3182
3183define void @test_vsoxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
3184; CHECK-LABEL: test_vsoxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:
3185; CHECK:       # %bb.0: # %entry
3186; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3187; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
3188; CHECK-NEXT:    ret
3189entry:
3190  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
3191  ret void
3192}
3193
3194define void @test_vsoxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3195; CHECK-LABEL: test_vsoxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:
3196; CHECK:       # %bb.0: # %entry
3197; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3198; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
3199; CHECK-NEXT:    ret
3200entry:
3201  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3202  ret void
3203}
3204
3205declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 4 x i8>, i32, i32)
3206declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
3207
3208define void @test_vsoxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
3209; CHECK-LABEL: test_vsoxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:
3210; CHECK:       # %bb.0: # %entry
3211; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3212; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
3213; CHECK-NEXT:    ret
3214entry:
3215  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
3216  ret void
3217}
3218
3219define void @test_vsoxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3220; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:
3221; CHECK:       # %bb.0: # %entry
3222; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3223; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
3224; CHECK-NEXT:    ret
3225entry:
3226  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3227  ret void
3228}
3229
3230declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 4 x i16>, i32, i32)
3231declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
3232
3233define void @test_vsoxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
3234; CHECK-LABEL: test_vsoxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:
3235; CHECK:       # %bb.0: # %entry
3236; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3237; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
3238; CHECK-NEXT:    ret
3239entry:
3240  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
3241  ret void
3242}
3243
3244define void @test_vsoxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3245; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:
3246; CHECK:       # %bb.0: # %entry
3247; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3248; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
3249; CHECK-NEXT:    ret
3250entry:
3251  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3252  ret void
3253}
3254
3255declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 4 x i32>, i32, i32)
3256declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
3257
3258define void @test_vsoxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
3259; CHECK-LABEL: test_vsoxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:
3260; CHECK:       # %bb.0: # %entry
3261; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3262; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
3263; CHECK-NEXT:    ret
3264entry:
3265  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
3266  ret void
3267}
3268
3269define void @test_vsoxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3270; CHECK-LABEL: test_vsoxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:
3271; CHECK:       # %bb.0: # %entry
3272; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3273; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
3274; CHECK-NEXT:    ret
3275entry:
3276  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3277  ret void
3278}
3279
3280declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 8 x i8>, i32, i32)
3281declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
3282
3283define void @test_vsoxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
3284; CHECK-LABEL: test_vsoxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:
3285; CHECK:       # %bb.0: # %entry
3286; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3287; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
3288; CHECK-NEXT:    ret
3289entry:
3290  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
3291  ret void
3292}
3293
3294define void @test_vsoxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
3295; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:
3296; CHECK:       # %bb.0: # %entry
3297; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3298; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
3299; CHECK-NEXT:    ret
3300entry:
3301  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
3302  ret void
3303}
3304
3305declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 8 x i16>, i32, i32)
3306declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
3307
3308define void @test_vsoxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
3309; CHECK-LABEL: test_vsoxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:
3310; CHECK:       # %bb.0: # %entry
3311; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3312; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
3313; CHECK-NEXT:    ret
3314entry:
3315  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
3316  ret void
3317}
3318
3319define void @test_vsoxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
3320; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:
3321; CHECK:       # %bb.0: # %entry
3322; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3323; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
3324; CHECK-NEXT:    ret
3325entry:
3326  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
3327  ret void
3328}
3329
3330declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 8 x i32>, i32, i32)
3331declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
3332
3333define void @test_vsoxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
3334; CHECK-LABEL: test_vsoxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:
3335; CHECK:       # %bb.0: # %entry
3336; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3337; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
3338; CHECK-NEXT:    ret
3339entry:
3340  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
3341  ret void
3342}
3343
3344define void @test_vsoxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
3345; CHECK-LABEL: test_vsoxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:
3346; CHECK:       # %bb.0: # %entry
3347; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
3348; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
3349; CHECK-NEXT:    ret
3350entry:
3351  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
3352  ret void
3353}
3354
3355declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 1 x i8>, i32, i32)
3356declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
3357
3358define void @test_vsoxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
3359; CHECK-LABEL: test_vsoxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:
3360; CHECK:       # %bb.0: # %entry
3361; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3362; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
3363; CHECK-NEXT:    ret
3364entry:
3365  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
3366  ret void
3367}
3368
3369define void @test_vsoxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3370; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:
3371; CHECK:       # %bb.0: # %entry
3372; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3373; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
3374; CHECK-NEXT:    ret
3375entry:
3376  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3377  ret void
3378}
3379
3380declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 1 x i16>, i32, i32)
3381declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
3382
3383define void @test_vsoxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
3384; CHECK-LABEL: test_vsoxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:
3385; CHECK:       # %bb.0: # %entry
3386; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3387; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
3388; CHECK-NEXT:    ret
3389entry:
3390  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
3391  ret void
3392}
3393
3394define void @test_vsoxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3395; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:
3396; CHECK:       # %bb.0: # %entry
3397; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3398; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
3399; CHECK-NEXT:    ret
3400entry:
3401  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3402  ret void
3403}
3404
3405declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 1 x i32>, i32, i32)
3406declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
3407
3408define void @test_vsoxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
3409; CHECK-LABEL: test_vsoxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:
3410; CHECK:       # %bb.0: # %entry
3411; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3412; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
3413; CHECK-NEXT:    ret
3414entry:
3415  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
3416  ret void
3417}
3418
3419define void @test_vsoxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3420; CHECK-LABEL: test_vsoxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:
3421; CHECK:       # %bb.0: # %entry
3422; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3423; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
3424; CHECK-NEXT:    ret
3425entry:
3426  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3427  ret void
3428}
3429
3430declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 2 x i8>, i32, i32)
3431declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
3432
3433define void @test_vsoxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
3434; CHECK-LABEL: test_vsoxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:
3435; CHECK:       # %bb.0: # %entry
3436; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3437; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
3438; CHECK-NEXT:    ret
3439entry:
3440  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
3441  ret void
3442}
3443
3444define void @test_vsoxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3445; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:
3446; CHECK:       # %bb.0: # %entry
3447; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3448; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
3449; CHECK-NEXT:    ret
3450entry:
3451  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3452  ret void
3453}
3454
3455declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 2 x i16>, i32, i32)
3456declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
3457
3458define void @test_vsoxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
3459; CHECK-LABEL: test_vsoxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:
3460; CHECK:       # %bb.0: # %entry
3461; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3462; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
3463; CHECK-NEXT:    ret
3464entry:
3465  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
3466  ret void
3467}
3468
3469define void @test_vsoxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3470; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:
3471; CHECK:       # %bb.0: # %entry
3472; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3473; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
3474; CHECK-NEXT:    ret
3475entry:
3476  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3477  ret void
3478}
3479
3480declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 2 x i32>, i32, i32)
3481declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
3482
3483define void @test_vsoxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
3484; CHECK-LABEL: test_vsoxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:
3485; CHECK:       # %bb.0: # %entry
3486; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3487; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
3488; CHECK-NEXT:    ret
3489entry:
3490  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
3491  ret void
3492}
3493
3494define void @test_vsoxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3495; CHECK-LABEL: test_vsoxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:
3496; CHECK:       # %bb.0: # %entry
3497; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3498; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
3499; CHECK-NEXT:    ret
3500entry:
3501  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3502  ret void
3503}
3504
3505declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 4 x i8>, i32, i32)
3506declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
3507
3508define void @test_vsoxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
3509; CHECK-LABEL: test_vsoxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:
3510; CHECK:       # %bb.0: # %entry
3511; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3512; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
3513; CHECK-NEXT:    ret
3514entry:
3515  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
3516  ret void
3517}
3518
3519define void @test_vsoxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3520; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:
3521; CHECK:       # %bb.0: # %entry
3522; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3523; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
3524; CHECK-NEXT:    ret
3525entry:
3526  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3527  ret void
3528}
3529
3530declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 4 x i16>, i32, i32)
3531declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
3532
3533define void @test_vsoxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
3534; CHECK-LABEL: test_vsoxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:
3535; CHECK:       # %bb.0: # %entry
3536; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3537; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
3538; CHECK-NEXT:    ret
3539entry:
3540  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
3541  ret void
3542}
3543
3544define void @test_vsoxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3545; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:
3546; CHECK:       # %bb.0: # %entry
3547; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3548; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
3549; CHECK-NEXT:    ret
3550entry:
3551  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3552  ret void
3553}
3554
3555declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 4 x i32>, i32, i32)
3556declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
3557
3558define void @test_vsoxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
3559; CHECK-LABEL: test_vsoxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:
3560; CHECK:       # %bb.0: # %entry
3561; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3562; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14
3563; CHECK-NEXT:    ret
3564entry:
3565  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
3566  ret void
3567}
3568
3569define void @test_vsoxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3570; CHECK-LABEL: test_vsoxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:
3571; CHECK:       # %bb.0: # %entry
3572; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3573; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14, v0.t
3574; CHECK-NEXT:    ret
3575entry:
3576  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3577  ret void
3578}
3579
3580declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 1 x i8>, i32, i32)
3581declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
3582
3583define void @test_vsoxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
3584; CHECK-LABEL: test_vsoxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:
3585; CHECK:       # %bb.0: # %entry
3586; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3587; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
3588; CHECK-NEXT:    ret
3589entry:
3590  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
3591  ret void
3592}
3593
3594define void @test_vsoxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3595; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:
3596; CHECK:       # %bb.0: # %entry
3597; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3598; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
3599; CHECK-NEXT:    ret
3600entry:
3601  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3602  ret void
3603}
3604
3605declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 1 x i16>, i32, i32)
3606declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
3607
3608define void @test_vsoxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
3609; CHECK-LABEL: test_vsoxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:
3610; CHECK:       # %bb.0: # %entry
3611; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3612; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
3613; CHECK-NEXT:    ret
3614entry:
3615  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
3616  ret void
3617}
3618
3619define void @test_vsoxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3620; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:
3621; CHECK:       # %bb.0: # %entry
3622; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3623; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
3624; CHECK-NEXT:    ret
3625entry:
3626  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3627  ret void
3628}
3629
3630declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 1 x i32>, i32, i32)
3631declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
3632
3633define void @test_vsoxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
3634; CHECK-LABEL: test_vsoxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:
3635; CHECK:       # %bb.0: # %entry
3636; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3637; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
3638; CHECK-NEXT:    ret
3639entry:
3640  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
3641  ret void
3642}
3643
3644define void @test_vsoxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3645; CHECK-LABEL: test_vsoxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:
3646; CHECK:       # %bb.0: # %entry
3647; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3648; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
3649; CHECK-NEXT:    ret
3650entry:
3651  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3652  ret void
3653}
3654
3655declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 2 x i8>, i32, i32)
3656declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
3657
3658define void @test_vsoxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
3659; CHECK-LABEL: test_vsoxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:
3660; CHECK:       # %bb.0: # %entry
3661; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3662; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
3663; CHECK-NEXT:    ret
3664entry:
3665  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
3666  ret void
3667}
3668
3669define void @test_vsoxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3670; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:
3671; CHECK:       # %bb.0: # %entry
3672; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3673; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
3674; CHECK-NEXT:    ret
3675entry:
3676  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3677  ret void
3678}
3679
3680declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 2 x i16>, i32, i32)
3681declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
3682
3683define void @test_vsoxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
3684; CHECK-LABEL: test_vsoxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:
3685; CHECK:       # %bb.0: # %entry
3686; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3687; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
3688; CHECK-NEXT:    ret
3689entry:
3690  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
3691  ret void
3692}
3693
3694define void @test_vsoxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3695; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:
3696; CHECK:       # %bb.0: # %entry
3697; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3698; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
3699; CHECK-NEXT:    ret
3700entry:
3701  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3702  ret void
3703}
3704
3705declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 2 x i32>, i32, i32)
3706declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
3707
3708define void @test_vsoxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
3709; CHECK-LABEL: test_vsoxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:
3710; CHECK:       # %bb.0: # %entry
3711; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3712; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
3713; CHECK-NEXT:    ret
3714entry:
3715  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
3716  ret void
3717}
3718
3719define void @test_vsoxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3720; CHECK-LABEL: test_vsoxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:
3721; CHECK:       # %bb.0: # %entry
3722; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3723; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
3724; CHECK-NEXT:    ret
3725entry:
3726  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3727  ret void
3728}
3729
3730declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 4 x i8>, i32, i32)
3731declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
3732
3733define void @test_vsoxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
3734; CHECK-LABEL: test_vsoxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:
3735; CHECK:       # %bb.0: # %entry
3736; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3737; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
3738; CHECK-NEXT:    ret
3739entry:
3740  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
3741  ret void
3742}
3743
3744define void @test_vsoxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3745; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:
3746; CHECK:       # %bb.0: # %entry
3747; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3748; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
3749; CHECK-NEXT:    ret
3750entry:
3751  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3752  ret void
3753}
3754
3755declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 4 x i16>, i32, i32)
3756declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
3757
3758define void @test_vsoxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
3759; CHECK-LABEL: test_vsoxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:
3760; CHECK:       # %bb.0: # %entry
3761; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3762; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
3763; CHECK-NEXT:    ret
3764entry:
3765  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
3766  ret void
3767}
3768
3769define void @test_vsoxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3770; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:
3771; CHECK:       # %bb.0: # %entry
3772; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3773; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
3774; CHECK-NEXT:    ret
3775entry:
3776  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3777  ret void
3778}
3779
3780declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 4 x i32>, i32, i32)
3781declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
3782
3783define void @test_vsoxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
3784; CHECK-LABEL: test_vsoxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:
3785; CHECK:       # %bb.0: # %entry
3786; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3787; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
3788; CHECK-NEXT:    ret
3789entry:
3790  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
3791  ret void
3792}
3793
3794define void @test_vsoxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3795; CHECK-LABEL: test_vsoxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:
3796; CHECK:       # %bb.0: # %entry
3797; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3798; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
3799; CHECK-NEXT:    ret
3800entry:
3801  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3802  ret void
3803}
3804
3805declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 1 x i8>, i32, i32)
3806declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
3807
3808define void @test_vsoxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
3809; CHECK-LABEL: test_vsoxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:
3810; CHECK:       # %bb.0: # %entry
3811; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3812; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
3813; CHECK-NEXT:    ret
3814entry:
3815  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
3816  ret void
3817}
3818
3819define void @test_vsoxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3820; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:
3821; CHECK:       # %bb.0: # %entry
3822; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3823; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
3824; CHECK-NEXT:    ret
3825entry:
3826  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3827  ret void
3828}
3829
3830declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 1 x i16>, i32, i32)
3831declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
3832
3833define void @test_vsoxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
3834; CHECK-LABEL: test_vsoxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:
3835; CHECK:       # %bb.0: # %entry
3836; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3837; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
3838; CHECK-NEXT:    ret
3839entry:
3840  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
3841  ret void
3842}
3843
3844define void @test_vsoxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3845; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:
3846; CHECK:       # %bb.0: # %entry
3847; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3848; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
3849; CHECK-NEXT:    ret
3850entry:
3851  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3852  ret void
3853}
3854
3855declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 1 x i32>, i32, i32)
3856declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
3857
3858define void @test_vsoxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
3859; CHECK-LABEL: test_vsoxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:
3860; CHECK:       # %bb.0: # %entry
3861; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3862; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
3863; CHECK-NEXT:    ret
3864entry:
3865  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
3866  ret void
3867}
3868
3869define void @test_vsoxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
3870; CHECK-LABEL: test_vsoxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:
3871; CHECK:       # %bb.0: # %entry
3872; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
3873; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
3874; CHECK-NEXT:    ret
3875entry:
3876  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
3877  ret void
3878}
3879
3880declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 2 x i8>, i32, i32)
3881declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
3882
3883define void @test_vsoxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
3884; CHECK-LABEL: test_vsoxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:
3885; CHECK:       # %bb.0: # %entry
3886; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3887; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
3888; CHECK-NEXT:    ret
3889entry:
3890  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
3891  ret void
3892}
3893
3894define void @test_vsoxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3895; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:
3896; CHECK:       # %bb.0: # %entry
3897; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3898; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
3899; CHECK-NEXT:    ret
3900entry:
3901  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3902  ret void
3903}
3904
3905declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 2 x i16>, i32, i32)
3906declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
3907
3908define void @test_vsoxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
3909; CHECK-LABEL: test_vsoxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:
3910; CHECK:       # %bb.0: # %entry
3911; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3912; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
3913; CHECK-NEXT:    ret
3914entry:
3915  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
3916  ret void
3917}
3918
3919define void @test_vsoxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3920; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:
3921; CHECK:       # %bb.0: # %entry
3922; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3923; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
3924; CHECK-NEXT:    ret
3925entry:
3926  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3927  ret void
3928}
3929
3930declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 2 x i32>, i32, i32)
3931declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
3932
3933define void @test_vsoxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
3934; CHECK-LABEL: test_vsoxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:
3935; CHECK:       # %bb.0: # %entry
3936; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3937; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
3938; CHECK-NEXT:    ret
3939entry:
3940  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
3941  ret void
3942}
3943
3944define void @test_vsoxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
3945; CHECK-LABEL: test_vsoxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:
3946; CHECK:       # %bb.0: # %entry
3947; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
3948; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
3949; CHECK-NEXT:    ret
3950entry:
3951  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
3952  ret void
3953}
3954
3955declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 4 x i8>, i32, i32)
3956declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
3957
3958define void @test_vsoxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
3959; CHECK-LABEL: test_vsoxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:
3960; CHECK:       # %bb.0: # %entry
3961; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3962; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
3963; CHECK-NEXT:    ret
3964entry:
3965  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
3966  ret void
3967}
3968
3969define void @test_vsoxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3970; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:
3971; CHECK:       # %bb.0: # %entry
3972; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3973; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
3974; CHECK-NEXT:    ret
3975entry:
3976  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
3977  ret void
3978}
3979
3980declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 4 x i16>, i32, i32)
3981declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
3982
3983define void @test_vsoxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
3984; CHECK-LABEL: test_vsoxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:
3985; CHECK:       # %bb.0: # %entry
3986; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3987; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
3988; CHECK-NEXT:    ret
3989entry:
3990  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
3991  ret void
3992}
3993
3994define void @test_vsoxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
3995; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:
3996; CHECK:       # %bb.0: # %entry
3997; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
3998; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
3999; CHECK-NEXT:    ret
4000entry:
4001  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
4002  ret void
4003}
4004
4005declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 4 x i32>, i32, i32)
4006declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
4007
4008define void @test_vsoxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
4009; CHECK-LABEL: test_vsoxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:
4010; CHECK:       # %bb.0: # %entry
4011; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4012; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16
4013; CHECK-NEXT:    ret
4014entry:
4015  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
4016  ret void
4017}
4018
4019define void @test_vsoxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4020; CHECK-LABEL: test_vsoxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:
4021; CHECK:       # %bb.0: # %entry
4022; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4023; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16, v0.t
4024; CHECK-NEXT:    ret
4025entry:
4026  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
4027  ret void
4028}
4029
4030declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 1 x i8>, i32, i32)
4031declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
4032
4033define void @test_vsoxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
4034; CHECK-LABEL: test_vsoxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:
4035; CHECK:       # %bb.0: # %entry
4036; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
4037; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
4038; CHECK-NEXT:    ret
4039entry:
4040  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
4041  ret void
4042}
4043
4044define void @test_vsoxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4045; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:
4046; CHECK:       # %bb.0: # %entry
4047; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
4048; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
4049; CHECK-NEXT:    ret
4050entry:
4051  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
4052  ret void
4053}
4054
4055declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 1 x i16>, i32, i32)
4056declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
4057
4058define void @test_vsoxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
4059; CHECK-LABEL: test_vsoxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:
4060; CHECK:       # %bb.0: # %entry
4061; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
4062; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
4063; CHECK-NEXT:    ret
4064entry:
4065  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
4066  ret void
4067}
4068
4069define void @test_vsoxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4070; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:
4071; CHECK:       # %bb.0: # %entry
4072; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
4073; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
4074; CHECK-NEXT:    ret
4075entry:
4076  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
4077  ret void
4078}
4079
4080declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 1 x i32>, i32, i32)
4081declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
4082
4083define void @test_vsoxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
4084; CHECK-LABEL: test_vsoxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:
4085; CHECK:       # %bb.0: # %entry
4086; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
4087; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
4088; CHECK-NEXT:    ret
4089entry:
4090  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
4091  ret void
4092}
4093
4094define void @test_vsoxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4095; CHECK-LABEL: test_vsoxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:
4096; CHECK:       # %bb.0: # %entry
4097; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
4098; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
4099; CHECK-NEXT:    ret
4100entry:
4101  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
4102  ret void
4103}
4104
4105declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 2 x i8>, i32, i32)
4106declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
4107
4108define void @test_vsoxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
4109; CHECK-LABEL: test_vsoxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:
4110; CHECK:       # %bb.0: # %entry
4111; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
4112; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
4113; CHECK-NEXT:    ret
4114entry:
4115  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
4116  ret void
4117}
4118
4119define void @test_vsoxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4120; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:
4121; CHECK:       # %bb.0: # %entry
4122; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
4123; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
4124; CHECK-NEXT:    ret
4125entry:
4126  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
4127  ret void
4128}
4129
4130declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 2 x i16>, i32, i32)
4131declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
4132
4133define void @test_vsoxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
4134; CHECK-LABEL: test_vsoxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:
4135; CHECK:       # %bb.0: # %entry
4136; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
4137; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
4138; CHECK-NEXT:    ret
4139entry:
4140  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
4141  ret void
4142}
4143
4144define void @test_vsoxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4145; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:
4146; CHECK:       # %bb.0: # %entry
4147; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
4148; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
4149; CHECK-NEXT:    ret
4150entry:
4151  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
4152  ret void
4153}
4154
4155declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 2 x i32>, i32, i32)
4156declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
4157
4158define void @test_vsoxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
4159; CHECK-LABEL: test_vsoxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:
4160; CHECK:       # %bb.0: # %entry
4161; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
4162; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
4163; CHECK-NEXT:    ret
4164entry:
4165  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
4166  ret void
4167}
4168
4169define void @test_vsoxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4170; CHECK-LABEL: test_vsoxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:
4171; CHECK:       # %bb.0: # %entry
4172; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
4173; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
4174; CHECK-NEXT:    ret
4175entry:
4176  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
4177  ret void
4178}
4179
4180declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 4 x i8>, i32, i32)
4181declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
4182
4183define void @test_vsoxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
4184; CHECK-LABEL: test_vsoxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:
4185; CHECK:       # %bb.0: # %entry
4186; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4187; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
4188; CHECK-NEXT:    ret
4189entry:
4190  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
4191  ret void
4192}
4193
4194define void @test_vsoxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4195; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:
4196; CHECK:       # %bb.0: # %entry
4197; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4198; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
4199; CHECK-NEXT:    ret
4200entry:
4201  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
4202  ret void
4203}
4204
4205declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 4 x i16>, i32, i32)
4206declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
4207
4208define void @test_vsoxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
4209; CHECK-LABEL: test_vsoxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:
4210; CHECK:       # %bb.0: # %entry
4211; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4212; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
4213; CHECK-NEXT:    ret
4214entry:
4215  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
4216  ret void
4217}
4218
4219define void @test_vsoxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4220; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:
4221; CHECK:       # %bb.0: # %entry
4222; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4223; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
4224; CHECK-NEXT:    ret
4225entry:
4226  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
4227  ret void
4228}
4229
4230declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 4 x i32>, i32, i32)
4231declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
4232
4233define void @test_vsoxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
4234; CHECK-LABEL: test_vsoxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:
4235; CHECK:       # %bb.0: # %entry
4236; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4237; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
4238; CHECK-NEXT:    ret
4239entry:
4240  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
4241  ret void
4242}
4243
4244define void @test_vsoxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4245; CHECK-LABEL: test_vsoxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:
4246; CHECK:       # %bb.0: # %entry
4247; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
4248; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
4249; CHECK-NEXT:    ret
4250entry:
4251  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
4252  ret void
4253}
4254
4255declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i8>, i32, i32)
4256declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
4257
4258define void @test_vsoxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
4259; CHECK-LABEL: test_vsoxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:
4260; CHECK:       # %bb.0: # %entry
4261; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4262; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
4263; CHECK-NEXT:    ret
4264entry:
4265  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
4266  ret void
4267}
4268
4269define void @test_vsoxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4270; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:
4271; CHECK:       # %bb.0: # %entry
4272; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4273; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
4274; CHECK-NEXT:    ret
4275entry:
4276  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4277  ret void
4278}
4279
4280declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i16>, i32, i32)
4281declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
4282
4283define void @test_vsoxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
4284; CHECK-LABEL: test_vsoxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:
4285; CHECK:       # %bb.0: # %entry
4286; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4287; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
4288; CHECK-NEXT:    ret
4289entry:
4290  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
4291  ret void
4292}
4293
4294define void @test_vsoxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4295; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:
4296; CHECK:       # %bb.0: # %entry
4297; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4298; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
4299; CHECK-NEXT:    ret
4300entry:
4301  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4302  ret void
4303}
4304
4305declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i32>, i32, i32)
4306declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
4307
4308define void @test_vsoxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
4309; CHECK-LABEL: test_vsoxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:
4310; CHECK:       # %bb.0: # %entry
4311; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4312; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
4313; CHECK-NEXT:    ret
4314entry:
4315  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
4316  ret void
4317}
4318
4319define void @test_vsoxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4320; CHECK-LABEL: test_vsoxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:
4321; CHECK:       # %bb.0: # %entry
4322; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4323; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
4324; CHECK-NEXT:    ret
4325entry:
4326  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4327  ret void
4328}
4329
4330declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 2 x i8>, i32, i32)
4331declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
4332
4333define void @test_vsoxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
4334; CHECK-LABEL: test_vsoxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:
4335; CHECK:       # %bb.0: # %entry
4336; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4337; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
4338; CHECK-NEXT:    ret
4339entry:
4340  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
4341  ret void
4342}
4343
4344define void @test_vsoxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4345; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:
4346; CHECK:       # %bb.0: # %entry
4347; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4348; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
4349; CHECK-NEXT:    ret
4350entry:
4351  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4352  ret void
4353}
4354
4355declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 2 x i16>, i32, i32)
4356declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
4357
4358define void @test_vsoxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
4359; CHECK-LABEL: test_vsoxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:
4360; CHECK:       # %bb.0: # %entry
4361; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4362; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
4363; CHECK-NEXT:    ret
4364entry:
4365  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
4366  ret void
4367}
4368
4369define void @test_vsoxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4370; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:
4371; CHECK:       # %bb.0: # %entry
4372; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4373; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
4374; CHECK-NEXT:    ret
4375entry:
4376  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4377  ret void
4378}
4379
4380declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 2 x i32>, i32, i32)
4381declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
4382
4383define void @test_vsoxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
4384; CHECK-LABEL: test_vsoxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:
4385; CHECK:       # %bb.0: # %entry
4386; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4387; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
4388; CHECK-NEXT:    ret
4389entry:
4390  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
4391  ret void
4392}
4393
4394define void @test_vsoxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4395; CHECK-LABEL: test_vsoxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:
4396; CHECK:       # %bb.0: # %entry
4397; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4398; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
4399; CHECK-NEXT:    ret
4400entry:
4401  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4402  ret void
4403}
4404
4405declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 4 x i8>, i32, i32)
4406declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
4407
4408define void @test_vsoxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
4409; CHECK-LABEL: test_vsoxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:
4410; CHECK:       # %bb.0: # %entry
4411; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4412; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
4413; CHECK-NEXT:    ret
4414entry:
4415  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 5)
4416  ret void
4417}
4418
4419define void @test_vsoxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4420; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:
4421; CHECK:       # %bb.0: # %entry
4422; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4423; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
4424; CHECK-NEXT:    ret
4425entry:
4426  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4427  ret void
4428}
4429
4430declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 4 x i16>, i32, i32)
4431declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
4432
4433define void @test_vsoxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
4434; CHECK-LABEL: test_vsoxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:
4435; CHECK:       # %bb.0: # %entry
4436; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4437; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
4438; CHECK-NEXT:    ret
4439entry:
4440  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 5)
4441  ret void
4442}
4443
4444define void @test_vsoxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4445; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:
4446; CHECK:       # %bb.0: # %entry
4447; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4448; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
4449; CHECK-NEXT:    ret
4450entry:
4451  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4452  ret void
4453}
4454
4455declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 4 x i32>, i32, i32)
4456declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
4457
4458define void @test_vsoxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
4459; CHECK-LABEL: test_vsoxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:
4460; CHECK:       # %bb.0: # %entry
4461; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4462; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
4463; CHECK-NEXT:    ret
4464entry:
4465  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 5)
4466  ret void
4467}
4468
4469define void @test_vsoxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4470; CHECK-LABEL: test_vsoxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:
4471; CHECK:       # %bb.0: # %entry
4472; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4473; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
4474; CHECK-NEXT:    ret
4475entry:
4476  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4477  ret void
4478}
4479
4480declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 8 x i8>, i32, i32)
4481declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 8 x i8>, <vscale x 8 x i1>, i32, i32)
4482
4483define void @test_vsoxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
4484; CHECK-LABEL: test_vsoxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:
4485; CHECK:       # %bb.0: # %entry
4486; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
4487; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
4488; CHECK-NEXT:    ret
4489entry:
4490  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 5)
4491  ret void
4492}
4493
4494define void @test_vsoxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
4495; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:
4496; CHECK:       # %bb.0: # %entry
4497; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
4498; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
4499; CHECK-NEXT:    ret
4500entry:
4501  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 5)
4502  ret void
4503}
4504
4505declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 8 x i16>, i32, i32)
4506declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 8 x i16>, <vscale x 8 x i1>, i32, i32)
4507
4508define void @test_vsoxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
4509; CHECK-LABEL: test_vsoxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:
4510; CHECK:       # %bb.0: # %entry
4511; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
4512; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
4513; CHECK-NEXT:    ret
4514entry:
4515  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 5)
4516  ret void
4517}
4518
4519define void @test_vsoxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
4520; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:
4521; CHECK:       # %bb.0: # %entry
4522; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
4523; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
4524; CHECK-NEXT:    ret
4525entry:
4526  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 5)
4527  ret void
4528}
4529
4530declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 8 x i32>, i32, i32)
4531declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 8 x i32>, <vscale x 8 x i1>, i32, i32)
4532
4533define void @test_vsoxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
4534; CHECK-LABEL: test_vsoxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:
4535; CHECK:       # %bb.0: # %entry
4536; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
4537; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
4538; CHECK-NEXT:    ret
4539entry:
4540  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 5)
4541  ret void
4542}
4543
4544define void @test_vsoxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
4545; CHECK-LABEL: test_vsoxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:
4546; CHECK:       # %bb.0: # %entry
4547; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
4548; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
4549; CHECK-NEXT:    ret
4550entry:
4551  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 5)
4552  ret void
4553}
4554
4555declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i8>, i32, i32)
4556declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
4557
4558define void @test_vsoxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
4559; CHECK-LABEL: test_vsoxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:
4560; CHECK:       # %bb.0: # %entry
4561; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4562; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
4563; CHECK-NEXT:    ret
4564entry:
4565  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
4566  ret void
4567}
4568
4569define void @test_vsoxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4570; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:
4571; CHECK:       # %bb.0: # %entry
4572; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4573; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
4574; CHECK-NEXT:    ret
4575entry:
4576  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4577  ret void
4578}
4579
4580declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i16>, i32, i32)
4581declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
4582
4583define void @test_vsoxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
4584; CHECK-LABEL: test_vsoxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:
4585; CHECK:       # %bb.0: # %entry
4586; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4587; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
4588; CHECK-NEXT:    ret
4589entry:
4590  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
4591  ret void
4592}
4593
4594define void @test_vsoxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4595; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:
4596; CHECK:       # %bb.0: # %entry
4597; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4598; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
4599; CHECK-NEXT:    ret
4600entry:
4601  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4602  ret void
4603}
4604
4605declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i32>, i32, i32)
4606declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
4607
4608define void @test_vsoxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
4609; CHECK-LABEL: test_vsoxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:
4610; CHECK:       # %bb.0: # %entry
4611; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4612; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
4613; CHECK-NEXT:    ret
4614entry:
4615  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
4616  ret void
4617}
4618
4619define void @test_vsoxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4620; CHECK-LABEL: test_vsoxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:
4621; CHECK:       # %bb.0: # %entry
4622; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4623; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
4624; CHECK-NEXT:    ret
4625entry:
4626  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4627  ret void
4628}
4629
4630declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 2 x i8>, i32, i32)
4631declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
4632
4633define void @test_vsoxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
4634; CHECK-LABEL: test_vsoxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:
4635; CHECK:       # %bb.0: # %entry
4636; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4637; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
4638; CHECK-NEXT:    ret
4639entry:
4640  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
4641  ret void
4642}
4643
4644define void @test_vsoxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4645; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:
4646; CHECK:       # %bb.0: # %entry
4647; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4648; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
4649; CHECK-NEXT:    ret
4650entry:
4651  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4652  ret void
4653}
4654
4655declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 2 x i16>, i32, i32)
4656declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
4657
4658define void @test_vsoxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
4659; CHECK-LABEL: test_vsoxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:
4660; CHECK:       # %bb.0: # %entry
4661; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4662; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
4663; CHECK-NEXT:    ret
4664entry:
4665  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
4666  ret void
4667}
4668
4669define void @test_vsoxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4670; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:
4671; CHECK:       # %bb.0: # %entry
4672; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4673; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
4674; CHECK-NEXT:    ret
4675entry:
4676  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4677  ret void
4678}
4679
4680declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 2 x i32>, i32, i32)
4681declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
4682
4683define void @test_vsoxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
4684; CHECK-LABEL: test_vsoxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:
4685; CHECK:       # %bb.0: # %entry
4686; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4687; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
4688; CHECK-NEXT:    ret
4689entry:
4690  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
4691  ret void
4692}
4693
4694define void @test_vsoxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4695; CHECK-LABEL: test_vsoxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:
4696; CHECK:       # %bb.0: # %entry
4697; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4698; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
4699; CHECK-NEXT:    ret
4700entry:
4701  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4702  ret void
4703}
4704
4705declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 4 x i8>, i32, i32)
4706declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
4707
4708define void @test_vsoxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
4709; CHECK-LABEL: test_vsoxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:
4710; CHECK:       # %bb.0: # %entry
4711; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4712; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
4713; CHECK-NEXT:    ret
4714entry:
4715  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 5)
4716  ret void
4717}
4718
4719define void @test_vsoxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4720; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:
4721; CHECK:       # %bb.0: # %entry
4722; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4723; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
4724; CHECK-NEXT:    ret
4725entry:
4726  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4727  ret void
4728}
4729
4730declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 4 x i16>, i32, i32)
4731declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
4732
4733define void @test_vsoxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
4734; CHECK-LABEL: test_vsoxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:
4735; CHECK:       # %bb.0: # %entry
4736; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4737; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
4738; CHECK-NEXT:    ret
4739entry:
4740  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 5)
4741  ret void
4742}
4743
4744define void @test_vsoxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4745; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:
4746; CHECK:       # %bb.0: # %entry
4747; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4748; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
4749; CHECK-NEXT:    ret
4750entry:
4751  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4752  ret void
4753}
4754
4755declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 4 x i32>, i32, i32)
4756declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
4757
4758define void @test_vsoxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
4759; CHECK-LABEL: test_vsoxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:
4760; CHECK:       # %bb.0: # %entry
4761; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4762; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14
4763; CHECK-NEXT:    ret
4764entry:
4765  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 5)
4766  ret void
4767}
4768
4769define void @test_vsoxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4770; CHECK-LABEL: test_vsoxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:
4771; CHECK:       # %bb.0: # %entry
4772; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4773; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14, v0.t
4774; CHECK-NEXT:    ret
4775entry:
4776  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4777  ret void
4778}
4779
4780declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i8>, i32, i32)
4781declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
4782
4783define void @test_vsoxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
4784; CHECK-LABEL: test_vsoxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:
4785; CHECK:       # %bb.0: # %entry
4786; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4787; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
4788; CHECK-NEXT:    ret
4789entry:
4790  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
4791  ret void
4792}
4793
4794define void @test_vsoxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4795; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:
4796; CHECK:       # %bb.0: # %entry
4797; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4798; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
4799; CHECK-NEXT:    ret
4800entry:
4801  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4802  ret void
4803}
4804
4805declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i16>, i32, i32)
4806declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
4807
4808define void @test_vsoxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
4809; CHECK-LABEL: test_vsoxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:
4810; CHECK:       # %bb.0: # %entry
4811; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4812; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
4813; CHECK-NEXT:    ret
4814entry:
4815  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
4816  ret void
4817}
4818
4819define void @test_vsoxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4820; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:
4821; CHECK:       # %bb.0: # %entry
4822; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4823; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
4824; CHECK-NEXT:    ret
4825entry:
4826  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4827  ret void
4828}
4829
4830declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i32>, i32, i32)
4831declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
4832
4833define void @test_vsoxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
4834; CHECK-LABEL: test_vsoxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:
4835; CHECK:       # %bb.0: # %entry
4836; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4837; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
4838; CHECK-NEXT:    ret
4839entry:
4840  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
4841  ret void
4842}
4843
4844define void @test_vsoxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
4845; CHECK-LABEL: test_vsoxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:
4846; CHECK:       # %bb.0: # %entry
4847; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
4848; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
4849; CHECK-NEXT:    ret
4850entry:
4851  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
4852  ret void
4853}
4854
4855declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 2 x i8>, i32, i32)
4856declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
4857
4858define void @test_vsoxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
4859; CHECK-LABEL: test_vsoxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:
4860; CHECK:       # %bb.0: # %entry
4861; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4862; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
4863; CHECK-NEXT:    ret
4864entry:
4865  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
4866  ret void
4867}
4868
4869define void @test_vsoxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4870; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:
4871; CHECK:       # %bb.0: # %entry
4872; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4873; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
4874; CHECK-NEXT:    ret
4875entry:
4876  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4877  ret void
4878}
4879
4880declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 2 x i16>, i32, i32)
4881declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
4882
4883define void @test_vsoxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
4884; CHECK-LABEL: test_vsoxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:
4885; CHECK:       # %bb.0: # %entry
4886; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4887; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
4888; CHECK-NEXT:    ret
4889entry:
4890  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
4891  ret void
4892}
4893
4894define void @test_vsoxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4895; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:
4896; CHECK:       # %bb.0: # %entry
4897; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4898; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
4899; CHECK-NEXT:    ret
4900entry:
4901  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4902  ret void
4903}
4904
4905declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 2 x i32>, i32, i32)
4906declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
4907
4908define void @test_vsoxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
4909; CHECK-LABEL: test_vsoxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:
4910; CHECK:       # %bb.0: # %entry
4911; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4912; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
4913; CHECK-NEXT:    ret
4914entry:
4915  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
4916  ret void
4917}
4918
4919define void @test_vsoxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
4920; CHECK-LABEL: test_vsoxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:
4921; CHECK:       # %bb.0: # %entry
4922; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
4923; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
4924; CHECK-NEXT:    ret
4925entry:
4926  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
4927  ret void
4928}
4929
4930declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 4 x i8>, i32, i32)
4931declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
4932
4933define void @test_vsoxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
4934; CHECK-LABEL: test_vsoxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:
4935; CHECK:       # %bb.0: # %entry
4936; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4937; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
4938; CHECK-NEXT:    ret
4939entry:
4940  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 5)
4941  ret void
4942}
4943
4944define void @test_vsoxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4945; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:
4946; CHECK:       # %bb.0: # %entry
4947; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4948; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
4949; CHECK-NEXT:    ret
4950entry:
4951  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4952  ret void
4953}
4954
4955declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 4 x i16>, i32, i32)
4956declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
4957
4958define void @test_vsoxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
4959; CHECK-LABEL: test_vsoxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:
4960; CHECK:       # %bb.0: # %entry
4961; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4962; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
4963; CHECK-NEXT:    ret
4964entry:
4965  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 5)
4966  ret void
4967}
4968
4969define void @test_vsoxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4970; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:
4971; CHECK:       # %bb.0: # %entry
4972; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4973; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
4974; CHECK-NEXT:    ret
4975entry:
4976  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
4977  ret void
4978}
4979
4980declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 4 x i32>, i32, i32)
4981declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
4982
4983define void @test_vsoxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
4984; CHECK-LABEL: test_vsoxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:
4985; CHECK:       # %bb.0: # %entry
4986; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4987; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
4988; CHECK-NEXT:    ret
4989entry:
4990  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 5)
4991  ret void
4992}
4993
4994define void @test_vsoxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
4995; CHECK-LABEL: test_vsoxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:
4996; CHECK:       # %bb.0: # %entry
4997; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
4998; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
4999; CHECK-NEXT:    ret
5000entry:
5001  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
5002  ret void
5003}
5004
5005declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i8>, i32, i32)
5006declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5007
5008define void @test_vsoxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5009; CHECK-LABEL: test_vsoxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:
5010; CHECK:       # %bb.0: # %entry
5011; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5012; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
5013; CHECK-NEXT:    ret
5014entry:
5015  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
5016  ret void
5017}
5018
5019define void @test_vsoxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5020; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:
5021; CHECK:       # %bb.0: # %entry
5022; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5023; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
5024; CHECK-NEXT:    ret
5025entry:
5026  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5027  ret void
5028}
5029
5030declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i16>, i32, i32)
5031declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
5032
5033define void @test_vsoxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
5034; CHECK-LABEL: test_vsoxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:
5035; CHECK:       # %bb.0: # %entry
5036; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5037; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
5038; CHECK-NEXT:    ret
5039entry:
5040  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
5041  ret void
5042}
5043
5044define void @test_vsoxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5045; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:
5046; CHECK:       # %bb.0: # %entry
5047; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5048; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
5049; CHECK-NEXT:    ret
5050entry:
5051  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5052  ret void
5053}
5054
5055declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i32>, i32, i32)
5056declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
5057
5058define void @test_vsoxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
5059; CHECK-LABEL: test_vsoxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:
5060; CHECK:       # %bb.0: # %entry
5061; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5062; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
5063; CHECK-NEXT:    ret
5064entry:
5065  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
5066  ret void
5067}
5068
5069define void @test_vsoxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5070; CHECK-LABEL: test_vsoxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:
5071; CHECK:       # %bb.0: # %entry
5072; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5073; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
5074; CHECK-NEXT:    ret
5075entry:
5076  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5077  ret void
5078}
5079
5080declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 2 x i8>, i32, i32)
5081declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
5082
5083define void @test_vsoxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
5084; CHECK-LABEL: test_vsoxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:
5085; CHECK:       # %bb.0: # %entry
5086; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5087; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
5088; CHECK-NEXT:    ret
5089entry:
5090  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
5091  ret void
5092}
5093
5094define void @test_vsoxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5095; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:
5096; CHECK:       # %bb.0: # %entry
5097; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5098; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
5099; CHECK-NEXT:    ret
5100entry:
5101  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5102  ret void
5103}
5104
5105declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 2 x i16>, i32, i32)
5106declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
5107
5108define void @test_vsoxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
5109; CHECK-LABEL: test_vsoxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:
5110; CHECK:       # %bb.0: # %entry
5111; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5112; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
5113; CHECK-NEXT:    ret
5114entry:
5115  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
5116  ret void
5117}
5118
5119define void @test_vsoxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5120; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:
5121; CHECK:       # %bb.0: # %entry
5122; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5123; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
5124; CHECK-NEXT:    ret
5125entry:
5126  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5127  ret void
5128}
5129
5130declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 2 x i32>, i32, i32)
5131declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
5132
5133define void @test_vsoxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
5134; CHECK-LABEL: test_vsoxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:
5135; CHECK:       # %bb.0: # %entry
5136; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5137; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
5138; CHECK-NEXT:    ret
5139entry:
5140  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
5141  ret void
5142}
5143
5144define void @test_vsoxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5145; CHECK-LABEL: test_vsoxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:
5146; CHECK:       # %bb.0: # %entry
5147; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5148; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
5149; CHECK-NEXT:    ret
5150entry:
5151  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5152  ret void
5153}
5154
5155declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i8>, i32, i32)
5156declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5157
5158define void @test_vsoxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5159; CHECK-LABEL: test_vsoxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:
5160; CHECK:       # %bb.0: # %entry
5161; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5162; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
5163; CHECK-NEXT:    ret
5164entry:
5165  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
5166  ret void
5167}
5168
5169define void @test_vsoxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5170; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:
5171; CHECK:       # %bb.0: # %entry
5172; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5173; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
5174; CHECK-NEXT:    ret
5175entry:
5176  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5177  ret void
5178}
5179
5180declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i16>, i32, i32)
5181declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
5182
5183define void @test_vsoxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
5184; CHECK-LABEL: test_vsoxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:
5185; CHECK:       # %bb.0: # %entry
5186; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5187; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
5188; CHECK-NEXT:    ret
5189entry:
5190  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
5191  ret void
5192}
5193
5194define void @test_vsoxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5195; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:
5196; CHECK:       # %bb.0: # %entry
5197; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5198; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
5199; CHECK-NEXT:    ret
5200entry:
5201  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5202  ret void
5203}
5204
5205declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i32>, i32, i32)
5206declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
5207
5208define void @test_vsoxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
5209; CHECK-LABEL: test_vsoxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:
5210; CHECK:       # %bb.0: # %entry
5211; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5212; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
5213; CHECK-NEXT:    ret
5214entry:
5215  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
5216  ret void
5217}
5218
5219define void @test_vsoxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5220; CHECK-LABEL: test_vsoxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:
5221; CHECK:       # %bb.0: # %entry
5222; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5223; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
5224; CHECK-NEXT:    ret
5225entry:
5226  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5227  ret void
5228}
5229
5230declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 2 x i8>, i32, i32)
5231declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
5232
5233define void @test_vsoxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
5234; CHECK-LABEL: test_vsoxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:
5235; CHECK:       # %bb.0: # %entry
5236; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5237; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
5238; CHECK-NEXT:    ret
5239entry:
5240  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
5241  ret void
5242}
5243
5244define void @test_vsoxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5245; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:
5246; CHECK:       # %bb.0: # %entry
5247; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5248; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
5249; CHECK-NEXT:    ret
5250entry:
5251  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5252  ret void
5253}
5254
5255declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 2 x i16>, i32, i32)
5256declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
5257
5258define void @test_vsoxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
5259; CHECK-LABEL: test_vsoxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:
5260; CHECK:       # %bb.0: # %entry
5261; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5262; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
5263; CHECK-NEXT:    ret
5264entry:
5265  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
5266  ret void
5267}
5268
5269define void @test_vsoxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5270; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:
5271; CHECK:       # %bb.0: # %entry
5272; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5273; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
5274; CHECK-NEXT:    ret
5275entry:
5276  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5277  ret void
5278}
5279
5280declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 2 x i32>, i32, i32)
5281declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
5282
5283define void @test_vsoxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
5284; CHECK-LABEL: test_vsoxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:
5285; CHECK:       # %bb.0: # %entry
5286; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5287; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
5288; CHECK-NEXT:    ret
5289entry:
5290  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
5291  ret void
5292}
5293
5294define void @test_vsoxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5295; CHECK-LABEL: test_vsoxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:
5296; CHECK:       # %bb.0: # %entry
5297; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5298; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
5299; CHECK-NEXT:    ret
5300entry:
5301  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5302  ret void
5303}
5304
5305declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i8>, i32, i32)
5306declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5307
5308define void @test_vsoxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5309; CHECK-LABEL: test_vsoxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:
5310; CHECK:       # %bb.0: # %entry
5311; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5312; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
5313; CHECK-NEXT:    ret
5314entry:
5315  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
5316  ret void
5317}
5318
5319define void @test_vsoxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5320; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:
5321; CHECK:       # %bb.0: # %entry
5322; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5323; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
5324; CHECK-NEXT:    ret
5325entry:
5326  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5327  ret void
5328}
5329
5330declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i16>, i32, i32)
5331declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
5332
5333define void @test_vsoxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
5334; CHECK-LABEL: test_vsoxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:
5335; CHECK:       # %bb.0: # %entry
5336; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5337; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
5338; CHECK-NEXT:    ret
5339entry:
5340  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
5341  ret void
5342}
5343
5344define void @test_vsoxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5345; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:
5346; CHECK:       # %bb.0: # %entry
5347; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5348; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
5349; CHECK-NEXT:    ret
5350entry:
5351  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5352  ret void
5353}
5354
5355declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i32>, i32, i32)
5356declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
5357
5358define void @test_vsoxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
5359; CHECK-LABEL: test_vsoxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:
5360; CHECK:       # %bb.0: # %entry
5361; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5362; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
5363; CHECK-NEXT:    ret
5364entry:
5365  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
5366  ret void
5367}
5368
5369define void @test_vsoxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5370; CHECK-LABEL: test_vsoxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:
5371; CHECK:       # %bb.0: # %entry
5372; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5373; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
5374; CHECK-NEXT:    ret
5375entry:
5376  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5377  ret void
5378}
5379
5380declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 2 x i8>, i32, i32)
5381declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
5382
5383define void @test_vsoxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
5384; CHECK-LABEL: test_vsoxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:
5385; CHECK:       # %bb.0: # %entry
5386; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5387; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
5388; CHECK-NEXT:    ret
5389entry:
5390  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
5391  ret void
5392}
5393
5394define void @test_vsoxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5395; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:
5396; CHECK:       # %bb.0: # %entry
5397; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5398; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
5399; CHECK-NEXT:    ret
5400entry:
5401  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5402  ret void
5403}
5404
5405declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 2 x i16>, i32, i32)
5406declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
5407
5408define void @test_vsoxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
5409; CHECK-LABEL: test_vsoxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:
5410; CHECK:       # %bb.0: # %entry
5411; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5412; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
5413; CHECK-NEXT:    ret
5414entry:
5415  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
5416  ret void
5417}
5418
5419define void @test_vsoxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5420; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:
5421; CHECK:       # %bb.0: # %entry
5422; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5423; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
5424; CHECK-NEXT:    ret
5425entry:
5426  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5427  ret void
5428}
5429
5430declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 2 x i32>, i32, i32)
5431declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
5432
5433define void @test_vsoxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
5434; CHECK-LABEL: test_vsoxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:
5435; CHECK:       # %bb.0: # %entry
5436; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5437; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
5438; CHECK-NEXT:    ret
5439entry:
5440  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
5441  ret void
5442}
5443
5444define void @test_vsoxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5445; CHECK-LABEL: test_vsoxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:
5446; CHECK:       # %bb.0: # %entry
5447; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5448; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
5449; CHECK-NEXT:    ret
5450entry:
5451  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5452  ret void
5453}
5454
5455declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i8>, i32, i32)
5456declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5457
5458define void @test_vsoxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5459; CHECK-LABEL: test_vsoxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:
5460; CHECK:       # %bb.0: # %entry
5461; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5462; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
5463; CHECK-NEXT:    ret
5464entry:
5465  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
5466  ret void
5467}
5468
5469define void @test_vsoxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5470; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:
5471; CHECK:       # %bb.0: # %entry
5472; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5473; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
5474; CHECK-NEXT:    ret
5475entry:
5476  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5477  ret void
5478}
5479
5480declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i16>, i32, i32)
5481declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
5482
5483define void @test_vsoxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
5484; CHECK-LABEL: test_vsoxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:
5485; CHECK:       # %bb.0: # %entry
5486; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5487; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
5488; CHECK-NEXT:    ret
5489entry:
5490  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
5491  ret void
5492}
5493
5494define void @test_vsoxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5495; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:
5496; CHECK:       # %bb.0: # %entry
5497; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5498; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
5499; CHECK-NEXT:    ret
5500entry:
5501  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5502  ret void
5503}
5504
5505declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i32>, i32, i32)
5506declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
5507
5508define void @test_vsoxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
5509; CHECK-LABEL: test_vsoxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:
5510; CHECK:       # %bb.0: # %entry
5511; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5512; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
5513; CHECK-NEXT:    ret
5514entry:
5515  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
5516  ret void
5517}
5518
5519define void @test_vsoxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5520; CHECK-LABEL: test_vsoxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:
5521; CHECK:       # %bb.0: # %entry
5522; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
5523; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
5524; CHECK-NEXT:    ret
5525entry:
5526  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
5527  ret void
5528}
5529
5530declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 2 x i8>, i32, i32)
5531declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
5532
5533define void @test_vsoxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
5534; CHECK-LABEL: test_vsoxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:
5535; CHECK:       # %bb.0: # %entry
5536; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5537; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
5538; CHECK-NEXT:    ret
5539entry:
5540  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
5541  ret void
5542}
5543
5544define void @test_vsoxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5545; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:
5546; CHECK:       # %bb.0: # %entry
5547; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5548; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
5549; CHECK-NEXT:    ret
5550entry:
5551  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5552  ret void
5553}
5554
5555declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 2 x i16>, i32, i32)
5556declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
5557
5558define void @test_vsoxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
5559; CHECK-LABEL: test_vsoxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:
5560; CHECK:       # %bb.0: # %entry
5561; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5562; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
5563; CHECK-NEXT:    ret
5564entry:
5565  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
5566  ret void
5567}
5568
5569define void @test_vsoxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5570; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:
5571; CHECK:       # %bb.0: # %entry
5572; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5573; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
5574; CHECK-NEXT:    ret
5575entry:
5576  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5577  ret void
5578}
5579
5580declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 2 x i32>, i32, i32)
5581declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
5582
5583define void @test_vsoxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
5584; CHECK-LABEL: test_vsoxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:
5585; CHECK:       # %bb.0: # %entry
5586; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5587; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
5588; CHECK-NEXT:    ret
5589entry:
5590  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
5591  ret void
5592}
5593
5594define void @test_vsoxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5595; CHECK-LABEL: test_vsoxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:
5596; CHECK:       # %bb.0: # %entry
5597; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
5598; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
5599; CHECK-NEXT:    ret
5600entry:
5601  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
5602  ret void
5603}
5604
5605declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 1 x i8>, i32, i32)
5606declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5607
5608define void @test_vsoxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5609; CHECK-LABEL: test_vsoxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:
5610; CHECK:       # %bb.0: # %entry
5611; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5612; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
5613; CHECK-NEXT:    ret
5614entry:
5615  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
5616  ret void
5617}
5618
5619define void @test_vsoxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5620; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:
5621; CHECK:       # %bb.0: # %entry
5622; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5623; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
5624; CHECK-NEXT:    ret
5625entry:
5626  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
5627  ret void
5628}
5629
5630declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 1 x i16>, i32, i32)
5631declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
5632
5633define void @test_vsoxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
5634; CHECK-LABEL: test_vsoxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:
5635; CHECK:       # %bb.0: # %entry
5636; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5637; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
5638; CHECK-NEXT:    ret
5639entry:
5640  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
5641  ret void
5642}
5643
5644define void @test_vsoxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5645; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:
5646; CHECK:       # %bb.0: # %entry
5647; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5648; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
5649; CHECK-NEXT:    ret
5650entry:
5651  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
5652  ret void
5653}
5654
5655declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 1 x i32>, i32, i32)
5656declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
5657
5658define void @test_vsoxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
5659; CHECK-LABEL: test_vsoxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:
5660; CHECK:       # %bb.0: # %entry
5661; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5662; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
5663; CHECK-NEXT:    ret
5664entry:
5665  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
5666  ret void
5667}
5668
5669define void @test_vsoxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5670; CHECK-LABEL: test_vsoxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:
5671; CHECK:       # %bb.0: # %entry
5672; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5673; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
5674; CHECK-NEXT:    ret
5675entry:
5676  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
5677  ret void
5678}
5679
5680declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 2 x i8>, i32, i32)
5681declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
5682
5683define void @test_vsoxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
5684; CHECK-LABEL: test_vsoxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:
5685; CHECK:       # %bb.0: # %entry
5686; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5687; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
5688; CHECK-NEXT:    ret
5689entry:
5690  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 6)
5691  ret void
5692}
5693
5694define void @test_vsoxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5695; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:
5696; CHECK:       # %bb.0: # %entry
5697; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5698; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
5699; CHECK-NEXT:    ret
5700entry:
5701  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
5702  ret void
5703}
5704
5705declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 2 x i16>, i32, i32)
5706declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
5707
5708define void @test_vsoxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
5709; CHECK-LABEL: test_vsoxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:
5710; CHECK:       # %bb.0: # %entry
5711; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5712; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
5713; CHECK-NEXT:    ret
5714entry:
5715  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 6)
5716  ret void
5717}
5718
5719define void @test_vsoxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5720; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:
5721; CHECK:       # %bb.0: # %entry
5722; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5723; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
5724; CHECK-NEXT:    ret
5725entry:
5726  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
5727  ret void
5728}
5729
5730declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 2 x i32>, i32, i32)
5731declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
5732
5733define void @test_vsoxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
5734; CHECK-LABEL: test_vsoxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:
5735; CHECK:       # %bb.0: # %entry
5736; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5737; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
5738; CHECK-NEXT:    ret
5739entry:
5740  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 6)
5741  ret void
5742}
5743
5744define void @test_vsoxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5745; CHECK-LABEL: test_vsoxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:
5746; CHECK:       # %bb.0: # %entry
5747; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5748; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
5749; CHECK-NEXT:    ret
5750entry:
5751  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
5752  ret void
5753}
5754
5755declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 4 x i8>, i32, i32)
5756declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i32, i32)
5757
5758define void @test_vsoxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
5759; CHECK-LABEL: test_vsoxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:
5760; CHECK:       # %bb.0: # %entry
5761; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
5762; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
5763; CHECK-NEXT:    ret
5764entry:
5765  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 6)
5766  ret void
5767}
5768
5769define void @test_vsoxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
5770; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:
5771; CHECK:       # %bb.0: # %entry
5772; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
5773; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
5774; CHECK-NEXT:    ret
5775entry:
5776  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 6)
5777  ret void
5778}
5779
5780declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 4 x i16>, i32, i32)
5781declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 4 x i16>, <vscale x 4 x i1>, i32, i32)
5782
5783define void @test_vsoxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
5784; CHECK-LABEL: test_vsoxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:
5785; CHECK:       # %bb.0: # %entry
5786; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
5787; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
5788; CHECK-NEXT:    ret
5789entry:
5790  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 6)
5791  ret void
5792}
5793
5794define void @test_vsoxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
5795; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:
5796; CHECK:       # %bb.0: # %entry
5797; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
5798; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
5799; CHECK-NEXT:    ret
5800entry:
5801  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 6)
5802  ret void
5803}
5804
5805declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 4 x i32>, i32, i32)
5806declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2), ptr, <vscale x 4 x i32>, <vscale x 4 x i1>, i32, i32)
5807
5808define void @test_vsoxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
5809; CHECK-LABEL: test_vsoxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:
5810; CHECK:       # %bb.0: # %entry
5811; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
5812; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
5813; CHECK-NEXT:    ret
5814entry:
5815  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 6)
5816  ret void
5817}
5818
5819define void @test_vsoxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
5820; CHECK-LABEL: test_vsoxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:
5821; CHECK:       # %bb.0: # %entry
5822; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
5823; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
5824; CHECK-NEXT:    ret
5825entry:
5826  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 6)
5827  ret void
5828}
5829
5830declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 1 x i8>, i32, i32)
5831declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5832
5833define void @test_vsoxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5834; CHECK-LABEL: test_vsoxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:
5835; CHECK:       # %bb.0: # %entry
5836; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5837; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
5838; CHECK-NEXT:    ret
5839entry:
5840  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
5841  ret void
5842}
5843
5844define void @test_vsoxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5845; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:
5846; CHECK:       # %bb.0: # %entry
5847; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5848; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
5849; CHECK-NEXT:    ret
5850entry:
5851  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
5852  ret void
5853}
5854
5855declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 1 x i16>, i32, i32)
5856declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
5857
5858define void @test_vsoxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
5859; CHECK-LABEL: test_vsoxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:
5860; CHECK:       # %bb.0: # %entry
5861; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5862; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
5863; CHECK-NEXT:    ret
5864entry:
5865  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
5866  ret void
5867}
5868
5869define void @test_vsoxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5870; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:
5871; CHECK:       # %bb.0: # %entry
5872; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5873; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
5874; CHECK-NEXT:    ret
5875entry:
5876  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
5877  ret void
5878}
5879
5880declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 1 x i32>, i32, i32)
5881declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
5882
5883define void @test_vsoxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
5884; CHECK-LABEL: test_vsoxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:
5885; CHECK:       # %bb.0: # %entry
5886; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5887; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
5888; CHECK-NEXT:    ret
5889entry:
5890  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
5891  ret void
5892}
5893
5894define void @test_vsoxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5895; CHECK-LABEL: test_vsoxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:
5896; CHECK:       # %bb.0: # %entry
5897; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5898; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
5899; CHECK-NEXT:    ret
5900entry:
5901  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
5902  ret void
5903}
5904
5905declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 2 x i8>, i32, i32)
5906declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
5907
5908define void @test_vsoxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
5909; CHECK-LABEL: test_vsoxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:
5910; CHECK:       # %bb.0: # %entry
5911; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5912; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
5913; CHECK-NEXT:    ret
5914entry:
5915  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 6)
5916  ret void
5917}
5918
5919define void @test_vsoxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5920; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:
5921; CHECK:       # %bb.0: # %entry
5922; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5923; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
5924; CHECK-NEXT:    ret
5925entry:
5926  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
5927  ret void
5928}
5929
5930declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 2 x i16>, i32, i32)
5931declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
5932
5933define void @test_vsoxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
5934; CHECK-LABEL: test_vsoxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:
5935; CHECK:       # %bb.0: # %entry
5936; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5937; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
5938; CHECK-NEXT:    ret
5939entry:
5940  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 6)
5941  ret void
5942}
5943
5944define void @test_vsoxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5945; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:
5946; CHECK:       # %bb.0: # %entry
5947; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5948; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
5949; CHECK-NEXT:    ret
5950entry:
5951  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
5952  ret void
5953}
5954
5955declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 2 x i32>, i32, i32)
5956declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
5957
5958define void @test_vsoxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
5959; CHECK-LABEL: test_vsoxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:
5960; CHECK:       # %bb.0: # %entry
5961; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5962; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14
5963; CHECK-NEXT:    ret
5964entry:
5965  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 6)
5966  ret void
5967}
5968
5969define void @test_vsoxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
5970; CHECK-LABEL: test_vsoxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:
5971; CHECK:       # %bb.0: # %entry
5972; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
5973; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14, v0.t
5974; CHECK-NEXT:    ret
5975entry:
5976  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
5977  ret void
5978}
5979
5980declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 1 x i8>, i32, i32)
5981declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
5982
5983define void @test_vsoxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
5984; CHECK-LABEL: test_vsoxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:
5985; CHECK:       # %bb.0: # %entry
5986; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5987; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
5988; CHECK-NEXT:    ret
5989entry:
5990  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
5991  ret void
5992}
5993
5994define void @test_vsoxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
5995; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:
5996; CHECK:       # %bb.0: # %entry
5997; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
5998; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
5999; CHECK-NEXT:    ret
6000entry:
6001  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6002  ret void
6003}
6004
6005declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 1 x i16>, i32, i32)
6006declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
6007
6008define void @test_vsoxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6009; CHECK-LABEL: test_vsoxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:
6010; CHECK:       # %bb.0: # %entry
6011; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6012; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
6013; CHECK-NEXT:    ret
6014entry:
6015  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
6016  ret void
6017}
6018
6019define void @test_vsoxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6020; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:
6021; CHECK:       # %bb.0: # %entry
6022; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6023; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
6024; CHECK-NEXT:    ret
6025entry:
6026  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6027  ret void
6028}
6029
6030declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 1 x i32>, i32, i32)
6031declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
6032
6033define void @test_vsoxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6034; CHECK-LABEL: test_vsoxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:
6035; CHECK:       # %bb.0: # %entry
6036; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6037; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
6038; CHECK-NEXT:    ret
6039entry:
6040  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
6041  ret void
6042}
6043
6044define void @test_vsoxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6045; CHECK-LABEL: test_vsoxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:
6046; CHECK:       # %bb.0: # %entry
6047; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6048; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
6049; CHECK-NEXT:    ret
6050entry:
6051  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6052  ret void
6053}
6054
6055declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 2 x i8>, i32, i32)
6056declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 2 x i8>, <vscale x 2 x i1>, i32, i32)
6057
6058define void @test_vsoxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
6059; CHECK-LABEL: test_vsoxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:
6060; CHECK:       # %bb.0: # %entry
6061; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
6062; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
6063; CHECK-NEXT:    ret
6064entry:
6065  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 6)
6066  ret void
6067}
6068
6069define void @test_vsoxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6070; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:
6071; CHECK:       # %bb.0: # %entry
6072; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
6073; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
6074; CHECK-NEXT:    ret
6075entry:
6076  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
6077  ret void
6078}
6079
6080declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 2 x i16>, i32, i32)
6081declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 2 x i16>, <vscale x 2 x i1>, i32, i32)
6082
6083define void @test_vsoxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
6084; CHECK-LABEL: test_vsoxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:
6085; CHECK:       # %bb.0: # %entry
6086; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
6087; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
6088; CHECK-NEXT:    ret
6089entry:
6090  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 6)
6091  ret void
6092}
6093
6094define void @test_vsoxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6095; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:
6096; CHECK:       # %bb.0: # %entry
6097; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
6098; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
6099; CHECK-NEXT:    ret
6100entry:
6101  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
6102  ret void
6103}
6104
6105declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 2 x i32>, i32, i32)
6106declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4), ptr, <vscale x 2 x i32>, <vscale x 2 x i1>, i32, i32)
6107
6108define void @test_vsoxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
6109; CHECK-LABEL: test_vsoxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:
6110; CHECK:       # %bb.0: # %entry
6111; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
6112; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
6113; CHECK-NEXT:    ret
6114entry:
6115  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 6)
6116  ret void
6117}
6118
6119define void @test_vsoxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6120; CHECK-LABEL: test_vsoxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:
6121; CHECK:       # %bb.0: # %entry
6122; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
6123; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
6124; CHECK-NEXT:    ret
6125entry:
6126  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
6127  ret void
6128}
6129
6130declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 1 x i8>, i32, i32)
6131declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
6132
6133define void @test_vsoxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
6134; CHECK-LABEL: test_vsoxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:
6135; CHECK:       # %bb.0: # %entry
6136; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6137; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
6138; CHECK-NEXT:    ret
6139entry:
6140  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
6141  ret void
6142}
6143
6144define void @test_vsoxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6145; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:
6146; CHECK:       # %bb.0: # %entry
6147; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6148; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
6149; CHECK-NEXT:    ret
6150entry:
6151  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6152  ret void
6153}
6154
6155declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 1 x i16>, i32, i32)
6156declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
6157
6158define void @test_vsoxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6159; CHECK-LABEL: test_vsoxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:
6160; CHECK:       # %bb.0: # %entry
6161; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6162; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
6163; CHECK-NEXT:    ret
6164entry:
6165  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
6166  ret void
6167}
6168
6169define void @test_vsoxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6170; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:
6171; CHECK:       # %bb.0: # %entry
6172; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6173; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
6174; CHECK-NEXT:    ret
6175entry:
6176  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6177  ret void
6178}
6179
6180declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 1 x i32>, i32, i32)
6181declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
6182
6183define void @test_vsoxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6184; CHECK-LABEL: test_vsoxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:
6185; CHECK:       # %bb.0: # %entry
6186; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6187; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
6188; CHECK-NEXT:    ret
6189entry:
6190  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
6191  ret void
6192}
6193
6194define void @test_vsoxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6195; CHECK-LABEL: test_vsoxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:
6196; CHECK:       # %bb.0: # %entry
6197; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6198; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
6199; CHECK-NEXT:    ret
6200entry:
6201  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6202  ret void
6203}
6204
6205declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 1 x i8>, i32, i32)
6206declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
6207
6208define void @test_vsoxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
6209; CHECK-LABEL: test_vsoxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:
6210; CHECK:       # %bb.0: # %entry
6211; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6212; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
6213; CHECK-NEXT:    ret
6214entry:
6215  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
6216  ret void
6217}
6218
6219define void @test_vsoxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6220; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:
6221; CHECK:       # %bb.0: # %entry
6222; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6223; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
6224; CHECK-NEXT:    ret
6225entry:
6226  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6227  ret void
6228}
6229
6230declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 1 x i16>, i32, i32)
6231declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
6232
6233define void @test_vsoxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6234; CHECK-LABEL: test_vsoxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:
6235; CHECK:       # %bb.0: # %entry
6236; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6237; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
6238; CHECK-NEXT:    ret
6239entry:
6240  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
6241  ret void
6242}
6243
6244define void @test_vsoxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6245; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:
6246; CHECK:       # %bb.0: # %entry
6247; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6248; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
6249; CHECK-NEXT:    ret
6250entry:
6251  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6252  ret void
6253}
6254
6255declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 1 x i32>, i32, i32)
6256declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
6257
6258define void @test_vsoxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6259; CHECK-LABEL: test_vsoxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:
6260; CHECK:       # %bb.0: # %entry
6261; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6262; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
6263; CHECK-NEXT:    ret
6264entry:
6265  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
6266  ret void
6267}
6268
6269define void @test_vsoxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6270; CHECK-LABEL: test_vsoxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:
6271; CHECK:       # %bb.0: # %entry
6272; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6273; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
6274; CHECK-NEXT:    ret
6275entry:
6276  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6277  ret void
6278}
6279
6280declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 1 x i8>, i32, i32)
6281declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
6282
6283define void @test_vsoxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
6284; CHECK-LABEL: test_vsoxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:
6285; CHECK:       # %bb.0: # %entry
6286; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6287; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
6288; CHECK-NEXT:    ret
6289entry:
6290  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
6291  ret void
6292}
6293
6294define void @test_vsoxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6295; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:
6296; CHECK:       # %bb.0: # %entry
6297; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6298; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
6299; CHECK-NEXT:    ret
6300entry:
6301  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6302  ret void
6303}
6304
6305declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 1 x i16>, i32, i32)
6306declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
6307
6308define void @test_vsoxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6309; CHECK-LABEL: test_vsoxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:
6310; CHECK:       # %bb.0: # %entry
6311; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6312; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
6313; CHECK-NEXT:    ret
6314entry:
6315  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
6316  ret void
6317}
6318
6319define void @test_vsoxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6320; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:
6321; CHECK:       # %bb.0: # %entry
6322; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6323; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
6324; CHECK-NEXT:    ret
6325entry:
6326  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6327  ret void
6328}
6329
6330declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 1 x i32>, i32, i32)
6331declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
6332
6333define void @test_vsoxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6334; CHECK-LABEL: test_vsoxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:
6335; CHECK:       # %bb.0: # %entry
6336; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6337; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
6338; CHECK-NEXT:    ret
6339entry:
6340  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
6341  ret void
6342}
6343
6344define void @test_vsoxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6345; CHECK-LABEL: test_vsoxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:
6346; CHECK:       # %bb.0: # %entry
6347; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6348; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
6349; CHECK-NEXT:    ret
6350entry:
6351  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6352  ret void
6353}
6354
6355declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 1 x i8>, i32, i32)
6356declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 1 x i8>, <vscale x 1 x i1>, i32, i32)
6357
6358define void @test_vsoxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
6359; CHECK-LABEL: test_vsoxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:
6360; CHECK:       # %bb.0: # %entry
6361; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6362; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
6363; CHECK-NEXT:    ret
6364entry:
6365  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
6366  ret void
6367}
6368
6369define void @test_vsoxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6370; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:
6371; CHECK:       # %bb.0: # %entry
6372; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6373; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
6374; CHECK-NEXT:    ret
6375entry:
6376  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6377  ret void
6378}
6379
6380declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 1 x i16>, i32, i32)
6381declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i32, i32)
6382
6383define void @test_vsoxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6384; CHECK-LABEL: test_vsoxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:
6385; CHECK:       # %bb.0: # %entry
6386; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6387; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
6388; CHECK-NEXT:    ret
6389entry:
6390  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
6391  ret void
6392}
6393
6394define void @test_vsoxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6395; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:
6396; CHECK:       # %bb.0: # %entry
6397; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6398; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
6399; CHECK-NEXT:    ret
6400entry:
6401  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6402  ret void
6403}
6404
6405declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 1 x i32>, i32, i32)
6406declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8), ptr, <vscale x 1 x i32>, <vscale x 1 x i1>, i32, i32)
6407
6408define void @test_vsoxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6409; CHECK-LABEL: test_vsoxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:
6410; CHECK:       # %bb.0: # %entry
6411; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6412; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
6413; CHECK-NEXT:    ret
6414entry:
6415  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
6416  ret void
6417}
6418
6419define void @test_vsoxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6420; CHECK-LABEL: test_vsoxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:
6421; CHECK:       # %bb.0: # %entry
6422; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
6423; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
6424; CHECK-NEXT:    ret
6425entry:
6426  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
6427  ret void
6428}
6429
6430
6431define void @test_vsoxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
6432; CHECK-LABEL: test_vsoxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:
6433; CHECK:       # %bb.0: # %entry
6434; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6435; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
6436; CHECK-NEXT:    ret
6437entry:
6438  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
6439  ret void
6440}
6441
6442define void @test_vsoxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6443; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:
6444; CHECK:       # %bb.0: # %entry
6445; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6446; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
6447; CHECK-NEXT:    ret
6448entry:
6449  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
6450  ret void
6451}
6452
6453
6454define void @test_vsoxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6455; CHECK-LABEL: test_vsoxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:
6456; CHECK:       # %bb.0: # %entry
6457; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6458; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
6459; CHECK-NEXT:    ret
6460entry:
6461  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
6462  ret void
6463}
6464
6465define void @test_vsoxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6466; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:
6467; CHECK:       # %bb.0: # %entry
6468; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6469; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
6470; CHECK-NEXT:    ret
6471entry:
6472  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
6473  ret void
6474}
6475
6476
6477define void @test_vsoxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6478; CHECK-LABEL: test_vsoxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:
6479; CHECK:       # %bb.0: # %entry
6480; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6481; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
6482; CHECK-NEXT:    ret
6483entry:
6484  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
6485  ret void
6486}
6487
6488define void @test_vsoxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6489; CHECK-LABEL: test_vsoxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:
6490; CHECK:       # %bb.0: # %entry
6491; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6492; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
6493; CHECK-NEXT:    ret
6494entry:
6495  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
6496  ret void
6497}
6498
6499
6500define void @test_vsoxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
6501; CHECK-LABEL: test_vsoxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:
6502; CHECK:       # %bb.0: # %entry
6503; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6504; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
6505; CHECK-NEXT:    ret
6506entry:
6507  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
6508  ret void
6509}
6510
6511define void @test_vsoxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6512; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:
6513; CHECK:       # %bb.0: # %entry
6514; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6515; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
6516; CHECK-NEXT:    ret
6517entry:
6518  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
6519  ret void
6520}
6521
6522
6523define void @test_vsoxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
6524; CHECK-LABEL: test_vsoxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:
6525; CHECK:       # %bb.0: # %entry
6526; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6527; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
6528; CHECK-NEXT:    ret
6529entry:
6530  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
6531  ret void
6532}
6533
6534define void @test_vsoxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6535; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:
6536; CHECK:       # %bb.0: # %entry
6537; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6538; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
6539; CHECK-NEXT:    ret
6540entry:
6541  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
6542  ret void
6543}
6544
6545
6546define void @test_vsoxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
6547; CHECK-LABEL: test_vsoxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:
6548; CHECK:       # %bb.0: # %entry
6549; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6550; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
6551; CHECK-NEXT:    ret
6552entry:
6553  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
6554  ret void
6555}
6556
6557define void @test_vsoxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6558; CHECK-LABEL: test_vsoxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:
6559; CHECK:       # %bb.0: # %entry
6560; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6561; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
6562; CHECK-NEXT:    ret
6563entry:
6564  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
6565  ret void
6566}
6567
6568
6569define void @test_vsoxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
6570; CHECK-LABEL: test_vsoxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:
6571; CHECK:       # %bb.0: # %entry
6572; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6573; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
6574; CHECK-NEXT:    ret
6575entry:
6576  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
6577  ret void
6578}
6579
6580define void @test_vsoxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
6581; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:
6582; CHECK:       # %bb.0: # %entry
6583; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6584; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
6585; CHECK-NEXT:    ret
6586entry:
6587  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
6588  ret void
6589}
6590
6591
6592define void @test_vsoxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
6593; CHECK-LABEL: test_vsoxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:
6594; CHECK:       # %bb.0: # %entry
6595; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6596; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
6597; CHECK-NEXT:    ret
6598entry:
6599  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
6600  ret void
6601}
6602
6603define void @test_vsoxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
6604; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:
6605; CHECK:       # %bb.0: # %entry
6606; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6607; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
6608; CHECK-NEXT:    ret
6609entry:
6610  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
6611  ret void
6612}
6613
6614
6615define void @test_vsoxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
6616; CHECK-LABEL: test_vsoxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:
6617; CHECK:       # %bb.0: # %entry
6618; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6619; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
6620; CHECK-NEXT:    ret
6621entry:
6622  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
6623  ret void
6624}
6625
6626define void @test_vsoxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
6627; CHECK-LABEL: test_vsoxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:
6628; CHECK:       # %bb.0: # %entry
6629; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6630; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
6631; CHECK-NEXT:    ret
6632entry:
6633  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
6634  ret void
6635}
6636
6637
6638define void @test_vsoxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
6639; CHECK-LABEL: test_vsoxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:
6640; CHECK:       # %bb.0: # %entry
6641; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6642; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
6643; CHECK-NEXT:    ret
6644entry:
6645  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
6646  ret void
6647}
6648
6649define void @test_vsoxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
6650; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:
6651; CHECK:       # %bb.0: # %entry
6652; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6653; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
6654; CHECK-NEXT:    ret
6655entry:
6656  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
6657  ret void
6658}
6659
6660
6661define void @test_vsoxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
6662; CHECK-LABEL: test_vsoxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:
6663; CHECK:       # %bb.0: # %entry
6664; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6665; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
6666; CHECK-NEXT:    ret
6667entry:
6668  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
6669  ret void
6670}
6671
6672define void @test_vsoxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
6673; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:
6674; CHECK:       # %bb.0: # %entry
6675; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6676; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
6677; CHECK-NEXT:    ret
6678entry:
6679  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
6680  ret void
6681}
6682
6683
6684define void @test_vsoxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
6685; CHECK-LABEL: test_vsoxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:
6686; CHECK:       # %bb.0: # %entry
6687; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6688; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
6689; CHECK-NEXT:    ret
6690entry:
6691  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
6692  ret void
6693}
6694
6695define void @test_vsoxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
6696; CHECK-LABEL: test_vsoxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:
6697; CHECK:       # %bb.0: # %entry
6698; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6699; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
6700; CHECK-NEXT:    ret
6701entry:
6702  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
6703  ret void
6704}
6705
6706
6707define void @test_vsoxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl) {
6708; CHECK-LABEL: test_vsoxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:
6709; CHECK:       # %bb.0: # %entry
6710; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
6711; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
6712; CHECK-NEXT:    ret
6713entry:
6714  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, i32 4)
6715  ret void
6716}
6717
6718define void @test_vsoxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 16 x i1> %mask) {
6719; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:
6720; CHECK:       # %bb.0: # %entry
6721; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
6722; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
6723; CHECK-NEXT:    ret
6724entry:
6725  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
6726  ret void
6727}
6728
6729
6730define void @test_vsoxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl) {
6731; CHECK-LABEL: test_vsoxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:
6732; CHECK:       # %bb.0: # %entry
6733; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
6734; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
6735; CHECK-NEXT:    ret
6736entry:
6737  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, i32 4)
6738  ret void
6739}
6740
6741define void @test_vsoxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 16 x i1> %mask) {
6742; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:
6743; CHECK:       # %bb.0: # %entry
6744; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
6745; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
6746; CHECK-NEXT:    ret
6747entry:
6748  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
6749  ret void
6750}
6751
6752
6753define void @test_vsoxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl) {
6754; CHECK-LABEL: test_vsoxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:
6755; CHECK:       # %bb.0: # %entry
6756; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
6757; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
6758; CHECK-NEXT:    ret
6759entry:
6760  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, i32 4)
6761  ret void
6762}
6763
6764define void @test_vsoxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 16 x i1> %mask) {
6765; CHECK-LABEL: test_vsoxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:
6766; CHECK:       # %bb.0: # %entry
6767; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
6768; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
6769; CHECK-NEXT:    ret
6770entry:
6771  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
6772  ret void
6773}
6774
6775
6776define void @test_vsoxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
6777; CHECK-LABEL: test_vsoxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:
6778; CHECK:       # %bb.0: # %entry
6779; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6780; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
6781; CHECK-NEXT:    ret
6782entry:
6783  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
6784  ret void
6785}
6786
6787define void @test_vsoxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6788; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:
6789; CHECK:       # %bb.0: # %entry
6790; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6791; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
6792; CHECK-NEXT:    ret
6793entry:
6794  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
6795  ret void
6796}
6797
6798
6799define void @test_vsoxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
6800; CHECK-LABEL: test_vsoxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:
6801; CHECK:       # %bb.0: # %entry
6802; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6803; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
6804; CHECK-NEXT:    ret
6805entry:
6806  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
6807  ret void
6808}
6809
6810define void @test_vsoxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6811; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:
6812; CHECK:       # %bb.0: # %entry
6813; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6814; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
6815; CHECK-NEXT:    ret
6816entry:
6817  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
6818  ret void
6819}
6820
6821
6822define void @test_vsoxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
6823; CHECK-LABEL: test_vsoxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:
6824; CHECK:       # %bb.0: # %entry
6825; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6826; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
6827; CHECK-NEXT:    ret
6828entry:
6829  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
6830  ret void
6831}
6832
6833define void @test_vsoxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
6834; CHECK-LABEL: test_vsoxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:
6835; CHECK:       # %bb.0: # %entry
6836; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
6837; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
6838; CHECK-NEXT:    ret
6839entry:
6840  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
6841  ret void
6842}
6843
6844
6845define void @test_vsoxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
6846; CHECK-LABEL: test_vsoxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:
6847; CHECK:       # %bb.0: # %entry
6848; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6849; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
6850; CHECK-NEXT:    ret
6851entry:
6852  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
6853  ret void
6854}
6855
6856define void @test_vsoxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6857; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:
6858; CHECK:       # %bb.0: # %entry
6859; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6860; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
6861; CHECK-NEXT:    ret
6862entry:
6863  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
6864  ret void
6865}
6866
6867
6868define void @test_vsoxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
6869; CHECK-LABEL: test_vsoxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:
6870; CHECK:       # %bb.0: # %entry
6871; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6872; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
6873; CHECK-NEXT:    ret
6874entry:
6875  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
6876  ret void
6877}
6878
6879define void @test_vsoxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6880; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:
6881; CHECK:       # %bb.0: # %entry
6882; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6883; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
6884; CHECK-NEXT:    ret
6885entry:
6886  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
6887  ret void
6888}
6889
6890
6891define void @test_vsoxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
6892; CHECK-LABEL: test_vsoxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:
6893; CHECK:       # %bb.0: # %entry
6894; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6895; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
6896; CHECK-NEXT:    ret
6897entry:
6898  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
6899  ret void
6900}
6901
6902define void @test_vsoxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
6903; CHECK-LABEL: test_vsoxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:
6904; CHECK:       # %bb.0: # %entry
6905; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
6906; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
6907; CHECK-NEXT:    ret
6908entry:
6909  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
6910  ret void
6911}
6912
6913
6914define void @test_vsoxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
6915; CHECK-LABEL: test_vsoxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:
6916; CHECK:       # %bb.0: # %entry
6917; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6918; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
6919; CHECK-NEXT:    ret
6920entry:
6921  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
6922  ret void
6923}
6924
6925define void @test_vsoxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
6926; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:
6927; CHECK:       # %bb.0: # %entry
6928; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6929; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
6930; CHECK-NEXT:    ret
6931entry:
6932  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
6933  ret void
6934}
6935
6936
6937define void @test_vsoxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
6938; CHECK-LABEL: test_vsoxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:
6939; CHECK:       # %bb.0: # %entry
6940; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6941; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
6942; CHECK-NEXT:    ret
6943entry:
6944  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
6945  ret void
6946}
6947
6948define void @test_vsoxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
6949; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:
6950; CHECK:       # %bb.0: # %entry
6951; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6952; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
6953; CHECK-NEXT:    ret
6954entry:
6955  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
6956  ret void
6957}
6958
6959
6960define void @test_vsoxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
6961; CHECK-LABEL: test_vsoxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:
6962; CHECK:       # %bb.0: # %entry
6963; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6964; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12
6965; CHECK-NEXT:    ret
6966entry:
6967  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
6968  ret void
6969}
6970
6971define void @test_vsoxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
6972; CHECK-LABEL: test_vsoxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:
6973; CHECK:       # %bb.0: # %entry
6974; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
6975; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12, v0.t
6976; CHECK-NEXT:    ret
6977entry:
6978  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
6979  ret void
6980}
6981
6982
6983define void @test_vsoxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
6984; CHECK-LABEL: test_vsoxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:
6985; CHECK:       # %bb.0: # %entry
6986; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6987; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
6988; CHECK-NEXT:    ret
6989entry:
6990  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
6991  ret void
6992}
6993
6994define void @test_vsoxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
6995; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:
6996; CHECK:       # %bb.0: # %entry
6997; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
6998; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
6999; CHECK-NEXT:    ret
7000entry:
7001  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
7002  ret void
7003}
7004
7005
7006define void @test_vsoxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
7007; CHECK-LABEL: test_vsoxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:
7008; CHECK:       # %bb.0: # %entry
7009; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7010; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
7011; CHECK-NEXT:    ret
7012entry:
7013  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
7014  ret void
7015}
7016
7017define void @test_vsoxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
7018; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:
7019; CHECK:       # %bb.0: # %entry
7020; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7021; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
7022; CHECK-NEXT:    ret
7023entry:
7024  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
7025  ret void
7026}
7027
7028
7029define void @test_vsoxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
7030; CHECK-LABEL: test_vsoxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:
7031; CHECK:       # %bb.0: # %entry
7032; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7033; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16
7034; CHECK-NEXT:    ret
7035entry:
7036  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
7037  ret void
7038}
7039
7040define void @test_vsoxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
7041; CHECK-LABEL: test_vsoxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:
7042; CHECK:       # %bb.0: # %entry
7043; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7044; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16, v0.t
7045; CHECK-NEXT:    ret
7046entry:
7047  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
7048  ret void
7049}
7050
7051
7052define void @test_vsoxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
7053; CHECK-LABEL: test_vsoxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:
7054; CHECK:       # %bb.0: # %entry
7055; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7056; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
7057; CHECK-NEXT:    ret
7058entry:
7059  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
7060  ret void
7061}
7062
7063define void @test_vsoxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7064; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:
7065; CHECK:       # %bb.0: # %entry
7066; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7067; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
7068; CHECK-NEXT:    ret
7069entry:
7070  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7071  ret void
7072}
7073
7074
7075define void @test_vsoxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
7076; CHECK-LABEL: test_vsoxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:
7077; CHECK:       # %bb.0: # %entry
7078; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7079; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
7080; CHECK-NEXT:    ret
7081entry:
7082  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
7083  ret void
7084}
7085
7086define void @test_vsoxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7087; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:
7088; CHECK:       # %bb.0: # %entry
7089; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7090; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
7091; CHECK-NEXT:    ret
7092entry:
7093  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7094  ret void
7095}
7096
7097
7098define void @test_vsoxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
7099; CHECK-LABEL: test_vsoxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:
7100; CHECK:       # %bb.0: # %entry
7101; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7102; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
7103; CHECK-NEXT:    ret
7104entry:
7105  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
7106  ret void
7107}
7108
7109define void @test_vsoxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7110; CHECK-LABEL: test_vsoxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:
7111; CHECK:       # %bb.0: # %entry
7112; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7113; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
7114; CHECK-NEXT:    ret
7115entry:
7116  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7117  ret void
7118}
7119
7120
7121define void @test_vsoxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
7122; CHECK-LABEL: test_vsoxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:
7123; CHECK:       # %bb.0: # %entry
7124; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7125; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
7126; CHECK-NEXT:    ret
7127entry:
7128  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
7129  ret void
7130}
7131
7132define void @test_vsoxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7133; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:
7134; CHECK:       # %bb.0: # %entry
7135; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7136; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
7137; CHECK-NEXT:    ret
7138entry:
7139  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7140  ret void
7141}
7142
7143
7144define void @test_vsoxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
7145; CHECK-LABEL: test_vsoxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:
7146; CHECK:       # %bb.0: # %entry
7147; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7148; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
7149; CHECK-NEXT:    ret
7150entry:
7151  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
7152  ret void
7153}
7154
7155define void @test_vsoxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7156; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:
7157; CHECK:       # %bb.0: # %entry
7158; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7159; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
7160; CHECK-NEXT:    ret
7161entry:
7162  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7163  ret void
7164}
7165
7166
7167define void @test_vsoxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
7168; CHECK-LABEL: test_vsoxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:
7169; CHECK:       # %bb.0: # %entry
7170; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7171; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
7172; CHECK-NEXT:    ret
7173entry:
7174  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
7175  ret void
7176}
7177
7178define void @test_vsoxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7179; CHECK-LABEL: test_vsoxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:
7180; CHECK:       # %bb.0: # %entry
7181; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7182; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
7183; CHECK-NEXT:    ret
7184entry:
7185  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7186  ret void
7187}
7188
7189
7190define void @test_vsoxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
7191; CHECK-LABEL: test_vsoxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:
7192; CHECK:       # %bb.0: # %entry
7193; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7194; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
7195; CHECK-NEXT:    ret
7196entry:
7197  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
7198  ret void
7199}
7200
7201define void @test_vsoxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7202; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:
7203; CHECK:       # %bb.0: # %entry
7204; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7205; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
7206; CHECK-NEXT:    ret
7207entry:
7208  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7209  ret void
7210}
7211
7212
7213define void @test_vsoxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
7214; CHECK-LABEL: test_vsoxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:
7215; CHECK:       # %bb.0: # %entry
7216; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7217; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
7218; CHECK-NEXT:    ret
7219entry:
7220  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
7221  ret void
7222}
7223
7224define void @test_vsoxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7225; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:
7226; CHECK:       # %bb.0: # %entry
7227; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7228; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
7229; CHECK-NEXT:    ret
7230entry:
7231  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7232  ret void
7233}
7234
7235
7236define void @test_vsoxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
7237; CHECK-LABEL: test_vsoxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:
7238; CHECK:       # %bb.0: # %entry
7239; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7240; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
7241; CHECK-NEXT:    ret
7242entry:
7243  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
7244  ret void
7245}
7246
7247define void @test_vsoxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7248; CHECK-LABEL: test_vsoxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:
7249; CHECK:       # %bb.0: # %entry
7250; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7251; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
7252; CHECK-NEXT:    ret
7253entry:
7254  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7255  ret void
7256}
7257
7258
7259define void @test_vsoxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
7260; CHECK-LABEL: test_vsoxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:
7261; CHECK:       # %bb.0: # %entry
7262; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7263; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
7264; CHECK-NEXT:    ret
7265entry:
7266  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
7267  ret void
7268}
7269
7270define void @test_vsoxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
7271; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:
7272; CHECK:       # %bb.0: # %entry
7273; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7274; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
7275; CHECK-NEXT:    ret
7276entry:
7277  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
7278  ret void
7279}
7280
7281
7282define void @test_vsoxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
7283; CHECK-LABEL: test_vsoxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:
7284; CHECK:       # %bb.0: # %entry
7285; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7286; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
7287; CHECK-NEXT:    ret
7288entry:
7289  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
7290  ret void
7291}
7292
7293define void @test_vsoxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
7294; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:
7295; CHECK:       # %bb.0: # %entry
7296; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7297; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
7298; CHECK-NEXT:    ret
7299entry:
7300  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
7301  ret void
7302}
7303
7304
7305define void @test_vsoxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
7306; CHECK-LABEL: test_vsoxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:
7307; CHECK:       # %bb.0: # %entry
7308; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7309; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
7310; CHECK-NEXT:    ret
7311entry:
7312  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
7313  ret void
7314}
7315
7316define void @test_vsoxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
7317; CHECK-LABEL: test_vsoxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:
7318; CHECK:       # %bb.0: # %entry
7319; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
7320; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
7321; CHECK-NEXT:    ret
7322entry:
7323  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
7324  ret void
7325}
7326
7327
7328define void @test_vsoxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
7329; CHECK-LABEL: test_vsoxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:
7330; CHECK:       # %bb.0: # %entry
7331; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7332; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
7333; CHECK-NEXT:    ret
7334entry:
7335  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
7336  ret void
7337}
7338
7339define void @test_vsoxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7340; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:
7341; CHECK:       # %bb.0: # %entry
7342; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7343; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
7344; CHECK-NEXT:    ret
7345entry:
7346  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7347  ret void
7348}
7349
7350
7351define void @test_vsoxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
7352; CHECK-LABEL: test_vsoxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:
7353; CHECK:       # %bb.0: # %entry
7354; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7355; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
7356; CHECK-NEXT:    ret
7357entry:
7358  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
7359  ret void
7360}
7361
7362define void @test_vsoxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7363; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:
7364; CHECK:       # %bb.0: # %entry
7365; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7366; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
7367; CHECK-NEXT:    ret
7368entry:
7369  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7370  ret void
7371}
7372
7373
7374define void @test_vsoxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
7375; CHECK-LABEL: test_vsoxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:
7376; CHECK:       # %bb.0: # %entry
7377; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7378; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
7379; CHECK-NEXT:    ret
7380entry:
7381  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
7382  ret void
7383}
7384
7385define void @test_vsoxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7386; CHECK-LABEL: test_vsoxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:
7387; CHECK:       # %bb.0: # %entry
7388; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7389; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
7390; CHECK-NEXT:    ret
7391entry:
7392  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7393  ret void
7394}
7395
7396
7397define void @test_vsoxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
7398; CHECK-LABEL: test_vsoxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:
7399; CHECK:       # %bb.0: # %entry
7400; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7401; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
7402; CHECK-NEXT:    ret
7403entry:
7404  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
7405  ret void
7406}
7407
7408define void @test_vsoxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7409; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:
7410; CHECK:       # %bb.0: # %entry
7411; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7412; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
7413; CHECK-NEXT:    ret
7414entry:
7415  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7416  ret void
7417}
7418
7419
7420define void @test_vsoxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
7421; CHECK-LABEL: test_vsoxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:
7422; CHECK:       # %bb.0: # %entry
7423; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7424; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
7425; CHECK-NEXT:    ret
7426entry:
7427  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
7428  ret void
7429}
7430
7431define void @test_vsoxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7432; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:
7433; CHECK:       # %bb.0: # %entry
7434; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7435; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
7436; CHECK-NEXT:    ret
7437entry:
7438  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7439  ret void
7440}
7441
7442
7443define void @test_vsoxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
7444; CHECK-LABEL: test_vsoxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:
7445; CHECK:       # %bb.0: # %entry
7446; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7447; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
7448; CHECK-NEXT:    ret
7449entry:
7450  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
7451  ret void
7452}
7453
7454define void @test_vsoxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7455; CHECK-LABEL: test_vsoxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:
7456; CHECK:       # %bb.0: # %entry
7457; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7458; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
7459; CHECK-NEXT:    ret
7460entry:
7461  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7462  ret void
7463}
7464
7465
7466define void @test_vsoxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
7467; CHECK-LABEL: test_vsoxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:
7468; CHECK:       # %bb.0: # %entry
7469; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7470; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
7471; CHECK-NEXT:    ret
7472entry:
7473  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
7474  ret void
7475}
7476
7477define void @test_vsoxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7478; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:
7479; CHECK:       # %bb.0: # %entry
7480; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7481; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
7482; CHECK-NEXT:    ret
7483entry:
7484  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7485  ret void
7486}
7487
7488
7489define void @test_vsoxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
7490; CHECK-LABEL: test_vsoxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:
7491; CHECK:       # %bb.0: # %entry
7492; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7493; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
7494; CHECK-NEXT:    ret
7495entry:
7496  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
7497  ret void
7498}
7499
7500define void @test_vsoxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7501; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:
7502; CHECK:       # %bb.0: # %entry
7503; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7504; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
7505; CHECK-NEXT:    ret
7506entry:
7507  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7508  ret void
7509}
7510
7511
7512define void @test_vsoxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
7513; CHECK-LABEL: test_vsoxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:
7514; CHECK:       # %bb.0: # %entry
7515; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7516; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14
7517; CHECK-NEXT:    ret
7518entry:
7519  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
7520  ret void
7521}
7522
7523define void @test_vsoxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7524; CHECK-LABEL: test_vsoxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:
7525; CHECK:       # %bb.0: # %entry
7526; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7527; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14, v0.t
7528; CHECK-NEXT:    ret
7529entry:
7530  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7531  ret void
7532}
7533
7534
7535define void @test_vsoxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
7536; CHECK-LABEL: test_vsoxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:
7537; CHECK:       # %bb.0: # %entry
7538; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7539; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
7540; CHECK-NEXT:    ret
7541entry:
7542  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
7543  ret void
7544}
7545
7546define void @test_vsoxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7547; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:
7548; CHECK:       # %bb.0: # %entry
7549; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7550; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
7551; CHECK-NEXT:    ret
7552entry:
7553  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7554  ret void
7555}
7556
7557
7558define void @test_vsoxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
7559; CHECK-LABEL: test_vsoxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:
7560; CHECK:       # %bb.0: # %entry
7561; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7562; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
7563; CHECK-NEXT:    ret
7564entry:
7565  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
7566  ret void
7567}
7568
7569define void @test_vsoxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7570; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:
7571; CHECK:       # %bb.0: # %entry
7572; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7573; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
7574; CHECK-NEXT:    ret
7575entry:
7576  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7577  ret void
7578}
7579
7580
7581define void @test_vsoxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
7582; CHECK-LABEL: test_vsoxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:
7583; CHECK:       # %bb.0: # %entry
7584; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7585; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
7586; CHECK-NEXT:    ret
7587entry:
7588  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
7589  ret void
7590}
7591
7592define void @test_vsoxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7593; CHECK-LABEL: test_vsoxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:
7594; CHECK:       # %bb.0: # %entry
7595; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7596; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
7597; CHECK-NEXT:    ret
7598entry:
7599  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7600  ret void
7601}
7602
7603
7604define void @test_vsoxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
7605; CHECK-LABEL: test_vsoxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:
7606; CHECK:       # %bb.0: # %entry
7607; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7608; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
7609; CHECK-NEXT:    ret
7610entry:
7611  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
7612  ret void
7613}
7614
7615define void @test_vsoxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7616; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:
7617; CHECK:       # %bb.0: # %entry
7618; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7619; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
7620; CHECK-NEXT:    ret
7621entry:
7622  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7623  ret void
7624}
7625
7626
7627define void @test_vsoxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
7628; CHECK-LABEL: test_vsoxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:
7629; CHECK:       # %bb.0: # %entry
7630; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7631; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
7632; CHECK-NEXT:    ret
7633entry:
7634  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
7635  ret void
7636}
7637
7638define void @test_vsoxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7639; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:
7640; CHECK:       # %bb.0: # %entry
7641; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7642; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
7643; CHECK-NEXT:    ret
7644entry:
7645  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7646  ret void
7647}
7648
7649
7650define void @test_vsoxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
7651; CHECK-LABEL: test_vsoxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:
7652; CHECK:       # %bb.0: # %entry
7653; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7654; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
7655; CHECK-NEXT:    ret
7656entry:
7657  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
7658  ret void
7659}
7660
7661define void @test_vsoxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7662; CHECK-LABEL: test_vsoxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:
7663; CHECK:       # %bb.0: # %entry
7664; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7665; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
7666; CHECK-NEXT:    ret
7667entry:
7668  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7669  ret void
7670}
7671
7672
7673define void @test_vsoxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
7674; CHECK-LABEL: test_vsoxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:
7675; CHECK:       # %bb.0: # %entry
7676; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7677; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
7678; CHECK-NEXT:    ret
7679entry:
7680  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
7681  ret void
7682}
7683
7684define void @test_vsoxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7685; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:
7686; CHECK:       # %bb.0: # %entry
7687; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7688; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
7689; CHECK-NEXT:    ret
7690entry:
7691  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7692  ret void
7693}
7694
7695
7696define void @test_vsoxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
7697; CHECK-LABEL: test_vsoxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:
7698; CHECK:       # %bb.0: # %entry
7699; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7700; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
7701; CHECK-NEXT:    ret
7702entry:
7703  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
7704  ret void
7705}
7706
7707define void @test_vsoxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7708; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:
7709; CHECK:       # %bb.0: # %entry
7710; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7711; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
7712; CHECK-NEXT:    ret
7713entry:
7714  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7715  ret void
7716}
7717
7718
7719define void @test_vsoxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
7720; CHECK-LABEL: test_vsoxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:
7721; CHECK:       # %bb.0: # %entry
7722; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7723; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
7724; CHECK-NEXT:    ret
7725entry:
7726  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
7727  ret void
7728}
7729
7730define void @test_vsoxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7731; CHECK-LABEL: test_vsoxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:
7732; CHECK:       # %bb.0: # %entry
7733; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7734; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
7735; CHECK-NEXT:    ret
7736entry:
7737  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7738  ret void
7739}
7740
7741
7742define void @test_vsoxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
7743; CHECK-LABEL: test_vsoxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:
7744; CHECK:       # %bb.0: # %entry
7745; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7746; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
7747; CHECK-NEXT:    ret
7748entry:
7749  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
7750  ret void
7751}
7752
7753define void @test_vsoxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7754; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:
7755; CHECK:       # %bb.0: # %entry
7756; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7757; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
7758; CHECK-NEXT:    ret
7759entry:
7760  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7761  ret void
7762}
7763
7764
7765define void @test_vsoxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
7766; CHECK-LABEL: test_vsoxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:
7767; CHECK:       # %bb.0: # %entry
7768; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7769; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
7770; CHECK-NEXT:    ret
7771entry:
7772  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
7773  ret void
7774}
7775
7776define void @test_vsoxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7777; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:
7778; CHECK:       # %bb.0: # %entry
7779; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7780; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
7781; CHECK-NEXT:    ret
7782entry:
7783  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7784  ret void
7785}
7786
7787
7788define void @test_vsoxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
7789; CHECK-LABEL: test_vsoxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:
7790; CHECK:       # %bb.0: # %entry
7791; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7792; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
7793; CHECK-NEXT:    ret
7794entry:
7795  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
7796  ret void
7797}
7798
7799define void @test_vsoxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7800; CHECK-LABEL: test_vsoxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:
7801; CHECK:       # %bb.0: # %entry
7802; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7803; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
7804; CHECK-NEXT:    ret
7805entry:
7806  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7807  ret void
7808}
7809
7810
7811define void @test_vsoxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
7812; CHECK-LABEL: test_vsoxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:
7813; CHECK:       # %bb.0: # %entry
7814; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7815; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
7816; CHECK-NEXT:    ret
7817entry:
7818  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
7819  ret void
7820}
7821
7822define void @test_vsoxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7823; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:
7824; CHECK:       # %bb.0: # %entry
7825; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7826; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
7827; CHECK-NEXT:    ret
7828entry:
7829  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7830  ret void
7831}
7832
7833
7834define void @test_vsoxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
7835; CHECK-LABEL: test_vsoxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:
7836; CHECK:       # %bb.0: # %entry
7837; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7838; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
7839; CHECK-NEXT:    ret
7840entry:
7841  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
7842  ret void
7843}
7844
7845define void @test_vsoxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7846; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:
7847; CHECK:       # %bb.0: # %entry
7848; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7849; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
7850; CHECK-NEXT:    ret
7851entry:
7852  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7853  ret void
7854}
7855
7856
7857define void @test_vsoxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
7858; CHECK-LABEL: test_vsoxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:
7859; CHECK:       # %bb.0: # %entry
7860; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7861; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
7862; CHECK-NEXT:    ret
7863entry:
7864  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
7865  ret void
7866}
7867
7868define void @test_vsoxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
7869; CHECK-LABEL: test_vsoxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:
7870; CHECK:       # %bb.0: # %entry
7871; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
7872; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
7873; CHECK-NEXT:    ret
7874entry:
7875  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
7876  ret void
7877}
7878
7879
7880define void @test_vsoxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
7881; CHECK-LABEL: test_vsoxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:
7882; CHECK:       # %bb.0: # %entry
7883; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7884; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
7885; CHECK-NEXT:    ret
7886entry:
7887  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
7888  ret void
7889}
7890
7891define void @test_vsoxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7892; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:
7893; CHECK:       # %bb.0: # %entry
7894; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7895; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
7896; CHECK-NEXT:    ret
7897entry:
7898  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7899  ret void
7900}
7901
7902
7903define void @test_vsoxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
7904; CHECK-LABEL: test_vsoxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:
7905; CHECK:       # %bb.0: # %entry
7906; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7907; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
7908; CHECK-NEXT:    ret
7909entry:
7910  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
7911  ret void
7912}
7913
7914define void @test_vsoxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7915; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:
7916; CHECK:       # %bb.0: # %entry
7917; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7918; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
7919; CHECK-NEXT:    ret
7920entry:
7921  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7922  ret void
7923}
7924
7925
7926define void @test_vsoxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
7927; CHECK-LABEL: test_vsoxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:
7928; CHECK:       # %bb.0: # %entry
7929; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7930; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16
7931; CHECK-NEXT:    ret
7932entry:
7933  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
7934  ret void
7935}
7936
7937define void @test_vsoxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
7938; CHECK-LABEL: test_vsoxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:
7939; CHECK:       # %bb.0: # %entry
7940; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
7941; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16, v0.t
7942; CHECK-NEXT:    ret
7943entry:
7944  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
7945  ret void
7946}
7947
7948
7949define void @test_vsoxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
7950; CHECK-LABEL: test_vsoxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:
7951; CHECK:       # %bb.0: # %entry
7952; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7953; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
7954; CHECK-NEXT:    ret
7955entry:
7956  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
7957  ret void
7958}
7959
7960define void @test_vsoxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7961; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:
7962; CHECK:       # %bb.0: # %entry
7963; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7964; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
7965; CHECK-NEXT:    ret
7966entry:
7967  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7968  ret void
7969}
7970
7971
7972define void @test_vsoxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
7973; CHECK-LABEL: test_vsoxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:
7974; CHECK:       # %bb.0: # %entry
7975; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7976; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
7977; CHECK-NEXT:    ret
7978entry:
7979  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
7980  ret void
7981}
7982
7983define void @test_vsoxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
7984; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:
7985; CHECK:       # %bb.0: # %entry
7986; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7987; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
7988; CHECK-NEXT:    ret
7989entry:
7990  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
7991  ret void
7992}
7993
7994
7995define void @test_vsoxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
7996; CHECK-LABEL: test_vsoxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:
7997; CHECK:       # %bb.0: # %entry
7998; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
7999; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
8000; CHECK-NEXT:    ret
8001entry:
8002  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
8003  ret void
8004}
8005
8006define void @test_vsoxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8007; CHECK-LABEL: test_vsoxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:
8008; CHECK:       # %bb.0: # %entry
8009; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
8010; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
8011; CHECK-NEXT:    ret
8012entry:
8013  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
8014  ret void
8015}
8016
8017
8018define void @test_vsoxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
8019; CHECK-LABEL: test_vsoxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:
8020; CHECK:       # %bb.0: # %entry
8021; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
8022; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
8023; CHECK-NEXT:    ret
8024entry:
8025  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
8026  ret void
8027}
8028
8029define void @test_vsoxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8030; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:
8031; CHECK:       # %bb.0: # %entry
8032; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
8033; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
8034; CHECK-NEXT:    ret
8035entry:
8036  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
8037  ret void
8038}
8039
8040
8041define void @test_vsoxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
8042; CHECK-LABEL: test_vsoxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:
8043; CHECK:       # %bb.0: # %entry
8044; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
8045; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
8046; CHECK-NEXT:    ret
8047entry:
8048  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
8049  ret void
8050}
8051
8052define void @test_vsoxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8053; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:
8054; CHECK:       # %bb.0: # %entry
8055; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
8056; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
8057; CHECK-NEXT:    ret
8058entry:
8059  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
8060  ret void
8061}
8062
8063
8064define void @test_vsoxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
8065; CHECK-LABEL: test_vsoxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:
8066; CHECK:       # %bb.0: # %entry
8067; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
8068; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
8069; CHECK-NEXT:    ret
8070entry:
8071  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
8072  ret void
8073}
8074
8075define void @test_vsoxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8076; CHECK-LABEL: test_vsoxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:
8077; CHECK:       # %bb.0: # %entry
8078; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
8079; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
8080; CHECK-NEXT:    ret
8081entry:
8082  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
8083  ret void
8084}
8085
8086
8087define void @test_vsoxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
8088; CHECK-LABEL: test_vsoxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:
8089; CHECK:       # %bb.0: # %entry
8090; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
8091; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
8092; CHECK-NEXT:    ret
8093entry:
8094  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
8095  ret void
8096}
8097
8098define void @test_vsoxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8099; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:
8100; CHECK:       # %bb.0: # %entry
8101; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
8102; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
8103; CHECK-NEXT:    ret
8104entry:
8105  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
8106  ret void
8107}
8108
8109
8110define void @test_vsoxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
8111; CHECK-LABEL: test_vsoxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:
8112; CHECK:       # %bb.0: # %entry
8113; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
8114; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
8115; CHECK-NEXT:    ret
8116entry:
8117  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
8118  ret void
8119}
8120
8121define void @test_vsoxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8122; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:
8123; CHECK:       # %bb.0: # %entry
8124; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
8125; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
8126; CHECK-NEXT:    ret
8127entry:
8128  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
8129  ret void
8130}
8131
8132
8133define void @test_vsoxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
8134; CHECK-LABEL: test_vsoxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:
8135; CHECK:       # %bb.0: # %entry
8136; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
8137; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
8138; CHECK-NEXT:    ret
8139entry:
8140  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
8141  ret void
8142}
8143
8144define void @test_vsoxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8145; CHECK-LABEL: test_vsoxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:
8146; CHECK:       # %bb.0: # %entry
8147; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
8148; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
8149; CHECK-NEXT:    ret
8150entry:
8151  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
8152  ret void
8153}
8154
8155
8156define void @test_vsoxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
8157; CHECK-LABEL: test_vsoxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:
8158; CHECK:       # %bb.0: # %entry
8159; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8160; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
8161; CHECK-NEXT:    ret
8162entry:
8163  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
8164  ret void
8165}
8166
8167define void @test_vsoxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8168; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:
8169; CHECK:       # %bb.0: # %entry
8170; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8171; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
8172; CHECK-NEXT:    ret
8173entry:
8174  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8175  ret void
8176}
8177
8178
8179define void @test_vsoxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
8180; CHECK-LABEL: test_vsoxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:
8181; CHECK:       # %bb.0: # %entry
8182; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8183; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
8184; CHECK-NEXT:    ret
8185entry:
8186  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
8187  ret void
8188}
8189
8190define void @test_vsoxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8191; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:
8192; CHECK:       # %bb.0: # %entry
8193; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8194; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
8195; CHECK-NEXT:    ret
8196entry:
8197  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8198  ret void
8199}
8200
8201
8202define void @test_vsoxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
8203; CHECK-LABEL: test_vsoxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:
8204; CHECK:       # %bb.0: # %entry
8205; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8206; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
8207; CHECK-NEXT:    ret
8208entry:
8209  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
8210  ret void
8211}
8212
8213define void @test_vsoxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8214; CHECK-LABEL: test_vsoxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:
8215; CHECK:       # %bb.0: # %entry
8216; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8217; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
8218; CHECK-NEXT:    ret
8219entry:
8220  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8221  ret void
8222}
8223
8224
8225define void @test_vsoxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
8226; CHECK-LABEL: test_vsoxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:
8227; CHECK:       # %bb.0: # %entry
8228; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8229; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
8230; CHECK-NEXT:    ret
8231entry:
8232  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
8233  ret void
8234}
8235
8236define void @test_vsoxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8237; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:
8238; CHECK:       # %bb.0: # %entry
8239; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8240; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
8241; CHECK-NEXT:    ret
8242entry:
8243  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8244  ret void
8245}
8246
8247
8248define void @test_vsoxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
8249; CHECK-LABEL: test_vsoxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:
8250; CHECK:       # %bb.0: # %entry
8251; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8252; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
8253; CHECK-NEXT:    ret
8254entry:
8255  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
8256  ret void
8257}
8258
8259define void @test_vsoxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8260; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:
8261; CHECK:       # %bb.0: # %entry
8262; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8263; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
8264; CHECK-NEXT:    ret
8265entry:
8266  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8267  ret void
8268}
8269
8270
8271define void @test_vsoxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
8272; CHECK-LABEL: test_vsoxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:
8273; CHECK:       # %bb.0: # %entry
8274; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8275; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
8276; CHECK-NEXT:    ret
8277entry:
8278  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
8279  ret void
8280}
8281
8282define void @test_vsoxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8283; CHECK-LABEL: test_vsoxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:
8284; CHECK:       # %bb.0: # %entry
8285; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8286; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
8287; CHECK-NEXT:    ret
8288entry:
8289  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8290  ret void
8291}
8292
8293
8294define void @test_vsoxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
8295; CHECK-LABEL: test_vsoxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:
8296; CHECK:       # %bb.0: # %entry
8297; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8298; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
8299; CHECK-NEXT:    ret
8300entry:
8301  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 5)
8302  ret void
8303}
8304
8305define void @test_vsoxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8306; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:
8307; CHECK:       # %bb.0: # %entry
8308; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8309; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
8310; CHECK-NEXT:    ret
8311entry:
8312  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8313  ret void
8314}
8315
8316
8317define void @test_vsoxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
8318; CHECK-LABEL: test_vsoxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:
8319; CHECK:       # %bb.0: # %entry
8320; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8321; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
8322; CHECK-NEXT:    ret
8323entry:
8324  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 5)
8325  ret void
8326}
8327
8328define void @test_vsoxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8329; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:
8330; CHECK:       # %bb.0: # %entry
8331; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8332; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
8333; CHECK-NEXT:    ret
8334entry:
8335  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8336  ret void
8337}
8338
8339
8340define void @test_vsoxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
8341; CHECK-LABEL: test_vsoxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:
8342; CHECK:       # %bb.0: # %entry
8343; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8344; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
8345; CHECK-NEXT:    ret
8346entry:
8347  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 5)
8348  ret void
8349}
8350
8351define void @test_vsoxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8352; CHECK-LABEL: test_vsoxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:
8353; CHECK:       # %bb.0: # %entry
8354; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8355; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
8356; CHECK-NEXT:    ret
8357entry:
8358  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8359  ret void
8360}
8361
8362
8363define void @test_vsoxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
8364; CHECK-LABEL: test_vsoxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:
8365; CHECK:       # %bb.0: # %entry
8366; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
8367; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
8368; CHECK-NEXT:    ret
8369entry:
8370  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 5)
8371  ret void
8372}
8373
8374define void @test_vsoxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
8375; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:
8376; CHECK:       # %bb.0: # %entry
8377; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
8378; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
8379; CHECK-NEXT:    ret
8380entry:
8381  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 5)
8382  ret void
8383}
8384
8385
8386define void @test_vsoxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
8387; CHECK-LABEL: test_vsoxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:
8388; CHECK:       # %bb.0: # %entry
8389; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
8390; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
8391; CHECK-NEXT:    ret
8392entry:
8393  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 5)
8394  ret void
8395}
8396
8397define void @test_vsoxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
8398; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:
8399; CHECK:       # %bb.0: # %entry
8400; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
8401; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
8402; CHECK-NEXT:    ret
8403entry:
8404  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 5)
8405  ret void
8406}
8407
8408
8409define void @test_vsoxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
8410; CHECK-LABEL: test_vsoxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:
8411; CHECK:       # %bb.0: # %entry
8412; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
8413; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
8414; CHECK-NEXT:    ret
8415entry:
8416  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 5)
8417  ret void
8418}
8419
8420define void @test_vsoxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
8421; CHECK-LABEL: test_vsoxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:
8422; CHECK:       # %bb.0: # %entry
8423; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
8424; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
8425; CHECK-NEXT:    ret
8426entry:
8427  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 5)
8428  ret void
8429}
8430
8431
8432define void @test_vsoxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
8433; CHECK-LABEL: test_vsoxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:
8434; CHECK:       # %bb.0: # %entry
8435; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8436; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
8437; CHECK-NEXT:    ret
8438entry:
8439  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
8440  ret void
8441}
8442
8443define void @test_vsoxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8444; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:
8445; CHECK:       # %bb.0: # %entry
8446; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8447; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
8448; CHECK-NEXT:    ret
8449entry:
8450  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8451  ret void
8452}
8453
8454
8455define void @test_vsoxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
8456; CHECK-LABEL: test_vsoxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:
8457; CHECK:       # %bb.0: # %entry
8458; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8459; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
8460; CHECK-NEXT:    ret
8461entry:
8462  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
8463  ret void
8464}
8465
8466define void @test_vsoxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8467; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:
8468; CHECK:       # %bb.0: # %entry
8469; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8470; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
8471; CHECK-NEXT:    ret
8472entry:
8473  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8474  ret void
8475}
8476
8477
8478define void @test_vsoxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
8479; CHECK-LABEL: test_vsoxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:
8480; CHECK:       # %bb.0: # %entry
8481; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8482; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
8483; CHECK-NEXT:    ret
8484entry:
8485  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
8486  ret void
8487}
8488
8489define void @test_vsoxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8490; CHECK-LABEL: test_vsoxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:
8491; CHECK:       # %bb.0: # %entry
8492; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8493; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
8494; CHECK-NEXT:    ret
8495entry:
8496  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8497  ret void
8498}
8499
8500
8501define void @test_vsoxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
8502; CHECK-LABEL: test_vsoxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:
8503; CHECK:       # %bb.0: # %entry
8504; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8505; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
8506; CHECK-NEXT:    ret
8507entry:
8508  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
8509  ret void
8510}
8511
8512define void @test_vsoxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8513; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:
8514; CHECK:       # %bb.0: # %entry
8515; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8516; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
8517; CHECK-NEXT:    ret
8518entry:
8519  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8520  ret void
8521}
8522
8523
8524define void @test_vsoxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
8525; CHECK-LABEL: test_vsoxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:
8526; CHECK:       # %bb.0: # %entry
8527; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8528; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
8529; CHECK-NEXT:    ret
8530entry:
8531  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
8532  ret void
8533}
8534
8535define void @test_vsoxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8536; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:
8537; CHECK:       # %bb.0: # %entry
8538; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8539; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
8540; CHECK-NEXT:    ret
8541entry:
8542  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8543  ret void
8544}
8545
8546
8547define void @test_vsoxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
8548; CHECK-LABEL: test_vsoxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:
8549; CHECK:       # %bb.0: # %entry
8550; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8551; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
8552; CHECK-NEXT:    ret
8553entry:
8554  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
8555  ret void
8556}
8557
8558define void @test_vsoxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8559; CHECK-LABEL: test_vsoxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:
8560; CHECK:       # %bb.0: # %entry
8561; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8562; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
8563; CHECK-NEXT:    ret
8564entry:
8565  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8566  ret void
8567}
8568
8569
8570define void @test_vsoxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
8571; CHECK-LABEL: test_vsoxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:
8572; CHECK:       # %bb.0: # %entry
8573; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8574; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
8575; CHECK-NEXT:    ret
8576entry:
8577  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 5)
8578  ret void
8579}
8580
8581define void @test_vsoxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8582; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:
8583; CHECK:       # %bb.0: # %entry
8584; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8585; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
8586; CHECK-NEXT:    ret
8587entry:
8588  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8589  ret void
8590}
8591
8592
8593define void @test_vsoxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
8594; CHECK-LABEL: test_vsoxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:
8595; CHECK:       # %bb.0: # %entry
8596; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8597; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
8598; CHECK-NEXT:    ret
8599entry:
8600  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 5)
8601  ret void
8602}
8603
8604define void @test_vsoxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8605; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:
8606; CHECK:       # %bb.0: # %entry
8607; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8608; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
8609; CHECK-NEXT:    ret
8610entry:
8611  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8612  ret void
8613}
8614
8615
8616define void @test_vsoxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
8617; CHECK-LABEL: test_vsoxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:
8618; CHECK:       # %bb.0: # %entry
8619; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8620; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14
8621; CHECK-NEXT:    ret
8622entry:
8623  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 5)
8624  ret void
8625}
8626
8627define void @test_vsoxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8628; CHECK-LABEL: test_vsoxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:
8629; CHECK:       # %bb.0: # %entry
8630; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8631; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14, v0.t
8632; CHECK-NEXT:    ret
8633entry:
8634  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8635  ret void
8636}
8637
8638
8639define void @test_vsoxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
8640; CHECK-LABEL: test_vsoxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:
8641; CHECK:       # %bb.0: # %entry
8642; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8643; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
8644; CHECK-NEXT:    ret
8645entry:
8646  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
8647  ret void
8648}
8649
8650define void @test_vsoxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8651; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:
8652; CHECK:       # %bb.0: # %entry
8653; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8654; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
8655; CHECK-NEXT:    ret
8656entry:
8657  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8658  ret void
8659}
8660
8661
8662define void @test_vsoxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
8663; CHECK-LABEL: test_vsoxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:
8664; CHECK:       # %bb.0: # %entry
8665; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8666; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
8667; CHECK-NEXT:    ret
8668entry:
8669  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
8670  ret void
8671}
8672
8673define void @test_vsoxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8674; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:
8675; CHECK:       # %bb.0: # %entry
8676; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8677; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
8678; CHECK-NEXT:    ret
8679entry:
8680  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8681  ret void
8682}
8683
8684
8685define void @test_vsoxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
8686; CHECK-LABEL: test_vsoxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:
8687; CHECK:       # %bb.0: # %entry
8688; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8689; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
8690; CHECK-NEXT:    ret
8691entry:
8692  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
8693  ret void
8694}
8695
8696define void @test_vsoxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8697; CHECK-LABEL: test_vsoxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:
8698; CHECK:       # %bb.0: # %entry
8699; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8700; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
8701; CHECK-NEXT:    ret
8702entry:
8703  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8704  ret void
8705}
8706
8707
8708define void @test_vsoxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
8709; CHECK-LABEL: test_vsoxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:
8710; CHECK:       # %bb.0: # %entry
8711; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8712; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
8713; CHECK-NEXT:    ret
8714entry:
8715  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
8716  ret void
8717}
8718
8719define void @test_vsoxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8720; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:
8721; CHECK:       # %bb.0: # %entry
8722; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8723; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
8724; CHECK-NEXT:    ret
8725entry:
8726  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8727  ret void
8728}
8729
8730
8731define void @test_vsoxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
8732; CHECK-LABEL: test_vsoxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:
8733; CHECK:       # %bb.0: # %entry
8734; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8735; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
8736; CHECK-NEXT:    ret
8737entry:
8738  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
8739  ret void
8740}
8741
8742define void @test_vsoxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8743; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:
8744; CHECK:       # %bb.0: # %entry
8745; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8746; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
8747; CHECK-NEXT:    ret
8748entry:
8749  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8750  ret void
8751}
8752
8753
8754define void @test_vsoxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
8755; CHECK-LABEL: test_vsoxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:
8756; CHECK:       # %bb.0: # %entry
8757; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8758; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
8759; CHECK-NEXT:    ret
8760entry:
8761  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
8762  ret void
8763}
8764
8765define void @test_vsoxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8766; CHECK-LABEL: test_vsoxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:
8767; CHECK:       # %bb.0: # %entry
8768; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8769; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
8770; CHECK-NEXT:    ret
8771entry:
8772  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8773  ret void
8774}
8775
8776
8777define void @test_vsoxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
8778; CHECK-LABEL: test_vsoxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:
8779; CHECK:       # %bb.0: # %entry
8780; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8781; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
8782; CHECK-NEXT:    ret
8783entry:
8784  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 5)
8785  ret void
8786}
8787
8788define void @test_vsoxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8789; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:
8790; CHECK:       # %bb.0: # %entry
8791; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8792; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
8793; CHECK-NEXT:    ret
8794entry:
8795  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8796  ret void
8797}
8798
8799
8800define void @test_vsoxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
8801; CHECK-LABEL: test_vsoxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:
8802; CHECK:       # %bb.0: # %entry
8803; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8804; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
8805; CHECK-NEXT:    ret
8806entry:
8807  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 5)
8808  ret void
8809}
8810
8811define void @test_vsoxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8812; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:
8813; CHECK:       # %bb.0: # %entry
8814; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8815; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
8816; CHECK-NEXT:    ret
8817entry:
8818  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8819  ret void
8820}
8821
8822
8823define void @test_vsoxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
8824; CHECK-LABEL: test_vsoxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:
8825; CHECK:       # %bb.0: # %entry
8826; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8827; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
8828; CHECK-NEXT:    ret
8829entry:
8830  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 5)
8831  ret void
8832}
8833
8834define void @test_vsoxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
8835; CHECK-LABEL: test_vsoxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:
8836; CHECK:       # %bb.0: # %entry
8837; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
8838; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
8839; CHECK-NEXT:    ret
8840entry:
8841  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 5)
8842  ret void
8843}
8844
8845
8846define void @test_vsoxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
8847; CHECK-LABEL: test_vsoxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:
8848; CHECK:       # %bb.0: # %entry
8849; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8850; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
8851; CHECK-NEXT:    ret
8852entry:
8853  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
8854  ret void
8855}
8856
8857define void @test_vsoxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8858; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:
8859; CHECK:       # %bb.0: # %entry
8860; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8861; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
8862; CHECK-NEXT:    ret
8863entry:
8864  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8865  ret void
8866}
8867
8868
8869define void @test_vsoxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
8870; CHECK-LABEL: test_vsoxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:
8871; CHECK:       # %bb.0: # %entry
8872; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8873; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
8874; CHECK-NEXT:    ret
8875entry:
8876  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
8877  ret void
8878}
8879
8880define void @test_vsoxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8881; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:
8882; CHECK:       # %bb.0: # %entry
8883; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8884; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
8885; CHECK-NEXT:    ret
8886entry:
8887  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8888  ret void
8889}
8890
8891
8892define void @test_vsoxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
8893; CHECK-LABEL: test_vsoxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:
8894; CHECK:       # %bb.0: # %entry
8895; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8896; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
8897; CHECK-NEXT:    ret
8898entry:
8899  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
8900  ret void
8901}
8902
8903define void @test_vsoxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8904; CHECK-LABEL: test_vsoxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:
8905; CHECK:       # %bb.0: # %entry
8906; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8907; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
8908; CHECK-NEXT:    ret
8909entry:
8910  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
8911  ret void
8912}
8913
8914
8915define void @test_vsoxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
8916; CHECK-LABEL: test_vsoxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:
8917; CHECK:       # %bb.0: # %entry
8918; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8919; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
8920; CHECK-NEXT:    ret
8921entry:
8922  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
8923  ret void
8924}
8925
8926define void @test_vsoxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8927; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:
8928; CHECK:       # %bb.0: # %entry
8929; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8930; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
8931; CHECK-NEXT:    ret
8932entry:
8933  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8934  ret void
8935}
8936
8937
8938define void @test_vsoxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
8939; CHECK-LABEL: test_vsoxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:
8940; CHECK:       # %bb.0: # %entry
8941; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8942; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
8943; CHECK-NEXT:    ret
8944entry:
8945  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
8946  ret void
8947}
8948
8949define void @test_vsoxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8950; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:
8951; CHECK:       # %bb.0: # %entry
8952; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8953; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
8954; CHECK-NEXT:    ret
8955entry:
8956  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8957  ret void
8958}
8959
8960
8961define void @test_vsoxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
8962; CHECK-LABEL: test_vsoxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:
8963; CHECK:       # %bb.0: # %entry
8964; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8965; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
8966; CHECK-NEXT:    ret
8967entry:
8968  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
8969  ret void
8970}
8971
8972define void @test_vsoxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
8973; CHECK-LABEL: test_vsoxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:
8974; CHECK:       # %bb.0: # %entry
8975; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
8976; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
8977; CHECK-NEXT:    ret
8978entry:
8979  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
8980  ret void
8981}
8982
8983
8984define void @test_vsoxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
8985; CHECK-LABEL: test_vsoxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:
8986; CHECK:       # %bb.0: # %entry
8987; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8988; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
8989; CHECK-NEXT:    ret
8990entry:
8991  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
8992  ret void
8993}
8994
8995define void @test_vsoxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
8996; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:
8997; CHECK:       # %bb.0: # %entry
8998; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
8999; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
9000; CHECK-NEXT:    ret
9001entry:
9002  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9003  ret void
9004}
9005
9006
9007define void @test_vsoxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9008; CHECK-LABEL: test_vsoxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:
9009; CHECK:       # %bb.0: # %entry
9010; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9011; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
9012; CHECK-NEXT:    ret
9013entry:
9014  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
9015  ret void
9016}
9017
9018define void @test_vsoxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9019; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:
9020; CHECK:       # %bb.0: # %entry
9021; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9022; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
9023; CHECK-NEXT:    ret
9024entry:
9025  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9026  ret void
9027}
9028
9029
9030define void @test_vsoxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9031; CHECK-LABEL: test_vsoxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:
9032; CHECK:       # %bb.0: # %entry
9033; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9034; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
9035; CHECK-NEXT:    ret
9036entry:
9037  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
9038  ret void
9039}
9040
9041define void @test_vsoxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9042; CHECK-LABEL: test_vsoxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:
9043; CHECK:       # %bb.0: # %entry
9044; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9045; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
9046; CHECK-NEXT:    ret
9047entry:
9048  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9049  ret void
9050}
9051
9052
9053define void @test_vsoxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
9054; CHECK-LABEL: test_vsoxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:
9055; CHECK:       # %bb.0: # %entry
9056; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9057; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
9058; CHECK-NEXT:    ret
9059entry:
9060  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
9061  ret void
9062}
9063
9064define void @test_vsoxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9065; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:
9066; CHECK:       # %bb.0: # %entry
9067; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9068; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
9069; CHECK-NEXT:    ret
9070entry:
9071  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9072  ret void
9073}
9074
9075
9076define void @test_vsoxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
9077; CHECK-LABEL: test_vsoxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:
9078; CHECK:       # %bb.0: # %entry
9079; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9080; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
9081; CHECK-NEXT:    ret
9082entry:
9083  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
9084  ret void
9085}
9086
9087define void @test_vsoxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9088; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:
9089; CHECK:       # %bb.0: # %entry
9090; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9091; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
9092; CHECK-NEXT:    ret
9093entry:
9094  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9095  ret void
9096}
9097
9098
9099define void @test_vsoxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
9100; CHECK-LABEL: test_vsoxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:
9101; CHECK:       # %bb.0: # %entry
9102; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9103; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
9104; CHECK-NEXT:    ret
9105entry:
9106  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
9107  ret void
9108}
9109
9110define void @test_vsoxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9111; CHECK-LABEL: test_vsoxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:
9112; CHECK:       # %bb.0: # %entry
9113; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9114; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
9115; CHECK-NEXT:    ret
9116entry:
9117  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9118  ret void
9119}
9120
9121
9122define void @test_vsoxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9123; CHECK-LABEL: test_vsoxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:
9124; CHECK:       # %bb.0: # %entry
9125; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9126; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
9127; CHECK-NEXT:    ret
9128entry:
9129  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
9130  ret void
9131}
9132
9133define void @test_vsoxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9134; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:
9135; CHECK:       # %bb.0: # %entry
9136; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9137; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
9138; CHECK-NEXT:    ret
9139entry:
9140  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9141  ret void
9142}
9143
9144
9145define void @test_vsoxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9146; CHECK-LABEL: test_vsoxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:
9147; CHECK:       # %bb.0: # %entry
9148; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9149; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
9150; CHECK-NEXT:    ret
9151entry:
9152  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
9153  ret void
9154}
9155
9156define void @test_vsoxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9157; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:
9158; CHECK:       # %bb.0: # %entry
9159; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9160; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
9161; CHECK-NEXT:    ret
9162entry:
9163  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9164  ret void
9165}
9166
9167
9168define void @test_vsoxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9169; CHECK-LABEL: test_vsoxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:
9170; CHECK:       # %bb.0: # %entry
9171; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9172; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
9173; CHECK-NEXT:    ret
9174entry:
9175  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
9176  ret void
9177}
9178
9179define void @test_vsoxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9180; CHECK-LABEL: test_vsoxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:
9181; CHECK:       # %bb.0: # %entry
9182; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9183; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
9184; CHECK-NEXT:    ret
9185entry:
9186  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9187  ret void
9188}
9189
9190
9191define void @test_vsoxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
9192; CHECK-LABEL: test_vsoxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:
9193; CHECK:       # %bb.0: # %entry
9194; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9195; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
9196; CHECK-NEXT:    ret
9197entry:
9198  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
9199  ret void
9200}
9201
9202define void @test_vsoxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9203; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:
9204; CHECK:       # %bb.0: # %entry
9205; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9206; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
9207; CHECK-NEXT:    ret
9208entry:
9209  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9210  ret void
9211}
9212
9213
9214define void @test_vsoxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
9215; CHECK-LABEL: test_vsoxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:
9216; CHECK:       # %bb.0: # %entry
9217; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9218; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
9219; CHECK-NEXT:    ret
9220entry:
9221  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
9222  ret void
9223}
9224
9225define void @test_vsoxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9226; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:
9227; CHECK:       # %bb.0: # %entry
9228; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9229; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
9230; CHECK-NEXT:    ret
9231entry:
9232  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9233  ret void
9234}
9235
9236
9237define void @test_vsoxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
9238; CHECK-LABEL: test_vsoxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:
9239; CHECK:       # %bb.0: # %entry
9240; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9241; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
9242; CHECK-NEXT:    ret
9243entry:
9244  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
9245  ret void
9246}
9247
9248define void @test_vsoxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9249; CHECK-LABEL: test_vsoxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:
9250; CHECK:       # %bb.0: # %entry
9251; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9252; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
9253; CHECK-NEXT:    ret
9254entry:
9255  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9256  ret void
9257}
9258
9259
9260define void @test_vsoxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9261; CHECK-LABEL: test_vsoxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:
9262; CHECK:       # %bb.0: # %entry
9263; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9264; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
9265; CHECK-NEXT:    ret
9266entry:
9267  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 5)
9268  ret void
9269}
9270
9271define void @test_vsoxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9272; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:
9273; CHECK:       # %bb.0: # %entry
9274; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9275; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
9276; CHECK-NEXT:    ret
9277entry:
9278  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9279  ret void
9280}
9281
9282
9283define void @test_vsoxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9284; CHECK-LABEL: test_vsoxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:
9285; CHECK:       # %bb.0: # %entry
9286; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9287; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
9288; CHECK-NEXT:    ret
9289entry:
9290  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 5)
9291  ret void
9292}
9293
9294define void @test_vsoxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9295; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:
9296; CHECK:       # %bb.0: # %entry
9297; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9298; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
9299; CHECK-NEXT:    ret
9300entry:
9301  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9302  ret void
9303}
9304
9305
9306define void @test_vsoxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9307; CHECK-LABEL: test_vsoxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:
9308; CHECK:       # %bb.0: # %entry
9309; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9310; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
9311; CHECK-NEXT:    ret
9312entry:
9313  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 5)
9314  ret void
9315}
9316
9317define void @test_vsoxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9318; CHECK-LABEL: test_vsoxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:
9319; CHECK:       # %bb.0: # %entry
9320; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
9321; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
9322; CHECK-NEXT:    ret
9323entry:
9324  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 5)
9325  ret void
9326}
9327
9328
9329define void @test_vsoxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
9330; CHECK-LABEL: test_vsoxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:
9331; CHECK:       # %bb.0: # %entry
9332; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9333; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
9334; CHECK-NEXT:    ret
9335entry:
9336  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 5)
9337  ret void
9338}
9339
9340define void @test_vsoxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9341; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:
9342; CHECK:       # %bb.0: # %entry
9343; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9344; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
9345; CHECK-NEXT:    ret
9346entry:
9347  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9348  ret void
9349}
9350
9351
9352define void @test_vsoxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
9353; CHECK-LABEL: test_vsoxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:
9354; CHECK:       # %bb.0: # %entry
9355; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9356; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
9357; CHECK-NEXT:    ret
9358entry:
9359  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 5)
9360  ret void
9361}
9362
9363define void @test_vsoxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9364; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:
9365; CHECK:       # %bb.0: # %entry
9366; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9367; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
9368; CHECK-NEXT:    ret
9369entry:
9370  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9371  ret void
9372}
9373
9374
9375define void @test_vsoxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
9376; CHECK-LABEL: test_vsoxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:
9377; CHECK:       # %bb.0: # %entry
9378; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9379; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
9380; CHECK-NEXT:    ret
9381entry:
9382  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 5)
9383  ret void
9384}
9385
9386define void @test_vsoxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9387; CHECK-LABEL: test_vsoxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:
9388; CHECK:       # %bb.0: # %entry
9389; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
9390; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
9391; CHECK-NEXT:    ret
9392entry:
9393  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 5)
9394  ret void
9395}
9396
9397
9398define void @test_vsoxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9399; CHECK-LABEL: test_vsoxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:
9400; CHECK:       # %bb.0: # %entry
9401; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9402; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
9403; CHECK-NEXT:    ret
9404entry:
9405  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
9406  ret void
9407}
9408
9409define void @test_vsoxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9410; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:
9411; CHECK:       # %bb.0: # %entry
9412; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9413; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
9414; CHECK-NEXT:    ret
9415entry:
9416  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9417  ret void
9418}
9419
9420
9421define void @test_vsoxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9422; CHECK-LABEL: test_vsoxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:
9423; CHECK:       # %bb.0: # %entry
9424; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9425; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
9426; CHECK-NEXT:    ret
9427entry:
9428  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
9429  ret void
9430}
9431
9432define void @test_vsoxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9433; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:
9434; CHECK:       # %bb.0: # %entry
9435; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9436; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
9437; CHECK-NEXT:    ret
9438entry:
9439  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9440  ret void
9441}
9442
9443
9444define void @test_vsoxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9445; CHECK-LABEL: test_vsoxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:
9446; CHECK:       # %bb.0: # %entry
9447; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9448; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
9449; CHECK-NEXT:    ret
9450entry:
9451  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
9452  ret void
9453}
9454
9455define void @test_vsoxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9456; CHECK-LABEL: test_vsoxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:
9457; CHECK:       # %bb.0: # %entry
9458; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9459; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
9460; CHECK-NEXT:    ret
9461entry:
9462  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9463  ret void
9464}
9465
9466
9467define void @test_vsoxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
9468; CHECK-LABEL: test_vsoxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:
9469; CHECK:       # %bb.0: # %entry
9470; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9471; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
9472; CHECK-NEXT:    ret
9473entry:
9474  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 6)
9475  ret void
9476}
9477
9478define void @test_vsoxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9479; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:
9480; CHECK:       # %bb.0: # %entry
9481; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9482; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
9483; CHECK-NEXT:    ret
9484entry:
9485  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9486  ret void
9487}
9488
9489
9490define void @test_vsoxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
9491; CHECK-LABEL: test_vsoxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:
9492; CHECK:       # %bb.0: # %entry
9493; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9494; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
9495; CHECK-NEXT:    ret
9496entry:
9497  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 6)
9498  ret void
9499}
9500
9501define void @test_vsoxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9502; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:
9503; CHECK:       # %bb.0: # %entry
9504; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9505; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
9506; CHECK-NEXT:    ret
9507entry:
9508  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9509  ret void
9510}
9511
9512
9513define void @test_vsoxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
9514; CHECK-LABEL: test_vsoxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:
9515; CHECK:       # %bb.0: # %entry
9516; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9517; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
9518; CHECK-NEXT:    ret
9519entry:
9520  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 6)
9521  ret void
9522}
9523
9524define void @test_vsoxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9525; CHECK-LABEL: test_vsoxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:
9526; CHECK:       # %bb.0: # %entry
9527; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9528; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
9529; CHECK-NEXT:    ret
9530entry:
9531  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9532  ret void
9533}
9534
9535
9536define void @test_vsoxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
9537; CHECK-LABEL: test_vsoxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:
9538; CHECK:       # %bb.0: # %entry
9539; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
9540; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
9541; CHECK-NEXT:    ret
9542entry:
9543  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 6)
9544  ret void
9545}
9546
9547define void @test_vsoxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
9548; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:
9549; CHECK:       # %bb.0: # %entry
9550; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
9551; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
9552; CHECK-NEXT:    ret
9553entry:
9554  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 6)
9555  ret void
9556}
9557
9558
9559define void @test_vsoxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
9560; CHECK-LABEL: test_vsoxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:
9561; CHECK:       # %bb.0: # %entry
9562; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
9563; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
9564; CHECK-NEXT:    ret
9565entry:
9566  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 6)
9567  ret void
9568}
9569
9570define void @test_vsoxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
9571; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:
9572; CHECK:       # %bb.0: # %entry
9573; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
9574; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
9575; CHECK-NEXT:    ret
9576entry:
9577  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 6)
9578  ret void
9579}
9580
9581
9582define void @test_vsoxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
9583; CHECK-LABEL: test_vsoxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:
9584; CHECK:       # %bb.0: # %entry
9585; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
9586; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
9587; CHECK-NEXT:    ret
9588entry:
9589  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 6)
9590  ret void
9591}
9592
9593define void @test_vsoxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
9594; CHECK-LABEL: test_vsoxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:
9595; CHECK:       # %bb.0: # %entry
9596; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
9597; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
9598; CHECK-NEXT:    ret
9599entry:
9600  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 6)
9601  ret void
9602}
9603
9604
9605define void @test_vsoxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9606; CHECK-LABEL: test_vsoxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:
9607; CHECK:       # %bb.0: # %entry
9608; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9609; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
9610; CHECK-NEXT:    ret
9611entry:
9612  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
9613  ret void
9614}
9615
9616define void @test_vsoxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9617; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:
9618; CHECK:       # %bb.0: # %entry
9619; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9620; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
9621; CHECK-NEXT:    ret
9622entry:
9623  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9624  ret void
9625}
9626
9627
9628define void @test_vsoxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9629; CHECK-LABEL: test_vsoxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:
9630; CHECK:       # %bb.0: # %entry
9631; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9632; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
9633; CHECK-NEXT:    ret
9634entry:
9635  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
9636  ret void
9637}
9638
9639define void @test_vsoxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9640; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:
9641; CHECK:       # %bb.0: # %entry
9642; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9643; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
9644; CHECK-NEXT:    ret
9645entry:
9646  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9647  ret void
9648}
9649
9650
9651define void @test_vsoxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9652; CHECK-LABEL: test_vsoxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:
9653; CHECK:       # %bb.0: # %entry
9654; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9655; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
9656; CHECK-NEXT:    ret
9657entry:
9658  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
9659  ret void
9660}
9661
9662define void @test_vsoxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9663; CHECK-LABEL: test_vsoxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:
9664; CHECK:       # %bb.0: # %entry
9665; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9666; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
9667; CHECK-NEXT:    ret
9668entry:
9669  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9670  ret void
9671}
9672
9673
9674define void @test_vsoxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
9675; CHECK-LABEL: test_vsoxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:
9676; CHECK:       # %bb.0: # %entry
9677; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9678; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
9679; CHECK-NEXT:    ret
9680entry:
9681  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 6)
9682  ret void
9683}
9684
9685define void @test_vsoxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9686; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:
9687; CHECK:       # %bb.0: # %entry
9688; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9689; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
9690; CHECK-NEXT:    ret
9691entry:
9692  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9693  ret void
9694}
9695
9696
9697define void @test_vsoxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
9698; CHECK-LABEL: test_vsoxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:
9699; CHECK:       # %bb.0: # %entry
9700; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9701; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
9702; CHECK-NEXT:    ret
9703entry:
9704  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 6)
9705  ret void
9706}
9707
9708define void @test_vsoxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9709; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:
9710; CHECK:       # %bb.0: # %entry
9711; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9712; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
9713; CHECK-NEXT:    ret
9714entry:
9715  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9716  ret void
9717}
9718
9719
9720define void @test_vsoxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
9721; CHECK-LABEL: test_vsoxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:
9722; CHECK:       # %bb.0: # %entry
9723; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9724; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14
9725; CHECK-NEXT:    ret
9726entry:
9727  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 6)
9728  ret void
9729}
9730
9731define void @test_vsoxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9732; CHECK-LABEL: test_vsoxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:
9733; CHECK:       # %bb.0: # %entry
9734; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9735; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v14, v0.t
9736; CHECK-NEXT:    ret
9737entry:
9738  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9739  ret void
9740}
9741
9742
9743define void @test_vsoxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9744; CHECK-LABEL: test_vsoxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:
9745; CHECK:       # %bb.0: # %entry
9746; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9747; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
9748; CHECK-NEXT:    ret
9749entry:
9750  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
9751  ret void
9752}
9753
9754define void @test_vsoxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9755; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:
9756; CHECK:       # %bb.0: # %entry
9757; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9758; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
9759; CHECK-NEXT:    ret
9760entry:
9761  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9762  ret void
9763}
9764
9765
9766define void @test_vsoxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9767; CHECK-LABEL: test_vsoxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:
9768; CHECK:       # %bb.0: # %entry
9769; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9770; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
9771; CHECK-NEXT:    ret
9772entry:
9773  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
9774  ret void
9775}
9776
9777define void @test_vsoxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9778; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:
9779; CHECK:       # %bb.0: # %entry
9780; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9781; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
9782; CHECK-NEXT:    ret
9783entry:
9784  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9785  ret void
9786}
9787
9788
9789define void @test_vsoxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9790; CHECK-LABEL: test_vsoxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:
9791; CHECK:       # %bb.0: # %entry
9792; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9793; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
9794; CHECK-NEXT:    ret
9795entry:
9796  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
9797  ret void
9798}
9799
9800define void @test_vsoxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9801; CHECK-LABEL: test_vsoxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:
9802; CHECK:       # %bb.0: # %entry
9803; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9804; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
9805; CHECK-NEXT:    ret
9806entry:
9807  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9808  ret void
9809}
9810
9811
9812define void @test_vsoxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
9813; CHECK-LABEL: test_vsoxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:
9814; CHECK:       # %bb.0: # %entry
9815; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9816; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
9817; CHECK-NEXT:    ret
9818entry:
9819  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 6)
9820  ret void
9821}
9822
9823define void @test_vsoxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9824; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:
9825; CHECK:       # %bb.0: # %entry
9826; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9827; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
9828; CHECK-NEXT:    ret
9829entry:
9830  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9831  ret void
9832}
9833
9834
9835define void @test_vsoxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
9836; CHECK-LABEL: test_vsoxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:
9837; CHECK:       # %bb.0: # %entry
9838; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9839; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
9840; CHECK-NEXT:    ret
9841entry:
9842  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 6)
9843  ret void
9844}
9845
9846define void @test_vsoxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9847; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:
9848; CHECK:       # %bb.0: # %entry
9849; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9850; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
9851; CHECK-NEXT:    ret
9852entry:
9853  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9854  ret void
9855}
9856
9857
9858define void @test_vsoxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
9859; CHECK-LABEL: test_vsoxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:
9860; CHECK:       # %bb.0: # %entry
9861; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9862; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
9863; CHECK-NEXT:    ret
9864entry:
9865  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 6)
9866  ret void
9867}
9868
9869define void @test_vsoxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
9870; CHECK-LABEL: test_vsoxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:
9871; CHECK:       # %bb.0: # %entry
9872; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
9873; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
9874; CHECK-NEXT:    ret
9875entry:
9876  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 6)
9877  ret void
9878}
9879
9880
9881define void @test_vsoxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9882; CHECK-LABEL: test_vsoxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:
9883; CHECK:       # %bb.0: # %entry
9884; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9885; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
9886; CHECK-NEXT:    ret
9887entry:
9888  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
9889  ret void
9890}
9891
9892define void @test_vsoxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9893; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:
9894; CHECK:       # %bb.0: # %entry
9895; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9896; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
9897; CHECK-NEXT:    ret
9898entry:
9899  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9900  ret void
9901}
9902
9903
9904define void @test_vsoxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9905; CHECK-LABEL: test_vsoxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:
9906; CHECK:       # %bb.0: # %entry
9907; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9908; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
9909; CHECK-NEXT:    ret
9910entry:
9911  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
9912  ret void
9913}
9914
9915define void @test_vsoxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9916; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:
9917; CHECK:       # %bb.0: # %entry
9918; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9919; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
9920; CHECK-NEXT:    ret
9921entry:
9922  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9923  ret void
9924}
9925
9926
9927define void @test_vsoxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9928; CHECK-LABEL: test_vsoxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:
9929; CHECK:       # %bb.0: # %entry
9930; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9931; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
9932; CHECK-NEXT:    ret
9933entry:
9934  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
9935  ret void
9936}
9937
9938define void @test_vsoxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9939; CHECK-LABEL: test_vsoxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:
9940; CHECK:       # %bb.0: # %entry
9941; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9942; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
9943; CHECK-NEXT:    ret
9944entry:
9945  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9946  ret void
9947}
9948
9949
9950define void @test_vsoxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
9951; CHECK-LABEL: test_vsoxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:
9952; CHECK:       # %bb.0: # %entry
9953; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9954; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
9955; CHECK-NEXT:    ret
9956entry:
9957  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
9958  ret void
9959}
9960
9961define void @test_vsoxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9962; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:
9963; CHECK:       # %bb.0: # %entry
9964; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9965; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
9966; CHECK-NEXT:    ret
9967entry:
9968  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9969  ret void
9970}
9971
9972
9973define void @test_vsoxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
9974; CHECK-LABEL: test_vsoxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:
9975; CHECK:       # %bb.0: # %entry
9976; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9977; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
9978; CHECK-NEXT:    ret
9979entry:
9980  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
9981  ret void
9982}
9983
9984define void @test_vsoxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
9985; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:
9986; CHECK:       # %bb.0: # %entry
9987; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
9988; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
9989; CHECK-NEXT:    ret
9990entry:
9991  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
9992  ret void
9993}
9994
9995
9996define void @test_vsoxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
9997; CHECK-LABEL: test_vsoxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:
9998; CHECK:       # %bb.0: # %entry
9999; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10000; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
10001; CHECK-NEXT:    ret
10002entry:
10003  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
10004  ret void
10005}
10006
10007define void @test_vsoxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10008; CHECK-LABEL: test_vsoxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:
10009; CHECK:       # %bb.0: # %entry
10010; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10011; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
10012; CHECK-NEXT:    ret
10013entry:
10014  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10015  ret void
10016}
10017
10018
10019define void @test_vsoxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
10020; CHECK-LABEL: test_vsoxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:
10021; CHECK:       # %bb.0: # %entry
10022; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10023; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
10024; CHECK-NEXT:    ret
10025entry:
10026  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
10027  ret void
10028}
10029
10030define void @test_vsoxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10031; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:
10032; CHECK:       # %bb.0: # %entry
10033; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10034; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
10035; CHECK-NEXT:    ret
10036entry:
10037  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10038  ret void
10039}
10040
10041
10042define void @test_vsoxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
10043; CHECK-LABEL: test_vsoxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:
10044; CHECK:       # %bb.0: # %entry
10045; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10046; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
10047; CHECK-NEXT:    ret
10048entry:
10049  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
10050  ret void
10051}
10052
10053define void @test_vsoxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10054; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:
10055; CHECK:       # %bb.0: # %entry
10056; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10057; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
10058; CHECK-NEXT:    ret
10059entry:
10060  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10061  ret void
10062}
10063
10064
10065define void @test_vsoxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
10066; CHECK-LABEL: test_vsoxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:
10067; CHECK:       # %bb.0: # %entry
10068; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10069; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
10070; CHECK-NEXT:    ret
10071entry:
10072  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
10073  ret void
10074}
10075
10076define void @test_vsoxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10077; CHECK-LABEL: test_vsoxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:
10078; CHECK:       # %bb.0: # %entry
10079; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10080; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
10081; CHECK-NEXT:    ret
10082entry:
10083  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10084  ret void
10085}
10086
10087
10088define void @test_vsoxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
10089; CHECK-LABEL: test_vsoxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:
10090; CHECK:       # %bb.0: # %entry
10091; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10092; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
10093; CHECK-NEXT:    ret
10094entry:
10095  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 6)
10096  ret void
10097}
10098
10099define void @test_vsoxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10100; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:
10101; CHECK:       # %bb.0: # %entry
10102; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10103; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
10104; CHECK-NEXT:    ret
10105entry:
10106  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10107  ret void
10108}
10109
10110
10111define void @test_vsoxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
10112; CHECK-LABEL: test_vsoxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:
10113; CHECK:       # %bb.0: # %entry
10114; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10115; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
10116; CHECK-NEXT:    ret
10117entry:
10118  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 6)
10119  ret void
10120}
10121
10122define void @test_vsoxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10123; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:
10124; CHECK:       # %bb.0: # %entry
10125; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10126; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
10127; CHECK-NEXT:    ret
10128entry:
10129  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10130  ret void
10131}
10132
10133
10134define void @test_vsoxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
10135; CHECK-LABEL: test_vsoxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:
10136; CHECK:       # %bb.0: # %entry
10137; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10138; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
10139; CHECK-NEXT:    ret
10140entry:
10141  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 6)
10142  ret void
10143}
10144
10145define void @test_vsoxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10146; CHECK-LABEL: test_vsoxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:
10147; CHECK:       # %bb.0: # %entry
10148; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
10149; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
10150; CHECK-NEXT:    ret
10151entry:
10152  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 6)
10153  ret void
10154}
10155
10156
10157define void @test_vsoxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
10158; CHECK-LABEL: test_vsoxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:
10159; CHECK:       # %bb.0: # %entry
10160; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10161; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
10162; CHECK-NEXT:    ret
10163entry:
10164  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
10165  ret void
10166}
10167
10168define void @test_vsoxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10169; CHECK-LABEL: test_vsoxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:
10170; CHECK:       # %bb.0: # %entry
10171; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10172; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
10173; CHECK-NEXT:    ret
10174entry:
10175  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10176  ret void
10177}
10178
10179
10180define void @test_vsoxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
10181; CHECK-LABEL: test_vsoxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:
10182; CHECK:       # %bb.0: # %entry
10183; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10184; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
10185; CHECK-NEXT:    ret
10186entry:
10187  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
10188  ret void
10189}
10190
10191define void @test_vsoxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10192; CHECK-LABEL: test_vsoxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:
10193; CHECK:       # %bb.0: # %entry
10194; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10195; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
10196; CHECK-NEXT:    ret
10197entry:
10198  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10199  ret void
10200}
10201
10202
10203define void @test_vsoxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
10204; CHECK-LABEL: test_vsoxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:
10205; CHECK:       # %bb.0: # %entry
10206; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10207; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
10208; CHECK-NEXT:    ret
10209entry:
10210  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
10211  ret void
10212}
10213
10214define void @test_vsoxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10215; CHECK-LABEL: test_vsoxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:
10216; CHECK:       # %bb.0: # %entry
10217; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10218; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
10219; CHECK-NEXT:    ret
10220entry:
10221  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10222  ret void
10223}
10224
10225
10226define void @test_vsoxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
10227; CHECK-LABEL: test_vsoxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:
10228; CHECK:       # %bb.0: # %entry
10229; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10230; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
10231; CHECK-NEXT:    ret
10232entry:
10233  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
10234  ret void
10235}
10236
10237define void @test_vsoxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10238; CHECK-LABEL: test_vsoxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:
10239; CHECK:       # %bb.0: # %entry
10240; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10241; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
10242; CHECK-NEXT:    ret
10243entry:
10244  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10245  ret void
10246}
10247
10248
10249define void @test_vsoxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
10250; CHECK-LABEL: test_vsoxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:
10251; CHECK:       # %bb.0: # %entry
10252; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10253; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
10254; CHECK-NEXT:    ret
10255entry:
10256  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
10257  ret void
10258}
10259
10260define void @test_vsoxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10261; CHECK-LABEL: test_vsoxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:
10262; CHECK:       # %bb.0: # %entry
10263; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10264; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
10265; CHECK-NEXT:    ret
10266entry:
10267  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10268  ret void
10269}
10270
10271
10272define void @test_vsoxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
10273; CHECK-LABEL: test_vsoxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:
10274; CHECK:       # %bb.0: # %entry
10275; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10276; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
10277; CHECK-NEXT:    ret
10278entry:
10279  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
10280  ret void
10281}
10282
10283define void @test_vsoxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10284; CHECK-LABEL: test_vsoxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:
10285; CHECK:       # %bb.0: # %entry
10286; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10287; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
10288; CHECK-NEXT:    ret
10289entry:
10290  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10291  ret void
10292}
10293
10294
10295define void @test_vsoxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
10296; CHECK-LABEL: test_vsoxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:
10297; CHECK:       # %bb.0: # %entry
10298; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10299; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10
10300; CHECK-NEXT:    ret
10301entry:
10302  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
10303  ret void
10304}
10305
10306define void @test_vsoxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10307; CHECK-LABEL: test_vsoxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:
10308; CHECK:       # %bb.0: # %entry
10309; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10310; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v10, v0.t
10311; CHECK-NEXT:    ret
10312entry:
10313  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10314  ret void
10315}
10316
10317
10318define void @test_vsoxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
10319; CHECK-LABEL: test_vsoxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:
10320; CHECK:       # %bb.0: # %entry
10321; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10322; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10
10323; CHECK-NEXT:    ret
10324entry:
10325  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
10326  ret void
10327}
10328
10329define void @test_vsoxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10330; CHECK-LABEL: test_vsoxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:
10331; CHECK:       # %bb.0: # %entry
10332; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10333; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v10, v0.t
10334; CHECK-NEXT:    ret
10335entry:
10336  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10337  ret void
10338}
10339
10340
10341define void @test_vsoxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
10342; CHECK-LABEL: test_vsoxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:
10343; CHECK:       # %bb.0: # %entry
10344; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10345; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10
10346; CHECK-NEXT:    ret
10347entry:
10348  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
10349  ret void
10350}
10351
10352define void @test_vsoxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10353; CHECK-LABEL: test_vsoxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:
10354; CHECK:       # %bb.0: # %entry
10355; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10356; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v10, v0.t
10357; CHECK-NEXT:    ret
10358entry:
10359  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10360  ret void
10361}
10362
10363
10364define void @test_vsoxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
10365; CHECK-LABEL: test_vsoxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:
10366; CHECK:       # %bb.0: # %entry
10367; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10368; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12
10369; CHECK-NEXT:    ret
10370entry:
10371  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
10372  ret void
10373}
10374
10375define void @test_vsoxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10376; CHECK-LABEL: test_vsoxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:
10377; CHECK:       # %bb.0: # %entry
10378; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10379; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v12, v0.t
10380; CHECK-NEXT:    ret
10381entry:
10382  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
10383  ret void
10384}
10385
10386
10387define void @test_vsoxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
10388; CHECK-LABEL: test_vsoxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:
10389; CHECK:       # %bb.0: # %entry
10390; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10391; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12
10392; CHECK-NEXT:    ret
10393entry:
10394  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
10395  ret void
10396}
10397
10398define void @test_vsoxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10399; CHECK-LABEL: test_vsoxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:
10400; CHECK:       # %bb.0: # %entry
10401; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10402; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v12, v0.t
10403; CHECK-NEXT:    ret
10404entry:
10405  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
10406  ret void
10407}
10408
10409
10410define void @test_vsoxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
10411; CHECK-LABEL: test_vsoxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:
10412; CHECK:       # %bb.0: # %entry
10413; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10414; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12
10415; CHECK-NEXT:    ret
10416entry:
10417  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
10418  ret void
10419}
10420
10421define void @test_vsoxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10422; CHECK-LABEL: test_vsoxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:
10423; CHECK:       # %bb.0: # %entry
10424; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10425; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v12, v0.t
10426; CHECK-NEXT:    ret
10427entry:
10428  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
10429  ret void
10430}
10431
10432
10433define void @test_vsoxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl) {
10434; CHECK-LABEL: test_vsoxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:
10435; CHECK:       # %bb.0: # %entry
10436; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
10437; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16
10438; CHECK-NEXT:    ret
10439entry:
10440  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, i32 4)
10441  ret void
10442}
10443
10444define void @test_vsoxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i32 %vl, <vscale x 16 x i1> %mask) {
10445; CHECK-LABEL: test_vsoxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:
10446; CHECK:       # %bb.0: # %entry
10447; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
10448; CHECK-NEXT:    vsoxseg2ei8.v v8, (a0), v16, v0.t
10449; CHECK-NEXT:    ret
10450entry:
10451  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
10452  ret void
10453}
10454
10455
10456define void @test_vsoxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl) {
10457; CHECK-LABEL: test_vsoxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:
10458; CHECK:       # %bb.0: # %entry
10459; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
10460; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16
10461; CHECK-NEXT:    ret
10462entry:
10463  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, i32 4)
10464  ret void
10465}
10466
10467define void @test_vsoxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i32 %vl, <vscale x 16 x i1> %mask) {
10468; CHECK-LABEL: test_vsoxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:
10469; CHECK:       # %bb.0: # %entry
10470; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
10471; CHECK-NEXT:    vsoxseg2ei16.v v8, (a0), v16, v0.t
10472; CHECK-NEXT:    ret
10473entry:
10474  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
10475  ret void
10476}
10477
10478
10479define void @test_vsoxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl) {
10480; CHECK-LABEL: test_vsoxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:
10481; CHECK:       # %bb.0: # %entry
10482; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
10483; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16
10484; CHECK-NEXT:    ret
10485entry:
10486  tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, i32 4)
10487  ret void
10488}
10489
10490define void @test_vsoxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i32 %vl, <vscale x 16 x i1> %mask) {
10491; CHECK-LABEL: test_vsoxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:
10492; CHECK:       # %bb.0: # %entry
10493; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
10494; CHECK-NEXT:    vsoxseg2ei32.v v8, (a0), v16, v0.t
10495; CHECK-NEXT:    ret
10496entry:
10497  tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i32 %vl, i32 4)
10498  ret void
10499}
10500
10501
10502define void @test_vsoxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
10503; CHECK-LABEL: test_vsoxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:
10504; CHECK:       # %bb.0: # %entry
10505; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10506; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
10507; CHECK-NEXT:    ret
10508entry:
10509  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
10510  ret void
10511}
10512
10513define void @test_vsoxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10514; CHECK-LABEL: test_vsoxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:
10515; CHECK:       # %bb.0: # %entry
10516; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10517; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
10518; CHECK-NEXT:    ret
10519entry:
10520  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10521  ret void
10522}
10523
10524
10525define void @test_vsoxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
10526; CHECK-LABEL: test_vsoxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:
10527; CHECK:       # %bb.0: # %entry
10528; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10529; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
10530; CHECK-NEXT:    ret
10531entry:
10532  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
10533  ret void
10534}
10535
10536define void @test_vsoxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10537; CHECK-LABEL: test_vsoxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:
10538; CHECK:       # %bb.0: # %entry
10539; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10540; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
10541; CHECK-NEXT:    ret
10542entry:
10543  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10544  ret void
10545}
10546
10547
10548define void @test_vsoxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
10549; CHECK-LABEL: test_vsoxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:
10550; CHECK:       # %bb.0: # %entry
10551; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10552; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
10553; CHECK-NEXT:    ret
10554entry:
10555  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
10556  ret void
10557}
10558
10559define void @test_vsoxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10560; CHECK-LABEL: test_vsoxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:
10561; CHECK:       # %bb.0: # %entry
10562; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10563; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
10564; CHECK-NEXT:    ret
10565entry:
10566  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10567  ret void
10568}
10569
10570
10571define void @test_vsoxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
10572; CHECK-LABEL: test_vsoxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:
10573; CHECK:       # %bb.0: # %entry
10574; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10575; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
10576; CHECK-NEXT:    ret
10577entry:
10578  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
10579  ret void
10580}
10581
10582define void @test_vsoxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10583; CHECK-LABEL: test_vsoxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:
10584; CHECK:       # %bb.0: # %entry
10585; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10586; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
10587; CHECK-NEXT:    ret
10588entry:
10589  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10590  ret void
10591}
10592
10593
10594define void @test_vsoxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
10595; CHECK-LABEL: test_vsoxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:
10596; CHECK:       # %bb.0: # %entry
10597; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10598; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
10599; CHECK-NEXT:    ret
10600entry:
10601  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
10602  ret void
10603}
10604
10605define void @test_vsoxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10606; CHECK-LABEL: test_vsoxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:
10607; CHECK:       # %bb.0: # %entry
10608; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10609; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
10610; CHECK-NEXT:    ret
10611entry:
10612  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10613  ret void
10614}
10615
10616
10617define void @test_vsoxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
10618; CHECK-LABEL: test_vsoxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:
10619; CHECK:       # %bb.0: # %entry
10620; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10621; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11
10622; CHECK-NEXT:    ret
10623entry:
10624  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
10625  ret void
10626}
10627
10628define void @test_vsoxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10629; CHECK-LABEL: test_vsoxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:
10630; CHECK:       # %bb.0: # %entry
10631; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10632; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v11, v0.t
10633; CHECK-NEXT:    ret
10634entry:
10635  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10636  ret void
10637}
10638
10639
10640define void @test_vsoxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
10641; CHECK-LABEL: test_vsoxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:
10642; CHECK:       # %bb.0: # %entry
10643; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10644; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11
10645; CHECK-NEXT:    ret
10646entry:
10647  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
10648  ret void
10649}
10650
10651define void @test_vsoxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10652; CHECK-LABEL: test_vsoxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:
10653; CHECK:       # %bb.0: # %entry
10654; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10655; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v11, v0.t
10656; CHECK-NEXT:    ret
10657entry:
10658  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10659  ret void
10660}
10661
10662
10663define void @test_vsoxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
10664; CHECK-LABEL: test_vsoxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:
10665; CHECK:       # %bb.0: # %entry
10666; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10667; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11
10668; CHECK-NEXT:    ret
10669entry:
10670  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
10671  ret void
10672}
10673
10674define void @test_vsoxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10675; CHECK-LABEL: test_vsoxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:
10676; CHECK:       # %bb.0: # %entry
10677; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10678; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v11, v0.t
10679; CHECK-NEXT:    ret
10680entry:
10681  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10682  ret void
10683}
10684
10685
10686define void @test_vsoxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
10687; CHECK-LABEL: test_vsoxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:
10688; CHECK:       # %bb.0: # %entry
10689; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10690; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12
10691; CHECK-NEXT:    ret
10692entry:
10693  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
10694  ret void
10695}
10696
10697define void @test_vsoxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10698; CHECK-LABEL: test_vsoxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:
10699; CHECK:       # %bb.0: # %entry
10700; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10701; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v12, v0.t
10702; CHECK-NEXT:    ret
10703entry:
10704  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10705  ret void
10706}
10707
10708
10709define void @test_vsoxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
10710; CHECK-LABEL: test_vsoxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:
10711; CHECK:       # %bb.0: # %entry
10712; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10713; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14
10714; CHECK-NEXT:    ret
10715entry:
10716  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
10717  ret void
10718}
10719
10720define void @test_vsoxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10721; CHECK-LABEL: test_vsoxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:
10722; CHECK:       # %bb.0: # %entry
10723; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10724; CHECK-NEXT:    vsoxseg3ei8.v v8, (a0), v14, v0.t
10725; CHECK-NEXT:    ret
10726entry:
10727  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
10728  ret void
10729}
10730
10731
10732define void @test_vsoxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
10733; CHECK-LABEL: test_vsoxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:
10734; CHECK:       # %bb.0: # %entry
10735; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10736; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14
10737; CHECK-NEXT:    ret
10738entry:
10739  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
10740  ret void
10741}
10742
10743define void @test_vsoxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10744; CHECK-LABEL: test_vsoxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:
10745; CHECK:       # %bb.0: # %entry
10746; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10747; CHECK-NEXT:    vsoxseg3ei16.v v8, (a0), v14, v0.t
10748; CHECK-NEXT:    ret
10749entry:
10750  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
10751  ret void
10752}
10753
10754
10755define void @test_vsoxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
10756; CHECK-LABEL: test_vsoxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:
10757; CHECK:       # %bb.0: # %entry
10758; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10759; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16
10760; CHECK-NEXT:    ret
10761entry:
10762  tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
10763  ret void
10764}
10765
10766define void @test_vsoxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10767; CHECK-LABEL: test_vsoxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:
10768; CHECK:       # %bb.0: # %entry
10769; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10770; CHECK-NEXT:    vsoxseg3ei32.v v8, (a0), v16, v0.t
10771; CHECK-NEXT:    ret
10772entry:
10773  tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
10774  ret void
10775}
10776
10777
10778define void @test_vsoxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
10779; CHECK-LABEL: test_vsoxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:
10780; CHECK:       # %bb.0: # %entry
10781; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10782; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
10783; CHECK-NEXT:    ret
10784entry:
10785  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
10786  ret void
10787}
10788
10789define void @test_vsoxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10790; CHECK-LABEL: test_vsoxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:
10791; CHECK:       # %bb.0: # %entry
10792; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10793; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
10794; CHECK-NEXT:    ret
10795entry:
10796  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10797  ret void
10798}
10799
10800
10801define void @test_vsoxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
10802; CHECK-LABEL: test_vsoxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:
10803; CHECK:       # %bb.0: # %entry
10804; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10805; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
10806; CHECK-NEXT:    ret
10807entry:
10808  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
10809  ret void
10810}
10811
10812define void @test_vsoxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10813; CHECK-LABEL: test_vsoxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:
10814; CHECK:       # %bb.0: # %entry
10815; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10816; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
10817; CHECK-NEXT:    ret
10818entry:
10819  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10820  ret void
10821}
10822
10823
10824define void @test_vsoxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
10825; CHECK-LABEL: test_vsoxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:
10826; CHECK:       # %bb.0: # %entry
10827; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10828; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
10829; CHECK-NEXT:    ret
10830entry:
10831  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
10832  ret void
10833}
10834
10835define void @test_vsoxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
10836; CHECK-LABEL: test_vsoxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:
10837; CHECK:       # %bb.0: # %entry
10838; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
10839; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
10840; CHECK-NEXT:    ret
10841entry:
10842  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
10843  ret void
10844}
10845
10846
10847define void @test_vsoxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
10848; CHECK-LABEL: test_vsoxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:
10849; CHECK:       # %bb.0: # %entry
10850; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10851; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
10852; CHECK-NEXT:    ret
10853entry:
10854  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
10855  ret void
10856}
10857
10858define void @test_vsoxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10859; CHECK-LABEL: test_vsoxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:
10860; CHECK:       # %bb.0: # %entry
10861; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10862; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
10863; CHECK-NEXT:    ret
10864entry:
10865  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10866  ret void
10867}
10868
10869
10870define void @test_vsoxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
10871; CHECK-LABEL: test_vsoxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:
10872; CHECK:       # %bb.0: # %entry
10873; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10874; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
10875; CHECK-NEXT:    ret
10876entry:
10877  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
10878  ret void
10879}
10880
10881define void @test_vsoxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10882; CHECK-LABEL: test_vsoxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:
10883; CHECK:       # %bb.0: # %entry
10884; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10885; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
10886; CHECK-NEXT:    ret
10887entry:
10888  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10889  ret void
10890}
10891
10892
10893define void @test_vsoxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
10894; CHECK-LABEL: test_vsoxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:
10895; CHECK:       # %bb.0: # %entry
10896; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10897; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
10898; CHECK-NEXT:    ret
10899entry:
10900  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
10901  ret void
10902}
10903
10904define void @test_vsoxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
10905; CHECK-LABEL: test_vsoxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:
10906; CHECK:       # %bb.0: # %entry
10907; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
10908; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
10909; CHECK-NEXT:    ret
10910entry:
10911  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
10912  ret void
10913}
10914
10915
10916define void @test_vsoxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
10917; CHECK-LABEL: test_vsoxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:
10918; CHECK:       # %bb.0: # %entry
10919; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10920; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12
10921; CHECK-NEXT:    ret
10922entry:
10923  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
10924  ret void
10925}
10926
10927define void @test_vsoxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10928; CHECK-LABEL: test_vsoxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:
10929; CHECK:       # %bb.0: # %entry
10930; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10931; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v12, v0.t
10932; CHECK-NEXT:    ret
10933entry:
10934  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10935  ret void
10936}
10937
10938
10939define void @test_vsoxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
10940; CHECK-LABEL: test_vsoxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:
10941; CHECK:       # %bb.0: # %entry
10942; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10943; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12
10944; CHECK-NEXT:    ret
10945entry:
10946  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
10947  ret void
10948}
10949
10950define void @test_vsoxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10951; CHECK-LABEL: test_vsoxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:
10952; CHECK:       # %bb.0: # %entry
10953; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10954; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v12, v0.t
10955; CHECK-NEXT:    ret
10956entry:
10957  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10958  ret void
10959}
10960
10961
10962define void @test_vsoxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
10963; CHECK-LABEL: test_vsoxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:
10964; CHECK:       # %bb.0: # %entry
10965; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10966; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12
10967; CHECK-NEXT:    ret
10968entry:
10969  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
10970  ret void
10971}
10972
10973define void @test_vsoxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
10974; CHECK-LABEL: test_vsoxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:
10975; CHECK:       # %bb.0: # %entry
10976; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
10977; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v12, v0.t
10978; CHECK-NEXT:    ret
10979entry:
10980  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
10981  ret void
10982}
10983
10984
10985define void @test_vsoxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl) {
10986; CHECK-LABEL: test_vsoxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:
10987; CHECK:       # %bb.0: # %entry
10988; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
10989; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16
10990; CHECK-NEXT:    ret
10991entry:
10992  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, i32 4)
10993  ret void
10994}
10995
10996define void @test_vsoxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i32 %vl, <vscale x 8 x i1> %mask) {
10997; CHECK-LABEL: test_vsoxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:
10998; CHECK:       # %bb.0: # %entry
10999; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
11000; CHECK-NEXT:    vsoxseg4ei8.v v8, (a0), v16, v0.t
11001; CHECK-NEXT:    ret
11002entry:
11003  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
11004  ret void
11005}
11006
11007
11008define void @test_vsoxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl) {
11009; CHECK-LABEL: test_vsoxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:
11010; CHECK:       # %bb.0: # %entry
11011; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
11012; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16
11013; CHECK-NEXT:    ret
11014entry:
11015  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, i32 4)
11016  ret void
11017}
11018
11019define void @test_vsoxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i32 %vl, <vscale x 8 x i1> %mask) {
11020; CHECK-LABEL: test_vsoxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:
11021; CHECK:       # %bb.0: # %entry
11022; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
11023; CHECK-NEXT:    vsoxseg4ei16.v v8, (a0), v16, v0.t
11024; CHECK-NEXT:    ret
11025entry:
11026  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
11027  ret void
11028}
11029
11030
11031define void @test_vsoxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl) {
11032; CHECK-LABEL: test_vsoxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:
11033; CHECK:       # %bb.0: # %entry
11034; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
11035; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16
11036; CHECK-NEXT:    ret
11037entry:
11038  tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, i32 4)
11039  ret void
11040}
11041
11042define void @test_vsoxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i32 %vl, <vscale x 8 x i1> %mask) {
11043; CHECK-LABEL: test_vsoxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:
11044; CHECK:       # %bb.0: # %entry
11045; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
11046; CHECK-NEXT:    vsoxseg4ei32.v v8, (a0), v16, v0.t
11047; CHECK-NEXT:    ret
11048entry:
11049  tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i32 %vl, i32 4)
11050  ret void
11051}
11052
11053
11054define void @test_vsoxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
11055; CHECK-LABEL: test_vsoxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:
11056; CHECK:       # %bb.0: # %entry
11057; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11058; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
11059; CHECK-NEXT:    ret
11060entry:
11061  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
11062  ret void
11063}
11064
11065define void @test_vsoxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11066; CHECK-LABEL: test_vsoxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:
11067; CHECK:       # %bb.0: # %entry
11068; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11069; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
11070; CHECK-NEXT:    ret
11071entry:
11072  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11073  ret void
11074}
11075
11076
11077define void @test_vsoxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
11078; CHECK-LABEL: test_vsoxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:
11079; CHECK:       # %bb.0: # %entry
11080; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11081; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
11082; CHECK-NEXT:    ret
11083entry:
11084  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
11085  ret void
11086}
11087
11088define void @test_vsoxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11089; CHECK-LABEL: test_vsoxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:
11090; CHECK:       # %bb.0: # %entry
11091; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11092; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
11093; CHECK-NEXT:    ret
11094entry:
11095  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11096  ret void
11097}
11098
11099
11100define void @test_vsoxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
11101; CHECK-LABEL: test_vsoxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:
11102; CHECK:       # %bb.0: # %entry
11103; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11104; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
11105; CHECK-NEXT:    ret
11106entry:
11107  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
11108  ret void
11109}
11110
11111define void @test_vsoxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11112; CHECK-LABEL: test_vsoxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:
11113; CHECK:       # %bb.0: # %entry
11114; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11115; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
11116; CHECK-NEXT:    ret
11117entry:
11118  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11119  ret void
11120}
11121
11122
11123define void @test_vsoxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
11124; CHECK-LABEL: test_vsoxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:
11125; CHECK:       # %bb.0: # %entry
11126; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11127; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
11128; CHECK-NEXT:    ret
11129entry:
11130  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
11131  ret void
11132}
11133
11134define void @test_vsoxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11135; CHECK-LABEL: test_vsoxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:
11136; CHECK:       # %bb.0: # %entry
11137; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11138; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
11139; CHECK-NEXT:    ret
11140entry:
11141  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11142  ret void
11143}
11144
11145
11146define void @test_vsoxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
11147; CHECK-LABEL: test_vsoxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:
11148; CHECK:       # %bb.0: # %entry
11149; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11150; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
11151; CHECK-NEXT:    ret
11152entry:
11153  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
11154  ret void
11155}
11156
11157define void @test_vsoxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11158; CHECK-LABEL: test_vsoxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:
11159; CHECK:       # %bb.0: # %entry
11160; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11161; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
11162; CHECK-NEXT:    ret
11163entry:
11164  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11165  ret void
11166}
11167
11168
11169define void @test_vsoxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
11170; CHECK-LABEL: test_vsoxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:
11171; CHECK:       # %bb.0: # %entry
11172; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11173; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13
11174; CHECK-NEXT:    ret
11175entry:
11176  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
11177  ret void
11178}
11179
11180define void @test_vsoxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11181; CHECK-LABEL: test_vsoxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:
11182; CHECK:       # %bb.0: # %entry
11183; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11184; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v13, v0.t
11185; CHECK-NEXT:    ret
11186entry:
11187  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11188  ret void
11189}
11190
11191
11192define void @test_vsoxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
11193; CHECK-LABEL: test_vsoxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:
11194; CHECK:       # %bb.0: # %entry
11195; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11196; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13
11197; CHECK-NEXT:    ret
11198entry:
11199  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
11200  ret void
11201}
11202
11203define void @test_vsoxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11204; CHECK-LABEL: test_vsoxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:
11205; CHECK:       # %bb.0: # %entry
11206; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11207; CHECK-NEXT:    vsoxseg5ei8.v v8, (a0), v13, v0.t
11208; CHECK-NEXT:    ret
11209entry:
11210  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11211  ret void
11212}
11213
11214
11215define void @test_vsoxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
11216; CHECK-LABEL: test_vsoxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:
11217; CHECK:       # %bb.0: # %entry
11218; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11219; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13
11220; CHECK-NEXT:    ret
11221entry:
11222  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
11223  ret void
11224}
11225
11226define void @test_vsoxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11227; CHECK-LABEL: test_vsoxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:
11228; CHECK:       # %bb.0: # %entry
11229; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11230; CHECK-NEXT:    vsoxseg5ei16.v v8, (a0), v13, v0.t
11231; CHECK-NEXT:    ret
11232entry:
11233  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11234  ret void
11235}
11236
11237
11238define void @test_vsoxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
11239; CHECK-LABEL: test_vsoxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:
11240; CHECK:       # %bb.0: # %entry
11241; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11242; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14
11243; CHECK-NEXT:    ret
11244entry:
11245  tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
11246  ret void
11247}
11248
11249define void @test_vsoxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11250; CHECK-LABEL: test_vsoxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:
11251; CHECK:       # %bb.0: # %entry
11252; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11253; CHECK-NEXT:    vsoxseg5ei32.v v8, (a0), v14, v0.t
11254; CHECK-NEXT:    ret
11255entry:
11256  tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11257  ret void
11258}
11259
11260
11261define void @test_vsoxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
11262; CHECK-LABEL: test_vsoxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:
11263; CHECK:       # %bb.0: # %entry
11264; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11265; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
11266; CHECK-NEXT:    ret
11267entry:
11268  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
11269  ret void
11270}
11271
11272define void @test_vsoxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11273; CHECK-LABEL: test_vsoxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:
11274; CHECK:       # %bb.0: # %entry
11275; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11276; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
11277; CHECK-NEXT:    ret
11278entry:
11279  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11280  ret void
11281}
11282
11283
11284define void @test_vsoxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
11285; CHECK-LABEL: test_vsoxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:
11286; CHECK:       # %bb.0: # %entry
11287; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11288; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
11289; CHECK-NEXT:    ret
11290entry:
11291  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
11292  ret void
11293}
11294
11295define void @test_vsoxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11296; CHECK-LABEL: test_vsoxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:
11297; CHECK:       # %bb.0: # %entry
11298; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11299; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
11300; CHECK-NEXT:    ret
11301entry:
11302  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11303  ret void
11304}
11305
11306
11307define void @test_vsoxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
11308; CHECK-LABEL: test_vsoxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:
11309; CHECK:       # %bb.0: # %entry
11310; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11311; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
11312; CHECK-NEXT:    ret
11313entry:
11314  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
11315  ret void
11316}
11317
11318define void @test_vsoxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11319; CHECK-LABEL: test_vsoxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:
11320; CHECK:       # %bb.0: # %entry
11321; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11322; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
11323; CHECK-NEXT:    ret
11324entry:
11325  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11326  ret void
11327}
11328
11329
11330define void @test_vsoxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
11331; CHECK-LABEL: test_vsoxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:
11332; CHECK:       # %bb.0: # %entry
11333; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11334; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
11335; CHECK-NEXT:    ret
11336entry:
11337  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
11338  ret void
11339}
11340
11341define void @test_vsoxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11342; CHECK-LABEL: test_vsoxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:
11343; CHECK:       # %bb.0: # %entry
11344; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11345; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
11346; CHECK-NEXT:    ret
11347entry:
11348  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11349  ret void
11350}
11351
11352
11353define void @test_vsoxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
11354; CHECK-LABEL: test_vsoxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:
11355; CHECK:       # %bb.0: # %entry
11356; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11357; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
11358; CHECK-NEXT:    ret
11359entry:
11360  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
11361  ret void
11362}
11363
11364define void @test_vsoxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11365; CHECK-LABEL: test_vsoxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:
11366; CHECK:       # %bb.0: # %entry
11367; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11368; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
11369; CHECK-NEXT:    ret
11370entry:
11371  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11372  ret void
11373}
11374
11375
11376define void @test_vsoxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
11377; CHECK-LABEL: test_vsoxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:
11378; CHECK:       # %bb.0: # %entry
11379; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11380; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
11381; CHECK-NEXT:    ret
11382entry:
11383  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
11384  ret void
11385}
11386
11387define void @test_vsoxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11388; CHECK-LABEL: test_vsoxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:
11389; CHECK:       # %bb.0: # %entry
11390; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11391; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
11392; CHECK-NEXT:    ret
11393entry:
11394  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11395  ret void
11396}
11397
11398
11399define void @test_vsoxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
11400; CHECK-LABEL: test_vsoxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:
11401; CHECK:       # %bb.0: # %entry
11402; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11403; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14
11404; CHECK-NEXT:    ret
11405entry:
11406  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
11407  ret void
11408}
11409
11410define void @test_vsoxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11411; CHECK-LABEL: test_vsoxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:
11412; CHECK:       # %bb.0: # %entry
11413; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11414; CHECK-NEXT:    vsoxseg6ei8.v v8, (a0), v14, v0.t
11415; CHECK-NEXT:    ret
11416entry:
11417  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11418  ret void
11419}
11420
11421
11422define void @test_vsoxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
11423; CHECK-LABEL: test_vsoxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:
11424; CHECK:       # %bb.0: # %entry
11425; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11426; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14
11427; CHECK-NEXT:    ret
11428entry:
11429  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
11430  ret void
11431}
11432
11433define void @test_vsoxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11434; CHECK-LABEL: test_vsoxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:
11435; CHECK:       # %bb.0: # %entry
11436; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11437; CHECK-NEXT:    vsoxseg6ei16.v v8, (a0), v14, v0.t
11438; CHECK-NEXT:    ret
11439entry:
11440  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11441  ret void
11442}
11443
11444
11445define void @test_vsoxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
11446; CHECK-LABEL: test_vsoxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:
11447; CHECK:       # %bb.0: # %entry
11448; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11449; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14
11450; CHECK-NEXT:    ret
11451entry:
11452  tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
11453  ret void
11454}
11455
11456define void @test_vsoxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11457; CHECK-LABEL: test_vsoxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:
11458; CHECK:       # %bb.0: # %entry
11459; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11460; CHECK-NEXT:    vsoxseg6ei32.v v8, (a0), v14, v0.t
11461; CHECK-NEXT:    ret
11462entry:
11463  tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11464  ret void
11465}
11466
11467
11468define void @test_vsoxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
11469; CHECK-LABEL: test_vsoxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:
11470; CHECK:       # %bb.0: # %entry
11471; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11472; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
11473; CHECK-NEXT:    ret
11474entry:
11475  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
11476  ret void
11477}
11478
11479define void @test_vsoxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11480; CHECK-LABEL: test_vsoxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:
11481; CHECK:       # %bb.0: # %entry
11482; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11483; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
11484; CHECK-NEXT:    ret
11485entry:
11486  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11487  ret void
11488}
11489
11490
11491define void @test_vsoxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
11492; CHECK-LABEL: test_vsoxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:
11493; CHECK:       # %bb.0: # %entry
11494; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11495; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
11496; CHECK-NEXT:    ret
11497entry:
11498  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
11499  ret void
11500}
11501
11502define void @test_vsoxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11503; CHECK-LABEL: test_vsoxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:
11504; CHECK:       # %bb.0: # %entry
11505; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11506; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
11507; CHECK-NEXT:    ret
11508entry:
11509  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11510  ret void
11511}
11512
11513
11514define void @test_vsoxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
11515; CHECK-LABEL: test_vsoxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:
11516; CHECK:       # %bb.0: # %entry
11517; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11518; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
11519; CHECK-NEXT:    ret
11520entry:
11521  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
11522  ret void
11523}
11524
11525define void @test_vsoxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11526; CHECK-LABEL: test_vsoxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:
11527; CHECK:       # %bb.0: # %entry
11528; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11529; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
11530; CHECK-NEXT:    ret
11531entry:
11532  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11533  ret void
11534}
11535
11536
11537define void @test_vsoxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
11538; CHECK-LABEL: test_vsoxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:
11539; CHECK:       # %bb.0: # %entry
11540; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11541; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
11542; CHECK-NEXT:    ret
11543entry:
11544  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
11545  ret void
11546}
11547
11548define void @test_vsoxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11549; CHECK-LABEL: test_vsoxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:
11550; CHECK:       # %bb.0: # %entry
11551; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11552; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
11553; CHECK-NEXT:    ret
11554entry:
11555  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11556  ret void
11557}
11558
11559
11560define void @test_vsoxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
11561; CHECK-LABEL: test_vsoxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:
11562; CHECK:       # %bb.0: # %entry
11563; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11564; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
11565; CHECK-NEXT:    ret
11566entry:
11567  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
11568  ret void
11569}
11570
11571define void @test_vsoxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11572; CHECK-LABEL: test_vsoxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:
11573; CHECK:       # %bb.0: # %entry
11574; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11575; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
11576; CHECK-NEXT:    ret
11577entry:
11578  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11579  ret void
11580}
11581
11582
11583define void @test_vsoxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
11584; CHECK-LABEL: test_vsoxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:
11585; CHECK:       # %bb.0: # %entry
11586; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11587; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15
11588; CHECK-NEXT:    ret
11589entry:
11590  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
11591  ret void
11592}
11593
11594define void @test_vsoxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11595; CHECK-LABEL: test_vsoxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:
11596; CHECK:       # %bb.0: # %entry
11597; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11598; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v15, v0.t
11599; CHECK-NEXT:    ret
11600entry:
11601  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11602  ret void
11603}
11604
11605
11606define void @test_vsoxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
11607; CHECK-LABEL: test_vsoxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:
11608; CHECK:       # %bb.0: # %entry
11609; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11610; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15
11611; CHECK-NEXT:    ret
11612entry:
11613  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
11614  ret void
11615}
11616
11617define void @test_vsoxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11618; CHECK-LABEL: test_vsoxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:
11619; CHECK:       # %bb.0: # %entry
11620; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11621; CHECK-NEXT:    vsoxseg7ei8.v v8, (a0), v15, v0.t
11622; CHECK-NEXT:    ret
11623entry:
11624  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11625  ret void
11626}
11627
11628
11629define void @test_vsoxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
11630; CHECK-LABEL: test_vsoxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:
11631; CHECK:       # %bb.0: # %entry
11632; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11633; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15
11634; CHECK-NEXT:    ret
11635entry:
11636  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
11637  ret void
11638}
11639
11640define void @test_vsoxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11641; CHECK-LABEL: test_vsoxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:
11642; CHECK:       # %bb.0: # %entry
11643; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11644; CHECK-NEXT:    vsoxseg7ei16.v v8, (a0), v15, v0.t
11645; CHECK-NEXT:    ret
11646entry:
11647  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11648  ret void
11649}
11650
11651
11652define void @test_vsoxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
11653; CHECK-LABEL: test_vsoxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:
11654; CHECK:       # %bb.0: # %entry
11655; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11656; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16
11657; CHECK-NEXT:    ret
11658entry:
11659  tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
11660  ret void
11661}
11662
11663define void @test_vsoxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11664; CHECK-LABEL: test_vsoxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:
11665; CHECK:       # %bb.0: # %entry
11666; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11667; CHECK-NEXT:    vsoxseg7ei32.v v8, (a0), v16, v0.t
11668; CHECK-NEXT:    ret
11669entry:
11670  tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11671  ret void
11672}
11673
11674
11675define void @test_vsoxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl) {
11676; CHECK-LABEL: test_vsoxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:
11677; CHECK:       # %bb.0: # %entry
11678; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11679; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
11680; CHECK-NEXT:    ret
11681entry:
11682  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, i32 4)
11683  ret void
11684}
11685
11686define void @test_vsoxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11687; CHECK-LABEL: test_vsoxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:
11688; CHECK:       # %bb.0: # %entry
11689; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11690; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
11691; CHECK-NEXT:    ret
11692entry:
11693  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11694  ret void
11695}
11696
11697
11698define void @test_vsoxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl) {
11699; CHECK-LABEL: test_vsoxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:
11700; CHECK:       # %bb.0: # %entry
11701; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11702; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
11703; CHECK-NEXT:    ret
11704entry:
11705  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, i32 4)
11706  ret void
11707}
11708
11709define void @test_vsoxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11710; CHECK-LABEL: test_vsoxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:
11711; CHECK:       # %bb.0: # %entry
11712; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11713; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
11714; CHECK-NEXT:    ret
11715entry:
11716  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11717  ret void
11718}
11719
11720
11721define void @test_vsoxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl) {
11722; CHECK-LABEL: test_vsoxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:
11723; CHECK:       # %bb.0: # %entry
11724; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11725; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
11726; CHECK-NEXT:    ret
11727entry:
11728  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, i32 4)
11729  ret void
11730}
11731
11732define void @test_vsoxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i32 %vl, <vscale x 1 x i1> %mask) {
11733; CHECK-LABEL: test_vsoxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:
11734; CHECK:       # %bb.0: # %entry
11735; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
11736; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
11737; CHECK-NEXT:    ret
11738entry:
11739  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i32 %vl, i32 4)
11740  ret void
11741}
11742
11743
11744define void @test_vsoxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl) {
11745; CHECK-LABEL: test_vsoxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:
11746; CHECK:       # %bb.0: # %entry
11747; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11748; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
11749; CHECK-NEXT:    ret
11750entry:
11751  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, i32 4)
11752  ret void
11753}
11754
11755define void @test_vsoxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11756; CHECK-LABEL: test_vsoxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:
11757; CHECK:       # %bb.0: # %entry
11758; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11759; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
11760; CHECK-NEXT:    ret
11761entry:
11762  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11763  ret void
11764}
11765
11766
11767define void @test_vsoxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl) {
11768; CHECK-LABEL: test_vsoxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:
11769; CHECK:       # %bb.0: # %entry
11770; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11771; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
11772; CHECK-NEXT:    ret
11773entry:
11774  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, i32 4)
11775  ret void
11776}
11777
11778define void @test_vsoxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11779; CHECK-LABEL: test_vsoxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:
11780; CHECK:       # %bb.0: # %entry
11781; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11782; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
11783; CHECK-NEXT:    ret
11784entry:
11785  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11786  ret void
11787}
11788
11789
11790define void @test_vsoxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl) {
11791; CHECK-LABEL: test_vsoxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:
11792; CHECK:       # %bb.0: # %entry
11793; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11794; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
11795; CHECK-NEXT:    ret
11796entry:
11797  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, i32 4)
11798  ret void
11799}
11800
11801define void @test_vsoxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i32 %vl, <vscale x 2 x i1> %mask) {
11802; CHECK-LABEL: test_vsoxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:
11803; CHECK:       # %bb.0: # %entry
11804; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
11805; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
11806; CHECK-NEXT:    ret
11807entry:
11808  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i32 %vl, i32 4)
11809  ret void
11810}
11811
11812
11813define void @test_vsoxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl) {
11814; CHECK-LABEL: test_vsoxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:
11815; CHECK:       # %bb.0: # %entry
11816; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11817; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16
11818; CHECK-NEXT:    ret
11819entry:
11820  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, i32 4)
11821  ret void
11822}
11823
11824define void @test_vsoxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11825; CHECK-LABEL: test_vsoxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:
11826; CHECK:       # %bb.0: # %entry
11827; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11828; CHECK-NEXT:    vsoxseg8ei8.v v8, (a0), v16, v0.t
11829; CHECK-NEXT:    ret
11830entry:
11831  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11832  ret void
11833}
11834
11835
11836define void @test_vsoxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl) {
11837; CHECK-LABEL: test_vsoxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:
11838; CHECK:       # %bb.0: # %entry
11839; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11840; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16
11841; CHECK-NEXT:    ret
11842entry:
11843  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, i32 4)
11844  ret void
11845}
11846
11847define void @test_vsoxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11848; CHECK-LABEL: test_vsoxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:
11849; CHECK:       # %bb.0: # %entry
11850; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11851; CHECK-NEXT:    vsoxseg8ei16.v v8, (a0), v16, v0.t
11852; CHECK-NEXT:    ret
11853entry:
11854  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11855  ret void
11856}
11857
11858
11859define void @test_vsoxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl) {
11860; CHECK-LABEL: test_vsoxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:
11861; CHECK:       # %bb.0: # %entry
11862; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11863; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16
11864; CHECK-NEXT:    ret
11865entry:
11866  tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, i32 4)
11867  ret void
11868}
11869
11870define void @test_vsoxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i32 %vl, <vscale x 4 x i1> %mask) {
11871; CHECK-LABEL: test_vsoxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:
11872; CHECK:       # %bb.0: # %entry
11873; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
11874; CHECK-NEXT:    vsoxseg8ei32.v v8, (a0), v16, v0.t
11875; CHECK-NEXT:    ret
11876entry:
11877  tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i32 %vl, i32 4)
11878  ret void
11879}
11880
11881