xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vselect-int.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7define <vscale x 1 x i8> @vmerge_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %cond) {
8; CHECK-LABEL: vmerge_vv_nxv1i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
11; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
12; CHECK-NEXT:    ret
13  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vmerge_xv_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b, <vscale x 1 x i1> %cond) {
18; CHECK-LABEL: vmerge_xv_nxv1i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
21; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
22; CHECK-NEXT:    ret
23  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
24  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
25  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %splat, <vscale x 1 x i8> %va
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vmerge_iv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %cond) {
30; CHECK-LABEL: vmerge_iv_nxv1i8:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
33; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
34; CHECK-NEXT:    ret
35  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> splat (i8 3), <vscale x 1 x i8> %va
36  ret <vscale x 1 x i8> %vc
37}
38
39define <vscale x 2 x i8> @vmerge_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %cond) {
40; CHECK-LABEL: vmerge_vv_nxv2i8:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
43; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
44; CHECK-NEXT:    ret
45  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
46  ret <vscale x 2 x i8> %vc
47}
48
49define <vscale x 2 x i8> @vmerge_xv_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b, <vscale x 2 x i1> %cond) {
50; CHECK-LABEL: vmerge_xv_nxv2i8:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
53; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
54; CHECK-NEXT:    ret
55  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
56  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
57  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i8> %splat, <vscale x 2 x i8> %va
58  ret <vscale x 2 x i8> %vc
59}
60
61define <vscale x 2 x i8> @vmerge_iv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %cond) {
62; CHECK-LABEL: vmerge_iv_nxv2i8:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
65; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
66; CHECK-NEXT:    ret
67  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i8> splat (i8 3), <vscale x 2 x i8> %va
68  ret <vscale x 2 x i8> %vc
69}
70
71define <vscale x 3 x i8> @vmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %cond) {
72; CHECK-LABEL: vmerge_vv_nxv3i8:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
75; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
76; CHECK-NEXT:    ret
77  %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb
78  ret <vscale x 3 x i8> %vc
79}
80
81define <vscale x 3 x i8> @vmerge_xv_nxv3i8(<vscale x 3 x i8> %va, i8 signext %b, <vscale x 3 x i1> %cond) {
82; CHECK-LABEL: vmerge_xv_nxv3i8:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
85; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
86; CHECK-NEXT:    ret
87  %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0
88  %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer
89  %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %splat, <vscale x 3 x i8> %va
90  ret <vscale x 3 x i8> %vc
91}
92
93define <vscale x 3 x i8> @vmerge_iv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %cond) {
94; CHECK-LABEL: vmerge_iv_nxv3i8:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
97; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
98; CHECK-NEXT:    ret
99  %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> splat (i8 3), <vscale x 3 x i8> %va
100  ret <vscale x 3 x i8> %vc
101}
102
103define <vscale x 4 x i8> @vmerge_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %cond) {
104; CHECK-LABEL: vmerge_vv_nxv4i8:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
107; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
108; CHECK-NEXT:    ret
109  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
110  ret <vscale x 4 x i8> %vc
111}
112
113define <vscale x 4 x i8> @vmerge_xv_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b, <vscale x 4 x i1> %cond) {
114; CHECK-LABEL: vmerge_xv_nxv4i8:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
117; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
118; CHECK-NEXT:    ret
119  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
120  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
121  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i8> %splat, <vscale x 4 x i8> %va
122  ret <vscale x 4 x i8> %vc
123}
124
125define <vscale x 4 x i8> @vmerge_iv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %cond) {
126; CHECK-LABEL: vmerge_iv_nxv4i8:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
129; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
130; CHECK-NEXT:    ret
131  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i8> splat (i8 3), <vscale x 4 x i8> %va
132  ret <vscale x 4 x i8> %vc
133}
134
135define <vscale x 8 x i8> @vmerge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %cond) {
136; CHECK-LABEL: vmerge_vv_nxv8i8:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
139; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
140; CHECK-NEXT:    ret
141  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
142  ret <vscale x 8 x i8> %vc
143}
144
145define <vscale x 8 x i8> @vmerge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b, <vscale x 8 x i1> %cond) {
146; CHECK-LABEL: vmerge_xv_nxv8i8:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
149; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
150; CHECK-NEXT:    ret
151  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
152  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
153  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i8> %splat, <vscale x 8 x i8> %va
154  ret <vscale x 8 x i8> %vc
155}
156
157define <vscale x 8 x i8> @vmerge_iv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %cond) {
158; CHECK-LABEL: vmerge_iv_nxv8i8:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
161; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
162; CHECK-NEXT:    ret
163  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i8> splat (i8 3), <vscale x 8 x i8> %va
164  ret <vscale x 8 x i8> %vc
165}
166
167define <vscale x 16 x i8> @vmerge_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %cond) {
168; CHECK-LABEL: vmerge_vv_nxv16i8:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
171; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
172; CHECK-NEXT:    ret
173  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
174  ret <vscale x 16 x i8> %vc
175}
176
177define <vscale x 16 x i8> @vmerge_xv_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b, <vscale x 16 x i1> %cond) {
178; CHECK-LABEL: vmerge_xv_nxv16i8:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
181; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
182; CHECK-NEXT:    ret
183  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
184  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
185  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> %splat, <vscale x 16 x i8> %va
186  ret <vscale x 16 x i8> %vc
187}
188
189define <vscale x 16 x i8> @vmerge_iv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %cond) {
190; CHECK-LABEL: vmerge_iv_nxv16i8:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
193; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
194; CHECK-NEXT:    ret
195  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> splat (i8 3), <vscale x 16 x i8> %va
196  ret <vscale x 16 x i8> %vc
197}
198
199define <vscale x 32 x i8> @vmerge_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %cond) {
200; CHECK-LABEL: vmerge_vv_nxv32i8:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
203; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
204; CHECK-NEXT:    ret
205  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
206  ret <vscale x 32 x i8> %vc
207}
208
209define <vscale x 32 x i8> @vmerge_xv_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b, <vscale x 32 x i1> %cond) {
210; CHECK-LABEL: vmerge_xv_nxv32i8:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
213; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
214; CHECK-NEXT:    ret
215  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
216  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
217  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i8> %splat, <vscale x 32 x i8> %va
218  ret <vscale x 32 x i8> %vc
219}
220
221define <vscale x 32 x i8> @vmerge_iv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %cond) {
222; CHECK-LABEL: vmerge_iv_nxv32i8:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
225; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
226; CHECK-NEXT:    ret
227  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i8> splat (i8 3), <vscale x 32 x i8> %va
228  ret <vscale x 32 x i8> %vc
229}
230
231define <vscale x 64 x i8> @vmerge_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %cond) {
232; CHECK-LABEL: vmerge_vv_nxv64i8:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
235; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
236; CHECK-NEXT:    ret
237  %vc = select <vscale x 64 x i1> %cond, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
238  ret <vscale x 64 x i8> %vc
239}
240
241define <vscale x 64 x i8> @vmerge_xv_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b, <vscale x 64 x i1> %cond) {
242; CHECK-LABEL: vmerge_xv_nxv64i8:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
245; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
246; CHECK-NEXT:    ret
247  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
248  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
249  %vc = select <vscale x 64 x i1> %cond, <vscale x 64 x i8> %splat, <vscale x 64 x i8> %va
250  ret <vscale x 64 x i8> %vc
251}
252
253define <vscale x 64 x i8> @vmerge_iv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %cond) {
254; CHECK-LABEL: vmerge_iv_nxv64i8:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
257; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
258; CHECK-NEXT:    ret
259  %vc = select <vscale x 64 x i1> %cond, <vscale x 64 x i8> splat (i8 3), <vscale x 64 x i8> %va
260  ret <vscale x 64 x i8> %vc
261}
262
263define <vscale x 1 x i16> @vmerge_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %cond) {
264; CHECK-LABEL: vmerge_vv_nxv1i16:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
267; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
268; CHECK-NEXT:    ret
269  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
270  ret <vscale x 1 x i16> %vc
271}
272
273define <vscale x 1 x i16> @vmerge_xv_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b, <vscale x 1 x i1> %cond) {
274; CHECK-LABEL: vmerge_xv_nxv1i16:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
277; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
278; CHECK-NEXT:    ret
279  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
280  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
281  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i16> %splat, <vscale x 1 x i16> %va
282  ret <vscale x 1 x i16> %vc
283}
284
285define <vscale x 1 x i16> @vmerge_iv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %cond) {
286; CHECK-LABEL: vmerge_iv_nxv1i16:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
289; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
290; CHECK-NEXT:    ret
291  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i16> splat (i16 3), <vscale x 1 x i16> %va
292  ret <vscale x 1 x i16> %vc
293}
294
295define <vscale x 2 x i16> @vmerge_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %cond) {
296; CHECK-LABEL: vmerge_vv_nxv2i16:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
299; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
300; CHECK-NEXT:    ret
301  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
302  ret <vscale x 2 x i16> %vc
303}
304
305define <vscale x 2 x i16> @vmerge_xv_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b, <vscale x 2 x i1> %cond) {
306; CHECK-LABEL: vmerge_xv_nxv2i16:
307; CHECK:       # %bb.0:
308; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
309; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
310; CHECK-NEXT:    ret
311  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
312  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
313  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i16> %splat, <vscale x 2 x i16> %va
314  ret <vscale x 2 x i16> %vc
315}
316
317define <vscale x 2 x i16> @vmerge_iv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %cond) {
318; CHECK-LABEL: vmerge_iv_nxv2i16:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
321; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
322; CHECK-NEXT:    ret
323  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i16> splat (i16 3), <vscale x 2 x i16> %va
324  ret <vscale x 2 x i16> %vc
325}
326
327define <vscale x 4 x i16> @vmerge_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %cond) {
328; CHECK-LABEL: vmerge_vv_nxv4i16:
329; CHECK:       # %bb.0:
330; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
331; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
332; CHECK-NEXT:    ret
333  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
334  ret <vscale x 4 x i16> %vc
335}
336
337define <vscale x 4 x i16> @vmerge_xv_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b, <vscale x 4 x i1> %cond) {
338; CHECK-LABEL: vmerge_xv_nxv4i16:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
341; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
342; CHECK-NEXT:    ret
343  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
344  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
345  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i16> %splat, <vscale x 4 x i16> %va
346  ret <vscale x 4 x i16> %vc
347}
348
349define <vscale x 4 x i16> @vmerge_iv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %cond) {
350; CHECK-LABEL: vmerge_iv_nxv4i16:
351; CHECK:       # %bb.0:
352; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
353; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
354; CHECK-NEXT:    ret
355  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i16> splat (i16 3), <vscale x 4 x i16> %va
356  ret <vscale x 4 x i16> %vc
357}
358
359define <vscale x 8 x i16> @vmerge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %cond) {
360; CHECK-LABEL: vmerge_vv_nxv8i16:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
363; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
364; CHECK-NEXT:    ret
365  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
366  ret <vscale x 8 x i16> %vc
367}
368
369define <vscale x 8 x i16> @vmerge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b, <vscale x 8 x i1> %cond) {
370; CHECK-LABEL: vmerge_xv_nxv8i16:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
373; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
374; CHECK-NEXT:    ret
375  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
376  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
377  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> %splat, <vscale x 8 x i16> %va
378  ret <vscale x 8 x i16> %vc
379}
380
381define <vscale x 8 x i16> @vmerge_iv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %cond) {
382; CHECK-LABEL: vmerge_iv_nxv8i16:
383; CHECK:       # %bb.0:
384; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
385; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
386; CHECK-NEXT:    ret
387  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> splat (i16 3), <vscale x 8 x i16> %va
388  ret <vscale x 8 x i16> %vc
389}
390
391define <vscale x 16 x i16> @vmerge_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %cond) {
392; CHECK-LABEL: vmerge_vv_nxv16i16:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
395; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
396; CHECK-NEXT:    ret
397  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
398  ret <vscale x 16 x i16> %vc
399}
400
401define <vscale x 16 x i16> @vmerge_xv_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b, <vscale x 16 x i1> %cond) {
402; CHECK-LABEL: vmerge_xv_nxv16i16:
403; CHECK:       # %bb.0:
404; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
405; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
406; CHECK-NEXT:    ret
407  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
408  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
409  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i16> %splat, <vscale x 16 x i16> %va
410  ret <vscale x 16 x i16> %vc
411}
412
413define <vscale x 16 x i16> @vmerge_iv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %cond) {
414; CHECK-LABEL: vmerge_iv_nxv16i16:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
417; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
418; CHECK-NEXT:    ret
419  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i16> splat (i16 3), <vscale x 16 x i16> %va
420  ret <vscale x 16 x i16> %vc
421}
422
423define <vscale x 32 x i16> @vmerge_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %cond) {
424; CHECK-LABEL: vmerge_vv_nxv32i16:
425; CHECK:       # %bb.0:
426; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
427; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
428; CHECK-NEXT:    ret
429  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
430  ret <vscale x 32 x i16> %vc
431}
432
433define <vscale x 32 x i16> @vmerge_xv_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b, <vscale x 32 x i1> %cond) {
434; CHECK-LABEL: vmerge_xv_nxv32i16:
435; CHECK:       # %bb.0:
436; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
437; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
438; CHECK-NEXT:    ret
439  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
440  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
441  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i16> %splat, <vscale x 32 x i16> %va
442  ret <vscale x 32 x i16> %vc
443}
444
445define <vscale x 32 x i16> @vmerge_iv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %cond) {
446; CHECK-LABEL: vmerge_iv_nxv32i16:
447; CHECK:       # %bb.0:
448; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
449; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
450; CHECK-NEXT:    ret
451  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i16> splat (i16 3), <vscale x 32 x i16> %va
452  ret <vscale x 32 x i16> %vc
453}
454
455define <vscale x 1 x i32> @vmerge_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %cond) {
456; CHECK-LABEL: vmerge_vv_nxv1i32:
457; CHECK:       # %bb.0:
458; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
459; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
460; CHECK-NEXT:    ret
461  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
462  ret <vscale x 1 x i32> %vc
463}
464
465define <vscale x 1 x i32> @vmerge_xv_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b, <vscale x 1 x i1> %cond) {
466; CHECK-LABEL: vmerge_xv_nxv1i32:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
469; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
470; CHECK-NEXT:    ret
471  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
472  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
473  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i32> %splat, <vscale x 1 x i32> %va
474  ret <vscale x 1 x i32> %vc
475}
476
477define <vscale x 1 x i32> @vmerge_iv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %cond) {
478; CHECK-LABEL: vmerge_iv_nxv1i32:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
481; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
482; CHECK-NEXT:    ret
483  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i32> splat (i32 3), <vscale x 1 x i32> %va
484  ret <vscale x 1 x i32> %vc
485}
486
487define <vscale x 2 x i32> @vmerge_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %cond) {
488; CHECK-LABEL: vmerge_vv_nxv2i32:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
491; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
492; CHECK-NEXT:    ret
493  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
494  ret <vscale x 2 x i32> %vc
495}
496
497define <vscale x 2 x i32> @vmerge_xv_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b, <vscale x 2 x i1> %cond) {
498; CHECK-LABEL: vmerge_xv_nxv2i32:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
501; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
502; CHECK-NEXT:    ret
503  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
504  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
505  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> %splat, <vscale x 2 x i32> %va
506  ret <vscale x 2 x i32> %vc
507}
508
509define <vscale x 2 x i32> @vmerge_iv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %cond) {
510; CHECK-LABEL: vmerge_iv_nxv2i32:
511; CHECK:       # %bb.0:
512; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
513; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
514; CHECK-NEXT:    ret
515  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> splat (i32 3), <vscale x 2 x i32> %va
516  ret <vscale x 2 x i32> %vc
517}
518
519define <vscale x 4 x i32> @vmerge_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %cond) {
520; CHECK-LABEL: vmerge_vv_nxv4i32:
521; CHECK:       # %bb.0:
522; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
523; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
524; CHECK-NEXT:    ret
525  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
526  ret <vscale x 4 x i32> %vc
527}
528
529define <vscale x 4 x i32> @vmerge_xv_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b, <vscale x 4 x i1> %cond) {
530; CHECK-LABEL: vmerge_xv_nxv4i32:
531; CHECK:       # %bb.0:
532; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
533; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
534; CHECK-NEXT:    ret
535  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
536  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
537  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> %splat, <vscale x 4 x i32> %va
538  ret <vscale x 4 x i32> %vc
539}
540
541define <vscale x 4 x i32> @vmerge_iv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %cond) {
542; CHECK-LABEL: vmerge_iv_nxv4i32:
543; CHECK:       # %bb.0:
544; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
545; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
546; CHECK-NEXT:    ret
547  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> %va
548  ret <vscale x 4 x i32> %vc
549}
550
551define <vscale x 8 x i32> @vmerge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %cond) {
552; CHECK-LABEL: vmerge_vv_nxv8i32:
553; CHECK:       # %bb.0:
554; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
555; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
556; CHECK-NEXT:    ret
557  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
558  ret <vscale x 8 x i32> %vc
559}
560
561define <vscale x 8 x i32> @vmerge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %cond) {
562; CHECK-LABEL: vmerge_xv_nxv8i32:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
565; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
566; CHECK-NEXT:    ret
567  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
568  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
569  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %va
570  ret <vscale x 8 x i32> %vc
571}
572
573define <vscale x 8 x i32> @vmerge_iv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %cond) {
574; CHECK-LABEL: vmerge_iv_nxv8i32:
575; CHECK:       # %bb.0:
576; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
577; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
578; CHECK-NEXT:    ret
579  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i32> splat (i32 3), <vscale x 8 x i32> %va
580  ret <vscale x 8 x i32> %vc
581}
582
583define <vscale x 16 x i32> @vmerge_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %cond) {
584; CHECK-LABEL: vmerge_vv_nxv16i32:
585; CHECK:       # %bb.0:
586; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
587; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
588; CHECK-NEXT:    ret
589  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
590  ret <vscale x 16 x i32> %vc
591}
592
593define <vscale x 16 x i32> @vmerge_xv_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b, <vscale x 16 x i1> %cond) {
594; CHECK-LABEL: vmerge_xv_nxv16i32:
595; CHECK:       # %bb.0:
596; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
597; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
598; CHECK-NEXT:    ret
599  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
600  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
601  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i32> %splat, <vscale x 16 x i32> %va
602  ret <vscale x 16 x i32> %vc
603}
604
605define <vscale x 16 x i32> @vmerge_iv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %cond) {
606; CHECK-LABEL: vmerge_iv_nxv16i32:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
609; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
610; CHECK-NEXT:    ret
611  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i32> splat (i32 3), <vscale x 16 x i32> %va
612  ret <vscale x 16 x i32> %vc
613}
614
615define <vscale x 1 x i64> @vmerge_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %cond) {
616; CHECK-LABEL: vmerge_vv_nxv1i64:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
619; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
620; CHECK-NEXT:    ret
621  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
622  ret <vscale x 1 x i64> %vc
623}
624
625define <vscale x 1 x i64> @vmerge_xv_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %cond) {
626; RV32-LABEL: vmerge_xv_nxv1i64:
627; RV32:       # %bb.0:
628; RV32-NEXT:    addi sp, sp, -16
629; RV32-NEXT:    .cfi_def_cfa_offset 16
630; RV32-NEXT:    sw a0, 8(sp)
631; RV32-NEXT:    sw a1, 12(sp)
632; RV32-NEXT:    addi a0, sp, 8
633; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
634; RV32-NEXT:    vlse64.v v8, (a0), zero, v0.t
635; RV32-NEXT:    addi sp, sp, 16
636; RV32-NEXT:    .cfi_def_cfa_offset 0
637; RV32-NEXT:    ret
638;
639; RV64-LABEL: vmerge_xv_nxv1i64:
640; RV64:       # %bb.0:
641; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
642; RV64-NEXT:    vmerge.vxm v8, v8, a0, v0
643; RV64-NEXT:    ret
644  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
645  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
646  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %splat, <vscale x 1 x i64> %va
647  ret <vscale x 1 x i64> %vc
648}
649
650define <vscale x 1 x i64> @vmerge_iv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %cond) {
651; CHECK-LABEL: vmerge_iv_nxv1i64:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
654; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
655; CHECK-NEXT:    ret
656  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> splat (i64 3), <vscale x 1 x i64> %va
657  ret <vscale x 1 x i64> %vc
658}
659
660define <vscale x 2 x i64> @vmerge_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %cond) {
661; CHECK-LABEL: vmerge_vv_nxv2i64:
662; CHECK:       # %bb.0:
663; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
664; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
665; CHECK-NEXT:    ret
666  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
667  ret <vscale x 2 x i64> %vc
668}
669
670define <vscale x 2 x i64> @vmerge_xv_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %cond) {
671; RV32-LABEL: vmerge_xv_nxv2i64:
672; RV32:       # %bb.0:
673; RV32-NEXT:    addi sp, sp, -16
674; RV32-NEXT:    .cfi_def_cfa_offset 16
675; RV32-NEXT:    sw a0, 8(sp)
676; RV32-NEXT:    sw a1, 12(sp)
677; RV32-NEXT:    addi a0, sp, 8
678; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
679; RV32-NEXT:    vlse64.v v8, (a0), zero, v0.t
680; RV32-NEXT:    addi sp, sp, 16
681; RV32-NEXT:    .cfi_def_cfa_offset 0
682; RV32-NEXT:    ret
683;
684; RV64-LABEL: vmerge_xv_nxv2i64:
685; RV64:       # %bb.0:
686; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
687; RV64-NEXT:    vmerge.vxm v8, v8, a0, v0
688; RV64-NEXT:    ret
689  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
690  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
691  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %splat, <vscale x 2 x i64> %va
692  ret <vscale x 2 x i64> %vc
693}
694
695define <vscale x 2 x i64> @vmerge_iv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %cond) {
696; CHECK-LABEL: vmerge_iv_nxv2i64:
697; CHECK:       # %bb.0:
698; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
699; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
700; CHECK-NEXT:    ret
701  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> splat (i64 3), <vscale x 2 x i64> %va
702  ret <vscale x 2 x i64> %vc
703}
704
705define <vscale x 4 x i64> @vmerge_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %cond) {
706; CHECK-LABEL: vmerge_vv_nxv4i64:
707; CHECK:       # %bb.0:
708; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
709; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
710; CHECK-NEXT:    ret
711  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
712  ret <vscale x 4 x i64> %vc
713}
714
715define <vscale x 4 x i64> @vmerge_xv_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %cond) {
716; RV32-LABEL: vmerge_xv_nxv4i64:
717; RV32:       # %bb.0:
718; RV32-NEXT:    addi sp, sp, -16
719; RV32-NEXT:    .cfi_def_cfa_offset 16
720; RV32-NEXT:    sw a0, 8(sp)
721; RV32-NEXT:    sw a1, 12(sp)
722; RV32-NEXT:    addi a0, sp, 8
723; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
724; RV32-NEXT:    vlse64.v v8, (a0), zero, v0.t
725; RV32-NEXT:    addi sp, sp, 16
726; RV32-NEXT:    .cfi_def_cfa_offset 0
727; RV32-NEXT:    ret
728;
729; RV64-LABEL: vmerge_xv_nxv4i64:
730; RV64:       # %bb.0:
731; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
732; RV64-NEXT:    vmerge.vxm v8, v8, a0, v0
733; RV64-NEXT:    ret
734  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
735  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
736  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> %splat, <vscale x 4 x i64> %va
737  ret <vscale x 4 x i64> %vc
738}
739
740define <vscale x 4 x i64> @vmerge_iv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %cond) {
741; CHECK-LABEL: vmerge_iv_nxv4i64:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
744; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
745; CHECK-NEXT:    ret
746  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> splat (i64 3), <vscale x 4 x i64> %va
747  ret <vscale x 4 x i64> %vc
748}
749
750define <vscale x 8 x i64> @vmerge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %cond) {
751; CHECK-LABEL: vmerge_vv_nxv8i64:
752; CHECK:       # %bb.0:
753; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
754; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
755; CHECK-NEXT:    ret
756  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
757  ret <vscale x 8 x i64> %vc
758}
759
760define <vscale x 8 x i64> @vmerge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %cond) {
761; RV32-LABEL: vmerge_xv_nxv8i64:
762; RV32:       # %bb.0:
763; RV32-NEXT:    addi sp, sp, -16
764; RV32-NEXT:    .cfi_def_cfa_offset 16
765; RV32-NEXT:    sw a0, 8(sp)
766; RV32-NEXT:    sw a1, 12(sp)
767; RV32-NEXT:    addi a0, sp, 8
768; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
769; RV32-NEXT:    vlse64.v v8, (a0), zero, v0.t
770; RV32-NEXT:    addi sp, sp, 16
771; RV32-NEXT:    .cfi_def_cfa_offset 0
772; RV32-NEXT:    ret
773;
774; RV64-LABEL: vmerge_xv_nxv8i64:
775; RV64:       # %bb.0:
776; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
777; RV64-NEXT:    vmerge.vxm v8, v8, a0, v0
778; RV64-NEXT:    ret
779  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
780  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
781  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %splat, <vscale x 8 x i64> %va
782  ret <vscale x 8 x i64> %vc
783}
784
785define <vscale x 8 x i64> @vmerge_iv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %cond) {
786; CHECK-LABEL: vmerge_iv_nxv8i64:
787; CHECK:       # %bb.0:
788; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
789; CHECK-NEXT:    vmerge.vim v8, v8, 3, v0
790; CHECK-NEXT:    ret
791  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> splat (i64 3), <vscale x 8 x i64> %va
792  ret <vscale x 8 x i64> %vc
793}
794
795define <vscale x 8 x i64> @vmerge_truelhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
796; CHECK-LABEL: vmerge_truelhs_nxv8i64_0:
797; CHECK:       # %bb.0:
798; CHECK-NEXT:    ret
799  %vc = select <vscale x 8 x i1> splat (i1 1), <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
800  ret <vscale x 8 x i64> %vc
801}
802
803define <vscale x 8 x i64> @vmerge_falselhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
804; CHECK-LABEL: vmerge_falselhs_nxv8i64_0:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
807; CHECK-NEXT:    vmv8r.v v8, v16
808; CHECK-NEXT:    ret
809  %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
810  ret <vscale x 8 x i64> %vc
811}
812