xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,CHECK-ZVFH
4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,CHECK-ZVFH
6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
7; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,CHECK-ZVFHMIN
8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
9; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,CHECK-ZVFHMIN
10
11define <vscale x 1 x half> @vfmerge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %cond) {
12; CHECK-LABEL: vfmerge_vv_nxv1f16:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
15; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
16; CHECK-NEXT:    ret
17  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %va, <vscale x 1 x half> %vb
18  ret <vscale x 1 x half> %vc
19}
20
21define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %cond) {
22; CHECK-ZVFH-LABEL: vfmerge_fv_nxv1f16:
23; CHECK-ZVFH:       # %bb.0:
24; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
25; CHECK-ZVFH-NEXT:    vfmerge.vfm v8, v8, fa0, v0
26; CHECK-ZVFH-NEXT:    ret
27;
28; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv1f16:
29; CHECK-ZVFHMIN:       # %bb.0:
30; CHECK-ZVFHMIN-NEXT:    fmv.x.h a0, fa0
31; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
32; CHECK-ZVFHMIN-NEXT:    vmv.v.x v9, a0
33; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v9, v0
34; CHECK-ZVFHMIN-NEXT:    ret
35  %head = insertelement <vscale x 1 x half> poison, half %b, i32 0
36  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
37  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %splat, <vscale x 1 x half> %va
38  ret <vscale x 1 x half> %vc
39}
40
41define <vscale x 2 x half> @vfmerge_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %cond) {
42; CHECK-LABEL: vfmerge_vv_nxv2f16:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
45; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
46; CHECK-NEXT:    ret
47  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %va, <vscale x 2 x half> %vb
48  ret <vscale x 2 x half> %vc
49}
50
51define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %cond) {
52; CHECK-ZVFH-LABEL: vfmerge_fv_nxv2f16:
53; CHECK-ZVFH:       # %bb.0:
54; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
55; CHECK-ZVFH-NEXT:    vfmerge.vfm v8, v8, fa0, v0
56; CHECK-ZVFH-NEXT:    ret
57;
58; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv2f16:
59; CHECK-ZVFHMIN:       # %bb.0:
60; CHECK-ZVFHMIN-NEXT:    fmv.x.h a0, fa0
61; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
62; CHECK-ZVFHMIN-NEXT:    vmv.v.x v9, a0
63; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v9, v0
64; CHECK-ZVFHMIN-NEXT:    ret
65  %head = insertelement <vscale x 2 x half> poison, half %b, i32 0
66  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
67  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %splat, <vscale x 2 x half> %va
68  ret <vscale x 2 x half> %vc
69}
70
71define <vscale x 4 x half> @vfmerge_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %cond) {
72; CHECK-LABEL: vfmerge_vv_nxv4f16:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
75; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
76; CHECK-NEXT:    ret
77  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %va, <vscale x 4 x half> %vb
78  ret <vscale x 4 x half> %vc
79}
80
81define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %cond) {
82; CHECK-ZVFH-LABEL: vfmerge_fv_nxv4f16:
83; CHECK-ZVFH:       # %bb.0:
84; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
85; CHECK-ZVFH-NEXT:    vfmerge.vfm v8, v8, fa0, v0
86; CHECK-ZVFH-NEXT:    ret
87;
88; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv4f16:
89; CHECK-ZVFHMIN:       # %bb.0:
90; CHECK-ZVFHMIN-NEXT:    fmv.x.h a0, fa0
91; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
92; CHECK-ZVFHMIN-NEXT:    vmv.v.x v9, a0
93; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v9, v0
94; CHECK-ZVFHMIN-NEXT:    ret
95  %head = insertelement <vscale x 4 x half> poison, half %b, i32 0
96  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
97  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %splat, <vscale x 4 x half> %va
98  ret <vscale x 4 x half> %vc
99}
100
101define <vscale x 8 x half> @vfmerge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %cond) {
102; CHECK-LABEL: vfmerge_vv_nxv8f16:
103; CHECK:       # %bb.0:
104; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
105; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
106; CHECK-NEXT:    ret
107  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
108  ret <vscale x 8 x half> %vc
109}
110
111define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %cond) {
112; CHECK-ZVFH-LABEL: vfmerge_fv_nxv8f16:
113; CHECK-ZVFH:       # %bb.0:
114; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
115; CHECK-ZVFH-NEXT:    vfmerge.vfm v8, v8, fa0, v0
116; CHECK-ZVFH-NEXT:    ret
117;
118; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv8f16:
119; CHECK-ZVFHMIN:       # %bb.0:
120; CHECK-ZVFHMIN-NEXT:    fmv.x.h a0, fa0
121; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
122; CHECK-ZVFHMIN-NEXT:    vmv.v.x v10, a0
123; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v10, v0
124; CHECK-ZVFHMIN-NEXT:    ret
125  %head = insertelement <vscale x 8 x half> poison, half %b, i32 0
126  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
127  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va
128  ret <vscale x 8 x half> %vc
129}
130
131define <vscale x 8 x half> @vfmerge_zv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %cond) {
132; CHECK-ZVFH-LABEL: vfmerge_zv_nxv8f16:
133; CHECK-ZVFH:       # %bb.0:
134; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
135; CHECK-ZVFH-NEXT:    vmerge.vim v8, v8, 0, v0
136; CHECK-ZVFH-NEXT:    ret
137;
138; CHECK-ZVFHMIN-LABEL: vfmerge_zv_nxv8f16:
139; CHECK-ZVFHMIN:       # %bb.0:
140; CHECK-ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
141; CHECK-ZVFHMIN-NEXT:    vmv.v.i v10, 0
142; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v10, v0
143; CHECK-ZVFHMIN-NEXT:    ret
144  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> splat (half zeroinitializer), <vscale x 8 x half> %va
145  ret <vscale x 8 x half> %vc
146}
147
148define <vscale x 8 x half> @vfmerge_nzv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %cond) {
149; CHECK-ZVFH-LABEL: vfmerge_nzv_nxv8f16:
150; CHECK-ZVFH:       # %bb.0:
151; CHECK-ZVFH-NEXT:    lui a0, 1048568
152; CHECK-ZVFH-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
153; CHECK-ZVFH-NEXT:    vmerge.vxm v8, v8, a0, v0
154; CHECK-ZVFH-NEXT:    ret
155;
156; CHECK-ZVFHMIN-LABEL: vfmerge_nzv_nxv8f16:
157; CHECK-ZVFHMIN:       # %bb.0:
158; CHECK-ZVFHMIN-NEXT:    lui a0, 1048568
159; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
160; CHECK-ZVFHMIN-NEXT:    vmv.v.x v10, a0
161; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v10, v0
162; CHECK-ZVFHMIN-NEXT:    ret
163  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> splat (half -0.0), <vscale x 8 x half> %va
164  ret <vscale x 8 x half> %vc
165}
166
167define <vscale x 8 x half> @vmerge_truelhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
168; CHECK-LABEL: vmerge_truelhs_nxv8f16_0:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    ret
171  %vc = select <vscale x 8 x i1> splat (i1 1), <vscale x 8 x half> %va, <vscale x 8 x half> %vb
172  ret <vscale x 8 x half> %vc
173}
174
175define <vscale x 8 x half> @vmerge_falselhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
176; CHECK-LABEL: vmerge_falselhs_nxv8f16_0:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
179; CHECK-NEXT:    vmv2r.v v8, v10
180; CHECK-NEXT:    ret
181  %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
182  ret <vscale x 8 x half> %vc
183}
184
185define <vscale x 16 x half> @vfmerge_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %cond) {
186; CHECK-LABEL: vfmerge_vv_nxv16f16:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
189; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
190; CHECK-NEXT:    ret
191  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %va, <vscale x 16 x half> %vb
192  ret <vscale x 16 x half> %vc
193}
194
195define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %cond) {
196; CHECK-ZVFH-LABEL: vfmerge_fv_nxv16f16:
197; CHECK-ZVFH:       # %bb.0:
198; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
199; CHECK-ZVFH-NEXT:    vfmerge.vfm v8, v8, fa0, v0
200; CHECK-ZVFH-NEXT:    ret
201;
202; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv16f16:
203; CHECK-ZVFHMIN:       # %bb.0:
204; CHECK-ZVFHMIN-NEXT:    fmv.x.h a0, fa0
205; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
206; CHECK-ZVFHMIN-NEXT:    vmv.v.x v12, a0
207; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v12, v0
208; CHECK-ZVFHMIN-NEXT:    ret
209  %head = insertelement <vscale x 16 x half> poison, half %b, i32 0
210  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
211  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %splat, <vscale x 16 x half> %va
212  ret <vscale x 16 x half> %vc
213}
214
215define <vscale x 32 x half> @vfmerge_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %cond) {
216; CHECK-LABEL: vfmerge_vv_nxv32f16:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
219; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
220; CHECK-NEXT:    ret
221  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %va, <vscale x 32 x half> %vb
222  ret <vscale x 32 x half> %vc
223}
224
225define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %cond) {
226; CHECK-ZVFH-LABEL: vfmerge_fv_nxv32f16:
227; CHECK-ZVFH:       # %bb.0:
228; CHECK-ZVFH-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
229; CHECK-ZVFH-NEXT:    vfmerge.vfm v8, v8, fa0, v0
230; CHECK-ZVFH-NEXT:    ret
231;
232; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv32f16:
233; CHECK-ZVFHMIN:       # %bb.0:
234; CHECK-ZVFHMIN-NEXT:    fmv.x.h a0, fa0
235; CHECK-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
236; CHECK-ZVFHMIN-NEXT:    vmv.v.x v16, a0
237; CHECK-ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v16, v0
238; CHECK-ZVFHMIN-NEXT:    ret
239  %head = insertelement <vscale x 32 x half> poison, half %b, i32 0
240  %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer
241  %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %splat, <vscale x 32 x half> %va
242  ret <vscale x 32 x half> %vc
243}
244
245define <vscale x 1 x float> @vfmerge_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %cond) {
246; CHECK-LABEL: vfmerge_vv_nxv1f32:
247; CHECK:       # %bb.0:
248; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
249; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
250; CHECK-NEXT:    ret
251  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x float> %va, <vscale x 1 x float> %vb
252  ret <vscale x 1 x float> %vc
253}
254
255define <vscale x 1 x float> @vfmerge_fv_nxv1f32(<vscale x 1 x float> %va, float %b, <vscale x 1 x i1> %cond) {
256; CHECK-LABEL: vfmerge_fv_nxv1f32:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
259; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
260; CHECK-NEXT:    ret
261  %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
262  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
263  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x float> %splat, <vscale x 1 x float> %va
264  ret <vscale x 1 x float> %vc
265}
266
267define <vscale x 2 x float> @vfmerge_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %cond) {
268; CHECK-LABEL: vfmerge_vv_nxv2f32:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
271; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
272; CHECK-NEXT:    ret
273  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x float> %va, <vscale x 2 x float> %vb
274  ret <vscale x 2 x float> %vc
275}
276
277define <vscale x 2 x float> @vfmerge_fv_nxv2f32(<vscale x 2 x float> %va, float %b, <vscale x 2 x i1> %cond) {
278; CHECK-LABEL: vfmerge_fv_nxv2f32:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
281; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
282; CHECK-NEXT:    ret
283  %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
284  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
285  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x float> %splat, <vscale x 2 x float> %va
286  ret <vscale x 2 x float> %vc
287}
288
289define <vscale x 4 x float> @vfmerge_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %cond) {
290; CHECK-LABEL: vfmerge_vv_nxv4f32:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
293; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
294; CHECK-NEXT:    ret
295  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %va, <vscale x 4 x float> %vb
296  ret <vscale x 4 x float> %vc
297}
298
299define <vscale x 4 x float> @vfmerge_fv_nxv4f32(<vscale x 4 x float> %va, float %b, <vscale x 4 x i1> %cond) {
300; CHECK-LABEL: vfmerge_fv_nxv4f32:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
303; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
304; CHECK-NEXT:    ret
305  %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
306  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
307  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %splat, <vscale x 4 x float> %va
308  ret <vscale x 4 x float> %vc
309}
310
311define <vscale x 8 x float> @vfmerge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %cond) {
312; CHECK-LABEL: vfmerge_vv_nxv8f32:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
315; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
316; CHECK-NEXT:    ret
317  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> %va, <vscale x 8 x float> %vb
318  ret <vscale x 8 x float> %vc
319}
320
321define <vscale x 8 x float> @vfmerge_fv_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %cond) {
322; CHECK-LABEL: vfmerge_fv_nxv8f32:
323; CHECK:       # %bb.0:
324; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
325; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
326; CHECK-NEXT:    ret
327  %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
328  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
329  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> %splat, <vscale x 8 x float> %va
330  ret <vscale x 8 x float> %vc
331}
332
333define <vscale x 8 x float> @vfmerge_zv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %cond) {
334; CHECK-LABEL: vfmerge_zv_nxv8f32:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
337; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
338; CHECK-NEXT:    ret
339  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> splat (float zeroinitializer), <vscale x 8 x float> %va
340  ret <vscale x 8 x float> %vc
341}
342
343define <vscale x 8 x float> @vfmerge_nzv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %cond) {
344; CHECK-LABEL: vfmerge_nzv_nxv8f32:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    lui a0, 524288
347; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
348; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
349; CHECK-NEXT:    ret
350  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> splat (float -0.0), <vscale x 8 x float> %va
351  ret <vscale x 8 x float> %vc
352}
353
354define <vscale x 16 x float> @vfmerge_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %cond) {
355; CHECK-LABEL: vfmerge_vv_nxv16f32:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
358; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
359; CHECK-NEXT:    ret
360  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x float> %va, <vscale x 16 x float> %vb
361  ret <vscale x 16 x float> %vc
362}
363
364define <vscale x 16 x float> @vfmerge_fv_nxv16f32(<vscale x 16 x float> %va, float %b, <vscale x 16 x i1> %cond) {
365; CHECK-LABEL: vfmerge_fv_nxv16f32:
366; CHECK:       # %bb.0:
367; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
368; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
369; CHECK-NEXT:    ret
370  %head = insertelement <vscale x 16 x float> poison, float %b, i32 0
371  %splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> poison, <vscale x 16 x i32> zeroinitializer
372  %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x float> %splat, <vscale x 16 x float> %va
373  ret <vscale x 16 x float> %vc
374}
375
376define <vscale x 1 x double> @vfmerge_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %cond) {
377; CHECK-LABEL: vfmerge_vv_nxv1f64:
378; CHECK:       # %bb.0:
379; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
380; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
381; CHECK-NEXT:    ret
382  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x double> %va, <vscale x 1 x double> %vb
383  ret <vscale x 1 x double> %vc
384}
385
386define <vscale x 1 x double> @vfmerge_fv_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %cond) {
387; CHECK-LABEL: vfmerge_fv_nxv1f64:
388; CHECK:       # %bb.0:
389; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
390; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
391; CHECK-NEXT:    ret
392  %head = insertelement <vscale x 1 x double> poison, double %b, i32 0
393  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
394  %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x double> %splat, <vscale x 1 x double> %va
395  ret <vscale x 1 x double> %vc
396}
397
398define <vscale x 2 x double> @vfmerge_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %cond) {
399; CHECK-LABEL: vfmerge_vv_nxv2f64:
400; CHECK:       # %bb.0:
401; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
402; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
403; CHECK-NEXT:    ret
404  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x double> %va, <vscale x 2 x double> %vb
405  ret <vscale x 2 x double> %vc
406}
407
408define <vscale x 2 x double> @vfmerge_fv_nxv2f64(<vscale x 2 x double> %va, double %b, <vscale x 2 x i1> %cond) {
409; CHECK-LABEL: vfmerge_fv_nxv2f64:
410; CHECK:       # %bb.0:
411; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
412; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
413; CHECK-NEXT:    ret
414  %head = insertelement <vscale x 2 x double> poison, double %b, i32 0
415  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
416  %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x double> %splat, <vscale x 2 x double> %va
417  ret <vscale x 2 x double> %vc
418}
419
420define <vscale x 4 x double> @vfmerge_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %cond) {
421; CHECK-LABEL: vfmerge_vv_nxv4f64:
422; CHECK:       # %bb.0:
423; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
424; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
425; CHECK-NEXT:    ret
426  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x double> %va, <vscale x 4 x double> %vb
427  ret <vscale x 4 x double> %vc
428}
429
430define <vscale x 4 x double> @vfmerge_fv_nxv4f64(<vscale x 4 x double> %va, double %b, <vscale x 4 x i1> %cond) {
431; CHECK-LABEL: vfmerge_fv_nxv4f64:
432; CHECK:       # %bb.0:
433; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
434; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
435; CHECK-NEXT:    ret
436  %head = insertelement <vscale x 4 x double> poison, double %b, i32 0
437  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
438  %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x double> %splat, <vscale x 4 x double> %va
439  ret <vscale x 4 x double> %vc
440}
441
442define <vscale x 8 x double> @vfmerge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %cond) {
443; CHECK-LABEL: vfmerge_vv_nxv8f64:
444; CHECK:       # %bb.0:
445; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
446; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
447; CHECK-NEXT:    ret
448  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> %va, <vscale x 8 x double> %vb
449  ret <vscale x 8 x double> %vc
450}
451
452define <vscale x 8 x double> @vfmerge_fv_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %cond) {
453; CHECK-LABEL: vfmerge_fv_nxv8f64:
454; CHECK:       # %bb.0:
455; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
456; CHECK-NEXT:    vfmerge.vfm v8, v8, fa0, v0
457; CHECK-NEXT:    ret
458  %head = insertelement <vscale x 8 x double> poison, double %b, i32 0
459  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
460  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> %splat, <vscale x 8 x double> %va
461  ret <vscale x 8 x double> %vc
462}
463
464define <vscale x 8 x double> @vfmerge_zv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %cond) {
465; CHECK-LABEL: vfmerge_zv_nxv8f64:
466; CHECK:       # %bb.0:
467; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
468; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
469; CHECK-NEXT:    ret
470  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> splat (double zeroinitializer), <vscale x 8 x double> %va
471  ret <vscale x 8 x double> %vc
472}
473
474define <vscale x 8 x double> @vfmerge_nzv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %cond) {
475; RV32-LABEL: vfmerge_nzv_nxv8f64:
476; RV32:       # %bb.0:
477; RV32-NEXT:    fcvt.d.w fa5, zero
478; RV32-NEXT:    fneg.d fa5, fa5
479; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
480; RV32-NEXT:    vfmerge.vfm v8, v8, fa5, v0
481; RV32-NEXT:    ret
482;
483; RV64-LABEL: vfmerge_nzv_nxv8f64:
484; RV64:       # %bb.0:
485; RV64-NEXT:    li a0, -1
486; RV64-NEXT:    slli a0, a0, 63
487; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
488; RV64-NEXT:    vmerge.vxm v8, v8, a0, v0
489; RV64-NEXT:    ret
490  %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> splat (double -0.0), <vscale x 8 x double> %va
491  ret <vscale x 8 x double> %vc
492}
493
494define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {
495; CHECK-LABEL: vselect_combine_regression:
496; CHECK:       # %bb.0:
497; CHECK-NEXT:    csrr a1, vlenb
498; CHECK-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
499; CHECK-NEXT:    vmseq.vi v24, v16, 0
500; CHECK-NEXT:    vmseq.vi v0, v8, 0
501; CHECK-NEXT:    vmv.v.i v16, 0
502; CHECK-NEXT:    slli a1, a1, 3
503; CHECK-NEXT:    vmv.v.i v8, 0
504; CHECK-NEXT:    add a1, a0, a1
505; CHECK-NEXT:    vle64.v v8, (a0), v0.t
506; CHECK-NEXT:    vmv1r.v v0, v24
507; CHECK-NEXT:    vle64.v v16, (a1), v0.t
508; CHECK-NEXT:    ret
509  %cond = icmp eq <vscale x 16 x i64> %va, zeroinitializer
510  %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
511  ret <vscale x 16 x double> %sel
512}
513
514define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16 x i1> %ma, <vscale x 16 x i1> %mb, ptr %out) {
515; CHECK-LABEL: vselect_legalize_regression:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    vsetvli a2, zero, e8, m2, ta, ma
518; CHECK-NEXT:    vlm.v v24, (a0)
519; CHECK-NEXT:    csrr a0, vlenb
520; CHECK-NEXT:    srli a2, a0, 3
521; CHECK-NEXT:    slli a0, a0, 3
522; CHECK-NEXT:    vmand.mm v7, v0, v24
523; CHECK-NEXT:    vsetvli a3, zero, e8, mf4, ta, ma
524; CHECK-NEXT:    vslidedown.vx v0, v7, a2
525; CHECK-NEXT:    add a0, a1, a0
526; CHECK-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
527; CHECK-NEXT:    vmv.v.i v24, 0
528; CHECK-NEXT:    vmerge.vvm v16, v24, v16, v0
529; CHECK-NEXT:    vmv1r.v v0, v7
530; CHECK-NEXT:    vmv.v.i v24, 0
531; CHECK-NEXT:    vmerge.vvm v8, v24, v8, v0
532; CHECK-NEXT:    vs8r.v v8, (a1)
533; CHECK-NEXT:    vs8r.v v16, (a0)
534; CHECK-NEXT:    ret
535  %cond = and <vscale x 16 x i1> %ma, %mb
536  %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %a, <vscale x 16 x double> zeroinitializer
537  store <vscale x 16 x double> %sel, ptr %out
538  ret void
539}
540