xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB
6
7declare <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
8declare <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>)
9
10define <vscale x 1 x i8> @vror_vv_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {
11; CHECK-LABEL: vror_vv_nxv1i8:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
14; CHECK-NEXT:    vand.vi v10, v9, 7
15; CHECK-NEXT:    vrsub.vi v9, v9, 0
16; CHECK-NEXT:    vsrl.vv v10, v8, v10
17; CHECK-NEXT:    vand.vi v9, v9, 7
18; CHECK-NEXT:    vsll.vv v8, v8, v9
19; CHECK-NEXT:    vor.vv v8, v10, v8
20; CHECK-NEXT:    ret
21;
22; CHECK-ZVKB-LABEL: vror_vv_nxv1i8:
23; CHECK-ZVKB:       # %bb.0:
24; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
25; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
26; CHECK-ZVKB-NEXT:    ret
27  %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b)
28  ret <vscale x 1 x i8> %x
29}
30
31define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
32; CHECK-LABEL: vror_vx_nxv1i8:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
35; CHECK-NEXT:    vmv.v.x v9, a0
36; CHECK-NEXT:    vand.vi v10, v9, 7
37; CHECK-NEXT:    vrsub.vi v9, v9, 0
38; CHECK-NEXT:    vsrl.vv v10, v8, v10
39; CHECK-NEXT:    vand.vi v9, v9, 7
40; CHECK-NEXT:    vsll.vv v8, v8, v9
41; CHECK-NEXT:    vor.vv v8, v10, v8
42; CHECK-NEXT:    ret
43;
44; CHECK-ZVKB-LABEL: vror_vx_nxv1i8:
45; CHECK-ZVKB:       # %bb.0:
46; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
47; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
48; CHECK-ZVKB-NEXT:    ret
49  %b.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
50  %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
51  %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
52  ret <vscale x 1 x i8> %x
53}
54
55define <vscale x 1 x i8> @vror_vi_nxv1i8(<vscale x 1 x i8> %a) {
56; CHECK-LABEL: vror_vi_nxv1i8:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
59; CHECK-NEXT:    vsll.vi v9, v8, 7
60; CHECK-NEXT:    vsrl.vi v8, v8, 1
61; CHECK-NEXT:    vor.vv v8, v8, v9
62; CHECK-NEXT:    ret
63;
64; CHECK-ZVKB-LABEL: vror_vi_nxv1i8:
65; CHECK-ZVKB:       # %bb.0:
66; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
67; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
68; CHECK-ZVKB-NEXT:    ret
69  %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> splat (i8 1))
70  ret <vscale x 1 x i8> %x
71}
72
73define <vscale x 1 x i8> @vror_vi_rotl_nxv1i8(<vscale x 1 x i8> %a) {
74; CHECK-LABEL: vror_vi_rotl_nxv1i8:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
77; CHECK-NEXT:    vsrl.vi v9, v8, 7
78; CHECK-NEXT:    vadd.vv v8, v8, v8
79; CHECK-NEXT:    vor.vv v8, v8, v9
80; CHECK-NEXT:    ret
81;
82; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i8:
83; CHECK-ZVKB:       # %bb.0:
84; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
85; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
86; CHECK-ZVKB-NEXT:    ret
87  %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> splat (i8 1))
88  ret <vscale x 1 x i8> %x
89}
90
91declare <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>)
92declare <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>)
93
94define <vscale x 2 x i8> @vror_vv_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
95; CHECK-LABEL: vror_vv_nxv2i8:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
98; CHECK-NEXT:    vand.vi v10, v9, 7
99; CHECK-NEXT:    vrsub.vi v9, v9, 0
100; CHECK-NEXT:    vsrl.vv v10, v8, v10
101; CHECK-NEXT:    vand.vi v9, v9, 7
102; CHECK-NEXT:    vsll.vv v8, v8, v9
103; CHECK-NEXT:    vor.vv v8, v10, v8
104; CHECK-NEXT:    ret
105;
106; CHECK-ZVKB-LABEL: vror_vv_nxv2i8:
107; CHECK-ZVKB:       # %bb.0:
108; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
109; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
110; CHECK-ZVKB-NEXT:    ret
111  %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b)
112  ret <vscale x 2 x i8> %x
113}
114
115define <vscale x 2 x i8> @vror_vx_nxv2i8(<vscale x 2 x i8> %a, i8 %b) {
116; CHECK-LABEL: vror_vx_nxv2i8:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
119; CHECK-NEXT:    vmv.v.x v9, a0
120; CHECK-NEXT:    vand.vi v10, v9, 7
121; CHECK-NEXT:    vrsub.vi v9, v9, 0
122; CHECK-NEXT:    vsrl.vv v10, v8, v10
123; CHECK-NEXT:    vand.vi v9, v9, 7
124; CHECK-NEXT:    vsll.vv v8, v8, v9
125; CHECK-NEXT:    vor.vv v8, v10, v8
126; CHECK-NEXT:    ret
127;
128; CHECK-ZVKB-LABEL: vror_vx_nxv2i8:
129; CHECK-ZVKB:       # %bb.0:
130; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
131; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
132; CHECK-ZVKB-NEXT:    ret
133  %b.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
134  %b.splat = shufflevector <vscale x 2 x i8> %b.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
135  %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b.splat)
136  ret <vscale x 2 x i8> %x
137}
138
139define <vscale x 2 x i8> @vror_vi_nxv2i8(<vscale x 2 x i8> %a) {
140; CHECK-LABEL: vror_vi_nxv2i8:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
143; CHECK-NEXT:    vsll.vi v9, v8, 7
144; CHECK-NEXT:    vsrl.vi v8, v8, 1
145; CHECK-NEXT:    vor.vv v8, v8, v9
146; CHECK-NEXT:    ret
147;
148; CHECK-ZVKB-LABEL: vror_vi_nxv2i8:
149; CHECK-ZVKB:       # %bb.0:
150; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
151; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
152; CHECK-ZVKB-NEXT:    ret
153  %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> splat (i8 1))
154  ret <vscale x 2 x i8> %x
155}
156
157define <vscale x 2 x i8> @vror_vi_rotl_nxv2i8(<vscale x 2 x i8> %a) {
158; CHECK-LABEL: vror_vi_rotl_nxv2i8:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
161; CHECK-NEXT:    vsrl.vi v9, v8, 7
162; CHECK-NEXT:    vadd.vv v8, v8, v8
163; CHECK-NEXT:    vor.vv v8, v8, v9
164; CHECK-NEXT:    ret
165;
166; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i8:
167; CHECK-ZVKB:       # %bb.0:
168; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
169; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
170; CHECK-ZVKB-NEXT:    ret
171  %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> splat (i8 1))
172  ret <vscale x 2 x i8> %x
173}
174
175declare <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>)
176declare <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>)
177
178define <vscale x 4 x i8> @vror_vv_nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
179; CHECK-LABEL: vror_vv_nxv4i8:
180; CHECK:       # %bb.0:
181; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
182; CHECK-NEXT:    vand.vi v10, v9, 7
183; CHECK-NEXT:    vrsub.vi v9, v9, 0
184; CHECK-NEXT:    vsrl.vv v10, v8, v10
185; CHECK-NEXT:    vand.vi v9, v9, 7
186; CHECK-NEXT:    vsll.vv v8, v8, v9
187; CHECK-NEXT:    vor.vv v8, v10, v8
188; CHECK-NEXT:    ret
189;
190; CHECK-ZVKB-LABEL: vror_vv_nxv4i8:
191; CHECK-ZVKB:       # %bb.0:
192; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
193; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
194; CHECK-ZVKB-NEXT:    ret
195  %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b)
196  ret <vscale x 4 x i8> %x
197}
198
199define <vscale x 4 x i8> @vror_vx_nxv4i8(<vscale x 4 x i8> %a, i8 %b) {
200; CHECK-LABEL: vror_vx_nxv4i8:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
203; CHECK-NEXT:    vmv.v.x v9, a0
204; CHECK-NEXT:    vand.vi v10, v9, 7
205; CHECK-NEXT:    vrsub.vi v9, v9, 0
206; CHECK-NEXT:    vsrl.vv v10, v8, v10
207; CHECK-NEXT:    vand.vi v9, v9, 7
208; CHECK-NEXT:    vsll.vv v8, v8, v9
209; CHECK-NEXT:    vor.vv v8, v10, v8
210; CHECK-NEXT:    ret
211;
212; CHECK-ZVKB-LABEL: vror_vx_nxv4i8:
213; CHECK-ZVKB:       # %bb.0:
214; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
215; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
216; CHECK-ZVKB-NEXT:    ret
217  %b.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
218  %b.splat = shufflevector <vscale x 4 x i8> %b.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
219  %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b.splat)
220  ret <vscale x 4 x i8> %x
221}
222
223define <vscale x 4 x i8> @vror_vi_nxv4i8(<vscale x 4 x i8> %a) {
224; CHECK-LABEL: vror_vi_nxv4i8:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
227; CHECK-NEXT:    vsll.vi v9, v8, 7
228; CHECK-NEXT:    vsrl.vi v8, v8, 1
229; CHECK-NEXT:    vor.vv v8, v8, v9
230; CHECK-NEXT:    ret
231;
232; CHECK-ZVKB-LABEL: vror_vi_nxv4i8:
233; CHECK-ZVKB:       # %bb.0:
234; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
235; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
236; CHECK-ZVKB-NEXT:    ret
237  %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> splat (i8 1))
238  ret <vscale x 4 x i8> %x
239}
240
241define <vscale x 4 x i8> @vror_vi_rotl_nxv4i8(<vscale x 4 x i8> %a) {
242; CHECK-LABEL: vror_vi_rotl_nxv4i8:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
245; CHECK-NEXT:    vsrl.vi v9, v8, 7
246; CHECK-NEXT:    vadd.vv v8, v8, v8
247; CHECK-NEXT:    vor.vv v8, v8, v9
248; CHECK-NEXT:    ret
249;
250; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i8:
251; CHECK-ZVKB:       # %bb.0:
252; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
253; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
254; CHECK-ZVKB-NEXT:    ret
255  %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> splat (i8 1))
256  ret <vscale x 4 x i8> %x
257}
258
259declare <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>)
260declare <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>)
261
262define <vscale x 8 x i8> @vror_vv_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
263; CHECK-LABEL: vror_vv_nxv8i8:
264; CHECK:       # %bb.0:
265; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
266; CHECK-NEXT:    vand.vi v10, v9, 7
267; CHECK-NEXT:    vrsub.vi v9, v9, 0
268; CHECK-NEXT:    vsrl.vv v10, v8, v10
269; CHECK-NEXT:    vand.vi v9, v9, 7
270; CHECK-NEXT:    vsll.vv v8, v8, v9
271; CHECK-NEXT:    vor.vv v8, v10, v8
272; CHECK-NEXT:    ret
273;
274; CHECK-ZVKB-LABEL: vror_vv_nxv8i8:
275; CHECK-ZVKB:       # %bb.0:
276; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
277; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
278; CHECK-ZVKB-NEXT:    ret
279  %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
280  ret <vscale x 8 x i8> %x
281}
282
283define <vscale x 8 x i8> @vror_vx_nxv8i8(<vscale x 8 x i8> %a, i8 %b) {
284; CHECK-LABEL: vror_vx_nxv8i8:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
287; CHECK-NEXT:    vmv.v.x v9, a0
288; CHECK-NEXT:    vand.vi v10, v9, 7
289; CHECK-NEXT:    vrsub.vi v9, v9, 0
290; CHECK-NEXT:    vsrl.vv v10, v8, v10
291; CHECK-NEXT:    vand.vi v9, v9, 7
292; CHECK-NEXT:    vsll.vv v8, v8, v9
293; CHECK-NEXT:    vor.vv v8, v10, v8
294; CHECK-NEXT:    ret
295;
296; CHECK-ZVKB-LABEL: vror_vx_nxv8i8:
297; CHECK-ZVKB:       # %bb.0:
298; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
299; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
300; CHECK-ZVKB-NEXT:    ret
301  %b.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
302  %b.splat = shufflevector <vscale x 8 x i8> %b.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
303  %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b.splat)
304  ret <vscale x 8 x i8> %x
305}
306
307define <vscale x 8 x i8> @vror_vi_nxv8i8(<vscale x 8 x i8> %a) {
308; CHECK-LABEL: vror_vi_nxv8i8:
309; CHECK:       # %bb.0:
310; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
311; CHECK-NEXT:    vsll.vi v9, v8, 7
312; CHECK-NEXT:    vsrl.vi v8, v8, 1
313; CHECK-NEXT:    vor.vv v8, v8, v9
314; CHECK-NEXT:    ret
315;
316; CHECK-ZVKB-LABEL: vror_vi_nxv8i8:
317; CHECK-ZVKB:       # %bb.0:
318; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
319; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
320; CHECK-ZVKB-NEXT:    ret
321  %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> splat (i8 1))
322  ret <vscale x 8 x i8> %x
323}
324
325define <vscale x 8 x i8> @vror_vi_rotl_nxv8i8(<vscale x 8 x i8> %a) {
326; CHECK-LABEL: vror_vi_rotl_nxv8i8:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
329; CHECK-NEXT:    vsrl.vi v9, v8, 7
330; CHECK-NEXT:    vadd.vv v8, v8, v8
331; CHECK-NEXT:    vor.vv v8, v8, v9
332; CHECK-NEXT:    ret
333;
334; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i8:
335; CHECK-ZVKB:       # %bb.0:
336; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
337; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
338; CHECK-ZVKB-NEXT:    ret
339  %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> splat (i8 1))
340  ret <vscale x 8 x i8> %x
341}
342
343declare <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
344declare <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
345
346define <vscale x 16 x i8> @vror_vv_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
347; CHECK-LABEL: vror_vv_nxv16i8:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
350; CHECK-NEXT:    vand.vi v12, v10, 7
351; CHECK-NEXT:    vrsub.vi v10, v10, 0
352; CHECK-NEXT:    vsrl.vv v12, v8, v12
353; CHECK-NEXT:    vand.vi v10, v10, 7
354; CHECK-NEXT:    vsll.vv v8, v8, v10
355; CHECK-NEXT:    vor.vv v8, v12, v8
356; CHECK-NEXT:    ret
357;
358; CHECK-ZVKB-LABEL: vror_vv_nxv16i8:
359; CHECK-ZVKB:       # %bb.0:
360; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
361; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
362; CHECK-ZVKB-NEXT:    ret
363  %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
364  ret <vscale x 16 x i8> %x
365}
366
367define <vscale x 16 x i8> @vror_vx_nxv16i8(<vscale x 16 x i8> %a, i8 %b) {
368; CHECK-LABEL: vror_vx_nxv16i8:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
371; CHECK-NEXT:    vmv.v.x v10, a0
372; CHECK-NEXT:    vand.vi v12, v10, 7
373; CHECK-NEXT:    vrsub.vi v10, v10, 0
374; CHECK-NEXT:    vsrl.vv v12, v8, v12
375; CHECK-NEXT:    vand.vi v10, v10, 7
376; CHECK-NEXT:    vsll.vv v8, v8, v10
377; CHECK-NEXT:    vor.vv v8, v12, v8
378; CHECK-NEXT:    ret
379;
380; CHECK-ZVKB-LABEL: vror_vx_nxv16i8:
381; CHECK-ZVKB:       # %bb.0:
382; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
383; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
384; CHECK-ZVKB-NEXT:    ret
385  %b.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
386  %b.splat = shufflevector <vscale x 16 x i8> %b.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
387  %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b.splat)
388  ret <vscale x 16 x i8> %x
389}
390
391define <vscale x 16 x i8> @vror_vi_nxv16i8(<vscale x 16 x i8> %a) {
392; CHECK-LABEL: vror_vi_nxv16i8:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
395; CHECK-NEXT:    vsll.vi v10, v8, 7
396; CHECK-NEXT:    vsrl.vi v8, v8, 1
397; CHECK-NEXT:    vor.vv v8, v8, v10
398; CHECK-NEXT:    ret
399;
400; CHECK-ZVKB-LABEL: vror_vi_nxv16i8:
401; CHECK-ZVKB:       # %bb.0:
402; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
403; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
404; CHECK-ZVKB-NEXT:    ret
405  %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat (i8 1))
406  ret <vscale x 16 x i8> %x
407}
408
409define <vscale x 16 x i8> @vror_vi_rotl_nxv16i8(<vscale x 16 x i8> %a) {
410; CHECK-LABEL: vror_vi_rotl_nxv16i8:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
413; CHECK-NEXT:    vsrl.vi v10, v8, 7
414; CHECK-NEXT:    vadd.vv v8, v8, v8
415; CHECK-NEXT:    vor.vv v8, v8, v10
416; CHECK-NEXT:    ret
417;
418; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i8:
419; CHECK-ZVKB:       # %bb.0:
420; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
421; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
422; CHECK-ZVKB-NEXT:    ret
423  %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat (i8 1))
424  ret <vscale x 16 x i8> %x
425}
426
427declare <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>)
428declare <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>)
429
430define <vscale x 32 x i8> @vror_vv_nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
431; CHECK-LABEL: vror_vv_nxv32i8:
432; CHECK:       # %bb.0:
433; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
434; CHECK-NEXT:    vand.vi v16, v12, 7
435; CHECK-NEXT:    vrsub.vi v12, v12, 0
436; CHECK-NEXT:    vsrl.vv v16, v8, v16
437; CHECK-NEXT:    vand.vi v12, v12, 7
438; CHECK-NEXT:    vsll.vv v8, v8, v12
439; CHECK-NEXT:    vor.vv v8, v16, v8
440; CHECK-NEXT:    ret
441;
442; CHECK-ZVKB-LABEL: vror_vv_nxv32i8:
443; CHECK-ZVKB:       # %bb.0:
444; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
445; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
446; CHECK-ZVKB-NEXT:    ret
447  %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b)
448  ret <vscale x 32 x i8> %x
449}
450
451define <vscale x 32 x i8> @vror_vx_nxv32i8(<vscale x 32 x i8> %a, i8 %b) {
452; CHECK-LABEL: vror_vx_nxv32i8:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
455; CHECK-NEXT:    vmv.v.x v12, a0
456; CHECK-NEXT:    vand.vi v16, v12, 7
457; CHECK-NEXT:    vrsub.vi v12, v12, 0
458; CHECK-NEXT:    vsrl.vv v16, v8, v16
459; CHECK-NEXT:    vand.vi v12, v12, 7
460; CHECK-NEXT:    vsll.vv v8, v8, v12
461; CHECK-NEXT:    vor.vv v8, v16, v8
462; CHECK-NEXT:    ret
463;
464; CHECK-ZVKB-LABEL: vror_vx_nxv32i8:
465; CHECK-ZVKB:       # %bb.0:
466; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
467; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
468; CHECK-ZVKB-NEXT:    ret
469  %b.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
470  %b.splat = shufflevector <vscale x 32 x i8> %b.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
471  %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b.splat)
472  ret <vscale x 32 x i8> %x
473}
474
475define <vscale x 32 x i8> @vror_vi_nxv32i8(<vscale x 32 x i8> %a) {
476; CHECK-LABEL: vror_vi_nxv32i8:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
479; CHECK-NEXT:    vsll.vi v12, v8, 7
480; CHECK-NEXT:    vsrl.vi v8, v8, 1
481; CHECK-NEXT:    vor.vv v8, v8, v12
482; CHECK-NEXT:    ret
483;
484; CHECK-ZVKB-LABEL: vror_vi_nxv32i8:
485; CHECK-ZVKB:       # %bb.0:
486; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
487; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
488; CHECK-ZVKB-NEXT:    ret
489  %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> splat (i8 1))
490  ret <vscale x 32 x i8> %x
491}
492
493define <vscale x 32 x i8> @vror_vi_rotl_nxv32i8(<vscale x 32 x i8> %a) {
494; CHECK-LABEL: vror_vi_rotl_nxv32i8:
495; CHECK:       # %bb.0:
496; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
497; CHECK-NEXT:    vsrl.vi v12, v8, 7
498; CHECK-NEXT:    vadd.vv v8, v8, v8
499; CHECK-NEXT:    vor.vv v8, v8, v12
500; CHECK-NEXT:    ret
501;
502; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv32i8:
503; CHECK-ZVKB:       # %bb.0:
504; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
505; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
506; CHECK-ZVKB-NEXT:    ret
507  %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> splat (i8 1))
508  ret <vscale x 32 x i8> %x
509}
510
511declare <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>)
512declare <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>)
513
514define <vscale x 64 x i8> @vror_vv_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
515; CHECK-LABEL: vror_vv_nxv64i8:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
518; CHECK-NEXT:    vand.vi v24, v16, 7
519; CHECK-NEXT:    vrsub.vi v16, v16, 0
520; CHECK-NEXT:    vsrl.vv v24, v8, v24
521; CHECK-NEXT:    vand.vi v16, v16, 7
522; CHECK-NEXT:    vsll.vv v8, v8, v16
523; CHECK-NEXT:    vor.vv v8, v24, v8
524; CHECK-NEXT:    ret
525;
526; CHECK-ZVKB-LABEL: vror_vv_nxv64i8:
527; CHECK-ZVKB:       # %bb.0:
528; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
529; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v16
530; CHECK-ZVKB-NEXT:    ret
531  %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
532  ret <vscale x 64 x i8> %x
533}
534
535define <vscale x 64 x i8> @vror_vx_nxv64i8(<vscale x 64 x i8> %a, i8 %b) {
536; CHECK-LABEL: vror_vx_nxv64i8:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
539; CHECK-NEXT:    vmv.v.x v16, a0
540; CHECK-NEXT:    vand.vi v24, v16, 7
541; CHECK-NEXT:    vrsub.vi v16, v16, 0
542; CHECK-NEXT:    vsrl.vv v24, v8, v24
543; CHECK-NEXT:    vand.vi v16, v16, 7
544; CHECK-NEXT:    vsll.vv v8, v8, v16
545; CHECK-NEXT:    vor.vv v8, v24, v8
546; CHECK-NEXT:    ret
547;
548; CHECK-ZVKB-LABEL: vror_vx_nxv64i8:
549; CHECK-ZVKB:       # %bb.0:
550; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
551; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
552; CHECK-ZVKB-NEXT:    ret
553  %b.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
554  %b.splat = shufflevector <vscale x 64 x i8> %b.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
555  %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b.splat)
556  ret <vscale x 64 x i8> %x
557}
558
559define <vscale x 64 x i8> @vror_vi_nxv64i8(<vscale x 64 x i8> %a) {
560; CHECK-LABEL: vror_vi_nxv64i8:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
563; CHECK-NEXT:    vsll.vi v16, v8, 7
564; CHECK-NEXT:    vsrl.vi v8, v8, 1
565; CHECK-NEXT:    vor.vv v8, v8, v16
566; CHECK-NEXT:    ret
567;
568; CHECK-ZVKB-LABEL: vror_vi_nxv64i8:
569; CHECK-ZVKB:       # %bb.0:
570; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
571; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
572; CHECK-ZVKB-NEXT:    ret
573  %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> splat (i8 1))
574  ret <vscale x 64 x i8> %x
575}
576
577define <vscale x 64 x i8> @vror_vi_rotl_nxv64i8(<vscale x 64 x i8> %a) {
578; CHECK-LABEL: vror_vi_rotl_nxv64i8:
579; CHECK:       # %bb.0:
580; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
581; CHECK-NEXT:    vsrl.vi v16, v8, 7
582; CHECK-NEXT:    vadd.vv v8, v8, v8
583; CHECK-NEXT:    vor.vv v8, v8, v16
584; CHECK-NEXT:    ret
585;
586; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv64i8:
587; CHECK-ZVKB:       # %bb.0:
588; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
589; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
590; CHECK-ZVKB-NEXT:    ret
591  %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> splat (i8 1))
592  ret <vscale x 64 x i8> %x
593}
594
595declare <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>)
596declare <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>)
597
598define <vscale x 1 x i16> @vror_vv_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {
599; CHECK-LABEL: vror_vv_nxv1i16:
600; CHECK:       # %bb.0:
601; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
602; CHECK-NEXT:    vand.vi v10, v9, 15
603; CHECK-NEXT:    vrsub.vi v9, v9, 0
604; CHECK-NEXT:    vsrl.vv v10, v8, v10
605; CHECK-NEXT:    vand.vi v9, v9, 15
606; CHECK-NEXT:    vsll.vv v8, v8, v9
607; CHECK-NEXT:    vor.vv v8, v10, v8
608; CHECK-NEXT:    ret
609;
610; CHECK-ZVKB-LABEL: vror_vv_nxv1i16:
611; CHECK-ZVKB:       # %bb.0:
612; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
613; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
614; CHECK-ZVKB-NEXT:    ret
615  %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b)
616  ret <vscale x 1 x i16> %x
617}
618
619define <vscale x 1 x i16> @vror_vx_nxv1i16(<vscale x 1 x i16> %a, i16 %b) {
620; CHECK-LABEL: vror_vx_nxv1i16:
621; CHECK:       # %bb.0:
622; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
623; CHECK-NEXT:    vmv.v.x v9, a0
624; CHECK-NEXT:    vand.vi v10, v9, 15
625; CHECK-NEXT:    vrsub.vi v9, v9, 0
626; CHECK-NEXT:    vsrl.vv v10, v8, v10
627; CHECK-NEXT:    vand.vi v9, v9, 15
628; CHECK-NEXT:    vsll.vv v8, v8, v9
629; CHECK-NEXT:    vor.vv v8, v10, v8
630; CHECK-NEXT:    ret
631;
632; CHECK-ZVKB-LABEL: vror_vx_nxv1i16:
633; CHECK-ZVKB:       # %bb.0:
634; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
635; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
636; CHECK-ZVKB-NEXT:    ret
637  %b.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
638  %b.splat = shufflevector <vscale x 1 x i16> %b.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
639  %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b.splat)
640  ret <vscale x 1 x i16> %x
641}
642
643define <vscale x 1 x i16> @vror_vi_nxv1i16(<vscale x 1 x i16> %a) {
644; CHECK-LABEL: vror_vi_nxv1i16:
645; CHECK:       # %bb.0:
646; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
647; CHECK-NEXT:    vsll.vi v9, v8, 15
648; CHECK-NEXT:    vsrl.vi v8, v8, 1
649; CHECK-NEXT:    vor.vv v8, v8, v9
650; CHECK-NEXT:    ret
651;
652; CHECK-ZVKB-LABEL: vror_vi_nxv1i16:
653; CHECK-ZVKB:       # %bb.0:
654; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
655; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
656; CHECK-ZVKB-NEXT:    ret
657  %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> splat (i16 1))
658  ret <vscale x 1 x i16> %x
659}
660
661define <vscale x 1 x i16> @vror_vi_rotl_nxv1i16(<vscale x 1 x i16> %a) {
662; CHECK-LABEL: vror_vi_rotl_nxv1i16:
663; CHECK:       # %bb.0:
664; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
665; CHECK-NEXT:    vsrl.vi v9, v8, 15
666; CHECK-NEXT:    vadd.vv v8, v8, v8
667; CHECK-NEXT:    vor.vv v8, v8, v9
668; CHECK-NEXT:    ret
669;
670; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i16:
671; CHECK-ZVKB:       # %bb.0:
672; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
673; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
674; CHECK-ZVKB-NEXT:    ret
675  %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> splat (i16 1))
676  ret <vscale x 1 x i16> %x
677}
678
679declare <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)
680declare <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>)
681
682define <vscale x 2 x i16> @vror_vv_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {
683; CHECK-LABEL: vror_vv_nxv2i16:
684; CHECK:       # %bb.0:
685; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
686; CHECK-NEXT:    vand.vi v10, v9, 15
687; CHECK-NEXT:    vrsub.vi v9, v9, 0
688; CHECK-NEXT:    vsrl.vv v10, v8, v10
689; CHECK-NEXT:    vand.vi v9, v9, 15
690; CHECK-NEXT:    vsll.vv v8, v8, v9
691; CHECK-NEXT:    vor.vv v8, v10, v8
692; CHECK-NEXT:    ret
693;
694; CHECK-ZVKB-LABEL: vror_vv_nxv2i16:
695; CHECK-ZVKB:       # %bb.0:
696; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
697; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
698; CHECK-ZVKB-NEXT:    ret
699  %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b)
700  ret <vscale x 2 x i16> %x
701}
702
703define <vscale x 2 x i16> @vror_vx_nxv2i16(<vscale x 2 x i16> %a, i16 %b) {
704; CHECK-LABEL: vror_vx_nxv2i16:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
707; CHECK-NEXT:    vmv.v.x v9, a0
708; CHECK-NEXT:    vand.vi v10, v9, 15
709; CHECK-NEXT:    vrsub.vi v9, v9, 0
710; CHECK-NEXT:    vsrl.vv v10, v8, v10
711; CHECK-NEXT:    vand.vi v9, v9, 15
712; CHECK-NEXT:    vsll.vv v8, v8, v9
713; CHECK-NEXT:    vor.vv v8, v10, v8
714; CHECK-NEXT:    ret
715;
716; CHECK-ZVKB-LABEL: vror_vx_nxv2i16:
717; CHECK-ZVKB:       # %bb.0:
718; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
719; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
720; CHECK-ZVKB-NEXT:    ret
721  %b.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
722  %b.splat = shufflevector <vscale x 2 x i16> %b.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
723  %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b.splat)
724  ret <vscale x 2 x i16> %x
725}
726
727define <vscale x 2 x i16> @vror_vi_nxv2i16(<vscale x 2 x i16> %a) {
728; CHECK-LABEL: vror_vi_nxv2i16:
729; CHECK:       # %bb.0:
730; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
731; CHECK-NEXT:    vsll.vi v9, v8, 15
732; CHECK-NEXT:    vsrl.vi v8, v8, 1
733; CHECK-NEXT:    vor.vv v8, v8, v9
734; CHECK-NEXT:    ret
735;
736; CHECK-ZVKB-LABEL: vror_vi_nxv2i16:
737; CHECK-ZVKB:       # %bb.0:
738; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
739; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
740; CHECK-ZVKB-NEXT:    ret
741  %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> splat (i16 1))
742  ret <vscale x 2 x i16> %x
743}
744
745define <vscale x 2 x i16> @vror_vi_rotl_nxv2i16(<vscale x 2 x i16> %a) {
746; CHECK-LABEL: vror_vi_rotl_nxv2i16:
747; CHECK:       # %bb.0:
748; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
749; CHECK-NEXT:    vsrl.vi v9, v8, 15
750; CHECK-NEXT:    vadd.vv v8, v8, v8
751; CHECK-NEXT:    vor.vv v8, v8, v9
752; CHECK-NEXT:    ret
753;
754; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i16:
755; CHECK-ZVKB:       # %bb.0:
756; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
757; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
758; CHECK-ZVKB-NEXT:    ret
759  %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> splat (i16 1))
760  ret <vscale x 2 x i16> %x
761}
762
763declare <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>)
764declare <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>)
765
766define <vscale x 4 x i16> @vror_vv_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
767; CHECK-LABEL: vror_vv_nxv4i16:
768; CHECK:       # %bb.0:
769; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
770; CHECK-NEXT:    vand.vi v10, v9, 15
771; CHECK-NEXT:    vrsub.vi v9, v9, 0
772; CHECK-NEXT:    vsrl.vv v10, v8, v10
773; CHECK-NEXT:    vand.vi v9, v9, 15
774; CHECK-NEXT:    vsll.vv v8, v8, v9
775; CHECK-NEXT:    vor.vv v8, v10, v8
776; CHECK-NEXT:    ret
777;
778; CHECK-ZVKB-LABEL: vror_vv_nxv4i16:
779; CHECK-ZVKB:       # %bb.0:
780; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
781; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
782; CHECK-ZVKB-NEXT:    ret
783  %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
784  ret <vscale x 4 x i16> %x
785}
786
787define <vscale x 4 x i16> @vror_vx_nxv4i16(<vscale x 4 x i16> %a, i16 %b) {
788; CHECK-LABEL: vror_vx_nxv4i16:
789; CHECK:       # %bb.0:
790; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
791; CHECK-NEXT:    vmv.v.x v9, a0
792; CHECK-NEXT:    vand.vi v10, v9, 15
793; CHECK-NEXT:    vrsub.vi v9, v9, 0
794; CHECK-NEXT:    vsrl.vv v10, v8, v10
795; CHECK-NEXT:    vand.vi v9, v9, 15
796; CHECK-NEXT:    vsll.vv v8, v8, v9
797; CHECK-NEXT:    vor.vv v8, v10, v8
798; CHECK-NEXT:    ret
799;
800; CHECK-ZVKB-LABEL: vror_vx_nxv4i16:
801; CHECK-ZVKB:       # %bb.0:
802; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
803; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
804; CHECK-ZVKB-NEXT:    ret
805  %b.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
806  %b.splat = shufflevector <vscale x 4 x i16> %b.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
807  %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b.splat)
808  ret <vscale x 4 x i16> %x
809}
810
811define <vscale x 4 x i16> @vror_vi_nxv4i16(<vscale x 4 x i16> %a) {
812; CHECK-LABEL: vror_vi_nxv4i16:
813; CHECK:       # %bb.0:
814; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
815; CHECK-NEXT:    vsll.vi v9, v8, 15
816; CHECK-NEXT:    vsrl.vi v8, v8, 1
817; CHECK-NEXT:    vor.vv v8, v8, v9
818; CHECK-NEXT:    ret
819;
820; CHECK-ZVKB-LABEL: vror_vi_nxv4i16:
821; CHECK-ZVKB:       # %bb.0:
822; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
823; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
824; CHECK-ZVKB-NEXT:    ret
825  %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> splat (i16 1))
826  ret <vscale x 4 x i16> %x
827}
828
829define <vscale x 4 x i16> @vror_vi_rotl_nxv4i16(<vscale x 4 x i16> %a) {
830; CHECK-LABEL: vror_vi_rotl_nxv4i16:
831; CHECK:       # %bb.0:
832; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
833; CHECK-NEXT:    vsrl.vi v9, v8, 15
834; CHECK-NEXT:    vadd.vv v8, v8, v8
835; CHECK-NEXT:    vor.vv v8, v8, v9
836; CHECK-NEXT:    ret
837;
838; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i16:
839; CHECK-ZVKB:       # %bb.0:
840; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
841; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
842; CHECK-ZVKB-NEXT:    ret
843  %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> splat (i16 1))
844  ret <vscale x 4 x i16> %x
845}
846
847declare <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
848declare <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
849
850define <vscale x 8 x i16> @vror_vv_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
851; CHECK-LABEL: vror_vv_nxv8i16:
852; CHECK:       # %bb.0:
853; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
854; CHECK-NEXT:    vand.vi v12, v10, 15
855; CHECK-NEXT:    vrsub.vi v10, v10, 0
856; CHECK-NEXT:    vsrl.vv v12, v8, v12
857; CHECK-NEXT:    vand.vi v10, v10, 15
858; CHECK-NEXT:    vsll.vv v8, v8, v10
859; CHECK-NEXT:    vor.vv v8, v12, v8
860; CHECK-NEXT:    ret
861;
862; CHECK-ZVKB-LABEL: vror_vv_nxv8i16:
863; CHECK-ZVKB:       # %bb.0:
864; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
865; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
866; CHECK-ZVKB-NEXT:    ret
867  %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
868  ret <vscale x 8 x i16> %x
869}
870
871define <vscale x 8 x i16> @vror_vx_nxv8i16(<vscale x 8 x i16> %a, i16 %b) {
872; CHECK-LABEL: vror_vx_nxv8i16:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
875; CHECK-NEXT:    vmv.v.x v10, a0
876; CHECK-NEXT:    vand.vi v12, v10, 15
877; CHECK-NEXT:    vrsub.vi v10, v10, 0
878; CHECK-NEXT:    vsrl.vv v12, v8, v12
879; CHECK-NEXT:    vand.vi v10, v10, 15
880; CHECK-NEXT:    vsll.vv v8, v8, v10
881; CHECK-NEXT:    vor.vv v8, v12, v8
882; CHECK-NEXT:    ret
883;
884; CHECK-ZVKB-LABEL: vror_vx_nxv8i16:
885; CHECK-ZVKB:       # %bb.0:
886; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
887; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
888; CHECK-ZVKB-NEXT:    ret
889  %b.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
890  %b.splat = shufflevector <vscale x 8 x i16> %b.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
891  %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b.splat)
892  ret <vscale x 8 x i16> %x
893}
894
895define <vscale x 8 x i16> @vror_vi_nxv8i16(<vscale x 8 x i16> %a) {
896; CHECK-LABEL: vror_vi_nxv8i16:
897; CHECK:       # %bb.0:
898; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
899; CHECK-NEXT:    vsll.vi v10, v8, 15
900; CHECK-NEXT:    vsrl.vi v8, v8, 1
901; CHECK-NEXT:    vor.vv v8, v8, v10
902; CHECK-NEXT:    ret
903;
904; CHECK-ZVKB-LABEL: vror_vi_nxv8i16:
905; CHECK-ZVKB:       # %bb.0:
906; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
907; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
908; CHECK-ZVKB-NEXT:    ret
909  %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat (i16 1))
910  ret <vscale x 8 x i16> %x
911}
912
913define <vscale x 8 x i16> @vror_vi_rotl_nxv8i16(<vscale x 8 x i16> %a) {
914; CHECK-LABEL: vror_vi_rotl_nxv8i16:
915; CHECK:       # %bb.0:
916; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
917; CHECK-NEXT:    vsrl.vi v10, v8, 15
918; CHECK-NEXT:    vadd.vv v8, v8, v8
919; CHECK-NEXT:    vor.vv v8, v8, v10
920; CHECK-NEXT:    ret
921;
922; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i16:
923; CHECK-ZVKB:       # %bb.0:
924; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
925; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
926; CHECK-ZVKB-NEXT:    ret
927  %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat (i16 1))
928  ret <vscale x 8 x i16> %x
929}
930
931declare <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>)
932declare <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>)
933
934define <vscale x 16 x i16> @vror_vv_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
935; CHECK-LABEL: vror_vv_nxv16i16:
936; CHECK:       # %bb.0:
937; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
938; CHECK-NEXT:    vand.vi v16, v12, 15
939; CHECK-NEXT:    vrsub.vi v12, v12, 0
940; CHECK-NEXT:    vsrl.vv v16, v8, v16
941; CHECK-NEXT:    vand.vi v12, v12, 15
942; CHECK-NEXT:    vsll.vv v8, v8, v12
943; CHECK-NEXT:    vor.vv v8, v16, v8
944; CHECK-NEXT:    ret
945;
946; CHECK-ZVKB-LABEL: vror_vv_nxv16i16:
947; CHECK-ZVKB:       # %bb.0:
948; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
949; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
950; CHECK-ZVKB-NEXT:    ret
951  %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
952  ret <vscale x 16 x i16> %x
953}
954
955define <vscale x 16 x i16> @vror_vx_nxv16i16(<vscale x 16 x i16> %a, i16 %b) {
956; CHECK-LABEL: vror_vx_nxv16i16:
957; CHECK:       # %bb.0:
958; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
959; CHECK-NEXT:    vmv.v.x v12, a0
960; CHECK-NEXT:    vand.vi v16, v12, 15
961; CHECK-NEXT:    vrsub.vi v12, v12, 0
962; CHECK-NEXT:    vsrl.vv v16, v8, v16
963; CHECK-NEXT:    vand.vi v12, v12, 15
964; CHECK-NEXT:    vsll.vv v8, v8, v12
965; CHECK-NEXT:    vor.vv v8, v16, v8
966; CHECK-NEXT:    ret
967;
968; CHECK-ZVKB-LABEL: vror_vx_nxv16i16:
969; CHECK-ZVKB:       # %bb.0:
970; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
971; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
972; CHECK-ZVKB-NEXT:    ret
973  %b.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
974  %b.splat = shufflevector <vscale x 16 x i16> %b.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
975  %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b.splat)
976  ret <vscale x 16 x i16> %x
977}
978
979define <vscale x 16 x i16> @vror_vi_nxv16i16(<vscale x 16 x i16> %a) {
980; CHECK-LABEL: vror_vi_nxv16i16:
981; CHECK:       # %bb.0:
982; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
983; CHECK-NEXT:    vsll.vi v12, v8, 15
984; CHECK-NEXT:    vsrl.vi v8, v8, 1
985; CHECK-NEXT:    vor.vv v8, v8, v12
986; CHECK-NEXT:    ret
987;
988; CHECK-ZVKB-LABEL: vror_vi_nxv16i16:
989; CHECK-ZVKB:       # %bb.0:
990; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
991; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
992; CHECK-ZVKB-NEXT:    ret
993  %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> splat (i16 1))
994  ret <vscale x 16 x i16> %x
995}
996
997define <vscale x 16 x i16> @vror_vi_rotl_nxv16i16(<vscale x 16 x i16> %a) {
998; CHECK-LABEL: vror_vi_rotl_nxv16i16:
999; CHECK:       # %bb.0:
1000; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
1001; CHECK-NEXT:    vsrl.vi v12, v8, 15
1002; CHECK-NEXT:    vadd.vv v8, v8, v8
1003; CHECK-NEXT:    vor.vv v8, v8, v12
1004; CHECK-NEXT:    ret
1005;
1006; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i16:
1007; CHECK-ZVKB:       # %bb.0:
1008; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
1009; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
1010; CHECK-ZVKB-NEXT:    ret
1011  %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> splat (i16 1))
1012  ret <vscale x 16 x i16> %x
1013}
1014
1015declare <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>)
1016declare <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>)
1017
1018define <vscale x 32 x i16> @vror_vv_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
1019; CHECK-LABEL: vror_vv_nxv32i16:
1020; CHECK:       # %bb.0:
1021; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1022; CHECK-NEXT:    vand.vi v24, v16, 15
1023; CHECK-NEXT:    vrsub.vi v16, v16, 0
1024; CHECK-NEXT:    vsrl.vv v24, v8, v24
1025; CHECK-NEXT:    vand.vi v16, v16, 15
1026; CHECK-NEXT:    vsll.vv v8, v8, v16
1027; CHECK-NEXT:    vor.vv v8, v24, v8
1028; CHECK-NEXT:    ret
1029;
1030; CHECK-ZVKB-LABEL: vror_vv_nxv32i16:
1031; CHECK-ZVKB:       # %bb.0:
1032; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1033; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v16
1034; CHECK-ZVKB-NEXT:    ret
1035  %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
1036  ret <vscale x 32 x i16> %x
1037}
1038
1039define <vscale x 32 x i16> @vror_vx_nxv32i16(<vscale x 32 x i16> %a, i16 %b) {
1040; CHECK-LABEL: vror_vx_nxv32i16:
1041; CHECK:       # %bb.0:
1042; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
1043; CHECK-NEXT:    vmv.v.x v16, a0
1044; CHECK-NEXT:    vand.vi v24, v16, 15
1045; CHECK-NEXT:    vrsub.vi v16, v16, 0
1046; CHECK-NEXT:    vsrl.vv v24, v8, v24
1047; CHECK-NEXT:    vand.vi v16, v16, 15
1048; CHECK-NEXT:    vsll.vv v8, v8, v16
1049; CHECK-NEXT:    vor.vv v8, v24, v8
1050; CHECK-NEXT:    ret
1051;
1052; CHECK-ZVKB-LABEL: vror_vx_nxv32i16:
1053; CHECK-ZVKB:       # %bb.0:
1054; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
1055; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1056; CHECK-ZVKB-NEXT:    ret
1057  %b.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
1058  %b.splat = shufflevector <vscale x 32 x i16> %b.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
1059  %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b.splat)
1060  ret <vscale x 32 x i16> %x
1061}
1062
1063define <vscale x 32 x i16> @vror_vi_nxv32i16(<vscale x 32 x i16> %a) {
1064; CHECK-LABEL: vror_vi_nxv32i16:
1065; CHECK:       # %bb.0:
1066; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1067; CHECK-NEXT:    vsll.vi v16, v8, 15
1068; CHECK-NEXT:    vsrl.vi v8, v8, 1
1069; CHECK-NEXT:    vor.vv v8, v8, v16
1070; CHECK-NEXT:    ret
1071;
1072; CHECK-ZVKB-LABEL: vror_vi_nxv32i16:
1073; CHECK-ZVKB:       # %bb.0:
1074; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1075; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1076; CHECK-ZVKB-NEXT:    ret
1077  %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> splat (i16 1))
1078  ret <vscale x 32 x i16> %x
1079}
1080
1081define <vscale x 32 x i16> @vror_vi_rotl_nxv32i16(<vscale x 32 x i16> %a) {
1082; CHECK-LABEL: vror_vi_rotl_nxv32i16:
1083; CHECK:       # %bb.0:
1084; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1085; CHECK-NEXT:    vsrl.vi v16, v8, 15
1086; CHECK-NEXT:    vadd.vv v8, v8, v8
1087; CHECK-NEXT:    vor.vv v8, v8, v16
1088; CHECK-NEXT:    ret
1089;
1090; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv32i16:
1091; CHECK-ZVKB:       # %bb.0:
1092; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1093; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
1094; CHECK-ZVKB-NEXT:    ret
1095  %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> splat (i16 1))
1096  ret <vscale x 32 x i16> %x
1097}
1098
1099declare <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>)
1100declare <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>)
1101
1102define <vscale x 1 x i32> @vror_vv_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {
1103; CHECK-LABEL: vror_vv_nxv1i32:
1104; CHECK:       # %bb.0:
1105; CHECK-NEXT:    li a0, 31
1106; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
1107; CHECK-NEXT:    vrsub.vi v10, v9, 0
1108; CHECK-NEXT:    vand.vx v9, v9, a0
1109; CHECK-NEXT:    vand.vx v10, v10, a0
1110; CHECK-NEXT:    vsrl.vv v9, v8, v9
1111; CHECK-NEXT:    vsll.vv v8, v8, v10
1112; CHECK-NEXT:    vor.vv v8, v9, v8
1113; CHECK-NEXT:    ret
1114;
1115; CHECK-ZVKB-LABEL: vror_vv_nxv1i32:
1116; CHECK-ZVKB:       # %bb.0:
1117; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
1118; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1119; CHECK-ZVKB-NEXT:    ret
1120  %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b)
1121  ret <vscale x 1 x i32> %x
1122}
1123
1124define <vscale x 1 x i32> @vror_vx_nxv1i32(<vscale x 1 x i32> %a, i32 %b) {
1125; CHECK-RV32-LABEL: vror_vx_nxv1i32:
1126; CHECK-RV32:       # %bb.0:
1127; CHECK-RV32-NEXT:    andi a1, a0, 31
1128; CHECK-RV32-NEXT:    neg a0, a0
1129; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
1130; CHECK-RV32-NEXT:    vsrl.vx v9, v8, a1
1131; CHECK-RV32-NEXT:    andi a0, a0, 31
1132; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
1133; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
1134; CHECK-RV32-NEXT:    ret
1135;
1136; CHECK-RV64-LABEL: vror_vx_nxv1i32:
1137; CHECK-RV64:       # %bb.0:
1138; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
1139; CHECK-RV64-NEXT:    vmv.v.x v9, a0
1140; CHECK-RV64-NEXT:    li a0, 31
1141; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
1142; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
1143; CHECK-RV64-NEXT:    vsrl.vv v10, v8, v10
1144; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
1145; CHECK-RV64-NEXT:    vsll.vv v8, v8, v9
1146; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
1147; CHECK-RV64-NEXT:    ret
1148;
1149; CHECK-ZVKB-LABEL: vror_vx_nxv1i32:
1150; CHECK-ZVKB:       # %bb.0:
1151; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
1152; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1153; CHECK-ZVKB-NEXT:    ret
1154  %b.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
1155  %b.splat = shufflevector <vscale x 1 x i32> %b.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
1156  %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b.splat)
1157  ret <vscale x 1 x i32> %x
1158}
1159
1160define <vscale x 1 x i32> @vror_vi_nxv1i32(<vscale x 1 x i32> %a) {
1161; CHECK-LABEL: vror_vi_nxv1i32:
1162; CHECK:       # %bb.0:
1163; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
1164; CHECK-NEXT:    vsll.vi v9, v8, 31
1165; CHECK-NEXT:    vsrl.vi v8, v8, 1
1166; CHECK-NEXT:    vor.vv v8, v8, v9
1167; CHECK-NEXT:    ret
1168;
1169; CHECK-ZVKB-LABEL: vror_vi_nxv1i32:
1170; CHECK-ZVKB:       # %bb.0:
1171; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
1172; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1173; CHECK-ZVKB-NEXT:    ret
1174  %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> splat (i32 1))
1175  ret <vscale x 1 x i32> %x
1176}
1177
1178define <vscale x 1 x i32> @vror_vi_rotl_nxv1i32(<vscale x 1 x i32> %a) {
1179; CHECK-LABEL: vror_vi_rotl_nxv1i32:
1180; CHECK:       # %bb.0:
1181; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
1182; CHECK-NEXT:    vsrl.vi v9, v8, 31
1183; CHECK-NEXT:    vadd.vv v8, v8, v8
1184; CHECK-NEXT:    vor.vv v8, v8, v9
1185; CHECK-NEXT:    ret
1186;
1187; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i32:
1188; CHECK-ZVKB:       # %bb.0:
1189; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
1190; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1191; CHECK-ZVKB-NEXT:    ret
1192  %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> splat (i32 1))
1193  ret <vscale x 1 x i32> %x
1194}
1195
1196declare <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>)
1197declare <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>)
1198
1199define <vscale x 2 x i32> @vror_vv_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
1200; CHECK-LABEL: vror_vv_nxv2i32:
1201; CHECK:       # %bb.0:
1202; CHECK-NEXT:    li a0, 31
1203; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
1204; CHECK-NEXT:    vrsub.vi v10, v9, 0
1205; CHECK-NEXT:    vand.vx v9, v9, a0
1206; CHECK-NEXT:    vand.vx v10, v10, a0
1207; CHECK-NEXT:    vsrl.vv v9, v8, v9
1208; CHECK-NEXT:    vsll.vv v8, v8, v10
1209; CHECK-NEXT:    vor.vv v8, v9, v8
1210; CHECK-NEXT:    ret
1211;
1212; CHECK-ZVKB-LABEL: vror_vv_nxv2i32:
1213; CHECK-ZVKB:       # %bb.0:
1214; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1215; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1216; CHECK-ZVKB-NEXT:    ret
1217  %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
1218  ret <vscale x 2 x i32> %x
1219}
1220
1221define <vscale x 2 x i32> @vror_vx_nxv2i32(<vscale x 2 x i32> %a, i32 %b) {
1222; CHECK-RV32-LABEL: vror_vx_nxv2i32:
1223; CHECK-RV32:       # %bb.0:
1224; CHECK-RV32-NEXT:    andi a1, a0, 31
1225; CHECK-RV32-NEXT:    neg a0, a0
1226; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
1227; CHECK-RV32-NEXT:    vsrl.vx v9, v8, a1
1228; CHECK-RV32-NEXT:    andi a0, a0, 31
1229; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
1230; CHECK-RV32-NEXT:    vor.vv v8, v9, v8
1231; CHECK-RV32-NEXT:    ret
1232;
1233; CHECK-RV64-LABEL: vror_vx_nxv2i32:
1234; CHECK-RV64:       # %bb.0:
1235; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
1236; CHECK-RV64-NEXT:    vmv.v.x v9, a0
1237; CHECK-RV64-NEXT:    li a0, 31
1238; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
1239; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
1240; CHECK-RV64-NEXT:    vsrl.vv v10, v8, v10
1241; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
1242; CHECK-RV64-NEXT:    vsll.vv v8, v8, v9
1243; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
1244; CHECK-RV64-NEXT:    ret
1245;
1246; CHECK-ZVKB-LABEL: vror_vx_nxv2i32:
1247; CHECK-ZVKB:       # %bb.0:
1248; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
1249; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1250; CHECK-ZVKB-NEXT:    ret
1251  %b.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
1252  %b.splat = shufflevector <vscale x 2 x i32> %b.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
1253  %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b.splat)
1254  ret <vscale x 2 x i32> %x
1255}
1256
1257define <vscale x 2 x i32> @vror_vi_nxv2i32(<vscale x 2 x i32> %a) {
1258; CHECK-LABEL: vror_vi_nxv2i32:
1259; CHECK:       # %bb.0:
1260; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1261; CHECK-NEXT:    vsll.vi v9, v8, 31
1262; CHECK-NEXT:    vsrl.vi v8, v8, 1
1263; CHECK-NEXT:    vor.vv v8, v8, v9
1264; CHECK-NEXT:    ret
1265;
1266; CHECK-ZVKB-LABEL: vror_vi_nxv2i32:
1267; CHECK-ZVKB:       # %bb.0:
1268; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1269; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1270; CHECK-ZVKB-NEXT:    ret
1271  %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> splat (i32 1))
1272  ret <vscale x 2 x i32> %x
1273}
1274
1275define <vscale x 2 x i32> @vror_vi_rotl_nxv2i32(<vscale x 2 x i32> %a) {
1276; CHECK-LABEL: vror_vi_rotl_nxv2i32:
1277; CHECK:       # %bb.0:
1278; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1279; CHECK-NEXT:    vsrl.vi v9, v8, 31
1280; CHECK-NEXT:    vadd.vv v8, v8, v8
1281; CHECK-NEXT:    vor.vv v8, v8, v9
1282; CHECK-NEXT:    ret
1283;
1284; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i32:
1285; CHECK-ZVKB:       # %bb.0:
1286; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1287; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1288; CHECK-ZVKB-NEXT:    ret
1289  %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> splat (i32 1))
1290  ret <vscale x 2 x i32> %x
1291}
1292
1293declare <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1294declare <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
1295
1296define <vscale x 4 x i32> @vror_vv_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
1297; CHECK-LABEL: vror_vv_nxv4i32:
1298; CHECK:       # %bb.0:
1299; CHECK-NEXT:    li a0, 31
1300; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
1301; CHECK-NEXT:    vrsub.vi v12, v10, 0
1302; CHECK-NEXT:    vand.vx v10, v10, a0
1303; CHECK-NEXT:    vand.vx v12, v12, a0
1304; CHECK-NEXT:    vsrl.vv v10, v8, v10
1305; CHECK-NEXT:    vsll.vv v8, v8, v12
1306; CHECK-NEXT:    vor.vv v8, v10, v8
1307; CHECK-NEXT:    ret
1308;
1309; CHECK-ZVKB-LABEL: vror_vv_nxv4i32:
1310; CHECK-ZVKB:       # %bb.0:
1311; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1312; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
1313; CHECK-ZVKB-NEXT:    ret
1314  %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
1315  ret <vscale x 4 x i32> %x
1316}
1317
1318define <vscale x 4 x i32> @vror_vx_nxv4i32(<vscale x 4 x i32> %a, i32 %b) {
1319; CHECK-RV32-LABEL: vror_vx_nxv4i32:
1320; CHECK-RV32:       # %bb.0:
1321; CHECK-RV32-NEXT:    andi a1, a0, 31
1322; CHECK-RV32-NEXT:    neg a0, a0
1323; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m2, ta, ma
1324; CHECK-RV32-NEXT:    vsrl.vx v10, v8, a1
1325; CHECK-RV32-NEXT:    andi a0, a0, 31
1326; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
1327; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
1328; CHECK-RV32-NEXT:    ret
1329;
1330; CHECK-RV64-LABEL: vror_vx_nxv4i32:
1331; CHECK-RV64:       # %bb.0:
1332; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
1333; CHECK-RV64-NEXT:    vmv.v.x v10, a0
1334; CHECK-RV64-NEXT:    li a0, 31
1335; CHECK-RV64-NEXT:    vand.vx v12, v10, a0
1336; CHECK-RV64-NEXT:    vrsub.vi v10, v10, 0
1337; CHECK-RV64-NEXT:    vsrl.vv v12, v8, v12
1338; CHECK-RV64-NEXT:    vand.vx v10, v10, a0
1339; CHECK-RV64-NEXT:    vsll.vv v8, v8, v10
1340; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
1341; CHECK-RV64-NEXT:    ret
1342;
1343; CHECK-ZVKB-LABEL: vror_vx_nxv4i32:
1344; CHECK-ZVKB:       # %bb.0:
1345; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
1346; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1347; CHECK-ZVKB-NEXT:    ret
1348  %b.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
1349  %b.splat = shufflevector <vscale x 4 x i32> %b.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
1350  %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b.splat)
1351  ret <vscale x 4 x i32> %x
1352}
1353
1354define <vscale x 4 x i32> @vror_vi_nxv4i32(<vscale x 4 x i32> %a) {
1355; CHECK-LABEL: vror_vi_nxv4i32:
1356; CHECK:       # %bb.0:
1357; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1358; CHECK-NEXT:    vsll.vi v10, v8, 31
1359; CHECK-NEXT:    vsrl.vi v8, v8, 1
1360; CHECK-NEXT:    vor.vv v8, v8, v10
1361; CHECK-NEXT:    ret
1362;
1363; CHECK-ZVKB-LABEL: vror_vi_nxv4i32:
1364; CHECK-ZVKB:       # %bb.0:
1365; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1366; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1367; CHECK-ZVKB-NEXT:    ret
1368  %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat (i32 1))
1369  ret <vscale x 4 x i32> %x
1370}
1371
1372define <vscale x 4 x i32> @vror_vi_rotl_nxv4i32(<vscale x 4 x i32> %a) {
1373; CHECK-LABEL: vror_vi_rotl_nxv4i32:
1374; CHECK:       # %bb.0:
1375; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1376; CHECK-NEXT:    vsrl.vi v10, v8, 31
1377; CHECK-NEXT:    vadd.vv v8, v8, v8
1378; CHECK-NEXT:    vor.vv v8, v8, v10
1379; CHECK-NEXT:    ret
1380;
1381; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i32:
1382; CHECK-ZVKB:       # %bb.0:
1383; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1384; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1385; CHECK-ZVKB-NEXT:    ret
1386  %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat (i32 1))
1387  ret <vscale x 4 x i32> %x
1388}
1389
1390declare <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>)
1391declare <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>)
1392
1393define <vscale x 8 x i32> @vror_vv_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
1394; CHECK-LABEL: vror_vv_nxv8i32:
1395; CHECK:       # %bb.0:
1396; CHECK-NEXT:    li a0, 31
1397; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1398; CHECK-NEXT:    vrsub.vi v16, v12, 0
1399; CHECK-NEXT:    vand.vx v12, v12, a0
1400; CHECK-NEXT:    vand.vx v16, v16, a0
1401; CHECK-NEXT:    vsrl.vv v12, v8, v12
1402; CHECK-NEXT:    vsll.vv v8, v8, v16
1403; CHECK-NEXT:    vor.vv v8, v12, v8
1404; CHECK-NEXT:    ret
1405;
1406; CHECK-ZVKB-LABEL: vror_vv_nxv8i32:
1407; CHECK-ZVKB:       # %bb.0:
1408; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1409; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
1410; CHECK-ZVKB-NEXT:    ret
1411  %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
1412  ret <vscale x 8 x i32> %x
1413}
1414
1415define <vscale x 8 x i32> @vror_vx_nxv8i32(<vscale x 8 x i32> %a, i32 %b) {
1416; CHECK-RV32-LABEL: vror_vx_nxv8i32:
1417; CHECK-RV32:       # %bb.0:
1418; CHECK-RV32-NEXT:    andi a1, a0, 31
1419; CHECK-RV32-NEXT:    neg a0, a0
1420; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m4, ta, ma
1421; CHECK-RV32-NEXT:    vsrl.vx v12, v8, a1
1422; CHECK-RV32-NEXT:    andi a0, a0, 31
1423; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
1424; CHECK-RV32-NEXT:    vor.vv v8, v12, v8
1425; CHECK-RV32-NEXT:    ret
1426;
1427; CHECK-RV64-LABEL: vror_vx_nxv8i32:
1428; CHECK-RV64:       # %bb.0:
1429; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1430; CHECK-RV64-NEXT:    vmv.v.x v12, a0
1431; CHECK-RV64-NEXT:    li a0, 31
1432; CHECK-RV64-NEXT:    vand.vx v16, v12, a0
1433; CHECK-RV64-NEXT:    vrsub.vi v12, v12, 0
1434; CHECK-RV64-NEXT:    vsrl.vv v16, v8, v16
1435; CHECK-RV64-NEXT:    vand.vx v12, v12, a0
1436; CHECK-RV64-NEXT:    vsll.vv v8, v8, v12
1437; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
1438; CHECK-RV64-NEXT:    ret
1439;
1440; CHECK-ZVKB-LABEL: vror_vx_nxv8i32:
1441; CHECK-ZVKB:       # %bb.0:
1442; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1443; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1444; CHECK-ZVKB-NEXT:    ret
1445  %b.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1446  %b.splat = shufflevector <vscale x 8 x i32> %b.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1447  %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b.splat)
1448  ret <vscale x 8 x i32> %x
1449}
1450
1451define <vscale x 8 x i32> @vror_vi_nxv8i32(<vscale x 8 x i32> %a) {
1452; CHECK-LABEL: vror_vi_nxv8i32:
1453; CHECK:       # %bb.0:
1454; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1455; CHECK-NEXT:    vsll.vi v12, v8, 31
1456; CHECK-NEXT:    vsrl.vi v8, v8, 1
1457; CHECK-NEXT:    vor.vv v8, v8, v12
1458; CHECK-NEXT:    ret
1459;
1460; CHECK-ZVKB-LABEL: vror_vi_nxv8i32:
1461; CHECK-ZVKB:       # %bb.0:
1462; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1463; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1464; CHECK-ZVKB-NEXT:    ret
1465  %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> splat (i32 1))
1466  ret <vscale x 8 x i32> %x
1467}
1468
1469define <vscale x 8 x i32> @vror_vi_rotl_nxv8i32(<vscale x 8 x i32> %a) {
1470; CHECK-LABEL: vror_vi_rotl_nxv8i32:
1471; CHECK:       # %bb.0:
1472; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1473; CHECK-NEXT:    vsrl.vi v12, v8, 31
1474; CHECK-NEXT:    vadd.vv v8, v8, v8
1475; CHECK-NEXT:    vor.vv v8, v8, v12
1476; CHECK-NEXT:    ret
1477;
1478; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i32:
1479; CHECK-ZVKB:       # %bb.0:
1480; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1481; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1482; CHECK-ZVKB-NEXT:    ret
1483  %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> splat (i32 1))
1484  ret <vscale x 8 x i32> %x
1485}
1486
1487declare <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>)
1488declare <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>)
1489
1490define <vscale x 16 x i32> @vror_vv_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
1491; CHECK-LABEL: vror_vv_nxv16i32:
1492; CHECK:       # %bb.0:
1493; CHECK-NEXT:    li a0, 31
1494; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
1495; CHECK-NEXT:    vrsub.vi v24, v16, 0
1496; CHECK-NEXT:    vand.vx v16, v16, a0
1497; CHECK-NEXT:    vand.vx v24, v24, a0
1498; CHECK-NEXT:    vsrl.vv v16, v8, v16
1499; CHECK-NEXT:    vsll.vv v8, v8, v24
1500; CHECK-NEXT:    vor.vv v8, v16, v8
1501; CHECK-NEXT:    ret
1502;
1503; CHECK-ZVKB-LABEL: vror_vv_nxv16i32:
1504; CHECK-ZVKB:       # %bb.0:
1505; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1506; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v16
1507; CHECK-ZVKB-NEXT:    ret
1508  %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
1509  ret <vscale x 16 x i32> %x
1510}
1511
1512define <vscale x 16 x i32> @vror_vx_nxv16i32(<vscale x 16 x i32> %a, i32 %b) {
1513; CHECK-RV32-LABEL: vror_vx_nxv16i32:
1514; CHECK-RV32:       # %bb.0:
1515; CHECK-RV32-NEXT:    andi a1, a0, 31
1516; CHECK-RV32-NEXT:    neg a0, a0
1517; CHECK-RV32-NEXT:    vsetvli a2, zero, e32, m8, ta, ma
1518; CHECK-RV32-NEXT:    vsrl.vx v16, v8, a1
1519; CHECK-RV32-NEXT:    andi a0, a0, 31
1520; CHECK-RV32-NEXT:    vsll.vx v8, v8, a0
1521; CHECK-RV32-NEXT:    vor.vv v8, v16, v8
1522; CHECK-RV32-NEXT:    ret
1523;
1524; CHECK-RV64-LABEL: vror_vx_nxv16i32:
1525; CHECK-RV64:       # %bb.0:
1526; CHECK-RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
1527; CHECK-RV64-NEXT:    vmv.v.x v16, a0
1528; CHECK-RV64-NEXT:    li a0, 31
1529; CHECK-RV64-NEXT:    vand.vx v24, v16, a0
1530; CHECK-RV64-NEXT:    vrsub.vi v16, v16, 0
1531; CHECK-RV64-NEXT:    vsrl.vv v24, v8, v24
1532; CHECK-RV64-NEXT:    vand.vx v16, v16, a0
1533; CHECK-RV64-NEXT:    vsll.vv v8, v8, v16
1534; CHECK-RV64-NEXT:    vor.vv v8, v24, v8
1535; CHECK-RV64-NEXT:    ret
1536;
1537; CHECK-ZVKB-LABEL: vror_vx_nxv16i32:
1538; CHECK-ZVKB:       # %bb.0:
1539; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
1540; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1541; CHECK-ZVKB-NEXT:    ret
1542  %b.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
1543  %b.splat = shufflevector <vscale x 16 x i32> %b.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
1544  %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b.splat)
1545  ret <vscale x 16 x i32> %x
1546}
1547
1548define <vscale x 16 x i32> @vror_vi_nxv16i32(<vscale x 16 x i32> %a) {
1549; CHECK-LABEL: vror_vi_nxv16i32:
1550; CHECK:       # %bb.0:
1551; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1552; CHECK-NEXT:    vsll.vi v16, v8, 31
1553; CHECK-NEXT:    vsrl.vi v8, v8, 1
1554; CHECK-NEXT:    vor.vv v8, v8, v16
1555; CHECK-NEXT:    ret
1556;
1557; CHECK-ZVKB-LABEL: vror_vi_nxv16i32:
1558; CHECK-ZVKB:       # %bb.0:
1559; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1560; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1561; CHECK-ZVKB-NEXT:    ret
1562  %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> splat (i32 1))
1563  ret <vscale x 16 x i32> %x
1564}
1565
1566define <vscale x 16 x i32> @vror_vi_rotl_nxv16i32(<vscale x 16 x i32> %a) {
1567; CHECK-LABEL: vror_vi_rotl_nxv16i32:
1568; CHECK:       # %bb.0:
1569; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1570; CHECK-NEXT:    vsrl.vi v16, v8, 31
1571; CHECK-NEXT:    vadd.vv v8, v8, v8
1572; CHECK-NEXT:    vor.vv v8, v8, v16
1573; CHECK-NEXT:    ret
1574;
1575; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i32:
1576; CHECK-ZVKB:       # %bb.0:
1577; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1578; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1579; CHECK-ZVKB-NEXT:    ret
1580  %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> splat (i32 1))
1581  ret <vscale x 16 x i32> %x
1582}
1583
1584declare <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>)
1585declare <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>)
1586
1587define <vscale x 1 x i64> @vror_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {
1588; CHECK-LABEL: vror_vv_nxv1i64:
1589; CHECK:       # %bb.0:
1590; CHECK-NEXT:    li a0, 63
1591; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1592; CHECK-NEXT:    vrsub.vi v10, v9, 0
1593; CHECK-NEXT:    vand.vx v9, v9, a0
1594; CHECK-NEXT:    vand.vx v10, v10, a0
1595; CHECK-NEXT:    vsrl.vv v9, v8, v9
1596; CHECK-NEXT:    vsll.vv v8, v8, v10
1597; CHECK-NEXT:    vor.vv v8, v9, v8
1598; CHECK-NEXT:    ret
1599;
1600; CHECK-ZVKB-LABEL: vror_vv_nxv1i64:
1601; CHECK-ZVKB:       # %bb.0:
1602; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
1603; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1604; CHECK-ZVKB-NEXT:    ret
1605  %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b)
1606  ret <vscale x 1 x i64> %x
1607}
1608
1609define <vscale x 1 x i64> @vror_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
1610; CHECK-RV32-LABEL: vror_vx_nxv1i64:
1611; CHECK-RV32:       # %bb.0:
1612; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1613; CHECK-RV32-NEXT:    vmv.v.x v9, a0
1614; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
1615; CHECK-RV32-NEXT:    vmv.v.i v10, 0
1616; CHECK-RV32-NEXT:    vwsub.vx v11, v10, a0
1617; CHECK-RV32-NEXT:    li a0, 63
1618; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
1619; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
1620; CHECK-RV32-NEXT:    vand.vx v10, v11, a0
1621; CHECK-RV32-NEXT:    vsll.vv v10, v8, v10
1622; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v9
1623; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
1624; CHECK-RV32-NEXT:    ret
1625;
1626; CHECK-RV64-LABEL: vror_vx_nxv1i64:
1627; CHECK-RV64:       # %bb.0:
1628; CHECK-RV64-NEXT:    andi a1, a0, 63
1629; CHECK-RV64-NEXT:    negw a0, a0
1630; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
1631; CHECK-RV64-NEXT:    vsrl.vx v9, v8, a1
1632; CHECK-RV64-NEXT:    andi a0, a0, 63
1633; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
1634; CHECK-RV64-NEXT:    vor.vv v8, v9, v8
1635; CHECK-RV64-NEXT:    ret
1636;
1637; CHECK-ZVKB-LABEL: vror_vx_nxv1i64:
1638; CHECK-ZVKB:       # %bb.0:
1639; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1640; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1641; CHECK-ZVKB-NEXT:    ret
1642  %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
1643  %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
1644  %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
1645  ret <vscale x 1 x i64> %x
1646}
1647
1648define <vscale x 1 x i64> @vror_vi_nxv1i64(<vscale x 1 x i64> %a) {
1649; CHECK-LABEL: vror_vi_nxv1i64:
1650; CHECK:       # %bb.0:
1651; CHECK-NEXT:    li a0, 63
1652; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1653; CHECK-NEXT:    vsll.vx v9, v8, a0
1654; CHECK-NEXT:    vsrl.vi v8, v8, 1
1655; CHECK-NEXT:    vor.vv v8, v8, v9
1656; CHECK-NEXT:    ret
1657;
1658; CHECK-ZVKB-LABEL: vror_vi_nxv1i64:
1659; CHECK-ZVKB:       # %bb.0:
1660; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
1661; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1662; CHECK-ZVKB-NEXT:    ret
1663  %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> splat (i64 1))
1664  ret <vscale x 1 x i64> %x
1665}
1666
1667define <vscale x 1 x i64> @vror_vi_rotl_nxv1i64(<vscale x 1 x i64> %a) {
1668; CHECK-LABEL: vror_vi_rotl_nxv1i64:
1669; CHECK:       # %bb.0:
1670; CHECK-NEXT:    li a0, 63
1671; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1672; CHECK-NEXT:    vsrl.vx v9, v8, a0
1673; CHECK-NEXT:    vadd.vv v8, v8, v8
1674; CHECK-NEXT:    vor.vv v8, v8, v9
1675; CHECK-NEXT:    ret
1676;
1677; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i64:
1678; CHECK-ZVKB:       # %bb.0:
1679; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
1680; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1681; CHECK-ZVKB-NEXT:    ret
1682  %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> splat (i64 1))
1683  ret <vscale x 1 x i64> %x
1684}
1685
1686declare <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1687declare <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1688
1689define <vscale x 2 x i64> @vror_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
1690; CHECK-LABEL: vror_vv_nxv2i64:
1691; CHECK:       # %bb.0:
1692; CHECK-NEXT:    li a0, 63
1693; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1694; CHECK-NEXT:    vrsub.vi v12, v10, 0
1695; CHECK-NEXT:    vand.vx v10, v10, a0
1696; CHECK-NEXT:    vand.vx v12, v12, a0
1697; CHECK-NEXT:    vsrl.vv v10, v8, v10
1698; CHECK-NEXT:    vsll.vv v8, v8, v12
1699; CHECK-NEXT:    vor.vv v8, v10, v8
1700; CHECK-NEXT:    ret
1701;
1702; CHECK-ZVKB-LABEL: vror_vv_nxv2i64:
1703; CHECK-ZVKB:       # %bb.0:
1704; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1705; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
1706; CHECK-ZVKB-NEXT:    ret
1707  %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
1708  ret <vscale x 2 x i64> %x
1709}
1710
1711define <vscale x 2 x i64> @vror_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
1712; CHECK-RV32-LABEL: vror_vx_nxv2i64:
1713; CHECK-RV32:       # %bb.0:
1714; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1715; CHECK-RV32-NEXT:    vmv.v.x v10, a0
1716; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1717; CHECK-RV32-NEXT:    vmv.v.i v12, 0
1718; CHECK-RV32-NEXT:    vwsub.vx v14, v12, a0
1719; CHECK-RV32-NEXT:    li a0, 63
1720; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1721; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
1722; CHECK-RV32-NEXT:    vand.vx v12, v14, a0
1723; CHECK-RV32-NEXT:    vsll.vv v12, v8, v12
1724; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
1725; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
1726; CHECK-RV32-NEXT:    ret
1727;
1728; CHECK-RV64-LABEL: vror_vx_nxv2i64:
1729; CHECK-RV64:       # %bb.0:
1730; CHECK-RV64-NEXT:    andi a1, a0, 63
1731; CHECK-RV64-NEXT:    negw a0, a0
1732; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m2, ta, ma
1733; CHECK-RV64-NEXT:    vsrl.vx v10, v8, a1
1734; CHECK-RV64-NEXT:    andi a0, a0, 63
1735; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
1736; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
1737; CHECK-RV64-NEXT:    ret
1738;
1739; CHECK-ZVKB-LABEL: vror_vx_nxv2i64:
1740; CHECK-ZVKB:       # %bb.0:
1741; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1742; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1743; CHECK-ZVKB-NEXT:    ret
1744  %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
1745  %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1746  %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
1747  ret <vscale x 2 x i64> %x
1748}
1749
1750define <vscale x 2 x i64> @vror_vi_nxv2i64(<vscale x 2 x i64> %a) {
1751; CHECK-LABEL: vror_vi_nxv2i64:
1752; CHECK:       # %bb.0:
1753; CHECK-NEXT:    li a0, 63
1754; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1755; CHECK-NEXT:    vsll.vx v10, v8, a0
1756; CHECK-NEXT:    vsrl.vi v8, v8, 1
1757; CHECK-NEXT:    vor.vv v8, v8, v10
1758; CHECK-NEXT:    ret
1759;
1760; CHECK-ZVKB-LABEL: vror_vi_nxv2i64:
1761; CHECK-ZVKB:       # %bb.0:
1762; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1763; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1764; CHECK-ZVKB-NEXT:    ret
1765  %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat (i64 1))
1766  ret <vscale x 2 x i64> %x
1767}
1768
1769define <vscale x 2 x i64> @vror_vi_rotl_nxv2i64(<vscale x 2 x i64> %a) {
1770; CHECK-LABEL: vror_vi_rotl_nxv2i64:
1771; CHECK:       # %bb.0:
1772; CHECK-NEXT:    li a0, 63
1773; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1774; CHECK-NEXT:    vsrl.vx v10, v8, a0
1775; CHECK-NEXT:    vadd.vv v8, v8, v8
1776; CHECK-NEXT:    vor.vv v8, v8, v10
1777; CHECK-NEXT:    ret
1778;
1779; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i64:
1780; CHECK-ZVKB:       # %bb.0:
1781; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1782; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1783; CHECK-ZVKB-NEXT:    ret
1784  %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat (i64 1))
1785  ret <vscale x 2 x i64> %x
1786}
1787
1788declare <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)
1789declare <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)
1790
1791define <vscale x 4 x i64> @vror_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
1792; CHECK-LABEL: vror_vv_nxv4i64:
1793; CHECK:       # %bb.0:
1794; CHECK-NEXT:    li a0, 63
1795; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1796; CHECK-NEXT:    vrsub.vi v16, v12, 0
1797; CHECK-NEXT:    vand.vx v12, v12, a0
1798; CHECK-NEXT:    vand.vx v16, v16, a0
1799; CHECK-NEXT:    vsrl.vv v12, v8, v12
1800; CHECK-NEXT:    vsll.vv v8, v8, v16
1801; CHECK-NEXT:    vor.vv v8, v12, v8
1802; CHECK-NEXT:    ret
1803;
1804; CHECK-ZVKB-LABEL: vror_vv_nxv4i64:
1805; CHECK-ZVKB:       # %bb.0:
1806; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1807; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
1808; CHECK-ZVKB-NEXT:    ret
1809  %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
1810  ret <vscale x 4 x i64> %x
1811}
1812
1813define <vscale x 4 x i64> @vror_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
1814; CHECK-RV32-LABEL: vror_vx_nxv4i64:
1815; CHECK-RV32:       # %bb.0:
1816; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1817; CHECK-RV32-NEXT:    vmv.v.x v12, a0
1818; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1819; CHECK-RV32-NEXT:    vmv.v.i v16, 0
1820; CHECK-RV32-NEXT:    vwsub.vx v20, v16, a0
1821; CHECK-RV32-NEXT:    li a0, 63
1822; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
1823; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
1824; CHECK-RV32-NEXT:    vand.vx v16, v20, a0
1825; CHECK-RV32-NEXT:    vsll.vv v16, v8, v16
1826; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v12
1827; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
1828; CHECK-RV32-NEXT:    ret
1829;
1830; CHECK-RV64-LABEL: vror_vx_nxv4i64:
1831; CHECK-RV64:       # %bb.0:
1832; CHECK-RV64-NEXT:    andi a1, a0, 63
1833; CHECK-RV64-NEXT:    negw a0, a0
1834; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m4, ta, ma
1835; CHECK-RV64-NEXT:    vsrl.vx v12, v8, a1
1836; CHECK-RV64-NEXT:    andi a0, a0, 63
1837; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
1838; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
1839; CHECK-RV64-NEXT:    ret
1840;
1841; CHECK-ZVKB-LABEL: vror_vx_nxv4i64:
1842; CHECK-ZVKB:       # %bb.0:
1843; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1844; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1845; CHECK-ZVKB-NEXT:    ret
1846  %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1847  %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1848  %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
1849  ret <vscale x 4 x i64> %x
1850}
1851
1852define <vscale x 4 x i64> @vror_vi_nxv4i64(<vscale x 4 x i64> %a) {
1853; CHECK-LABEL: vror_vi_nxv4i64:
1854; CHECK:       # %bb.0:
1855; CHECK-NEXT:    li a0, 63
1856; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1857; CHECK-NEXT:    vsll.vx v12, v8, a0
1858; CHECK-NEXT:    vsrl.vi v8, v8, 1
1859; CHECK-NEXT:    vor.vv v8, v8, v12
1860; CHECK-NEXT:    ret
1861;
1862; CHECK-ZVKB-LABEL: vror_vi_nxv4i64:
1863; CHECK-ZVKB:       # %bb.0:
1864; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1865; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1866; CHECK-ZVKB-NEXT:    ret
1867  %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> splat (i64 1))
1868  ret <vscale x 4 x i64> %x
1869}
1870
1871define <vscale x 4 x i64> @vror_vi_rotl_nxv4i64(<vscale x 4 x i64> %a) {
1872; CHECK-LABEL: vror_vi_rotl_nxv4i64:
1873; CHECK:       # %bb.0:
1874; CHECK-NEXT:    li a0, 63
1875; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1876; CHECK-NEXT:    vsrl.vx v12, v8, a0
1877; CHECK-NEXT:    vadd.vv v8, v8, v8
1878; CHECK-NEXT:    vor.vv v8, v8, v12
1879; CHECK-NEXT:    ret
1880;
1881; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i64:
1882; CHECK-ZVKB:       # %bb.0:
1883; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1884; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1885; CHECK-ZVKB-NEXT:    ret
1886  %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> splat (i64 1))
1887  ret <vscale x 4 x i64> %x
1888}
1889
1890declare <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>)
1891declare <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>)
1892
1893define <vscale x 8 x i64> @vror_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
1894; CHECK-LABEL: vror_vv_nxv8i64:
1895; CHECK:       # %bb.0:
1896; CHECK-NEXT:    li a0, 63
1897; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1898; CHECK-NEXT:    vrsub.vi v24, v16, 0
1899; CHECK-NEXT:    vand.vx v16, v16, a0
1900; CHECK-NEXT:    vand.vx v24, v24, a0
1901; CHECK-NEXT:    vsrl.vv v16, v8, v16
1902; CHECK-NEXT:    vsll.vv v8, v8, v24
1903; CHECK-NEXT:    vor.vv v8, v16, v8
1904; CHECK-NEXT:    ret
1905;
1906; CHECK-ZVKB-LABEL: vror_vv_nxv8i64:
1907; CHECK-ZVKB:       # %bb.0:
1908; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1909; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v16
1910; CHECK-ZVKB-NEXT:    ret
1911  %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
1912  ret <vscale x 8 x i64> %x
1913}
1914
1915define <vscale x 8 x i64> @vror_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
1916; CHECK-RV32-LABEL: vror_vx_nxv8i64:
1917; CHECK-RV32:       # %bb.0:
1918; CHECK-RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1919; CHECK-RV32-NEXT:    vmv.v.x v16, a0
1920; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
1921; CHECK-RV32-NEXT:    vmv.v.i v24, 0
1922; CHECK-RV32-NEXT:    vwsub.vx v0, v24, a0
1923; CHECK-RV32-NEXT:    li a0, 63
1924; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
1925; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
1926; CHECK-RV32-NEXT:    vand.vx v24, v0, a0
1927; CHECK-RV32-NEXT:    vsll.vv v24, v8, v24
1928; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v16
1929; CHECK-RV32-NEXT:    vor.vv v8, v8, v24
1930; CHECK-RV32-NEXT:    ret
1931;
1932; CHECK-RV64-LABEL: vror_vx_nxv8i64:
1933; CHECK-RV64:       # %bb.0:
1934; CHECK-RV64-NEXT:    andi a1, a0, 63
1935; CHECK-RV64-NEXT:    negw a0, a0
1936; CHECK-RV64-NEXT:    vsetvli a2, zero, e64, m8, ta, ma
1937; CHECK-RV64-NEXT:    vsrl.vx v16, v8, a1
1938; CHECK-RV64-NEXT:    andi a0, a0, 63
1939; CHECK-RV64-NEXT:    vsll.vx v8, v8, a0
1940; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
1941; CHECK-RV64-NEXT:    ret
1942;
1943; CHECK-ZVKB-LABEL: vror_vx_nxv8i64:
1944; CHECK-ZVKB:       # %bb.0:
1945; CHECK-ZVKB-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1946; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1947; CHECK-ZVKB-NEXT:    ret
1948  %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1949  %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1950  %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
1951  ret <vscale x 8 x i64> %x
1952}
1953
1954define <vscale x 8 x i64> @vror_vi_nxv8i64(<vscale x 8 x i64> %a) {
1955; CHECK-LABEL: vror_vi_nxv8i64:
1956; CHECK:       # %bb.0:
1957; CHECK-NEXT:    li a0, 63
1958; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1959; CHECK-NEXT:    vsll.vx v16, v8, a0
1960; CHECK-NEXT:    vsrl.vi v8, v8, 1
1961; CHECK-NEXT:    vor.vv v8, v8, v16
1962; CHECK-NEXT:    ret
1963;
1964; CHECK-ZVKB-LABEL: vror_vi_nxv8i64:
1965; CHECK-ZVKB:       # %bb.0:
1966; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1967; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1968; CHECK-ZVKB-NEXT:    ret
1969  %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> splat (i64 1))
1970  ret <vscale x 8 x i64> %x
1971}
1972
1973define <vscale x 8 x i64> @vror_vi_rotl_nxv8i64(<vscale x 8 x i64> %a) {
1974; CHECK-LABEL: vror_vi_rotl_nxv8i64:
1975; CHECK:       # %bb.0:
1976; CHECK-NEXT:    li a0, 63
1977; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1978; CHECK-NEXT:    vsrl.vx v16, v8, a0
1979; CHECK-NEXT:    vadd.vv v8, v8, v8
1980; CHECK-NEXT:    vor.vv v8, v8, v16
1981; CHECK-NEXT:    ret
1982;
1983; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i64:
1984; CHECK-ZVKB:       # %bb.0:
1985; CHECK-ZVKB-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1986; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1987; CHECK-ZVKB-NEXT:    ret
1988  %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> splat (i64 1))
1989  ret <vscale x 8 x i64> %x
1990}
1991