xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vmax_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vmax_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
9; CHECK-NEXT:    vmaxu.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %cmp = icmp ugt <vscale x 1 x i8> %va, %vb
12  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb
13  ret <vscale x 1 x i8> %vc
14}
15
16define <vscale x 1 x i8> @vmax_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
17; CHECK-LABEL: vmax_vx_nxv1i8:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
20; CHECK-NEXT:    vmaxu.vx v8, v8, a0
21; CHECK-NEXT:    ret
22  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
23  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
24  %cmp = icmp ugt <vscale x 1 x i8> %va, %splat
25  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> %splat
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vmax_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
30; CHECK-LABEL: vmax_vi_nxv1i8_0:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    li a0, -3
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
34; CHECK-NEXT:    vmaxu.vx v8, v8, a0
35; CHECK-NEXT:    ret
36  %cmp = icmp ugt <vscale x 1 x i8> %va, splat (i8 -3)
37  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -3)
38  ret <vscale x 1 x i8> %vc
39}
40
41define <vscale x 2 x i8> @vmax_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
42; CHECK-LABEL: vmax_vv_nxv2i8:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
45; CHECK-NEXT:    vmaxu.vv v8, v8, v9
46; CHECK-NEXT:    ret
47  %cmp = icmp ugt <vscale x 2 x i8> %va, %vb
48  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb
49  ret <vscale x 2 x i8> %vc
50}
51
52define <vscale x 2 x i8> @vmax_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
53; CHECK-LABEL: vmax_vx_nxv2i8:
54; CHECK:       # %bb.0:
55; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
56; CHECK-NEXT:    vmaxu.vx v8, v8, a0
57; CHECK-NEXT:    ret
58  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
59  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
60  %cmp = icmp ugt <vscale x 2 x i8> %va, %splat
61  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> %splat
62  ret <vscale x 2 x i8> %vc
63}
64
65define <vscale x 2 x i8> @vmax_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
66; CHECK-LABEL: vmax_vi_nxv2i8_0:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    li a0, -3
69; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
70; CHECK-NEXT:    vmaxu.vx v8, v8, a0
71; CHECK-NEXT:    ret
72  %cmp = icmp ugt <vscale x 2 x i8> %va, splat (i8 -3)
73  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -3)
74  ret <vscale x 2 x i8> %vc
75}
76
77define <vscale x 4 x i8> @vmax_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
78; CHECK-LABEL: vmax_vv_nxv4i8:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
81; CHECK-NEXT:    vmaxu.vv v8, v8, v9
82; CHECK-NEXT:    ret
83  %cmp = icmp ugt <vscale x 4 x i8> %va, %vb
84  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb
85  ret <vscale x 4 x i8> %vc
86}
87
88define <vscale x 4 x i8> @vmax_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
89; CHECK-LABEL: vmax_vx_nxv4i8:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
92; CHECK-NEXT:    vmaxu.vx v8, v8, a0
93; CHECK-NEXT:    ret
94  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
95  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
96  %cmp = icmp ugt <vscale x 4 x i8> %va, %splat
97  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> %splat
98  ret <vscale x 4 x i8> %vc
99}
100
101define <vscale x 4 x i8> @vmax_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
102; CHECK-LABEL: vmax_vi_nxv4i8_0:
103; CHECK:       # %bb.0:
104; CHECK-NEXT:    li a0, -3
105; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
106; CHECK-NEXT:    vmaxu.vx v8, v8, a0
107; CHECK-NEXT:    ret
108  %cmp = icmp ugt <vscale x 4 x i8> %va, splat (i8 -3)
109  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -3)
110  ret <vscale x 4 x i8> %vc
111}
112
113define <vscale x 8 x i8> @vmax_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
114; CHECK-LABEL: vmax_vv_nxv8i8:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
117; CHECK-NEXT:    vmaxu.vv v8, v8, v9
118; CHECK-NEXT:    ret
119  %cmp = icmp ugt <vscale x 8 x i8> %va, %vb
120  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb
121  ret <vscale x 8 x i8> %vc
122}
123
124define <vscale x 8 x i8> @vmax_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
125; CHECK-LABEL: vmax_vx_nxv8i8:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
128; CHECK-NEXT:    vmaxu.vx v8, v8, a0
129; CHECK-NEXT:    ret
130  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
131  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
132  %cmp = icmp ugt <vscale x 8 x i8> %va, %splat
133  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> %splat
134  ret <vscale x 8 x i8> %vc
135}
136
137define <vscale x 8 x i8> @vmax_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
138; CHECK-LABEL: vmax_vi_nxv8i8_0:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    li a0, -3
141; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
142; CHECK-NEXT:    vmaxu.vx v8, v8, a0
143; CHECK-NEXT:    ret
144  %cmp = icmp ugt <vscale x 8 x i8> %va, splat (i8 -3)
145  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -3)
146  ret <vscale x 8 x i8> %vc
147}
148
149define <vscale x 16 x i8> @vmax_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
150; CHECK-LABEL: vmax_vv_nxv16i8:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
153; CHECK-NEXT:    vmaxu.vv v8, v8, v10
154; CHECK-NEXT:    ret
155  %cmp = icmp ugt <vscale x 16 x i8> %va, %vb
156  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb
157  ret <vscale x 16 x i8> %vc
158}
159
160define <vscale x 16 x i8> @vmax_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
161; CHECK-LABEL: vmax_vx_nxv16i8:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
164; CHECK-NEXT:    vmaxu.vx v8, v8, a0
165; CHECK-NEXT:    ret
166  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
167  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
168  %cmp = icmp ugt <vscale x 16 x i8> %va, %splat
169  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> %splat
170  ret <vscale x 16 x i8> %vc
171}
172
173define <vscale x 16 x i8> @vmax_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
174; CHECK-LABEL: vmax_vi_nxv16i8_0:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    li a0, -3
177; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
178; CHECK-NEXT:    vmaxu.vx v8, v8, a0
179; CHECK-NEXT:    ret
180  %cmp = icmp ugt <vscale x 16 x i8> %va, splat (i8 -3)
181  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -3)
182  ret <vscale x 16 x i8> %vc
183}
184
185define <vscale x 32 x i8> @vmax_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
186; CHECK-LABEL: vmax_vv_nxv32i8:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
189; CHECK-NEXT:    vmaxu.vv v8, v8, v12
190; CHECK-NEXT:    ret
191  %cmp = icmp ugt <vscale x 32 x i8> %va, %vb
192  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb
193  ret <vscale x 32 x i8> %vc
194}
195
196define <vscale x 32 x i8> @vmax_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
197; CHECK-LABEL: vmax_vx_nxv32i8:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
200; CHECK-NEXT:    vmaxu.vx v8, v8, a0
201; CHECK-NEXT:    ret
202  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
203  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
204  %cmp = icmp ugt <vscale x 32 x i8> %va, %splat
205  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> %splat
206  ret <vscale x 32 x i8> %vc
207}
208
209define <vscale x 32 x i8> @vmax_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
210; CHECK-LABEL: vmax_vi_nxv32i8_0:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    li a0, -3
213; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
214; CHECK-NEXT:    vmaxu.vx v8, v8, a0
215; CHECK-NEXT:    ret
216  %cmp = icmp ugt <vscale x 32 x i8> %va, splat (i8 -3)
217  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -3)
218  ret <vscale x 32 x i8> %vc
219}
220
221define <vscale x 64 x i8> @vmax_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
222; CHECK-LABEL: vmax_vv_nxv64i8:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
225; CHECK-NEXT:    vmaxu.vv v8, v8, v16
226; CHECK-NEXT:    ret
227  %cmp = icmp ugt <vscale x 64 x i8> %va, %vb
228  %vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb
229  ret <vscale x 64 x i8> %vc
230}
231
232define <vscale x 64 x i8> @vmax_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
233; CHECK-LABEL: vmax_vx_nxv64i8:
234; CHECK:       # %bb.0:
235; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
236; CHECK-NEXT:    vmaxu.vx v8, v8, a0
237; CHECK-NEXT:    ret
238  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
239  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
240  %cmp = icmp ugt <vscale x 64 x i8> %va, %splat
241  %vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> %splat
242  ret <vscale x 64 x i8> %vc
243}
244
245define <vscale x 64 x i8> @vmax_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
246; CHECK-LABEL: vmax_vi_nxv64i8_0:
247; CHECK:       # %bb.0:
248; CHECK-NEXT:    li a0, -3
249; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
250; CHECK-NEXT:    vmaxu.vx v8, v8, a0
251; CHECK-NEXT:    ret
252  %cmp = icmp ugt <vscale x 64 x i8> %va, splat (i8 -3)
253  %vc = select <vscale x 64 x i1> %cmp, <vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -3)
254  ret <vscale x 64 x i8> %vc
255}
256
257define <vscale x 1 x i16> @vmax_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
258; CHECK-LABEL: vmax_vv_nxv1i16:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
261; CHECK-NEXT:    vmaxu.vv v8, v8, v9
262; CHECK-NEXT:    ret
263  %cmp = icmp ugt <vscale x 1 x i16> %va, %vb
264  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb
265  ret <vscale x 1 x i16> %vc
266}
267
268define <vscale x 1 x i16> @vmax_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
269; CHECK-LABEL: vmax_vx_nxv1i16:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
272; CHECK-NEXT:    vmaxu.vx v8, v8, a0
273; CHECK-NEXT:    ret
274  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
275  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
276  %cmp = icmp ugt <vscale x 1 x i16> %va, %splat
277  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> %splat
278  ret <vscale x 1 x i16> %vc
279}
280
281define <vscale x 1 x i16> @vmax_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
282; CHECK-LABEL: vmax_vi_nxv1i16_0:
283; CHECK:       # %bb.0:
284; CHECK-NEXT:    li a0, -3
285; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
286; CHECK-NEXT:    vmaxu.vx v8, v8, a0
287; CHECK-NEXT:    ret
288  %cmp = icmp ugt <vscale x 1 x i16> %va, splat (i16 -3)
289  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -3)
290  ret <vscale x 1 x i16> %vc
291}
292
293define <vscale x 2 x i16> @vmax_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
294; CHECK-LABEL: vmax_vv_nxv2i16:
295; CHECK:       # %bb.0:
296; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
297; CHECK-NEXT:    vmaxu.vv v8, v8, v9
298; CHECK-NEXT:    ret
299  %cmp = icmp ugt <vscale x 2 x i16> %va, %vb
300  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb
301  ret <vscale x 2 x i16> %vc
302}
303
304define <vscale x 2 x i16> @vmax_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
305; CHECK-LABEL: vmax_vx_nxv2i16:
306; CHECK:       # %bb.0:
307; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
308; CHECK-NEXT:    vmaxu.vx v8, v8, a0
309; CHECK-NEXT:    ret
310  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
311  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
312  %cmp = icmp ugt <vscale x 2 x i16> %va, %splat
313  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> %splat
314  ret <vscale x 2 x i16> %vc
315}
316
317define <vscale x 2 x i16> @vmax_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
318; CHECK-LABEL: vmax_vi_nxv2i16_0:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    li a0, -3
321; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
322; CHECK-NEXT:    vmaxu.vx v8, v8, a0
323; CHECK-NEXT:    ret
324  %cmp = icmp ugt <vscale x 2 x i16> %va, splat (i16 -3)
325  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -3)
326  ret <vscale x 2 x i16> %vc
327}
328
329define <vscale x 4 x i16> @vmax_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
330; CHECK-LABEL: vmax_vv_nxv4i16:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
333; CHECK-NEXT:    vmaxu.vv v8, v8, v9
334; CHECK-NEXT:    ret
335  %cmp = icmp ugt <vscale x 4 x i16> %va, %vb
336  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb
337  ret <vscale x 4 x i16> %vc
338}
339
340define <vscale x 4 x i16> @vmax_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
341; CHECK-LABEL: vmax_vx_nxv4i16:
342; CHECK:       # %bb.0:
343; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
344; CHECK-NEXT:    vmaxu.vx v8, v8, a0
345; CHECK-NEXT:    ret
346  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
347  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
348  %cmp = icmp ugt <vscale x 4 x i16> %va, %splat
349  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> %splat
350  ret <vscale x 4 x i16> %vc
351}
352
353define <vscale x 4 x i16> @vmax_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
354; CHECK-LABEL: vmax_vi_nxv4i16_0:
355; CHECK:       # %bb.0:
356; CHECK-NEXT:    li a0, -3
357; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
358; CHECK-NEXT:    vmaxu.vx v8, v8, a0
359; CHECK-NEXT:    ret
360  %cmp = icmp ugt <vscale x 4 x i16> %va, splat (i16 -3)
361  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -3)
362  ret <vscale x 4 x i16> %vc
363}
364
365define <vscale x 8 x i16> @vmax_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
366; CHECK-LABEL: vmax_vv_nxv8i16:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
369; CHECK-NEXT:    vmaxu.vv v8, v8, v10
370; CHECK-NEXT:    ret
371  %cmp = icmp ugt <vscale x 8 x i16> %va, %vb
372  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb
373  ret <vscale x 8 x i16> %vc
374}
375
376define <vscale x 8 x i16> @vmax_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
377; CHECK-LABEL: vmax_vx_nxv8i16:
378; CHECK:       # %bb.0:
379; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
380; CHECK-NEXT:    vmaxu.vx v8, v8, a0
381; CHECK-NEXT:    ret
382  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
383  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
384  %cmp = icmp ugt <vscale x 8 x i16> %va, %splat
385  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> %splat
386  ret <vscale x 8 x i16> %vc
387}
388
389define <vscale x 8 x i16> @vmax_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
390; CHECK-LABEL: vmax_vi_nxv8i16_0:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    li a0, -3
393; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
394; CHECK-NEXT:    vmaxu.vx v8, v8, a0
395; CHECK-NEXT:    ret
396  %cmp = icmp ugt <vscale x 8 x i16> %va, splat (i16 -3)
397  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -3)
398  ret <vscale x 8 x i16> %vc
399}
400
401define <vscale x 16 x i16> @vmax_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
402; CHECK-LABEL: vmax_vv_nxv16i16:
403; CHECK:       # %bb.0:
404; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
405; CHECK-NEXT:    vmaxu.vv v8, v8, v12
406; CHECK-NEXT:    ret
407  %cmp = icmp ugt <vscale x 16 x i16> %va, %vb
408  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb
409  ret <vscale x 16 x i16> %vc
410}
411
412define <vscale x 16 x i16> @vmax_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
413; CHECK-LABEL: vmax_vx_nxv16i16:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
416; CHECK-NEXT:    vmaxu.vx v8, v8, a0
417; CHECK-NEXT:    ret
418  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
419  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
420  %cmp = icmp ugt <vscale x 16 x i16> %va, %splat
421  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> %splat
422  ret <vscale x 16 x i16> %vc
423}
424
425define <vscale x 16 x i16> @vmax_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
426; CHECK-LABEL: vmax_vi_nxv16i16_0:
427; CHECK:       # %bb.0:
428; CHECK-NEXT:    li a0, -3
429; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
430; CHECK-NEXT:    vmaxu.vx v8, v8, a0
431; CHECK-NEXT:    ret
432  %cmp = icmp ugt <vscale x 16 x i16> %va, splat (i16 -3)
433  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -3)
434  ret <vscale x 16 x i16> %vc
435}
436
437define <vscale x 32 x i16> @vmax_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
438; CHECK-LABEL: vmax_vv_nxv32i16:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
441; CHECK-NEXT:    vmaxu.vv v8, v8, v16
442; CHECK-NEXT:    ret
443  %cmp = icmp ugt <vscale x 32 x i16> %va, %vb
444  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb
445  ret <vscale x 32 x i16> %vc
446}
447
448define <vscale x 32 x i16> @vmax_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
449; CHECK-LABEL: vmax_vx_nxv32i16:
450; CHECK:       # %bb.0:
451; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
452; CHECK-NEXT:    vmaxu.vx v8, v8, a0
453; CHECK-NEXT:    ret
454  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
455  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
456  %cmp = icmp ugt <vscale x 32 x i16> %va, %splat
457  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> %splat
458  ret <vscale x 32 x i16> %vc
459}
460
461define <vscale x 32 x i16> @vmax_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
462; CHECK-LABEL: vmax_vi_nxv32i16_0:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    li a0, -3
465; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
466; CHECK-NEXT:    vmaxu.vx v8, v8, a0
467; CHECK-NEXT:    ret
468  %cmp = icmp ugt <vscale x 32 x i16> %va, splat (i16 -3)
469  %vc = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -3)
470  ret <vscale x 32 x i16> %vc
471}
472
473define <vscale x 1 x i32> @vmax_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
474; CHECK-LABEL: vmax_vv_nxv1i32:
475; CHECK:       # %bb.0:
476; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
477; CHECK-NEXT:    vmaxu.vv v8, v8, v9
478; CHECK-NEXT:    ret
479  %cmp = icmp ugt <vscale x 1 x i32> %va, %vb
480  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb
481  ret <vscale x 1 x i32> %vc
482}
483
484define <vscale x 1 x i32> @vmax_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
485; CHECK-LABEL: vmax_vx_nxv1i32:
486; CHECK:       # %bb.0:
487; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
488; CHECK-NEXT:    vmaxu.vx v8, v8, a0
489; CHECK-NEXT:    ret
490  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
491  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
492  %cmp = icmp ugt <vscale x 1 x i32> %va, %splat
493  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> %splat
494  ret <vscale x 1 x i32> %vc
495}
496
497define <vscale x 1 x i32> @vmax_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
498; CHECK-LABEL: vmax_vi_nxv1i32_0:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    li a0, -3
501; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
502; CHECK-NEXT:    vmaxu.vx v8, v8, a0
503; CHECK-NEXT:    ret
504  %cmp = icmp ugt <vscale x 1 x i32> %va, splat (i32 -3)
505  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -3)
506  ret <vscale x 1 x i32> %vc
507}
508
509define <vscale x 2 x i32> @vmax_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
510; CHECK-LABEL: vmax_vv_nxv2i32:
511; CHECK:       # %bb.0:
512; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
513; CHECK-NEXT:    vmaxu.vv v8, v8, v9
514; CHECK-NEXT:    ret
515  %cmp = icmp ugt <vscale x 2 x i32> %va, %vb
516  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb
517  ret <vscale x 2 x i32> %vc
518}
519
520define <vscale x 2 x i32> @vmax_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
521; CHECK-LABEL: vmax_vx_nxv2i32:
522; CHECK:       # %bb.0:
523; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
524; CHECK-NEXT:    vmaxu.vx v8, v8, a0
525; CHECK-NEXT:    ret
526  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
527  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
528  %cmp = icmp ugt <vscale x 2 x i32> %va, %splat
529  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> %splat
530  ret <vscale x 2 x i32> %vc
531}
532
533define <vscale x 2 x i32> @vmax_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
534; CHECK-LABEL: vmax_vi_nxv2i32_0:
535; CHECK:       # %bb.0:
536; CHECK-NEXT:    li a0, -3
537; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
538; CHECK-NEXT:    vmaxu.vx v8, v8, a0
539; CHECK-NEXT:    ret
540  %cmp = icmp ugt <vscale x 2 x i32> %va, splat (i32 -3)
541  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -3)
542  ret <vscale x 2 x i32> %vc
543}
544
545define <vscale x 4 x i32> @vmax_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
546; CHECK-LABEL: vmax_vv_nxv4i32:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
549; CHECK-NEXT:    vmaxu.vv v8, v8, v10
550; CHECK-NEXT:    ret
551  %cmp = icmp ugt <vscale x 4 x i32> %va, %vb
552  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb
553  ret <vscale x 4 x i32> %vc
554}
555
556define <vscale x 4 x i32> @vmax_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
557; CHECK-LABEL: vmax_vx_nxv4i32:
558; CHECK:       # %bb.0:
559; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
560; CHECK-NEXT:    vmaxu.vx v8, v8, a0
561; CHECK-NEXT:    ret
562  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
563  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
564  %cmp = icmp ugt <vscale x 4 x i32> %va, %splat
565  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> %splat
566  ret <vscale x 4 x i32> %vc
567}
568
569define <vscale x 4 x i32> @vmax_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
570; CHECK-LABEL: vmax_vi_nxv4i32_0:
571; CHECK:       # %bb.0:
572; CHECK-NEXT:    li a0, -3
573; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
574; CHECK-NEXT:    vmaxu.vx v8, v8, a0
575; CHECK-NEXT:    ret
576  %cmp = icmp ugt <vscale x 4 x i32> %va, splat (i32 -3)
577  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -3)
578  ret <vscale x 4 x i32> %vc
579}
580
581define <vscale x 8 x i32> @vmax_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
582; CHECK-LABEL: vmax_vv_nxv8i32:
583; CHECK:       # %bb.0:
584; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
585; CHECK-NEXT:    vmaxu.vv v8, v8, v12
586; CHECK-NEXT:    ret
587  %cmp = icmp ugt <vscale x 8 x i32> %va, %vb
588  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb
589  ret <vscale x 8 x i32> %vc
590}
591
592define <vscale x 8 x i32> @vmax_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
593; CHECK-LABEL: vmax_vx_nxv8i32:
594; CHECK:       # %bb.0:
595; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
596; CHECK-NEXT:    vmaxu.vx v8, v8, a0
597; CHECK-NEXT:    ret
598  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
599  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
600  %cmp = icmp ugt <vscale x 8 x i32> %va, %splat
601  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %splat
602  ret <vscale x 8 x i32> %vc
603}
604
605define <vscale x 8 x i32> @vmax_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
606; CHECK-LABEL: vmax_vi_nxv8i32_0:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    li a0, -3
609; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
610; CHECK-NEXT:    vmaxu.vx v8, v8, a0
611; CHECK-NEXT:    ret
612  %cmp = icmp ugt <vscale x 8 x i32> %va, splat (i32 -3)
613  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -3)
614  ret <vscale x 8 x i32> %vc
615}
616
617define <vscale x 16 x i32> @vmax_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
618; CHECK-LABEL: vmax_vv_nxv16i32:
619; CHECK:       # %bb.0:
620; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
621; CHECK-NEXT:    vmaxu.vv v8, v8, v16
622; CHECK-NEXT:    ret
623  %cmp = icmp ugt <vscale x 16 x i32> %va, %vb
624  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb
625  ret <vscale x 16 x i32> %vc
626}
627
628define <vscale x 16 x i32> @vmax_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
629; CHECK-LABEL: vmax_vx_nxv16i32:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
632; CHECK-NEXT:    vmaxu.vx v8, v8, a0
633; CHECK-NEXT:    ret
634  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
635  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
636  %cmp = icmp ugt <vscale x 16 x i32> %va, %splat
637  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> %splat
638  ret <vscale x 16 x i32> %vc
639}
640
641define <vscale x 16 x i32> @vmax_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
642; CHECK-LABEL: vmax_vi_nxv16i32_0:
643; CHECK:       # %bb.0:
644; CHECK-NEXT:    li a0, -3
645; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
646; CHECK-NEXT:    vmaxu.vx v8, v8, a0
647; CHECK-NEXT:    ret
648  %cmp = icmp ugt <vscale x 16 x i32> %va, splat (i32 -3)
649  %vc = select <vscale x 16 x i1> %cmp, <vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -3)
650  ret <vscale x 16 x i32> %vc
651}
652
653define <vscale x 1 x i64> @vmax_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
654; CHECK-LABEL: vmax_vv_nxv1i64:
655; CHECK:       # %bb.0:
656; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
657; CHECK-NEXT:    vmaxu.vv v8, v8, v9
658; CHECK-NEXT:    ret
659  %cmp = icmp ugt <vscale x 1 x i64> %va, %vb
660  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb
661  ret <vscale x 1 x i64> %vc
662}
663
664define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
665; RV32-LABEL: vmax_vx_nxv1i64:
666; RV32:       # %bb.0:
667; RV32-NEXT:    addi sp, sp, -16
668; RV32-NEXT:    .cfi_def_cfa_offset 16
669; RV32-NEXT:    sw a0, 8(sp)
670; RV32-NEXT:    sw a1, 12(sp)
671; RV32-NEXT:    addi a0, sp, 8
672; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
673; RV32-NEXT:    vlse64.v v9, (a0), zero
674; RV32-NEXT:    vmaxu.vv v8, v8, v9
675; RV32-NEXT:    addi sp, sp, 16
676; RV32-NEXT:    .cfi_def_cfa_offset 0
677; RV32-NEXT:    ret
678;
679; RV64-LABEL: vmax_vx_nxv1i64:
680; RV64:       # %bb.0:
681; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
682; RV64-NEXT:    vmaxu.vx v8, v8, a0
683; RV64-NEXT:    ret
684  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
685  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
686  %cmp = icmp ugt <vscale x 1 x i64> %va, %splat
687  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> %splat
688  ret <vscale x 1 x i64> %vc
689}
690
691define <vscale x 1 x i64> @vmax_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
692; CHECK-LABEL: vmax_vi_nxv1i64_0:
693; CHECK:       # %bb.0:
694; CHECK-NEXT:    li a0, -3
695; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
696; CHECK-NEXT:    vmaxu.vx v8, v8, a0
697; CHECK-NEXT:    ret
698  %cmp = icmp ugt <vscale x 1 x i64> %va, splat (i64 -3)
699  %vc = select <vscale x 1 x i1> %cmp, <vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -3)
700  ret <vscale x 1 x i64> %vc
701}
702
703define <vscale x 2 x i64> @vmax_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
704; CHECK-LABEL: vmax_vv_nxv2i64:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
707; CHECK-NEXT:    vmaxu.vv v8, v8, v10
708; CHECK-NEXT:    ret
709  %cmp = icmp ugt <vscale x 2 x i64> %va, %vb
710  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb
711  ret <vscale x 2 x i64> %vc
712}
713
714define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
715; RV32-LABEL: vmax_vx_nxv2i64:
716; RV32:       # %bb.0:
717; RV32-NEXT:    addi sp, sp, -16
718; RV32-NEXT:    .cfi_def_cfa_offset 16
719; RV32-NEXT:    sw a0, 8(sp)
720; RV32-NEXT:    sw a1, 12(sp)
721; RV32-NEXT:    addi a0, sp, 8
722; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
723; RV32-NEXT:    vlse64.v v10, (a0), zero
724; RV32-NEXT:    vmaxu.vv v8, v8, v10
725; RV32-NEXT:    addi sp, sp, 16
726; RV32-NEXT:    .cfi_def_cfa_offset 0
727; RV32-NEXT:    ret
728;
729; RV64-LABEL: vmax_vx_nxv2i64:
730; RV64:       # %bb.0:
731; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
732; RV64-NEXT:    vmaxu.vx v8, v8, a0
733; RV64-NEXT:    ret
734  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
735  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
736  %cmp = icmp ugt <vscale x 2 x i64> %va, %splat
737  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> %splat
738  ret <vscale x 2 x i64> %vc
739}
740
741define <vscale x 2 x i64> @vmax_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
742; CHECK-LABEL: vmax_vi_nxv2i64_0:
743; CHECK:       # %bb.0:
744; CHECK-NEXT:    li a0, -3
745; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
746; CHECK-NEXT:    vmaxu.vx v8, v8, a0
747; CHECK-NEXT:    ret
748  %cmp = icmp ugt <vscale x 2 x i64> %va, splat (i64 -3)
749  %vc = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -3)
750  ret <vscale x 2 x i64> %vc
751}
752
753define <vscale x 4 x i64> @vmax_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
754; CHECK-LABEL: vmax_vv_nxv4i64:
755; CHECK:       # %bb.0:
756; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
757; CHECK-NEXT:    vmaxu.vv v8, v8, v12
758; CHECK-NEXT:    ret
759  %cmp = icmp ugt <vscale x 4 x i64> %va, %vb
760  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb
761  ret <vscale x 4 x i64> %vc
762}
763
764define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
765; RV32-LABEL: vmax_vx_nxv4i64:
766; RV32:       # %bb.0:
767; RV32-NEXT:    addi sp, sp, -16
768; RV32-NEXT:    .cfi_def_cfa_offset 16
769; RV32-NEXT:    sw a0, 8(sp)
770; RV32-NEXT:    sw a1, 12(sp)
771; RV32-NEXT:    addi a0, sp, 8
772; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
773; RV32-NEXT:    vlse64.v v12, (a0), zero
774; RV32-NEXT:    vmaxu.vv v8, v8, v12
775; RV32-NEXT:    addi sp, sp, 16
776; RV32-NEXT:    .cfi_def_cfa_offset 0
777; RV32-NEXT:    ret
778;
779; RV64-LABEL: vmax_vx_nxv4i64:
780; RV64:       # %bb.0:
781; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
782; RV64-NEXT:    vmaxu.vx v8, v8, a0
783; RV64-NEXT:    ret
784  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
785  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
786  %cmp = icmp ugt <vscale x 4 x i64> %va, %splat
787  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> %splat
788  ret <vscale x 4 x i64> %vc
789}
790
791define <vscale x 4 x i64> @vmax_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
792; CHECK-LABEL: vmax_vi_nxv4i64_0:
793; CHECK:       # %bb.0:
794; CHECK-NEXT:    li a0, -3
795; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
796; CHECK-NEXT:    vmaxu.vx v8, v8, a0
797; CHECK-NEXT:    ret
798  %cmp = icmp ugt <vscale x 4 x i64> %va, splat (i64 -3)
799  %vc = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -3)
800  ret <vscale x 4 x i64> %vc
801}
802
803define <vscale x 8 x i64> @vmax_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
804; CHECK-LABEL: vmax_vv_nxv8i64:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
807; CHECK-NEXT:    vmaxu.vv v8, v8, v16
808; CHECK-NEXT:    ret
809  %cmp = icmp ugt <vscale x 8 x i64> %va, %vb
810  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb
811  ret <vscale x 8 x i64> %vc
812}
813
814define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
815; RV32-LABEL: vmax_vx_nxv8i64:
816; RV32:       # %bb.0:
817; RV32-NEXT:    addi sp, sp, -16
818; RV32-NEXT:    .cfi_def_cfa_offset 16
819; RV32-NEXT:    sw a0, 8(sp)
820; RV32-NEXT:    sw a1, 12(sp)
821; RV32-NEXT:    addi a0, sp, 8
822; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
823; RV32-NEXT:    vlse64.v v16, (a0), zero
824; RV32-NEXT:    vmaxu.vv v8, v8, v16
825; RV32-NEXT:    addi sp, sp, 16
826; RV32-NEXT:    .cfi_def_cfa_offset 0
827; RV32-NEXT:    ret
828;
829; RV64-LABEL: vmax_vx_nxv8i64:
830; RV64:       # %bb.0:
831; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
832; RV64-NEXT:    vmaxu.vx v8, v8, a0
833; RV64-NEXT:    ret
834  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
835  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
836  %cmp = icmp ugt <vscale x 8 x i64> %va, %splat
837  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
838  ret <vscale x 8 x i64> %vc
839}
840
841define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
842; CHECK-LABEL: vmax_vi_nxv8i64_0:
843; CHECK:       # %bb.0:
844; CHECK-NEXT:    li a0, -3
845; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
846; CHECK-NEXT:    vmaxu.vx v8, v8, a0
847; CHECK-NEXT:    ret
848  %cmp = icmp ugt <vscale x 8 x i64> %va, splat (i64 -3)
849  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -3)
850  ret <vscale x 8 x i64> %vc
851}
852
853define <vscale x 8 x i32> @vmax_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
854; CHECK-LABEL: vmax_vv_mask_nxv8i32:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
857; CHECK-NEXT:    vmv.v.i v16, 0
858; CHECK-NEXT:    vmerge.vvm v12, v16, v12, v0
859; CHECK-NEXT:    vmaxu.vv v8, v8, v12
860; CHECK-NEXT:    ret
861  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
862  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
863  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
864  ret <vscale x 8 x i32> %vc
865}
866
867define <vscale x 8 x i32> @vmax_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
868; CHECK-LABEL: vmax_vx_mask_nxv8i32:
869; CHECK:       # %bb.0:
870; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
871; CHECK-NEXT:    vmv.v.i v12, 0
872; CHECK-NEXT:    vmerge.vxm v12, v12, a0, v0
873; CHECK-NEXT:    vmaxu.vv v8, v8, v12
874; CHECK-NEXT:    ret
875  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
876  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
877  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
878  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
879  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
880  ret <vscale x 8 x i32> %vc
881}
882
883define <vscale x 8 x i32> @vmax_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
884; CHECK-LABEL: vmax_vi_mask_nxv8i32:
885; CHECK:       # %bb.0:
886; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
887; CHECK-NEXT:    vmv.v.i v12, 0
888; CHECK-NEXT:    vmerge.vim v12, v12, -3, v0
889; CHECK-NEXT:    vmaxu.vv v8, v8, v12
890; CHECK-NEXT:    ret
891  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 -3), <vscale x 8 x i32> zeroinitializer
892  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
893  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
894  ret <vscale x 8 x i32> %vc
895}
896