1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ 3; RUN: -verify-machineinstrs | FileCheck %s 4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ 5; RUN: -verify-machineinstrs | FileCheck %s 6 7declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( 8 <vscale x 1 x i1>, 9 <vscale x 1 x i1>, 10 iXLen); 11 12define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind { 13; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1: 14; CHECK: # %bb.0: # %entry 15; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 16; CHECK-NEXT: vmand.mm v0, v0, v8 17; CHECK-NEXT: ret 18entry: 19 %a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1( 20 <vscale x 1 x i1> %0, 21 <vscale x 1 x i1> %1, 22 iXLen %2) 23 24 ret <vscale x 1 x i1> %a 25} 26 27declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( 28 <vscale x 2 x i1>, 29 <vscale x 2 x i1>, 30 iXLen); 31 32define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind { 33; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1: 34; CHECK: # %bb.0: # %entry 35; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 36; CHECK-NEXT: vmand.mm v0, v0, v8 37; CHECK-NEXT: ret 38entry: 39 %a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1( 40 <vscale x 2 x i1> %0, 41 <vscale x 2 x i1> %1, 42 iXLen %2) 43 44 ret <vscale x 2 x i1> %a 45} 46 47declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( 48 <vscale x 4 x i1>, 49 <vscale x 4 x i1>, 50 iXLen); 51 52define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind { 53; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1: 54; CHECK: # %bb.0: # %entry 55; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 56; CHECK-NEXT: vmand.mm v0, v0, v8 57; CHECK-NEXT: ret 58entry: 59 %a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1( 60 <vscale x 4 x i1> %0, 61 <vscale x 4 x i1> %1, 62 iXLen %2) 63 64 ret <vscale x 4 x i1> %a 65} 66 67declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( 68 <vscale x 8 x i1>, 69 <vscale x 8 x i1>, 70 iXLen); 71 72define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind { 73; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 76; CHECK-NEXT: vmand.mm v0, v0, v8 77; CHECK-NEXT: ret 78entry: 79 %a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1( 80 <vscale x 8 x i1> %0, 81 <vscale x 8 x i1> %1, 82 iXLen %2) 83 84 ret <vscale x 8 x i1> %a 85} 86 87declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( 88 <vscale x 16 x i1>, 89 <vscale x 16 x i1>, 90 iXLen); 91 92define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind { 93; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1: 94; CHECK: # %bb.0: # %entry 95; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 96; CHECK-NEXT: vmand.mm v0, v0, v8 97; CHECK-NEXT: ret 98entry: 99 %a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1( 100 <vscale x 16 x i1> %0, 101 <vscale x 16 x i1> %1, 102 iXLen %2) 103 104 ret <vscale x 16 x i1> %a 105} 106 107declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( 108 <vscale x 32 x i1>, 109 <vscale x 32 x i1>, 110 iXLen); 111 112define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind { 113; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1: 114; CHECK: # %bb.0: # %entry 115; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 116; CHECK-NEXT: vmand.mm v0, v0, v8 117; CHECK-NEXT: ret 118entry: 119 %a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1( 120 <vscale x 32 x i1> %0, 121 <vscale x 32 x i1> %1, 122 iXLen %2) 123 124 ret <vscale x 32 x i1> %a 125} 126 127declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( 128 <vscale x 64 x i1>, 129 <vscale x 64 x i1>, 130 iXLen); 131 132define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind { 133; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1: 134; CHECK: # %bb.0: # %entry 135; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 136; CHECK-NEXT: vmand.mm v0, v0, v8 137; CHECK-NEXT: ret 138entry: 139 %a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1( 140 <vscale x 64 x i1> %0, 141 <vscale x 64 x i1> %1, 142 iXLen %2) 143 144 ret <vscale x 64 x i1> %a 145} 146