1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \ 3; RUN: -verify-machineinstrs | FileCheck %s 4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \ 5; RUN: -verify-machineinstrs | FileCheck %s 6 7declare iXLen @llvm.riscv.vfirst.iXLen.nxv1i1( 8 <vscale x 1 x i1>, 9 iXLen); 10 11define iXLen @intrinsic_vfirst_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind { 12; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1: 13; CHECK: # %bb.0: # %entry 14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 15; CHECK-NEXT: vfirst.m a0, v0 16; CHECK-NEXT: ret 17entry: 18 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1( 19 <vscale x 1 x i1> %0, 20 iXLen %1) 21 22 ret iXLen %a 23} 24 25define iXLen @intrinsic_vfirst_m_nxv1i1_zero(<vscale x 1 x i1> %0) nounwind { 26; CHECK-LABEL: intrinsic_vfirst_m_nxv1i1_zero: 27; CHECK: # %bb.0: # %entry 28; CHECK-NEXT: li a0, -1 29; CHECK-NEXT: ret 30entry: 31 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv1i1( 32 <vscale x 1 x i1> %0, 33 iXLen 0) 34 35 ret iXLen %a 36} 37 38declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1( 39 <vscale x 1 x i1>, 40 <vscale x 1 x i1>, 41 iXLen); 42 43define iXLen @intrinsic_vfirst_mask_m_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind { 44; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1: 45; CHECK: # %bb.0: # %entry 46; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 47; CHECK-NEXT: vmv1r.v v9, v0 48; CHECK-NEXT: vmv1r.v v0, v8 49; CHECK-NEXT: vfirst.m a0, v9, v0.t 50; CHECK-NEXT: ret 51entry: 52 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1( 53 <vscale x 1 x i1> %0, 54 <vscale x 1 x i1> %1, 55 iXLen %2) 56 57 ret iXLen %a 58} 59 60define iXLen @intrinsic_vfirst_mask_m_nxv1i1_zero(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind { 61; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv1i1_zero: 62; CHECK: # %bb.0: # %entry 63; CHECK-NEXT: li a0, -1 64; CHECK-NEXT: ret 65entry: 66 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv1i1( 67 <vscale x 1 x i1> %0, 68 <vscale x 1 x i1> %1, 69 iXLen 0) 70 71 ret iXLen %a 72} 73 74declare iXLen @llvm.riscv.vfirst.iXLen.nxv2i1( 75 <vscale x 2 x i1>, 76 iXLen); 77 78define iXLen @intrinsic_vfirst_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { 79; CHECK-LABEL: intrinsic_vfirst_m_nxv2i1: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 82; CHECK-NEXT: vfirst.m a0, v0 83; CHECK-NEXT: ret 84entry: 85 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv2i1( 86 <vscale x 2 x i1> %0, 87 iXLen %1) 88 89 ret iXLen %a 90} 91 92declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv2i1( 93 <vscale x 2 x i1>, 94 <vscale x 2 x i1>, 95 iXLen); 96 97define iXLen @intrinsic_vfirst_mask_m_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind { 98; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv2i1: 99; CHECK: # %bb.0: # %entry 100; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 101; CHECK-NEXT: vmv1r.v v9, v0 102; CHECK-NEXT: vmv1r.v v0, v8 103; CHECK-NEXT: vfirst.m a0, v9, v0.t 104; CHECK-NEXT: ret 105entry: 106 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv2i1( 107 <vscale x 2 x i1> %0, 108 <vscale x 2 x i1> %1, 109 iXLen %2) 110 111 ret iXLen %a 112} 113 114declare iXLen @llvm.riscv.vfirst.iXLen.nxv4i1( 115 <vscale x 4 x i1>, 116 iXLen); 117 118define iXLen @intrinsic_vfirst_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { 119; CHECK-LABEL: intrinsic_vfirst_m_nxv4i1: 120; CHECK: # %bb.0: # %entry 121; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 122; CHECK-NEXT: vfirst.m a0, v0 123; CHECK-NEXT: ret 124entry: 125 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv4i1( 126 <vscale x 4 x i1> %0, 127 iXLen %1) 128 129 ret iXLen %a 130} 131 132declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv4i1( 133 <vscale x 4 x i1>, 134 <vscale x 4 x i1>, 135 iXLen); 136 137define iXLen @intrinsic_vfirst_mask_m_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind { 138; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv4i1: 139; CHECK: # %bb.0: # %entry 140; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 141; CHECK-NEXT: vmv1r.v v9, v0 142; CHECK-NEXT: vmv1r.v v0, v8 143; CHECK-NEXT: vfirst.m a0, v9, v0.t 144; CHECK-NEXT: ret 145entry: 146 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv4i1( 147 <vscale x 4 x i1> %0, 148 <vscale x 4 x i1> %1, 149 iXLen %2) 150 151 ret iXLen %a 152} 153 154declare iXLen @llvm.riscv.vfirst.iXLen.nxv8i1( 155 <vscale x 8 x i1>, 156 iXLen); 157 158define iXLen @intrinsic_vfirst_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { 159; CHECK-LABEL: intrinsic_vfirst_m_nxv8i1: 160; CHECK: # %bb.0: # %entry 161; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 162; CHECK-NEXT: vfirst.m a0, v0 163; CHECK-NEXT: ret 164entry: 165 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv8i1( 166 <vscale x 8 x i1> %0, 167 iXLen %1) 168 169 ret iXLen %a 170} 171 172declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv8i1( 173 <vscale x 8 x i1>, 174 <vscale x 8 x i1>, 175 iXLen); 176 177define iXLen @intrinsic_vfirst_mask_m_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind { 178; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv8i1: 179; CHECK: # %bb.0: # %entry 180; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 181; CHECK-NEXT: vmv1r.v v9, v0 182; CHECK-NEXT: vmv1r.v v0, v8 183; CHECK-NEXT: vfirst.m a0, v9, v0.t 184; CHECK-NEXT: ret 185entry: 186 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv8i1( 187 <vscale x 8 x i1> %0, 188 <vscale x 8 x i1> %1, 189 iXLen %2) 190 191 ret iXLen %a 192} 193 194declare iXLen @llvm.riscv.vfirst.iXLen.nxv16i1( 195 <vscale x 16 x i1>, 196 iXLen); 197 198define iXLen @intrinsic_vfirst_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { 199; CHECK-LABEL: intrinsic_vfirst_m_nxv16i1: 200; CHECK: # %bb.0: # %entry 201; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 202; CHECK-NEXT: vfirst.m a0, v0 203; CHECK-NEXT: ret 204entry: 205 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv16i1( 206 <vscale x 16 x i1> %0, 207 iXLen %1) 208 209 ret iXLen %a 210} 211 212declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv16i1( 213 <vscale x 16 x i1>, 214 <vscale x 16 x i1>, 215 iXLen); 216 217define iXLen @intrinsic_vfirst_mask_m_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind { 218; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv16i1: 219; CHECK: # %bb.0: # %entry 220; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 221; CHECK-NEXT: vmv1r.v v9, v0 222; CHECK-NEXT: vmv1r.v v0, v8 223; CHECK-NEXT: vfirst.m a0, v9, v0.t 224; CHECK-NEXT: ret 225entry: 226 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv16i1( 227 <vscale x 16 x i1> %0, 228 <vscale x 16 x i1> %1, 229 iXLen %2) 230 231 ret iXLen %a 232} 233 234declare iXLen @llvm.riscv.vfirst.iXLen.nxv32i1( 235 <vscale x 32 x i1>, 236 iXLen); 237 238define iXLen @intrinsic_vfirst_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind { 239; CHECK-LABEL: intrinsic_vfirst_m_nxv32i1: 240; CHECK: # %bb.0: # %entry 241; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 242; CHECK-NEXT: vfirst.m a0, v0 243; CHECK-NEXT: ret 244entry: 245 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv32i1( 246 <vscale x 32 x i1> %0, 247 iXLen %1) 248 249 ret iXLen %a 250} 251 252declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv32i1( 253 <vscale x 32 x i1>, 254 <vscale x 32 x i1>, 255 iXLen); 256 257define iXLen @intrinsic_vfirst_mask_m_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind { 258; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv32i1: 259; CHECK: # %bb.0: # %entry 260; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 261; CHECK-NEXT: vmv1r.v v9, v0 262; CHECK-NEXT: vmv1r.v v0, v8 263; CHECK-NEXT: vfirst.m a0, v9, v0.t 264; CHECK-NEXT: ret 265entry: 266 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv32i1( 267 <vscale x 32 x i1> %0, 268 <vscale x 32 x i1> %1, 269 iXLen %2) 270 271 ret iXLen %a 272} 273 274declare iXLen @llvm.riscv.vfirst.iXLen.nxv64i1( 275 <vscale x 64 x i1>, 276 iXLen); 277 278define iXLen @intrinsic_vfirst_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind { 279; CHECK-LABEL: intrinsic_vfirst_m_nxv64i1: 280; CHECK: # %bb.0: # %entry 281; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 282; CHECK-NEXT: vfirst.m a0, v0 283; CHECK-NEXT: ret 284entry: 285 %a = call iXLen @llvm.riscv.vfirst.iXLen.nxv64i1( 286 <vscale x 64 x i1> %0, 287 iXLen %1) 288 289 ret iXLen %a 290} 291 292declare iXLen @llvm.riscv.vfirst.mask.iXLen.nxv64i1( 293 <vscale x 64 x i1>, 294 <vscale x 64 x i1>, 295 iXLen); 296 297define iXLen @intrinsic_vfirst_mask_m_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind { 298; CHECK-LABEL: intrinsic_vfirst_mask_m_nxv64i1: 299; CHECK: # %bb.0: # %entry 300; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 301; CHECK-NEXT: vmv1r.v v9, v0 302; CHECK-NEXT: vmv1r.v v0, v8 303; CHECK-NEXT: vfirst.m a0, v9, v0.t 304; CHECK-NEXT: ret 305entry: 306 %a = call iXLen @llvm.riscv.vfirst.mask.iXLen.nxv64i1( 307 <vscale x 64 x i1> %0, 308 <vscale x 64 x i1> %1, 309 iXLen %2) 310 311 ret iXLen %a 312} 313