xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
3; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
4; RUN:     --check-prefixes=CHECK,ZVFH
5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
6; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
7; RUN:     --check-prefixes=CHECK,ZVFH
8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
9; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
10; RUN:     --check-prefixes=CHECK,ZVFHMIN
11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
12; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
13; RUN:     --check-prefixes=CHECK,ZVFHMIN
14
15define <vscale x 2 x i1> @isnan_nxv2bf16(<vscale x 2 x bfloat> %x) {
16; CHECK-LABEL: isnan_nxv2bf16:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    lui a0, 8
19; CHECK-NEXT:    addi a1, a0, -1
20; CHECK-NEXT:    vsetvli a2, zero, e16, mf2, ta, ma
21; CHECK-NEXT:    vand.vx v8, v8, a1
22; CHECK-NEXT:    addi a0, a0, -128
23; CHECK-NEXT:    vmsgt.vx v0, v8, a0
24; CHECK-NEXT:    ret
25  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2bf16(<vscale x 2 x bfloat> %x, i32 3)  ; nan
26  ret <vscale x 2 x i1> %1
27}
28
29define <vscale x 2 x i1> @isnan_nxv2f16(<vscale x 2 x half> %x) {
30; ZVFH-LABEL: isnan_nxv2f16:
31; ZVFH:       # %bb.0:
32; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
33; ZVFH-NEXT:    vfclass.v v8, v8
34; ZVFH-NEXT:    li a0, 768
35; ZVFH-NEXT:    vand.vx v8, v8, a0
36; ZVFH-NEXT:    vmsne.vi v0, v8, 0
37; ZVFH-NEXT:    ret
38;
39; ZVFHMIN-LABEL: isnan_nxv2f16:
40; ZVFHMIN:       # %bb.0:
41; ZVFHMIN-NEXT:    lui a0, 8
42; ZVFHMIN-NEXT:    addi a0, a0, -1
43; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
44; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
45; ZVFHMIN-NEXT:    li a0, 31
46; ZVFHMIN-NEXT:    slli a0, a0, 10
47; ZVFHMIN-NEXT:    vmsgt.vx v0, v8, a0
48; ZVFHMIN-NEXT:    ret
49  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3)  ; nan
50  ret <vscale x 2 x i1> %1
51}
52
53define <vscale x 2 x i1> @isnan_nxv2f32(<vscale x 2 x float> %x) {
54; CHECK-LABEL: isnan_nxv2f32:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
57; CHECK-NEXT:    vfclass.v v8, v8
58; CHECK-NEXT:    li a0, 927
59; CHECK-NEXT:    vand.vx v8, v8, a0
60; CHECK-NEXT:    vmsne.vi v0, v8, 0
61; CHECK-NEXT:    ret
62  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float> %x, i32 639)
63  ret <vscale x 2 x i1> %1
64}
65
66
67define <vscale x 4 x i1> @isnan_nxv4f32(<vscale x 4 x float> %x) {
68; CHECK-LABEL: isnan_nxv4f32:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
71; CHECK-NEXT:    vfclass.v v8, v8
72; CHECK-NEXT:    li a0, 768
73; CHECK-NEXT:    vand.vx v8, v8, a0
74; CHECK-NEXT:    vmsne.vi v0, v8, 0
75; CHECK-NEXT:    ret
76  %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %x, i32 3)  ; nan
77  ret <vscale x 4 x i1> %1
78}
79
80define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x) {
81; CHECK-LABEL: isnan_nxv8f32:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
84; CHECK-NEXT:    vfclass.v v8, v8
85; CHECK-NEXT:    li a0, 512
86; CHECK-NEXT:    vmseq.vx v0, v8, a0
87; CHECK-NEXT:    ret
88  %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2)
89  ret <vscale x 8 x i1> %1
90}
91
92define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x) {
93; CHECK-LABEL: isnan_nxv16f32:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
96; CHECK-NEXT:    vfclass.v v8, v8
97; CHECK-NEXT:    li a0, 256
98; CHECK-NEXT:    vmseq.vx v0, v8, a0
99; CHECK-NEXT:    ret
100  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1)
101  ret <vscale x 16 x i1> %1
102}
103
104define <vscale x 2 x i1> @isnormal_nxv2f64(<vscale x 2 x double> %x) {
105; CHECK-LABEL: isnormal_nxv2f64:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
108; CHECK-NEXT:    vfclass.v v8, v8
109; CHECK-NEXT:    li a0, 129
110; CHECK-NEXT:    vand.vx v8, v8, a0
111; CHECK-NEXT:    vmsne.vi v0, v8, 0
112; CHECK-NEXT:    ret
113  %1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516) ; 0x204 = "inf"
114  ret <vscale x 2 x i1> %1
115}
116
117define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x) {
118; CHECK-LABEL: isposinf_nxv4f64:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
121; CHECK-NEXT:    vfclass.v v8, v8
122; CHECK-NEXT:    li a0, 128
123; CHECK-NEXT:    vmseq.vx v0, v8, a0
124; CHECK-NEXT:    ret
125  %1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512) ; 0x200 = "+inf"
126  ret <vscale x 4 x i1> %1
127}
128
129define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x) {
130; CHECK-LABEL: isneginf_nxv8f64:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
133; CHECK-NEXT:    vfclass.v v8, v8
134; CHECK-NEXT:    vmseq.vi v0, v8, 1
135; CHECK-NEXT:    ret
136  %1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4) ; "-inf"
137  ret <vscale x 8 x i1> %1
138}
139
140define <vscale x 16 x i1> @isfinite_nxv16f32(<vscale x 16 x float> %x) {
141; CHECK-LABEL: isfinite_nxv16f32:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
144; CHECK-NEXT:    vfclass.v v8, v8
145; CHECK-NEXT:    li a0, 126
146; CHECK-NEXT:    vand.vx v8, v8, a0
147; CHECK-NEXT:    vmsne.vi v0, v8, 0
148; CHECK-NEXT:    ret
149  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 504) ; 0x1f8 = "finite"
150  ret <vscale x 16 x i1> %1
151}
152
153define <vscale x 16 x i1> @isposfinite_nxv16f32(<vscale x 16 x float> %x) {
154; CHECK-LABEL: isposfinite_nxv16f32:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
157; CHECK-NEXT:    vfclass.v v8, v8
158; CHECK-NEXT:    li a0, 112
159; CHECK-NEXT:    vand.vx v8, v8, a0
160; CHECK-NEXT:    vmsne.vi v0, v8, 0
161; CHECK-NEXT:    ret
162  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 448) ; 0x1c0 = "+finite"
163  ret <vscale x 16 x i1> %1
164}
165
166define <vscale x 16 x i1> @isnegfinite_nxv16f32(<vscale x 16 x float> %x) {
167; CHECK-LABEL: isnegfinite_nxv16f32:
168; CHECK:       # %bb.0:
169; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
170; CHECK-NEXT:    vfclass.v v8, v8
171; CHECK-NEXT:    vand.vi v8, v8, 14
172; CHECK-NEXT:    vmsne.vi v0, v8, 0
173; CHECK-NEXT:    ret
174  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 56) ; 0x38 = "-finite"
175  ret <vscale x 16 x i1> %1
176}
177
178define <vscale x 16 x i1> @isnotfinite_nxv16f32(<vscale x 16 x float> %x) {
179; CHECK-LABEL: isnotfinite_nxv16f32:
180; CHECK:       # %bb.0:
181; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
182; CHECK-NEXT:    vfclass.v v8, v8
183; CHECK-NEXT:    li a0, 897
184; CHECK-NEXT:    vand.vx v8, v8, a0
185; CHECK-NEXT:    vmsne.vi v0, v8, 0
186; CHECK-NEXT:    ret
187  %1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 519) ; 0x207 = "inf|nan"
188  ret <vscale x 16 x i1> %1
189}
190
191declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half>, i32)
192declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float>, i32)
193declare <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float>, i32)
194declare <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float>, i32)
195declare <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float>, i32)
196declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double>, i32)
197declare <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double>, i32)
198declare <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double>, i32)
199