xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv32 -mattr=+m,+f,+d,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s
3; RUN: llc -mtriple riscv64 -mattr=+m,+f,+d,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s
4; RUN: llc -mtriple riscv32 -mattr=+m,+f,+d,+v,+zvfh,+zvfbfmin < %s | FileCheck %s
5; RUN: llc -mtriple riscv64 -mattr=+m,+f,+d,+v,+zvfh,+zvfbfmin < %s | FileCheck %s
6
7; Tests assume VLEN=128 or vscale_range_min=2.
8
9declare <vscale x 1 x i1> @llvm.vector.splice.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, i32)
10
11define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) #0 {
12; CHECK-LABEL: splice_nxv1i1_offset_negone:
13; CHECK:       # %bb.0:
14; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
15; CHECK-NEXT:    vmv1r.v v9, v0
16; CHECK-NEXT:    vmv1r.v v0, v8
17; CHECK-NEXT:    vmv.v.i v8, 0
18; CHECK-NEXT:    csrr a0, vlenb
19; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
20; CHECK-NEXT:    vmv1r.v v0, v9
21; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
22; CHECK-NEXT:    srli a0, a0, 3
23; CHECK-NEXT:    addi a0, a0, -1
24; CHECK-NEXT:    vslidedown.vx v8, v8, a0
25; CHECK-NEXT:    vslideup.vi v8, v10, 1
26; CHECK-NEXT:    vand.vi v8, v8, 1
27; CHECK-NEXT:    vmsne.vi v0, v8, 0
28; CHECK-NEXT:    ret
29  %res = call <vscale x 1 x i1> @llvm.vector.splice.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i32 -1)
30  ret <vscale x 1 x i1> %res
31}
32
33define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) #0 {
34; CHECK-LABEL: splice_nxv1i1_offset_max:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
37; CHECK-NEXT:    vmv1r.v v9, v0
38; CHECK-NEXT:    vmv1r.v v0, v8
39; CHECK-NEXT:    vmv.v.i v8, 0
40; CHECK-NEXT:    csrr a0, vlenb
41; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
42; CHECK-NEXT:    vmv1r.v v0, v9
43; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
44; CHECK-NEXT:    srli a0, a0, 3
45; CHECK-NEXT:    addi a0, a0, -1
46; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
47; CHECK-NEXT:    vslidedown.vi v8, v8, 1
48; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
49; CHECK-NEXT:    vslideup.vx v8, v10, a0
50; CHECK-NEXT:    vand.vi v8, v8, 1
51; CHECK-NEXT:    vmsne.vi v0, v8, 0
52; CHECK-NEXT:    ret
53  %res = call <vscale x 1 x i1> @llvm.vector.splice.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, i32 1)
54  ret <vscale x 1 x i1> %res
55}
56
57declare <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)
58
59define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 {
60; CHECK-LABEL: splice_nxv2i1_offset_negone:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
63; CHECK-NEXT:    vmv1r.v v9, v0
64; CHECK-NEXT:    vmv1r.v v0, v8
65; CHECK-NEXT:    vmv.v.i v8, 0
66; CHECK-NEXT:    csrr a0, vlenb
67; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
68; CHECK-NEXT:    vmv1r.v v0, v9
69; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
70; CHECK-NEXT:    srli a0, a0, 2
71; CHECK-NEXT:    addi a0, a0, -1
72; CHECK-NEXT:    vslidedown.vx v8, v8, a0
73; CHECK-NEXT:    vslideup.vi v8, v10, 1
74; CHECK-NEXT:    vand.vi v8, v8, 1
75; CHECK-NEXT:    vmsne.vi v0, v8, 0
76; CHECK-NEXT:    ret
77  %res = call <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 -1)
78  ret <vscale x 2 x i1> %res
79}
80
81define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 {
82; CHECK-LABEL: splice_nxv2i1_offset_max:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
85; CHECK-NEXT:    vmv1r.v v9, v0
86; CHECK-NEXT:    vmv1r.v v0, v8
87; CHECK-NEXT:    vmv.v.i v8, 0
88; CHECK-NEXT:    csrr a0, vlenb
89; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
90; CHECK-NEXT:    vmv1r.v v0, v9
91; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
92; CHECK-NEXT:    srli a0, a0, 2
93; CHECK-NEXT:    addi a0, a0, -3
94; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
95; CHECK-NEXT:    vslidedown.vi v8, v8, 3
96; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
97; CHECK-NEXT:    vslideup.vx v8, v10, a0
98; CHECK-NEXT:    vand.vi v8, v8, 1
99; CHECK-NEXT:    vmsne.vi v0, v8, 0
100; CHECK-NEXT:    ret
101  %res = call <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 3)
102  ret <vscale x 2 x i1> %res
103}
104
105declare <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, i32)
106
107define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 {
108; CHECK-LABEL: splice_nxv4i1_offset_negone:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
111; CHECK-NEXT:    vmv1r.v v9, v0
112; CHECK-NEXT:    vmv1r.v v0, v8
113; CHECK-NEXT:    vmv.v.i v8, 0
114; CHECK-NEXT:    csrr a0, vlenb
115; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
116; CHECK-NEXT:    vmv1r.v v0, v9
117; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
118; CHECK-NEXT:    srli a0, a0, 1
119; CHECK-NEXT:    addi a0, a0, -1
120; CHECK-NEXT:    vslidedown.vx v8, v8, a0
121; CHECK-NEXT:    vslideup.vi v8, v10, 1
122; CHECK-NEXT:    vand.vi v8, v8, 1
123; CHECK-NEXT:    vmsne.vi v0, v8, 0
124; CHECK-NEXT:    ret
125  %res = call <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 -1)
126  ret <vscale x 4 x i1> %res
127}
128
129define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 {
130; CHECK-LABEL: splice_nxv4i1_offset_max:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
133; CHECK-NEXT:    vmv1r.v v9, v0
134; CHECK-NEXT:    vmv1r.v v0, v8
135; CHECK-NEXT:    vmv.v.i v8, 0
136; CHECK-NEXT:    csrr a0, vlenb
137; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
138; CHECK-NEXT:    vmv1r.v v0, v9
139; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
140; CHECK-NEXT:    srli a0, a0, 1
141; CHECK-NEXT:    addi a0, a0, -7
142; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
143; CHECK-NEXT:    vslidedown.vi v8, v8, 7
144; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
145; CHECK-NEXT:    vslideup.vx v8, v10, a0
146; CHECK-NEXT:    vand.vi v8, v8, 1
147; CHECK-NEXT:    vmsne.vi v0, v8, 0
148; CHECK-NEXT:    ret
149  %res = call <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 7)
150  ret <vscale x 4 x i1> %res
151}
152
153declare <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, i32)
154
155define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 {
156; CHECK-LABEL: splice_nxv8i1_offset_negone:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
159; CHECK-NEXT:    vmv1r.v v9, v0
160; CHECK-NEXT:    vmv1r.v v0, v8
161; CHECK-NEXT:    vmv.v.i v8, 0
162; CHECK-NEXT:    csrr a0, vlenb
163; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
164; CHECK-NEXT:    vmv1r.v v0, v9
165; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
166; CHECK-NEXT:    addi a0, a0, -1
167; CHECK-NEXT:    vslidedown.vx v8, v8, a0
168; CHECK-NEXT:    vslideup.vi v8, v10, 1
169; CHECK-NEXT:    vand.vi v8, v8, 1
170; CHECK-NEXT:    vmsne.vi v0, v8, 0
171; CHECK-NEXT:    ret
172  %res = call <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 -1)
173  ret <vscale x 8 x i1> %res
174}
175
176define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 {
177; CHECK-LABEL: splice_nxv8i1_offset_max:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
180; CHECK-NEXT:    vmv1r.v v9, v0
181; CHECK-NEXT:    vmv1r.v v0, v8
182; CHECK-NEXT:    vmv.v.i v8, 0
183; CHECK-NEXT:    csrr a0, vlenb
184; CHECK-NEXT:    vmerge.vim v10, v8, 1, v0
185; CHECK-NEXT:    vmv1r.v v0, v9
186; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
187; CHECK-NEXT:    addi a0, a0, -15
188; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
189; CHECK-NEXT:    vslidedown.vi v8, v8, 15
190; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
191; CHECK-NEXT:    vslideup.vx v8, v10, a0
192; CHECK-NEXT:    vand.vi v8, v8, 1
193; CHECK-NEXT:    vmsne.vi v0, v8, 0
194; CHECK-NEXT:    ret
195  %res = call <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 15)
196  ret <vscale x 8 x i1> %res
197}
198
199declare <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)
200
201define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
202; CHECK-LABEL: splice_nxv16i1_offset_negone:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
205; CHECK-NEXT:    vmv1r.v v9, v0
206; CHECK-NEXT:    vmv1r.v v0, v8
207; CHECK-NEXT:    vmv.v.i v10, 0
208; CHECK-NEXT:    csrr a0, vlenb
209; CHECK-NEXT:    vmerge.vim v12, v10, 1, v0
210; CHECK-NEXT:    vmv1r.v v0, v9
211; CHECK-NEXT:    vmerge.vim v8, v10, 1, v0
212; CHECK-NEXT:    slli a0, a0, 1
213; CHECK-NEXT:    addi a0, a0, -1
214; CHECK-NEXT:    vslidedown.vx v8, v8, a0
215; CHECK-NEXT:    vslideup.vi v8, v12, 1
216; CHECK-NEXT:    vand.vi v8, v8, 1
217; CHECK-NEXT:    vmsne.vi v0, v8, 0
218; CHECK-NEXT:    ret
219  %res = call <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 -1)
220  ret <vscale x 16 x i1> %res
221}
222
223define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {
224; CHECK-LABEL: splice_nxv16i1_offset_max:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
227; CHECK-NEXT:    vmv1r.v v9, v0
228; CHECK-NEXT:    vmv1r.v v0, v8
229; CHECK-NEXT:    vmv.v.i v10, 0
230; CHECK-NEXT:    csrr a0, vlenb
231; CHECK-NEXT:    vmerge.vim v12, v10, 1, v0
232; CHECK-NEXT:    vmv1r.v v0, v9
233; CHECK-NEXT:    vmerge.vim v8, v10, 1, v0
234; CHECK-NEXT:    slli a0, a0, 1
235; CHECK-NEXT:    addi a0, a0, -31
236; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
237; CHECK-NEXT:    vslidedown.vi v8, v8, 31
238; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
239; CHECK-NEXT:    vslideup.vx v8, v12, a0
240; CHECK-NEXT:    vand.vi v8, v8, 1
241; CHECK-NEXT:    vmsne.vi v0, v8, 0
242; CHECK-NEXT:    ret
243  %res = call <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 31)
244  ret <vscale x 16 x i1> %res
245}
246
247declare <vscale x 32 x i1> @llvm.vector.splice.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, i32)
248
249define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b) #0 {
250; CHECK-LABEL: splice_nxv32i1_offset_negone:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
253; CHECK-NEXT:    vmv1r.v v9, v0
254; CHECK-NEXT:    vmv1r.v v0, v8
255; CHECK-NEXT:    vmv.v.i v12, 0
256; CHECK-NEXT:    csrr a0, vlenb
257; CHECK-NEXT:    vmerge.vim v16, v12, 1, v0
258; CHECK-NEXT:    vmv1r.v v0, v9
259; CHECK-NEXT:    vmerge.vim v8, v12, 1, v0
260; CHECK-NEXT:    slli a0, a0, 2
261; CHECK-NEXT:    addi a0, a0, -1
262; CHECK-NEXT:    vslidedown.vx v8, v8, a0
263; CHECK-NEXT:    vslideup.vi v8, v16, 1
264; CHECK-NEXT:    vand.vi v8, v8, 1
265; CHECK-NEXT:    vmsne.vi v0, v8, 0
266; CHECK-NEXT:    ret
267  %res = call <vscale x 32 x i1> @llvm.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 -1)
268  ret <vscale x 32 x i1> %res
269}
270
271define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b) #0 {
272; CHECK-LABEL: splice_nxv32i1_offset_max:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
275; CHECK-NEXT:    vmv.v.i v12, 0
276; CHECK-NEXT:    csrr a0, vlenb
277; CHECK-NEXT:    li a1, 63
278; CHECK-NEXT:    vmerge.vim v16, v12, 1, v0
279; CHECK-NEXT:    slli a0, a0, 2
280; CHECK-NEXT:    addi a0, a0, -63
281; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
282; CHECK-NEXT:    vslidedown.vx v16, v16, a1
283; CHECK-NEXT:    vmv1r.v v0, v8
284; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
285; CHECK-NEXT:    vmerge.vim v8, v12, 1, v0
286; CHECK-NEXT:    vslideup.vx v16, v8, a0
287; CHECK-NEXT:    vand.vi v8, v16, 1
288; CHECK-NEXT:    vmsne.vi v0, v8, 0
289; CHECK-NEXT:    ret
290  %res = call <vscale x 32 x i1> @llvm.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 63)
291  ret <vscale x 32 x i1> %res
292}
293
294declare <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, i32)
295
296define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) #0 {
297; CHECK-LABEL: splice_nxv64i1_offset_negone:
298; CHECK:       # %bb.0:
299; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
300; CHECK-NEXT:    vmv1r.v v9, v0
301; CHECK-NEXT:    vmv1r.v v0, v8
302; CHECK-NEXT:    vmv.v.i v24, 0
303; CHECK-NEXT:    csrr a0, vlenb
304; CHECK-NEXT:    vmerge.vim v16, v24, 1, v0
305; CHECK-NEXT:    vmv1r.v v0, v9
306; CHECK-NEXT:    vmerge.vim v8, v24, 1, v0
307; CHECK-NEXT:    slli a0, a0, 3
308; CHECK-NEXT:    addi a0, a0, -1
309; CHECK-NEXT:    vslidedown.vx v8, v8, a0
310; CHECK-NEXT:    vslideup.vi v8, v16, 1
311; CHECK-NEXT:    vand.vi v8, v8, 1
312; CHECK-NEXT:    vmsne.vi v0, v8, 0
313; CHECK-NEXT:    ret
314  %res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1)
315  ret <vscale x 64 x i1> %res
316}
317
318define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) #0 {
319; CHECK-LABEL: splice_nxv64i1_offset_max:
320; CHECK:       # %bb.0:
321; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
322; CHECK-NEXT:    vmv.v.i v16, 0
323; CHECK-NEXT:    csrr a0, vlenb
324; CHECK-NEXT:    li a1, 127
325; CHECK-NEXT:    vmerge.vim v24, v16, 1, v0
326; CHECK-NEXT:    slli a0, a0, 3
327; CHECK-NEXT:    addi a0, a0, -127
328; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
329; CHECK-NEXT:    vslidedown.vx v24, v24, a1
330; CHECK-NEXT:    vmv1r.v v0, v8
331; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
332; CHECK-NEXT:    vmerge.vim v8, v16, 1, v0
333; CHECK-NEXT:    vslideup.vx v24, v8, a0
334; CHECK-NEXT:    vand.vi v8, v24, 1
335; CHECK-NEXT:    vmsne.vi v0, v8, 0
336; CHECK-NEXT:    ret
337  %res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 127)
338  ret <vscale x 64 x i1> %res
339}
340
341declare <vscale x 1 x i8> @llvm.vector.splice.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, i32)
342
343define <vscale x 1 x i8> @splice_nxv1i8_offset_zero(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
344; CHECK-LABEL: splice_nxv1i8_offset_zero:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    ret
347  %res = call <vscale x 1 x i8> @llvm.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 0)
348  ret <vscale x 1 x i8> %res
349}
350
351define <vscale x 1 x i8> @splice_nxv1i8_offset_negone(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
352; CHECK-LABEL: splice_nxv1i8_offset_negone:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    csrr a0, vlenb
355; CHECK-NEXT:    srli a0, a0, 3
356; CHECK-NEXT:    addi a0, a0, -1
357; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
358; CHECK-NEXT:    vslidedown.vx v8, v8, a0
359; CHECK-NEXT:    vslideup.vi v8, v9, 1
360; CHECK-NEXT:    ret
361  %res = call <vscale x 1 x i8> @llvm.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -1)
362  ret <vscale x 1 x i8> %res
363}
364
365define <vscale x 1 x i8> @splice_nxv1i8_offset_min(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
366; CHECK-LABEL: splice_nxv1i8_offset_min:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    csrr a0, vlenb
369; CHECK-NEXT:    srli a0, a0, 3
370; CHECK-NEXT:    addi a0, a0, -2
371; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
372; CHECK-NEXT:    vslidedown.vx v8, v8, a0
373; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
374; CHECK-NEXT:    vslideup.vi v8, v9, 2
375; CHECK-NEXT:    ret
376  %res = call <vscale x 1 x i8> @llvm.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 -2)
377  ret <vscale x 1 x i8> %res
378}
379
380define <vscale x 1 x i8> @splice_nxv1i8_offset_max(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) #0 {
381; CHECK-LABEL: splice_nxv1i8_offset_max:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    csrr a0, vlenb
384; CHECK-NEXT:    srli a0, a0, 3
385; CHECK-NEXT:    addi a0, a0, -1
386; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
387; CHECK-NEXT:    vslidedown.vi v8, v8, 1
388; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
389; CHECK-NEXT:    vslideup.vx v8, v9, a0
390; CHECK-NEXT:    ret
391  %res = call <vscale x 1 x i8> @llvm.vector.splice.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, i32 1)
392  ret <vscale x 1 x i8> %res
393}
394
395declare <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, i32)
396
397define <vscale x 2 x i8> @splice_nxv2i8_offset_zero(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
398; CHECK-LABEL: splice_nxv2i8_offset_zero:
399; CHECK:       # %bb.0:
400; CHECK-NEXT:    ret
401  %res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 0)
402  ret <vscale x 2 x i8> %res
403}
404
405define <vscale x 2 x i8> @splice_nxv2i8_offset_negone(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
406; CHECK-LABEL: splice_nxv2i8_offset_negone:
407; CHECK:       # %bb.0:
408; CHECK-NEXT:    csrr a0, vlenb
409; CHECK-NEXT:    srli a0, a0, 2
410; CHECK-NEXT:    addi a0, a0, -1
411; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
412; CHECK-NEXT:    vslidedown.vx v8, v8, a0
413; CHECK-NEXT:    vslideup.vi v8, v9, 1
414; CHECK-NEXT:    ret
415  %res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -1)
416  ret <vscale x 2 x i8> %res
417}
418
419define <vscale x 2 x i8> @splice_nxv2i8_offset_min(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
420; CHECK-LABEL: splice_nxv2i8_offset_min:
421; CHECK:       # %bb.0:
422; CHECK-NEXT:    csrr a0, vlenb
423; CHECK-NEXT:    srli a0, a0, 2
424; CHECK-NEXT:    addi a0, a0, -4
425; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
426; CHECK-NEXT:    vslidedown.vx v8, v8, a0
427; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
428; CHECK-NEXT:    vslideup.vi v8, v9, 4
429; CHECK-NEXT:    ret
430  %res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -4)
431  ret <vscale x 2 x i8> %res
432}
433
434define <vscale x 2 x i8> @splice_nxv2i8_offset_max(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {
435; CHECK-LABEL: splice_nxv2i8_offset_max:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    csrr a0, vlenb
438; CHECK-NEXT:    srli a0, a0, 2
439; CHECK-NEXT:    addi a0, a0, -3
440; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
441; CHECK-NEXT:    vslidedown.vi v8, v8, 3
442; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
443; CHECK-NEXT:    vslideup.vx v8, v9, a0
444; CHECK-NEXT:    ret
445  %res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 3)
446  ret <vscale x 2 x i8> %res
447}
448
449declare <vscale x 4 x i8> @llvm.vector.splice.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, i32)
450
451define <vscale x 4 x i8> @splice_nxv4i8_offset_zero(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
452; CHECK-LABEL: splice_nxv4i8_offset_zero:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    ret
455  %res = call <vscale x 4 x i8> @llvm.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 0)
456  ret <vscale x 4 x i8> %res
457}
458
459define <vscale x 4 x i8> @splice_nxv4i8_offset_negone(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
460; CHECK-LABEL: splice_nxv4i8_offset_negone:
461; CHECK:       # %bb.0:
462; CHECK-NEXT:    csrr a0, vlenb
463; CHECK-NEXT:    srli a0, a0, 1
464; CHECK-NEXT:    addi a0, a0, -1
465; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
466; CHECK-NEXT:    vslidedown.vx v8, v8, a0
467; CHECK-NEXT:    vslideup.vi v8, v9, 1
468; CHECK-NEXT:    ret
469  %res = call <vscale x 4 x i8> @llvm.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -1)
470  ret <vscale x 4 x i8> %res
471}
472
473define <vscale x 4 x i8> @splice_nxv4i8_offset_min(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
474; CHECK-LABEL: splice_nxv4i8_offset_min:
475; CHECK:       # %bb.0:
476; CHECK-NEXT:    csrr a0, vlenb
477; CHECK-NEXT:    srli a0, a0, 1
478; CHECK-NEXT:    addi a0, a0, -8
479; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
480; CHECK-NEXT:    vslidedown.vx v8, v8, a0
481; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
482; CHECK-NEXT:    vslideup.vi v8, v9, 8
483; CHECK-NEXT:    ret
484  %res = call <vscale x 4 x i8> @llvm.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 -8)
485  ret <vscale x 4 x i8> %res
486}
487
488define <vscale x 4 x i8> @splice_nxv4i8_offset_max(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) #0 {
489; CHECK-LABEL: splice_nxv4i8_offset_max:
490; CHECK:       # %bb.0:
491; CHECK-NEXT:    csrr a0, vlenb
492; CHECK-NEXT:    srli a0, a0, 1
493; CHECK-NEXT:    addi a0, a0, -7
494; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
495; CHECK-NEXT:    vslidedown.vi v8, v8, 7
496; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
497; CHECK-NEXT:    vslideup.vx v8, v9, a0
498; CHECK-NEXT:    ret
499  %res = call <vscale x 4 x i8> @llvm.vector.splice.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, i32 7)
500  ret <vscale x 4 x i8> %res
501}
502
503declare <vscale x 8 x i8> @llvm.vector.splice.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i32)
504
505define <vscale x 8 x i8> @splice_nxv8i8_offset_zero(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
506; CHECK-LABEL: splice_nxv8i8_offset_zero:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    ret
509  %res = call <vscale x 8 x i8> @llvm.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 0)
510  ret <vscale x 8 x i8> %res
511}
512
513define <vscale x 8 x i8> @splice_nxv8i8_offset_negone(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
514; CHECK-LABEL: splice_nxv8i8_offset_negone:
515; CHECK:       # %bb.0:
516; CHECK-NEXT:    csrr a0, vlenb
517; CHECK-NEXT:    addi a0, a0, -1
518; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
519; CHECK-NEXT:    vslidedown.vx v8, v8, a0
520; CHECK-NEXT:    vslideup.vi v8, v9, 1
521; CHECK-NEXT:    ret
522  %res = call <vscale x 8 x i8> @llvm.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -1)
523  ret <vscale x 8 x i8> %res
524}
525
526define <vscale x 8 x i8> @splice_nxv8i8_offset_min(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
527; CHECK-LABEL: splice_nxv8i8_offset_min:
528; CHECK:       # %bb.0:
529; CHECK-NEXT:    csrr a0, vlenb
530; CHECK-NEXT:    addi a0, a0, -16
531; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
532; CHECK-NEXT:    vslidedown.vx v8, v8, a0
533; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
534; CHECK-NEXT:    vslideup.vi v8, v9, 16
535; CHECK-NEXT:    ret
536  %res = call <vscale x 8 x i8> @llvm.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 -16)
537  ret <vscale x 8 x i8> %res
538}
539
540define <vscale x 8 x i8> @splice_nxv8i8_offset_max(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) #0 {
541; CHECK-LABEL: splice_nxv8i8_offset_max:
542; CHECK:       # %bb.0:
543; CHECK-NEXT:    csrr a0, vlenb
544; CHECK-NEXT:    addi a0, a0, -15
545; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
546; CHECK-NEXT:    vslidedown.vi v8, v8, 15
547; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
548; CHECK-NEXT:    vslideup.vx v8, v9, a0
549; CHECK-NEXT:    ret
550  %res = call <vscale x 8 x i8> @llvm.vector.splice.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, i32 15)
551  ret <vscale x 8 x i8> %res
552}
553
554declare <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)
555
556define <vscale x 16 x i8> @splice_nxv16i8_offset_zero(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
557; CHECK-LABEL: splice_nxv16i8_offset_zero:
558; CHECK:       # %bb.0:
559; CHECK-NEXT:    ret
560  %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0)
561  ret <vscale x 16 x i8> %res
562}
563
564define <vscale x 16 x i8> @splice_nxv16i8_offset_negone(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
565; CHECK-LABEL: splice_nxv16i8_offset_negone:
566; CHECK:       # %bb.0:
567; CHECK-NEXT:    csrr a0, vlenb
568; CHECK-NEXT:    slli a0, a0, 1
569; CHECK-NEXT:    addi a0, a0, -1
570; CHECK-NEXT:    vsetivli zero, 1, e8, m2, ta, ma
571; CHECK-NEXT:    vslidedown.vx v8, v8, a0
572; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
573; CHECK-NEXT:    vslideup.vi v8, v10, 1
574; CHECK-NEXT:    ret
575  %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -1)
576  ret <vscale x 16 x i8> %res
577}
578
579define <vscale x 16 x i8> @splice_nxv16i8_offset_min(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
580; CHECK-LABEL: splice_nxv16i8_offset_min:
581; CHECK:       # %bb.0:
582; CHECK-NEXT:    csrr a0, vlenb
583; CHECK-NEXT:    slli a0, a0, 1
584; CHECK-NEXT:    addi a0, a0, -32
585; CHECK-NEXT:    li a1, 32
586; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
587; CHECK-NEXT:    vslidedown.vx v8, v8, a0
588; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
589; CHECK-NEXT:    vslideup.vx v8, v10, a1
590; CHECK-NEXT:    ret
591  %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -32)
592  ret <vscale x 16 x i8> %res
593}
594
595define <vscale x 16 x i8> @splice_nxv16i8_offset_max(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
596; CHECK-LABEL: splice_nxv16i8_offset_max:
597; CHECK:       # %bb.0:
598; CHECK-NEXT:    csrr a0, vlenb
599; CHECK-NEXT:    slli a0, a0, 1
600; CHECK-NEXT:    addi a0, a0, -31
601; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
602; CHECK-NEXT:    vslidedown.vi v8, v8, 31
603; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
604; CHECK-NEXT:    vslideup.vx v8, v10, a0
605; CHECK-NEXT:    ret
606  %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 31)
607  ret <vscale x 16 x i8> %res
608}
609
610declare <vscale x 32 x i8> @llvm.vector.splice.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, i32)
611
612define <vscale x 32 x i8> @splice_nxv32i8_offset_zero(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
613; CHECK-LABEL: splice_nxv32i8_offset_zero:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    ret
616  %res = call <vscale x 32 x i8> @llvm.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 0)
617  ret <vscale x 32 x i8> %res
618}
619
620define <vscale x 32 x i8> @splice_nxv32i8_offset_negone(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
621; CHECK-LABEL: splice_nxv32i8_offset_negone:
622; CHECK:       # %bb.0:
623; CHECK-NEXT:    csrr a0, vlenb
624; CHECK-NEXT:    slli a0, a0, 2
625; CHECK-NEXT:    addi a0, a0, -1
626; CHECK-NEXT:    vsetivli zero, 1, e8, m4, ta, ma
627; CHECK-NEXT:    vslidedown.vx v8, v8, a0
628; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
629; CHECK-NEXT:    vslideup.vi v8, v12, 1
630; CHECK-NEXT:    ret
631  %res = call <vscale x 32 x i8> @llvm.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -1)
632  ret <vscale x 32 x i8> %res
633}
634
635define <vscale x 32 x i8> @splice_nxv32i8_offset_min(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
636; CHECK-LABEL: splice_nxv32i8_offset_min:
637; CHECK:       # %bb.0:
638; CHECK-NEXT:    csrr a0, vlenb
639; CHECK-NEXT:    slli a0, a0, 2
640; CHECK-NEXT:    addi a0, a0, -64
641; CHECK-NEXT:    li a1, 64
642; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
643; CHECK-NEXT:    vslidedown.vx v8, v8, a0
644; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
645; CHECK-NEXT:    vslideup.vx v8, v12, a1
646; CHECK-NEXT:    ret
647  %res = call <vscale x 32 x i8> @llvm.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 -64)
648  ret <vscale x 32 x i8> %res
649}
650
651define <vscale x 32 x i8> @splice_nxv32i8_offset_max(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) #0 {
652; CHECK-LABEL: splice_nxv32i8_offset_max:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    csrr a0, vlenb
655; CHECK-NEXT:    slli a0, a0, 2
656; CHECK-NEXT:    addi a0, a0, -63
657; CHECK-NEXT:    li a1, 63
658; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
659; CHECK-NEXT:    vslidedown.vx v8, v8, a1
660; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
661; CHECK-NEXT:    vslideup.vx v8, v12, a0
662; CHECK-NEXT:    ret
663  %res = call <vscale x 32 x i8> @llvm.vector.splice.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, i32 63)
664  ret <vscale x 32 x i8> %res
665}
666
667declare <vscale x 64 x i8> @llvm.vector.splice.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, i32)
668
669define <vscale x 64 x i8> @splice_nxv64i8_offset_zero(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
670; CHECK-LABEL: splice_nxv64i8_offset_zero:
671; CHECK:       # %bb.0:
672; CHECK-NEXT:    ret
673  %res = call <vscale x 64 x i8> @llvm.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 0)
674  ret <vscale x 64 x i8> %res
675}
676
677define <vscale x 64 x i8> @splice_nxv64i8_offset_negone(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
678; CHECK-LABEL: splice_nxv64i8_offset_negone:
679; CHECK:       # %bb.0:
680; CHECK-NEXT:    csrr a0, vlenb
681; CHECK-NEXT:    slli a0, a0, 3
682; CHECK-NEXT:    addi a0, a0, -1
683; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
684; CHECK-NEXT:    vslidedown.vx v8, v8, a0
685; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
686; CHECK-NEXT:    vslideup.vi v8, v16, 1
687; CHECK-NEXT:    ret
688  %res = call <vscale x 64 x i8> @llvm.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -1)
689  ret <vscale x 64 x i8> %res
690}
691
692define <vscale x 64 x i8> @splice_nxv64i8_offset_min(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
693; CHECK-LABEL: splice_nxv64i8_offset_min:
694; CHECK:       # %bb.0:
695; CHECK-NEXT:    csrr a0, vlenb
696; CHECK-NEXT:    slli a0, a0, 3
697; CHECK-NEXT:    addi a0, a0, -128
698; CHECK-NEXT:    li a1, 128
699; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
700; CHECK-NEXT:    vslidedown.vx v8, v8, a0
701; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
702; CHECK-NEXT:    vslideup.vx v8, v16, a1
703; CHECK-NEXT:    ret
704  %res = call <vscale x 64 x i8> @llvm.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 -128)
705  ret <vscale x 64 x i8> %res
706}
707
708define <vscale x 64 x i8> @splice_nxv64i8_offset_max(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) #0 {
709; CHECK-LABEL: splice_nxv64i8_offset_max:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    csrr a0, vlenb
712; CHECK-NEXT:    slli a0, a0, 3
713; CHECK-NEXT:    addi a0, a0, -127
714; CHECK-NEXT:    li a1, 127
715; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
716; CHECK-NEXT:    vslidedown.vx v8, v8, a1
717; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
718; CHECK-NEXT:    vslideup.vx v8, v16, a0
719; CHECK-NEXT:    ret
720  %res = call <vscale x 64 x i8> @llvm.vector.splice.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, i32 127)
721  ret <vscale x 64 x i8> %res
722}
723
724declare <vscale x 1 x i16> @llvm.vector.splice.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, i32)
725
726define <vscale x 1 x i16> @splice_nxv1i16_offset_zero(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
727; CHECK-LABEL: splice_nxv1i16_offset_zero:
728; CHECK:       # %bb.0:
729; CHECK-NEXT:    ret
730  %res = call <vscale x 1 x i16> @llvm.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 0)
731  ret <vscale x 1 x i16> %res
732}
733
734define <vscale x 1 x i16> @splice_nxv1i16_offset_negone(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
735; CHECK-LABEL: splice_nxv1i16_offset_negone:
736; CHECK:       # %bb.0:
737; CHECK-NEXT:    csrr a0, vlenb
738; CHECK-NEXT:    srli a0, a0, 3
739; CHECK-NEXT:    addi a0, a0, -1
740; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
741; CHECK-NEXT:    vslidedown.vx v8, v8, a0
742; CHECK-NEXT:    vslideup.vi v8, v9, 1
743; CHECK-NEXT:    ret
744  %res = call <vscale x 1 x i16> @llvm.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -1)
745  ret <vscale x 1 x i16> %res
746}
747
748define <vscale x 1 x i16> @splice_nxv1i16_offset_min(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
749; CHECK-LABEL: splice_nxv1i16_offset_min:
750; CHECK:       # %bb.0:
751; CHECK-NEXT:    csrr a0, vlenb
752; CHECK-NEXT:    srli a0, a0, 3
753; CHECK-NEXT:    addi a0, a0, -2
754; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
755; CHECK-NEXT:    vslidedown.vx v8, v8, a0
756; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
757; CHECK-NEXT:    vslideup.vi v8, v9, 2
758; CHECK-NEXT:    ret
759  %res = call <vscale x 1 x i16> @llvm.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 -2)
760  ret <vscale x 1 x i16> %res
761}
762
763define <vscale x 1 x i16> @splice_nxv1i16_offset_max(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) #0 {
764; CHECK-LABEL: splice_nxv1i16_offset_max:
765; CHECK:       # %bb.0:
766; CHECK-NEXT:    csrr a0, vlenb
767; CHECK-NEXT:    srli a0, a0, 3
768; CHECK-NEXT:    addi a0, a0, -1
769; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
770; CHECK-NEXT:    vslidedown.vi v8, v8, 1
771; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
772; CHECK-NEXT:    vslideup.vx v8, v9, a0
773; CHECK-NEXT:    ret
774  %res = call <vscale x 1 x i16> @llvm.vector.splice.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, i32 1)
775  ret <vscale x 1 x i16> %res
776}
777
778declare <vscale x 2 x i16> @llvm.vector.splice.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, i32)
779
780define <vscale x 2 x i16> @splice_nxv2i16_offset_zero(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
781; CHECK-LABEL: splice_nxv2i16_offset_zero:
782; CHECK:       # %bb.0:
783; CHECK-NEXT:    ret
784  %res = call <vscale x 2 x i16> @llvm.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 0)
785  ret <vscale x 2 x i16> %res
786}
787
788define <vscale x 2 x i16> @splice_nxv2i16_offset_negone(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
789; CHECK-LABEL: splice_nxv2i16_offset_negone:
790; CHECK:       # %bb.0:
791; CHECK-NEXT:    csrr a0, vlenb
792; CHECK-NEXT:    srli a0, a0, 2
793; CHECK-NEXT:    addi a0, a0, -1
794; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
795; CHECK-NEXT:    vslidedown.vx v8, v8, a0
796; CHECK-NEXT:    vslideup.vi v8, v9, 1
797; CHECK-NEXT:    ret
798  %res = call <vscale x 2 x i16> @llvm.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -1)
799  ret <vscale x 2 x i16> %res
800}
801
802define <vscale x 2 x i16> @splice_nxv2i16_offset_min(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
803; CHECK-LABEL: splice_nxv2i16_offset_min:
804; CHECK:       # %bb.0:
805; CHECK-NEXT:    csrr a0, vlenb
806; CHECK-NEXT:    srli a0, a0, 2
807; CHECK-NEXT:    addi a0, a0, -4
808; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
809; CHECK-NEXT:    vslidedown.vx v8, v8, a0
810; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
811; CHECK-NEXT:    vslideup.vi v8, v9, 4
812; CHECK-NEXT:    ret
813  %res = call <vscale x 2 x i16> @llvm.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 -4)
814  ret <vscale x 2 x i16> %res
815}
816
817define <vscale x 2 x i16> @splice_nxv2i16_offset_max(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) #0 {
818; CHECK-LABEL: splice_nxv2i16_offset_max:
819; CHECK:       # %bb.0:
820; CHECK-NEXT:    csrr a0, vlenb
821; CHECK-NEXT:    srli a0, a0, 2
822; CHECK-NEXT:    addi a0, a0, -3
823; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
824; CHECK-NEXT:    vslidedown.vi v8, v8, 3
825; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
826; CHECK-NEXT:    vslideup.vx v8, v9, a0
827; CHECK-NEXT:    ret
828  %res = call <vscale x 2 x i16> @llvm.vector.splice.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, i32 3)
829  ret <vscale x 2 x i16> %res
830}
831
832declare <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, i32)
833
834define <vscale x 4 x i16> @splice_nxv4i16_offset_zero(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
835; CHECK-LABEL: splice_nxv4i16_offset_zero:
836; CHECK:       # %bb.0:
837; CHECK-NEXT:    ret
838  %res = call <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 0)
839  ret <vscale x 4 x i16> %res
840}
841
842define <vscale x 4 x i16> @splice_nxv4i16_offset_negone(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
843; CHECK-LABEL: splice_nxv4i16_offset_negone:
844; CHECK:       # %bb.0:
845; CHECK-NEXT:    csrr a0, vlenb
846; CHECK-NEXT:    srli a0, a0, 1
847; CHECK-NEXT:    addi a0, a0, -1
848; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
849; CHECK-NEXT:    vslidedown.vx v8, v8, a0
850; CHECK-NEXT:    vslideup.vi v8, v9, 1
851; CHECK-NEXT:    ret
852  %res = call <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -1)
853  ret <vscale x 4 x i16> %res
854}
855
856define <vscale x 4 x i16> @splice_nxv4i16_offset_min(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
857; CHECK-LABEL: splice_nxv4i16_offset_min:
858; CHECK:       # %bb.0:
859; CHECK-NEXT:    csrr a0, vlenb
860; CHECK-NEXT:    srli a0, a0, 1
861; CHECK-NEXT:    addi a0, a0, -8
862; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
863; CHECK-NEXT:    vslidedown.vx v8, v8, a0
864; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
865; CHECK-NEXT:    vslideup.vi v8, v9, 8
866; CHECK-NEXT:    ret
867  %res = call <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 -8)
868  ret <vscale x 4 x i16> %res
869}
870
871define <vscale x 4 x i16> @splice_nxv4i16_offset_max(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) #0 {
872; CHECK-LABEL: splice_nxv4i16_offset_max:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    csrr a0, vlenb
875; CHECK-NEXT:    srli a0, a0, 1
876; CHECK-NEXT:    addi a0, a0, -7
877; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
878; CHECK-NEXT:    vslidedown.vi v8, v8, 7
879; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
880; CHECK-NEXT:    vslideup.vx v8, v9, a0
881; CHECK-NEXT:    ret
882  %res = call <vscale x 4 x i16> @llvm.vector.splice.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, i32 7)
883  ret <vscale x 4 x i16> %res
884}
885
886declare <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
887
888define <vscale x 8 x i16> @splice_nxv8i16_offset_zero(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
889; CHECK-LABEL: splice_nxv8i16_offset_zero:
890; CHECK:       # %bb.0:
891; CHECK-NEXT:    ret
892  %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 0)
893  ret <vscale x 8 x i16> %res
894}
895
896define <vscale x 8 x i16> @splice_nxv8i16_offset_negone(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
897; CHECK-LABEL: splice_nxv8i16_offset_negone:
898; CHECK:       # %bb.0:
899; CHECK-NEXT:    csrr a0, vlenb
900; CHECK-NEXT:    addi a0, a0, -1
901; CHECK-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
902; CHECK-NEXT:    vslidedown.vx v8, v8, a0
903; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
904; CHECK-NEXT:    vslideup.vi v8, v10, 1
905; CHECK-NEXT:    ret
906  %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -1)
907  ret <vscale x 8 x i16> %res
908}
909
910define <vscale x 8 x i16> @splice_nxv8i16_offset_min(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
911; CHECK-LABEL: splice_nxv8i16_offset_min:
912; CHECK:       # %bb.0:
913; CHECK-NEXT:    csrr a0, vlenb
914; CHECK-NEXT:    addi a0, a0, -16
915; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
916; CHECK-NEXT:    vslidedown.vx v8, v8, a0
917; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
918; CHECK-NEXT:    vslideup.vi v8, v10, 16
919; CHECK-NEXT:    ret
920  %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -16)
921  ret <vscale x 8 x i16> %res
922}
923
924define <vscale x 8 x i16> @splice_nxv8i16_offset_max(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
925; CHECK-LABEL: splice_nxv8i16_offset_max:
926; CHECK:       # %bb.0:
927; CHECK-NEXT:    csrr a0, vlenb
928; CHECK-NEXT:    addi a0, a0, -15
929; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
930; CHECK-NEXT:    vslidedown.vi v8, v8, 15
931; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
932; CHECK-NEXT:    vslideup.vx v8, v10, a0
933; CHECK-NEXT:    ret
934  %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 15)
935  ret <vscale x 8 x i16> %res
936}
937
938declare <vscale x 16 x i16> @llvm.vector.splice.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, i32)
939
940define <vscale x 16 x i16> @splice_nxv16i16_offset_zero(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
941; CHECK-LABEL: splice_nxv16i16_offset_zero:
942; CHECK:       # %bb.0:
943; CHECK-NEXT:    ret
944  %res = call <vscale x 16 x i16> @llvm.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 0)
945  ret <vscale x 16 x i16> %res
946}
947
948define <vscale x 16 x i16> @splice_nxv16i16_offset_negone(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
949; CHECK-LABEL: splice_nxv16i16_offset_negone:
950; CHECK:       # %bb.0:
951; CHECK-NEXT:    csrr a0, vlenb
952; CHECK-NEXT:    slli a0, a0, 1
953; CHECK-NEXT:    addi a0, a0, -1
954; CHECK-NEXT:    vsetivli zero, 1, e16, m4, ta, ma
955; CHECK-NEXT:    vslidedown.vx v8, v8, a0
956; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
957; CHECK-NEXT:    vslideup.vi v8, v12, 1
958; CHECK-NEXT:    ret
959  %res = call <vscale x 16 x i16> @llvm.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -1)
960  ret <vscale x 16 x i16> %res
961}
962
963define <vscale x 16 x i16> @splice_nxv16i16_offset_min(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
964; CHECK-LABEL: splice_nxv16i16_offset_min:
965; CHECK:       # %bb.0:
966; CHECK-NEXT:    csrr a0, vlenb
967; CHECK-NEXT:    slli a0, a0, 1
968; CHECK-NEXT:    addi a0, a0, -32
969; CHECK-NEXT:    li a1, 32
970; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
971; CHECK-NEXT:    vslidedown.vx v8, v8, a0
972; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
973; CHECK-NEXT:    vslideup.vx v8, v12, a1
974; CHECK-NEXT:    ret
975  %res = call <vscale x 16 x i16> @llvm.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 -32)
976  ret <vscale x 16 x i16> %res
977}
978
979define <vscale x 16 x i16> @splice_nxv16i16_offset_max(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) #0 {
980; CHECK-LABEL: splice_nxv16i16_offset_max:
981; CHECK:       # %bb.0:
982; CHECK-NEXT:    csrr a0, vlenb
983; CHECK-NEXT:    slli a0, a0, 1
984; CHECK-NEXT:    addi a0, a0, -31
985; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
986; CHECK-NEXT:    vslidedown.vi v8, v8, 31
987; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
988; CHECK-NEXT:    vslideup.vx v8, v12, a0
989; CHECK-NEXT:    ret
990  %res = call <vscale x 16 x i16> @llvm.vector.splice.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, i32 31)
991  ret <vscale x 16 x i16> %res
992}
993
994declare <vscale x 32 x i16> @llvm.vector.splice.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, i32)
995
996define <vscale x 32 x i16> @splice_nxv32i16_offset_zero(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
997; CHECK-LABEL: splice_nxv32i16_offset_zero:
998; CHECK:       # %bb.0:
999; CHECK-NEXT:    ret
1000  %res = call <vscale x 32 x i16> @llvm.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 0)
1001  ret <vscale x 32 x i16> %res
1002}
1003
1004define <vscale x 32 x i16> @splice_nxv32i16_offset_negone(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
1005; CHECK-LABEL: splice_nxv32i16_offset_negone:
1006; CHECK:       # %bb.0:
1007; CHECK-NEXT:    csrr a0, vlenb
1008; CHECK-NEXT:    slli a0, a0, 2
1009; CHECK-NEXT:    addi a0, a0, -1
1010; CHECK-NEXT:    vsetivli zero, 1, e16, m8, ta, ma
1011; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1012; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1013; CHECK-NEXT:    vslideup.vi v8, v16, 1
1014; CHECK-NEXT:    ret
1015  %res = call <vscale x 32 x i16> @llvm.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -1)
1016  ret <vscale x 32 x i16> %res
1017}
1018
1019define <vscale x 32 x i16> @splice_nxv32i16_offset_min(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
1020; CHECK-LABEL: splice_nxv32i16_offset_min:
1021; CHECK:       # %bb.0:
1022; CHECK-NEXT:    csrr a0, vlenb
1023; CHECK-NEXT:    slli a0, a0, 2
1024; CHECK-NEXT:    addi a0, a0, -64
1025; CHECK-NEXT:    li a1, 64
1026; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
1027; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1028; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1029; CHECK-NEXT:    vslideup.vx v8, v16, a1
1030; CHECK-NEXT:    ret
1031  %res = call <vscale x 32 x i16> @llvm.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 -64)
1032  ret <vscale x 32 x i16> %res
1033}
1034
1035define <vscale x 32 x i16> @splice_nxv32i16_offset_max(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) #0 {
1036; CHECK-LABEL: splice_nxv32i16_offset_max:
1037; CHECK:       # %bb.0:
1038; CHECK-NEXT:    csrr a0, vlenb
1039; CHECK-NEXT:    slli a0, a0, 2
1040; CHECK-NEXT:    addi a0, a0, -63
1041; CHECK-NEXT:    li a1, 63
1042; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
1043; CHECK-NEXT:    vslidedown.vx v8, v8, a1
1044; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
1045; CHECK-NEXT:    vslideup.vx v8, v16, a0
1046; CHECK-NEXT:    ret
1047  %res = call <vscale x 32 x i16> @llvm.vector.splice.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, i32 63)
1048  ret <vscale x 32 x i16> %res
1049}
1050
1051declare <vscale x 1 x i32> @llvm.vector.splice.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, i32)
1052
1053define <vscale x 1 x i32> @splice_nxv1i32_offset_zero(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
1054; CHECK-LABEL: splice_nxv1i32_offset_zero:
1055; CHECK:       # %bb.0:
1056; CHECK-NEXT:    ret
1057  %res = call <vscale x 1 x i32> @llvm.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 0)
1058  ret <vscale x 1 x i32> %res
1059}
1060
1061define <vscale x 1 x i32> @splice_nxv1i32_offset_negone(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
1062; CHECK-LABEL: splice_nxv1i32_offset_negone:
1063; CHECK:       # %bb.0:
1064; CHECK-NEXT:    csrr a0, vlenb
1065; CHECK-NEXT:    srli a0, a0, 3
1066; CHECK-NEXT:    addi a0, a0, -1
1067; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
1068; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1069; CHECK-NEXT:    vslideup.vi v8, v9, 1
1070; CHECK-NEXT:    ret
1071  %res = call <vscale x 1 x i32> @llvm.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -1)
1072  ret <vscale x 1 x i32> %res
1073}
1074
1075define <vscale x 1 x i32> @splice_nxv1i32_offset_min(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
1076; CHECK-LABEL: splice_nxv1i32_offset_min:
1077; CHECK:       # %bb.0:
1078; CHECK-NEXT:    csrr a0, vlenb
1079; CHECK-NEXT:    srli a0, a0, 3
1080; CHECK-NEXT:    addi a0, a0, -2
1081; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1082; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1083; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
1084; CHECK-NEXT:    vslideup.vi v8, v9, 2
1085; CHECK-NEXT:    ret
1086  %res = call <vscale x 1 x i32> @llvm.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 -2)
1087  ret <vscale x 1 x i32> %res
1088}
1089
1090define <vscale x 1 x i32> @splice_nxv1i32_offset_max(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) #0 {
1091; CHECK-LABEL: splice_nxv1i32_offset_max:
1092; CHECK:       # %bb.0:
1093; CHECK-NEXT:    csrr a0, vlenb
1094; CHECK-NEXT:    srli a0, a0, 3
1095; CHECK-NEXT:    addi a0, a0, -1
1096; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
1097; CHECK-NEXT:    vslidedown.vi v8, v8, 1
1098; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
1099; CHECK-NEXT:    vslideup.vx v8, v9, a0
1100; CHECK-NEXT:    ret
1101  %res = call <vscale x 1 x i32> @llvm.vector.splice.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, i32 1)
1102  ret <vscale x 1 x i32> %res
1103}
1104
1105declare <vscale x 2 x i32> @llvm.vector.splice.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i32)
1106
1107define <vscale x 2 x i32> @splice_nxv2i32_offset_zero(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
1108; CHECK-LABEL: splice_nxv2i32_offset_zero:
1109; CHECK:       # %bb.0:
1110; CHECK-NEXT:    ret
1111  %res = call <vscale x 2 x i32> @llvm.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 0)
1112  ret <vscale x 2 x i32> %res
1113}
1114
1115define <vscale x 2 x i32> @splice_nxv2i32_offset_negone(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
1116; CHECK-LABEL: splice_nxv2i32_offset_negone:
1117; CHECK:       # %bb.0:
1118; CHECK-NEXT:    csrr a0, vlenb
1119; CHECK-NEXT:    srli a0, a0, 2
1120; CHECK-NEXT:    addi a0, a0, -1
1121; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
1122; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1123; CHECK-NEXT:    vslideup.vi v8, v9, 1
1124; CHECK-NEXT:    ret
1125  %res = call <vscale x 2 x i32> @llvm.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -1)
1126  ret <vscale x 2 x i32> %res
1127}
1128
1129define <vscale x 2 x i32> @splice_nxv2i32_offset_min(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
1130; CHECK-LABEL: splice_nxv2i32_offset_min:
1131; CHECK:       # %bb.0:
1132; CHECK-NEXT:    csrr a0, vlenb
1133; CHECK-NEXT:    srli a0, a0, 2
1134; CHECK-NEXT:    addi a0, a0, -4
1135; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1136; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1137; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
1138; CHECK-NEXT:    vslideup.vi v8, v9, 4
1139; CHECK-NEXT:    ret
1140  %res = call <vscale x 2 x i32> @llvm.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 -4)
1141  ret <vscale x 2 x i32> %res
1142}
1143
1144define <vscale x 2 x i32> @splice_nxv2i32_offset_max(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) #0 {
1145; CHECK-LABEL: splice_nxv2i32_offset_max:
1146; CHECK:       # %bb.0:
1147; CHECK-NEXT:    csrr a0, vlenb
1148; CHECK-NEXT:    srli a0, a0, 2
1149; CHECK-NEXT:    addi a0, a0, -3
1150; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
1151; CHECK-NEXT:    vslidedown.vi v8, v8, 3
1152; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
1153; CHECK-NEXT:    vslideup.vx v8, v9, a0
1154; CHECK-NEXT:    ret
1155  %res = call <vscale x 2 x i32> @llvm.vector.splice.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, i32 3)
1156  ret <vscale x 2 x i32> %res
1157}
1158
1159declare <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
1160
1161define <vscale x 4 x i32> @splice_nxv4i32_offset_zero(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
1162; CHECK-LABEL: splice_nxv4i32_offset_zero:
1163; CHECK:       # %bb.0:
1164; CHECK-NEXT:    ret
1165  %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 0)
1166  ret <vscale x 4 x i32> %res
1167}
1168
1169define <vscale x 4 x i32> @splice_nxv4i32_offset_negone(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
1170; CHECK-LABEL: splice_nxv4i32_offset_negone:
1171; CHECK:       # %bb.0:
1172; CHECK-NEXT:    csrr a0, vlenb
1173; CHECK-NEXT:    srli a0, a0, 1
1174; CHECK-NEXT:    addi a0, a0, -1
1175; CHECK-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
1176; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1177; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1178; CHECK-NEXT:    vslideup.vi v8, v10, 1
1179; CHECK-NEXT:    ret
1180  %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -1)
1181  ret <vscale x 4 x i32> %res
1182}
1183
1184define <vscale x 4 x i32> @splice_nxv4i32_offset_min(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
1185; CHECK-LABEL: splice_nxv4i32_offset_min:
1186; CHECK:       # %bb.0:
1187; CHECK-NEXT:    csrr a0, vlenb
1188; CHECK-NEXT:    srli a0, a0, 1
1189; CHECK-NEXT:    addi a0, a0, -8
1190; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1191; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1192; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
1193; CHECK-NEXT:    vslideup.vi v8, v10, 8
1194; CHECK-NEXT:    ret
1195  %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -8)
1196  ret <vscale x 4 x i32> %res
1197}
1198
1199define <vscale x 4 x i32> @splice_nxv4i32_offset_max(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
1200; CHECK-LABEL: splice_nxv4i32_offset_max:
1201; CHECK:       # %bb.0:
1202; CHECK-NEXT:    csrr a0, vlenb
1203; CHECK-NEXT:    srli a0, a0, 1
1204; CHECK-NEXT:    addi a0, a0, -7
1205; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
1206; CHECK-NEXT:    vslidedown.vi v8, v8, 7
1207; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
1208; CHECK-NEXT:    vslideup.vx v8, v10, a0
1209; CHECK-NEXT:    ret
1210  %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 7)
1211  ret <vscale x 4 x i32> %res
1212}
1213
1214declare <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32)
1215
1216define <vscale x 8 x i32> @splice_nxv8i32_offset_zero(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
1217; CHECK-LABEL: splice_nxv8i32_offset_zero:
1218; CHECK:       # %bb.0:
1219; CHECK-NEXT:    ret
1220  %res = call <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 0)
1221  ret <vscale x 8 x i32> %res
1222}
1223
1224define <vscale x 8 x i32> @splice_nxv8i32_offset_negone(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
1225; CHECK-LABEL: splice_nxv8i32_offset_negone:
1226; CHECK:       # %bb.0:
1227; CHECK-NEXT:    csrr a0, vlenb
1228; CHECK-NEXT:    addi a0, a0, -1
1229; CHECK-NEXT:    vsetivli zero, 1, e32, m4, ta, ma
1230; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1231; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1232; CHECK-NEXT:    vslideup.vi v8, v12, 1
1233; CHECK-NEXT:    ret
1234  %res = call <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -1)
1235  ret <vscale x 8 x i32> %res
1236}
1237
1238define <vscale x 8 x i32> @splice_nxv8i32_offset_min(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
1239; CHECK-LABEL: splice_nxv8i32_offset_min:
1240; CHECK:       # %bb.0:
1241; CHECK-NEXT:    csrr a0, vlenb
1242; CHECK-NEXT:    addi a0, a0, -16
1243; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1244; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1245; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1246; CHECK-NEXT:    vslideup.vi v8, v12, 16
1247; CHECK-NEXT:    ret
1248  %res = call <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -16)
1249  ret <vscale x 8 x i32> %res
1250}
1251
1252define <vscale x 8 x i32> @splice_nxv8i32_offset_max(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
1253; CHECK-LABEL: splice_nxv8i32_offset_max:
1254; CHECK:       # %bb.0:
1255; CHECK-NEXT:    csrr a0, vlenb
1256; CHECK-NEXT:    addi a0, a0, -15
1257; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1258; CHECK-NEXT:    vslidedown.vi v8, v8, 15
1259; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1260; CHECK-NEXT:    vslideup.vx v8, v12, a0
1261; CHECK-NEXT:    ret
1262  %res = call <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 15)
1263  ret <vscale x 8 x i32> %res
1264}
1265
1266declare <vscale x 16 x i32> @llvm.vector.splice.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, i32)
1267
1268define <vscale x 16 x i32> @splice_nxv16i32_offset_zero(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
1269; CHECK-LABEL: splice_nxv16i32_offset_zero:
1270; CHECK:       # %bb.0:
1271; CHECK-NEXT:    ret
1272  %res = call <vscale x 16 x i32> @llvm.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 0)
1273  ret <vscale x 16 x i32> %res
1274}
1275
1276define <vscale x 16 x i32> @splice_nxv16i32_offset_negone(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
1277; CHECK-LABEL: splice_nxv16i32_offset_negone:
1278; CHECK:       # %bb.0:
1279; CHECK-NEXT:    csrr a0, vlenb
1280; CHECK-NEXT:    slli a0, a0, 1
1281; CHECK-NEXT:    addi a0, a0, -1
1282; CHECK-NEXT:    vsetivli zero, 1, e32, m8, ta, ma
1283; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1284; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1285; CHECK-NEXT:    vslideup.vi v8, v16, 1
1286; CHECK-NEXT:    ret
1287  %res = call <vscale x 16 x i32> @llvm.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -1)
1288  ret <vscale x 16 x i32> %res
1289}
1290
1291define <vscale x 16 x i32> @splice_nxv16i32_offset_min(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
1292; CHECK-LABEL: splice_nxv16i32_offset_min:
1293; CHECK:       # %bb.0:
1294; CHECK-NEXT:    csrr a0, vlenb
1295; CHECK-NEXT:    slli a0, a0, 1
1296; CHECK-NEXT:    addi a0, a0, -32
1297; CHECK-NEXT:    li a1, 32
1298; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
1299; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1300; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
1301; CHECK-NEXT:    vslideup.vx v8, v16, a1
1302; CHECK-NEXT:    ret
1303  %res = call <vscale x 16 x i32> @llvm.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 -32)
1304  ret <vscale x 16 x i32> %res
1305}
1306
1307define <vscale x 16 x i32> @splice_nxv16i32_offset_max(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) #0 {
1308; CHECK-LABEL: splice_nxv16i32_offset_max:
1309; CHECK:       # %bb.0:
1310; CHECK-NEXT:    csrr a0, vlenb
1311; CHECK-NEXT:    slli a0, a0, 1
1312; CHECK-NEXT:    addi a0, a0, -31
1313; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1314; CHECK-NEXT:    vslidedown.vi v8, v8, 31
1315; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
1316; CHECK-NEXT:    vslideup.vx v8, v16, a0
1317; CHECK-NEXT:    ret
1318  %res = call <vscale x 16 x i32> @llvm.vector.splice.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, i32 31)
1319  ret <vscale x 16 x i32> %res
1320}
1321
1322declare <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i32)
1323
1324define <vscale x 1 x i64> @splice_nxv1i64_offset_zero(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
1325; CHECK-LABEL: splice_nxv1i64_offset_zero:
1326; CHECK:       # %bb.0:
1327; CHECK-NEXT:    ret
1328  %res = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 0)
1329  ret <vscale x 1 x i64> %res
1330}
1331
1332define <vscale x 1 x i64> @splice_nxv1i64_offset_negone(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
1333; CHECK-LABEL: splice_nxv1i64_offset_negone:
1334; CHECK:       # %bb.0:
1335; CHECK-NEXT:    csrr a0, vlenb
1336; CHECK-NEXT:    srli a0, a0, 3
1337; CHECK-NEXT:    addi a0, a0, -1
1338; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1339; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1340; CHECK-NEXT:    vslideup.vi v8, v9, 1
1341; CHECK-NEXT:    ret
1342  %res = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -1)
1343  ret <vscale x 1 x i64> %res
1344}
1345
1346define <vscale x 1 x i64> @splice_nxv1i64_offset_min(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
1347; CHECK-LABEL: splice_nxv1i64_offset_min:
1348; CHECK:       # %bb.0:
1349; CHECK-NEXT:    csrr a0, vlenb
1350; CHECK-NEXT:    srli a0, a0, 3
1351; CHECK-NEXT:    addi a0, a0, -2
1352; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1353; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1354; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
1355; CHECK-NEXT:    vslideup.vi v8, v9, 2
1356; CHECK-NEXT:    ret
1357  %res = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 -2)
1358  ret <vscale x 1 x i64> %res
1359}
1360
1361define <vscale x 1 x i64> @splice_nxv1i64_offset_max(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) #0 {
1362; CHECK-LABEL: splice_nxv1i64_offset_max:
1363; CHECK:       # %bb.0:
1364; CHECK-NEXT:    csrr a0, vlenb
1365; CHECK-NEXT:    srli a0, a0, 3
1366; CHECK-NEXT:    addi a0, a0, -1
1367; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1368; CHECK-NEXT:    vslidedown.vi v8, v8, 1
1369; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1370; CHECK-NEXT:    vslideup.vx v8, v9, a0
1371; CHECK-NEXT:    ret
1372  %res = call <vscale x 1 x i64> @llvm.vector.splice.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, i32 1)
1373  ret <vscale x 1 x i64> %res
1374}
1375
1376declare <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
1377
1378define <vscale x 2 x i64> @splice_nxv2i64_offset_zero(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
1379; CHECK-LABEL: splice_nxv2i64_offset_zero:
1380; CHECK:       # %bb.0:
1381; CHECK-NEXT:    ret
1382  %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 0)
1383  ret <vscale x 2 x i64> %res
1384}
1385
1386define <vscale x 2 x i64> @splice_nxv2i64_offset_negone(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
1387; CHECK-LABEL: splice_nxv2i64_offset_negone:
1388; CHECK:       # %bb.0:
1389; CHECK-NEXT:    csrr a0, vlenb
1390; CHECK-NEXT:    srli a0, a0, 2
1391; CHECK-NEXT:    addi a0, a0, -1
1392; CHECK-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
1393; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1394; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1395; CHECK-NEXT:    vslideup.vi v8, v10, 1
1396; CHECK-NEXT:    ret
1397  %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -1)
1398  ret <vscale x 2 x i64> %res
1399}
1400
1401define <vscale x 2 x i64> @splice_nxv2i64_offset_min(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
1402; CHECK-LABEL: splice_nxv2i64_offset_min:
1403; CHECK:       # %bb.0:
1404; CHECK-NEXT:    csrr a0, vlenb
1405; CHECK-NEXT:    srli a0, a0, 2
1406; CHECK-NEXT:    addi a0, a0, -4
1407; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1408; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1409; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1410; CHECK-NEXT:    vslideup.vi v8, v10, 4
1411; CHECK-NEXT:    ret
1412  %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -4)
1413  ret <vscale x 2 x i64> %res
1414}
1415
1416define <vscale x 2 x i64> @splice_nxv2i64_offset_max(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
1417; CHECK-LABEL: splice_nxv2i64_offset_max:
1418; CHECK:       # %bb.0:
1419; CHECK-NEXT:    csrr a0, vlenb
1420; CHECK-NEXT:    srli a0, a0, 2
1421; CHECK-NEXT:    addi a0, a0, -3
1422; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1423; CHECK-NEXT:    vslidedown.vi v8, v8, 3
1424; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1425; CHECK-NEXT:    vslideup.vx v8, v10, a0
1426; CHECK-NEXT:    ret
1427  %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 3)
1428  ret <vscale x 2 x i64> %res
1429}
1430
1431declare <vscale x 4 x i64> @llvm.vector.splice.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, i32)
1432
1433define <vscale x 4 x i64> @splice_nxv4i64_offset_zero(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
1434; CHECK-LABEL: splice_nxv4i64_offset_zero:
1435; CHECK:       # %bb.0:
1436; CHECK-NEXT:    ret
1437  %res = call <vscale x 4 x i64> @llvm.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 0)
1438  ret <vscale x 4 x i64> %res
1439}
1440
1441define <vscale x 4 x i64> @splice_nxv4i64_offset_negone(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
1442; CHECK-LABEL: splice_nxv4i64_offset_negone:
1443; CHECK:       # %bb.0:
1444; CHECK-NEXT:    csrr a0, vlenb
1445; CHECK-NEXT:    srli a0, a0, 1
1446; CHECK-NEXT:    addi a0, a0, -1
1447; CHECK-NEXT:    vsetivli zero, 1, e64, m4, ta, ma
1448; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1449; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1450; CHECK-NEXT:    vslideup.vi v8, v12, 1
1451; CHECK-NEXT:    ret
1452  %res = call <vscale x 4 x i64> @llvm.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -1)
1453  ret <vscale x 4 x i64> %res
1454}
1455
1456define <vscale x 4 x i64> @splice_nxv4i64_offset_min(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
1457; CHECK-LABEL: splice_nxv4i64_offset_min:
1458; CHECK:       # %bb.0:
1459; CHECK-NEXT:    csrr a0, vlenb
1460; CHECK-NEXT:    srli a0, a0, 1
1461; CHECK-NEXT:    addi a0, a0, -8
1462; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1463; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1464; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1465; CHECK-NEXT:    vslideup.vi v8, v12, 8
1466; CHECK-NEXT:    ret
1467  %res = call <vscale x 4 x i64> @llvm.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 -8)
1468  ret <vscale x 4 x i64> %res
1469}
1470
1471define <vscale x 4 x i64> @splice_nxv4i64_offset_max(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) #0 {
1472; CHECK-LABEL: splice_nxv4i64_offset_max:
1473; CHECK:       # %bb.0:
1474; CHECK-NEXT:    csrr a0, vlenb
1475; CHECK-NEXT:    srli a0, a0, 1
1476; CHECK-NEXT:    addi a0, a0, -7
1477; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1478; CHECK-NEXT:    vslidedown.vi v8, v8, 7
1479; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1480; CHECK-NEXT:    vslideup.vx v8, v12, a0
1481; CHECK-NEXT:    ret
1482  %res = call <vscale x 4 x i64> @llvm.vector.splice.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, i32 7)
1483  ret <vscale x 4 x i64> %res
1484}
1485
1486declare <vscale x 8 x i64> @llvm.vector.splice.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, i32)
1487
1488define <vscale x 8 x i64> @splice_nxv8i64_offset_zero(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
1489; CHECK-LABEL: splice_nxv8i64_offset_zero:
1490; CHECK:       # %bb.0:
1491; CHECK-NEXT:    ret
1492  %res = call <vscale x 8 x i64> @llvm.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 0)
1493  ret <vscale x 8 x i64> %res
1494}
1495
1496define <vscale x 8 x i64> @splice_nxv8i64_offset_negone(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
1497; CHECK-LABEL: splice_nxv8i64_offset_negone:
1498; CHECK:       # %bb.0:
1499; CHECK-NEXT:    csrr a0, vlenb
1500; CHECK-NEXT:    addi a0, a0, -1
1501; CHECK-NEXT:    vsetivli zero, 1, e64, m8, ta, ma
1502; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1503; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1504; CHECK-NEXT:    vslideup.vi v8, v16, 1
1505; CHECK-NEXT:    ret
1506  %res = call <vscale x 8 x i64> @llvm.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -1)
1507  ret <vscale x 8 x i64> %res
1508}
1509
1510define <vscale x 8 x i64> @splice_nxv8i64_offset_min(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
1511; CHECK-LABEL: splice_nxv8i64_offset_min:
1512; CHECK:       # %bb.0:
1513; CHECK-NEXT:    csrr a0, vlenb
1514; CHECK-NEXT:    addi a0, a0, -16
1515; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1516; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1517; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1518; CHECK-NEXT:    vslideup.vi v8, v16, 16
1519; CHECK-NEXT:    ret
1520  %res = call <vscale x 8 x i64> @llvm.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 -16)
1521  ret <vscale x 8 x i64> %res
1522}
1523
1524define <vscale x 8 x i64> @splice_nxv8i64_offset_max(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) #0 {
1525; CHECK-LABEL: splice_nxv8i64_offset_max:
1526; CHECK:       # %bb.0:
1527; CHECK-NEXT:    csrr a0, vlenb
1528; CHECK-NEXT:    addi a0, a0, -15
1529; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1530; CHECK-NEXT:    vslidedown.vi v8, v8, 15
1531; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1532; CHECK-NEXT:    vslideup.vx v8, v16, a0
1533; CHECK-NEXT:    ret
1534  %res = call <vscale x 8 x i64> @llvm.vector.splice.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, i32 15)
1535  ret <vscale x 8 x i64> %res
1536}
1537
1538declare <vscale x 1 x bfloat> @llvm.vector.splice.nxv1bf16(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i32)
1539
1540define <vscale x 1 x bfloat> @splice_nxv1bf16_offset_zero(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) #0 {
1541; CHECK-LABEL: splice_nxv1bf16_offset_zero:
1542; CHECK:       # %bb.0:
1543; CHECK-NEXT:    ret
1544  %res = call <vscale x 1 x bfloat> @llvm.vector.splice.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, i32 0)
1545  ret <vscale x 1 x bfloat> %res
1546}
1547
1548define <vscale x 1 x bfloat> @splice_nxv1bf16_offset_negone(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) #0 {
1549; CHECK-LABEL: splice_nxv1bf16_offset_negone:
1550; CHECK:       # %bb.0:
1551; CHECK-NEXT:    csrr a0, vlenb
1552; CHECK-NEXT:    srli a0, a0, 3
1553; CHECK-NEXT:    addi a0, a0, -1
1554; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
1555; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1556; CHECK-NEXT:    vslideup.vi v8, v9, 1
1557; CHECK-NEXT:    ret
1558  %res = call <vscale x 1 x bfloat> @llvm.vector.splice.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, i32 -1)
1559  ret <vscale x 1 x bfloat> %res
1560}
1561
1562define <vscale x 1 x bfloat> @splice_nxv1bf16_offset_min(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) #0 {
1563; CHECK-LABEL: splice_nxv1bf16_offset_min:
1564; CHECK:       # %bb.0:
1565; CHECK-NEXT:    csrr a0, vlenb
1566; CHECK-NEXT:    srli a0, a0, 3
1567; CHECK-NEXT:    addi a0, a0, -2
1568; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
1569; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1570; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
1571; CHECK-NEXT:    vslideup.vi v8, v9, 2
1572; CHECK-NEXT:    ret
1573  %res = call <vscale x 1 x bfloat> @llvm.vector.splice.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, i32 -2)
1574  ret <vscale x 1 x bfloat> %res
1575}
1576
1577define <vscale x 1 x bfloat> @splice_nxv1bf16_offset_max(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) #0 {
1578; CHECK-LABEL: splice_nxv1bf16_offset_max:
1579; CHECK:       # %bb.0:
1580; CHECK-NEXT:    csrr a0, vlenb
1581; CHECK-NEXT:    srli a0, a0, 3
1582; CHECK-NEXT:    addi a0, a0, -1
1583; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
1584; CHECK-NEXT:    vslidedown.vi v8, v8, 1
1585; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
1586; CHECK-NEXT:    vslideup.vx v8, v9, a0
1587; CHECK-NEXT:    ret
1588  %res = call <vscale x 1 x bfloat> @llvm.vector.splice.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b, i32 1)
1589  ret <vscale x 1 x bfloat> %res
1590}
1591
1592declare <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i32)
1593
1594define <vscale x 2 x bfloat> @splice_nxv2bf16_offset_zero(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {
1595; CHECK-LABEL: splice_nxv2bf16_offset_zero:
1596; CHECK:       # %bb.0:
1597; CHECK-NEXT:    ret
1598  %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 0)
1599  ret <vscale x 2 x bfloat> %res
1600}
1601
1602define <vscale x 2 x bfloat> @splice_nxv2bf16_offset_negone(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {
1603; CHECK-LABEL: splice_nxv2bf16_offset_negone:
1604; CHECK:       # %bb.0:
1605; CHECK-NEXT:    csrr a0, vlenb
1606; CHECK-NEXT:    srli a0, a0, 2
1607; CHECK-NEXT:    addi a0, a0, -1
1608; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
1609; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1610; CHECK-NEXT:    vslideup.vi v8, v9, 1
1611; CHECK-NEXT:    ret
1612  %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 -1)
1613  ret <vscale x 2 x bfloat> %res
1614}
1615
1616define <vscale x 2 x bfloat> @splice_nxv2bf16_offset_min(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {
1617; CHECK-LABEL: splice_nxv2bf16_offset_min:
1618; CHECK:       # %bb.0:
1619; CHECK-NEXT:    csrr a0, vlenb
1620; CHECK-NEXT:    srli a0, a0, 2
1621; CHECK-NEXT:    addi a0, a0, -4
1622; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
1623; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1624; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1625; CHECK-NEXT:    vslideup.vi v8, v9, 4
1626; CHECK-NEXT:    ret
1627  %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 -4)
1628  ret <vscale x 2 x bfloat> %res
1629}
1630
1631define <vscale x 2 x bfloat> @splice_nxv2bf16_offset_max(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {
1632; CHECK-LABEL: splice_nxv2bf16_offset_max:
1633; CHECK:       # %bb.0:
1634; CHECK-NEXT:    csrr a0, vlenb
1635; CHECK-NEXT:    srli a0, a0, 2
1636; CHECK-NEXT:    addi a0, a0, -3
1637; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
1638; CHECK-NEXT:    vslidedown.vi v8, v8, 3
1639; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
1640; CHECK-NEXT:    vslideup.vx v8, v9, a0
1641; CHECK-NEXT:    ret
1642  %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 3)
1643  ret <vscale x 2 x bfloat> %res
1644}
1645
1646declare <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i32)
1647
1648define <vscale x 4 x bfloat> @splice_nxv4bf16_offset_zero(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {
1649; CHECK-LABEL: splice_nxv4bf16_offset_zero:
1650; CHECK:       # %bb.0:
1651; CHECK-NEXT:    ret
1652  %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 0)
1653  ret <vscale x 4 x bfloat> %res
1654}
1655
1656define <vscale x 4 x bfloat> @splice_nxv4bf16_offset_negone(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {
1657; CHECK-LABEL: splice_nxv4bf16_offset_negone:
1658; CHECK:       # %bb.0:
1659; CHECK-NEXT:    csrr a0, vlenb
1660; CHECK-NEXT:    srli a0, a0, 1
1661; CHECK-NEXT:    addi a0, a0, -1
1662; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
1663; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1664; CHECK-NEXT:    vslideup.vi v8, v9, 1
1665; CHECK-NEXT:    ret
1666  %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 -1)
1667  ret <vscale x 4 x bfloat> %res
1668}
1669
1670define <vscale x 4 x bfloat> @splice_nxv4bf16_offset_min(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {
1671; CHECK-LABEL: splice_nxv4bf16_offset_min:
1672; CHECK:       # %bb.0:
1673; CHECK-NEXT:    csrr a0, vlenb
1674; CHECK-NEXT:    srli a0, a0, 1
1675; CHECK-NEXT:    addi a0, a0, -8
1676; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
1677; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1678; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
1679; CHECK-NEXT:    vslideup.vi v8, v9, 8
1680; CHECK-NEXT:    ret
1681  %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 -8)
1682  ret <vscale x 4 x bfloat> %res
1683}
1684
1685define <vscale x 4 x bfloat> @splice_nxv4bf16_offset_max(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {
1686; CHECK-LABEL: splice_nxv4bf16_offset_max:
1687; CHECK:       # %bb.0:
1688; CHECK-NEXT:    csrr a0, vlenb
1689; CHECK-NEXT:    srli a0, a0, 1
1690; CHECK-NEXT:    addi a0, a0, -7
1691; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
1692; CHECK-NEXT:    vslidedown.vi v8, v8, 7
1693; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
1694; CHECK-NEXT:    vslideup.vx v8, v9, a0
1695; CHECK-NEXT:    ret
1696  %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 7)
1697  ret <vscale x 4 x bfloat> %res
1698}
1699
1700declare <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
1701
1702define <vscale x 8 x bfloat> @splice_nxv8bf16_offset_zero(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
1703; CHECK-LABEL: splice_nxv8bf16_offset_zero:
1704; CHECK:       # %bb.0:
1705; CHECK-NEXT:    ret
1706  %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 0)
1707  ret <vscale x 8 x bfloat> %res
1708}
1709
1710define <vscale x 8 x bfloat> @splice_nxv8bf16_offset_negone(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
1711; CHECK-LABEL: splice_nxv8bf16_offset_negone:
1712; CHECK:       # %bb.0:
1713; CHECK-NEXT:    csrr a0, vlenb
1714; CHECK-NEXT:    addi a0, a0, -1
1715; CHECK-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
1716; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1717; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
1718; CHECK-NEXT:    vslideup.vi v8, v10, 1
1719; CHECK-NEXT:    ret
1720  %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 -1)
1721  ret <vscale x 8 x bfloat> %res
1722}
1723
1724define <vscale x 8 x bfloat> @splice_nxv8bf16_offset_min(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
1725; CHECK-LABEL: splice_nxv8bf16_offset_min:
1726; CHECK:       # %bb.0:
1727; CHECK-NEXT:    csrr a0, vlenb
1728; CHECK-NEXT:    addi a0, a0, -16
1729; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
1730; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1731; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
1732; CHECK-NEXT:    vslideup.vi v8, v10, 16
1733; CHECK-NEXT:    ret
1734  %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 -16)
1735  ret <vscale x 8 x bfloat> %res
1736}
1737
1738define <vscale x 8 x bfloat> @splice_nxv8bf16_offset_max(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {
1739; CHECK-LABEL: splice_nxv8bf16_offset_max:
1740; CHECK:       # %bb.0:
1741; CHECK-NEXT:    csrr a0, vlenb
1742; CHECK-NEXT:    addi a0, a0, -15
1743; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
1744; CHECK-NEXT:    vslidedown.vi v8, v8, 15
1745; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
1746; CHECK-NEXT:    vslideup.vx v8, v10, a0
1747; CHECK-NEXT:    ret
1748  %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 15)
1749  ret <vscale x 8 x bfloat> %res
1750}
1751
1752declare <vscale x 16 x bfloat> @llvm.vector.splice.nxv16bf16(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i32)
1753
1754define <vscale x 16 x bfloat> @splice_nxv16bf16_offset_zero(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) #0 {
1755; CHECK-LABEL: splice_nxv16bf16_offset_zero:
1756; CHECK:       # %bb.0:
1757; CHECK-NEXT:    ret
1758  %res = call <vscale x 16 x bfloat> @llvm.vector.splice.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b, i32 0)
1759  ret <vscale x 16 x bfloat> %res
1760}
1761
1762define <vscale x 16 x bfloat> @splice_nxv16bf16_offset_negone(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) #0 {
1763; CHECK-LABEL: splice_nxv16bf16_offset_negone:
1764; CHECK:       # %bb.0:
1765; CHECK-NEXT:    csrr a0, vlenb
1766; CHECK-NEXT:    slli a0, a0, 1
1767; CHECK-NEXT:    addi a0, a0, -1
1768; CHECK-NEXT:    vsetivli zero, 1, e16, m4, ta, ma
1769; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1770; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
1771; CHECK-NEXT:    vslideup.vi v8, v12, 1
1772; CHECK-NEXT:    ret
1773  %res = call <vscale x 16 x bfloat> @llvm.vector.splice.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b, i32 -1)
1774  ret <vscale x 16 x bfloat> %res
1775}
1776
1777define <vscale x 16 x bfloat> @splice_nxv16bf16_offset_min(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) #0 {
1778; CHECK-LABEL: splice_nxv16bf16_offset_min:
1779; CHECK:       # %bb.0:
1780; CHECK-NEXT:    csrr a0, vlenb
1781; CHECK-NEXT:    slli a0, a0, 1
1782; CHECK-NEXT:    addi a0, a0, -32
1783; CHECK-NEXT:    li a1, 32
1784; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
1785; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1786; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
1787; CHECK-NEXT:    vslideup.vx v8, v12, a1
1788; CHECK-NEXT:    ret
1789  %res = call <vscale x 16 x bfloat> @llvm.vector.splice.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b, i32 -32)
1790  ret <vscale x 16 x bfloat> %res
1791}
1792
1793define <vscale x 16 x bfloat> @splice_nxv16bf16_offset_max(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) #0 {
1794; CHECK-LABEL: splice_nxv16bf16_offset_max:
1795; CHECK:       # %bb.0:
1796; CHECK-NEXT:    csrr a0, vlenb
1797; CHECK-NEXT:    slli a0, a0, 1
1798; CHECK-NEXT:    addi a0, a0, -31
1799; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1800; CHECK-NEXT:    vslidedown.vi v8, v8, 31
1801; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
1802; CHECK-NEXT:    vslideup.vx v8, v12, a0
1803; CHECK-NEXT:    ret
1804  %res = call <vscale x 16 x bfloat> @llvm.vector.splice.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b, i32 31)
1805  ret <vscale x 16 x bfloat> %res
1806}
1807
1808declare <vscale x 32 x bfloat> @llvm.vector.splice.nxv32bf16(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i32)
1809
1810define <vscale x 32 x bfloat> @splice_nxv32bf16_offset_zero(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) #0 {
1811; CHECK-LABEL: splice_nxv32bf16_offset_zero:
1812; CHECK:       # %bb.0:
1813; CHECK-NEXT:    ret
1814  %res = call <vscale x 32 x bfloat> @llvm.vector.splice.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b, i32 0)
1815  ret <vscale x 32 x bfloat> %res
1816}
1817
1818define <vscale x 32 x bfloat> @splice_nxv32bf16_offset_negone(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) #0 {
1819; CHECK-LABEL: splice_nxv32bf16_offset_negone:
1820; CHECK:       # %bb.0:
1821; CHECK-NEXT:    csrr a0, vlenb
1822; CHECK-NEXT:    slli a0, a0, 2
1823; CHECK-NEXT:    addi a0, a0, -1
1824; CHECK-NEXT:    vsetivli zero, 1, e16, m8, ta, ma
1825; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1826; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1827; CHECK-NEXT:    vslideup.vi v8, v16, 1
1828; CHECK-NEXT:    ret
1829  %res = call <vscale x 32 x bfloat> @llvm.vector.splice.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b, i32 -1)
1830  ret <vscale x 32 x bfloat> %res
1831}
1832
1833define <vscale x 32 x bfloat> @splice_nxv32bf16_offset_min(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) #0 {
1834; CHECK-LABEL: splice_nxv32bf16_offset_min:
1835; CHECK:       # %bb.0:
1836; CHECK-NEXT:    csrr a0, vlenb
1837; CHECK-NEXT:    slli a0, a0, 2
1838; CHECK-NEXT:    addi a0, a0, -64
1839; CHECK-NEXT:    li a1, 64
1840; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
1841; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1842; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
1843; CHECK-NEXT:    vslideup.vx v8, v16, a1
1844; CHECK-NEXT:    ret
1845  %res = call <vscale x 32 x bfloat> @llvm.vector.splice.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b, i32 -64)
1846  ret <vscale x 32 x bfloat> %res
1847}
1848
1849define <vscale x 32 x bfloat> @splice_nxv32bf16_offset_max(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) #0 {
1850; CHECK-LABEL: splice_nxv32bf16_offset_max:
1851; CHECK:       # %bb.0:
1852; CHECK-NEXT:    csrr a0, vlenb
1853; CHECK-NEXT:    slli a0, a0, 2
1854; CHECK-NEXT:    addi a0, a0, -63
1855; CHECK-NEXT:    li a1, 63
1856; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
1857; CHECK-NEXT:    vslidedown.vx v8, v8, a1
1858; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
1859; CHECK-NEXT:    vslideup.vx v8, v16, a0
1860; CHECK-NEXT:    ret
1861  %res = call <vscale x 32 x bfloat> @llvm.vector.splice.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b, i32 63)
1862  ret <vscale x 32 x bfloat> %res
1863}
1864
1865declare <vscale x 1 x half> @llvm.vector.splice.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, i32)
1866
1867define <vscale x 1 x half> @splice_nxv1f16_offset_zero(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
1868; CHECK-LABEL: splice_nxv1f16_offset_zero:
1869; CHECK:       # %bb.0:
1870; CHECK-NEXT:    ret
1871  %res = call <vscale x 1 x half> @llvm.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 0)
1872  ret <vscale x 1 x half> %res
1873}
1874
1875define <vscale x 1 x half> @splice_nxv1f16_offset_negone(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
1876; CHECK-LABEL: splice_nxv1f16_offset_negone:
1877; CHECK:       # %bb.0:
1878; CHECK-NEXT:    csrr a0, vlenb
1879; CHECK-NEXT:    srli a0, a0, 3
1880; CHECK-NEXT:    addi a0, a0, -1
1881; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
1882; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1883; CHECK-NEXT:    vslideup.vi v8, v9, 1
1884; CHECK-NEXT:    ret
1885  %res = call <vscale x 1 x half> @llvm.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -1)
1886  ret <vscale x 1 x half> %res
1887}
1888
1889define <vscale x 1 x half> @splice_nxv1f16_offset_min(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
1890; CHECK-LABEL: splice_nxv1f16_offset_min:
1891; CHECK:       # %bb.0:
1892; CHECK-NEXT:    csrr a0, vlenb
1893; CHECK-NEXT:    srli a0, a0, 3
1894; CHECK-NEXT:    addi a0, a0, -2
1895; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
1896; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1897; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
1898; CHECK-NEXT:    vslideup.vi v8, v9, 2
1899; CHECK-NEXT:    ret
1900  %res = call <vscale x 1 x half> @llvm.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 -2)
1901  ret <vscale x 1 x half> %res
1902}
1903
1904define <vscale x 1 x half> @splice_nxv1f16_offset_max(<vscale x 1 x half> %a, <vscale x 1 x half> %b) #0 {
1905; CHECK-LABEL: splice_nxv1f16_offset_max:
1906; CHECK:       # %bb.0:
1907; CHECK-NEXT:    csrr a0, vlenb
1908; CHECK-NEXT:    srli a0, a0, 3
1909; CHECK-NEXT:    addi a0, a0, -1
1910; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
1911; CHECK-NEXT:    vslidedown.vi v8, v8, 1
1912; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
1913; CHECK-NEXT:    vslideup.vx v8, v9, a0
1914; CHECK-NEXT:    ret
1915  %res = call <vscale x 1 x half> @llvm.vector.splice.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b, i32 1)
1916  ret <vscale x 1 x half> %res
1917}
1918
1919declare <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, i32)
1920
1921define <vscale x 2 x half> @splice_nxv2f16_offset_zero(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
1922; CHECK-LABEL: splice_nxv2f16_offset_zero:
1923; CHECK:       # %bb.0:
1924; CHECK-NEXT:    ret
1925  %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 0)
1926  ret <vscale x 2 x half> %res
1927}
1928
1929define <vscale x 2 x half> @splice_nxv2f16_offset_negone(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
1930; CHECK-LABEL: splice_nxv2f16_offset_negone:
1931; CHECK:       # %bb.0:
1932; CHECK-NEXT:    csrr a0, vlenb
1933; CHECK-NEXT:    srli a0, a0, 2
1934; CHECK-NEXT:    addi a0, a0, -1
1935; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
1936; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1937; CHECK-NEXT:    vslideup.vi v8, v9, 1
1938; CHECK-NEXT:    ret
1939  %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -1)
1940  ret <vscale x 2 x half> %res
1941}
1942
1943define <vscale x 2 x half> @splice_nxv2f16_offset_min(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
1944; CHECK-LABEL: splice_nxv2f16_offset_min:
1945; CHECK:       # %bb.0:
1946; CHECK-NEXT:    csrr a0, vlenb
1947; CHECK-NEXT:    srli a0, a0, 2
1948; CHECK-NEXT:    addi a0, a0, -4
1949; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
1950; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1951; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
1952; CHECK-NEXT:    vslideup.vi v8, v9, 4
1953; CHECK-NEXT:    ret
1954  %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -4)
1955  ret <vscale x 2 x half> %res
1956}
1957
1958define <vscale x 2 x half> @splice_nxv2f16_offset_max(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
1959; CHECK-LABEL: splice_nxv2f16_offset_max:
1960; CHECK:       # %bb.0:
1961; CHECK-NEXT:    csrr a0, vlenb
1962; CHECK-NEXT:    srli a0, a0, 2
1963; CHECK-NEXT:    addi a0, a0, -3
1964; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
1965; CHECK-NEXT:    vslidedown.vi v8, v8, 3
1966; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
1967; CHECK-NEXT:    vslideup.vx v8, v9, a0
1968; CHECK-NEXT:    ret
1969  %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 3)
1970  ret <vscale x 2 x half> %res
1971}
1972
1973declare <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, i32)
1974
1975define <vscale x 4 x half> @splice_nxv4f16_offset_zero(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
1976; CHECK-LABEL: splice_nxv4f16_offset_zero:
1977; CHECK:       # %bb.0:
1978; CHECK-NEXT:    ret
1979  %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 0)
1980  ret <vscale x 4 x half> %res
1981}
1982
1983define <vscale x 4 x half> @splice_nxv4f16_offset_negone(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
1984; CHECK-LABEL: splice_nxv4f16_offset_negone:
1985; CHECK:       # %bb.0:
1986; CHECK-NEXT:    csrr a0, vlenb
1987; CHECK-NEXT:    srli a0, a0, 1
1988; CHECK-NEXT:    addi a0, a0, -1
1989; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
1990; CHECK-NEXT:    vslidedown.vx v8, v8, a0
1991; CHECK-NEXT:    vslideup.vi v8, v9, 1
1992; CHECK-NEXT:    ret
1993  %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -1)
1994  ret <vscale x 4 x half> %res
1995}
1996
1997define <vscale x 4 x half> @splice_nxv4f16_offset_min(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
1998; CHECK-LABEL: splice_nxv4f16_offset_min:
1999; CHECK:       # %bb.0:
2000; CHECK-NEXT:    csrr a0, vlenb
2001; CHECK-NEXT:    srli a0, a0, 1
2002; CHECK-NEXT:    addi a0, a0, -8
2003; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
2004; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2005; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
2006; CHECK-NEXT:    vslideup.vi v8, v9, 8
2007; CHECK-NEXT:    ret
2008  %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -8)
2009  ret <vscale x 4 x half> %res
2010}
2011
2012define <vscale x 4 x half> @splice_nxv4f16_offset_max(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
2013; CHECK-LABEL: splice_nxv4f16_offset_max:
2014; CHECK:       # %bb.0:
2015; CHECK-NEXT:    csrr a0, vlenb
2016; CHECK-NEXT:    srli a0, a0, 1
2017; CHECK-NEXT:    addi a0, a0, -7
2018; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
2019; CHECK-NEXT:    vslidedown.vi v8, v8, 7
2020; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
2021; CHECK-NEXT:    vslideup.vx v8, v9, a0
2022; CHECK-NEXT:    ret
2023  %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 7)
2024  ret <vscale x 4 x half> %res
2025}
2026
2027declare <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32)
2028
2029define <vscale x 8 x half> @splice_nxv8f16_offset_zero(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
2030; CHECK-LABEL: splice_nxv8f16_offset_zero:
2031; CHECK:       # %bb.0:
2032; CHECK-NEXT:    ret
2033  %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 0)
2034  ret <vscale x 8 x half> %res
2035}
2036
2037define <vscale x 8 x half> @splice_nxv8f16_offset_negone(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
2038; CHECK-LABEL: splice_nxv8f16_offset_negone:
2039; CHECK:       # %bb.0:
2040; CHECK-NEXT:    csrr a0, vlenb
2041; CHECK-NEXT:    addi a0, a0, -1
2042; CHECK-NEXT:    vsetivli zero, 1, e16, m2, ta, ma
2043; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2044; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
2045; CHECK-NEXT:    vslideup.vi v8, v10, 1
2046; CHECK-NEXT:    ret
2047  %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -1)
2048  ret <vscale x 8 x half> %res
2049}
2050
2051define <vscale x 8 x half> @splice_nxv8f16_offset_min(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
2052; CHECK-LABEL: splice_nxv8f16_offset_min:
2053; CHECK:       # %bb.0:
2054; CHECK-NEXT:    csrr a0, vlenb
2055; CHECK-NEXT:    addi a0, a0, -16
2056; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
2057; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2058; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
2059; CHECK-NEXT:    vslideup.vi v8, v10, 16
2060; CHECK-NEXT:    ret
2061  %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -16)
2062  ret <vscale x 8 x half> %res
2063}
2064
2065define <vscale x 8 x half> @splice_nxv8f16_offset_max(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
2066; CHECK-LABEL: splice_nxv8f16_offset_max:
2067; CHECK:       # %bb.0:
2068; CHECK-NEXT:    csrr a0, vlenb
2069; CHECK-NEXT:    addi a0, a0, -15
2070; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
2071; CHECK-NEXT:    vslidedown.vi v8, v8, 15
2072; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
2073; CHECK-NEXT:    vslideup.vx v8, v10, a0
2074; CHECK-NEXT:    ret
2075  %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 15)
2076  ret <vscale x 8 x half> %res
2077}
2078
2079declare <vscale x 16 x half> @llvm.vector.splice.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>, i32)
2080
2081define <vscale x 16 x half> @splice_nxv16f16_offset_zero(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
2082; CHECK-LABEL: splice_nxv16f16_offset_zero:
2083; CHECK:       # %bb.0:
2084; CHECK-NEXT:    ret
2085  %res = call <vscale x 16 x half> @llvm.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 0)
2086  ret <vscale x 16 x half> %res
2087}
2088
2089define <vscale x 16 x half> @splice_nxv16f16_offset_negone(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
2090; CHECK-LABEL: splice_nxv16f16_offset_negone:
2091; CHECK:       # %bb.0:
2092; CHECK-NEXT:    csrr a0, vlenb
2093; CHECK-NEXT:    slli a0, a0, 1
2094; CHECK-NEXT:    addi a0, a0, -1
2095; CHECK-NEXT:    vsetivli zero, 1, e16, m4, ta, ma
2096; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2097; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
2098; CHECK-NEXT:    vslideup.vi v8, v12, 1
2099; CHECK-NEXT:    ret
2100  %res = call <vscale x 16 x half> @llvm.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -1)
2101  ret <vscale x 16 x half> %res
2102}
2103
2104define <vscale x 16 x half> @splice_nxv16f16_offset_min(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
2105; CHECK-LABEL: splice_nxv16f16_offset_min:
2106; CHECK:       # %bb.0:
2107; CHECK-NEXT:    csrr a0, vlenb
2108; CHECK-NEXT:    slli a0, a0, 1
2109; CHECK-NEXT:    addi a0, a0, -32
2110; CHECK-NEXT:    li a1, 32
2111; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
2112; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2113; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
2114; CHECK-NEXT:    vslideup.vx v8, v12, a1
2115; CHECK-NEXT:    ret
2116  %res = call <vscale x 16 x half> @llvm.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 -32)
2117  ret <vscale x 16 x half> %res
2118}
2119
2120define <vscale x 16 x half> @splice_nxv16f16_offset_max(<vscale x 16 x half> %a, <vscale x 16 x half> %b) #0 {
2121; CHECK-LABEL: splice_nxv16f16_offset_max:
2122; CHECK:       # %bb.0:
2123; CHECK-NEXT:    csrr a0, vlenb
2124; CHECK-NEXT:    slli a0, a0, 1
2125; CHECK-NEXT:    addi a0, a0, -31
2126; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
2127; CHECK-NEXT:    vslidedown.vi v8, v8, 31
2128; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
2129; CHECK-NEXT:    vslideup.vx v8, v12, a0
2130; CHECK-NEXT:    ret
2131  %res = call <vscale x 16 x half> @llvm.vector.splice.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b, i32 31)
2132  ret <vscale x 16 x half> %res
2133}
2134
2135declare <vscale x 32 x half> @llvm.vector.splice.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>, i32)
2136
2137define <vscale x 32 x half> @splice_nxv32f16_offset_zero(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
2138; CHECK-LABEL: splice_nxv32f16_offset_zero:
2139; CHECK:       # %bb.0:
2140; CHECK-NEXT:    ret
2141  %res = call <vscale x 32 x half> @llvm.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 0)
2142  ret <vscale x 32 x half> %res
2143}
2144
2145define <vscale x 32 x half> @splice_nxv32f16_offset_negone(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
2146; CHECK-LABEL: splice_nxv32f16_offset_negone:
2147; CHECK:       # %bb.0:
2148; CHECK-NEXT:    csrr a0, vlenb
2149; CHECK-NEXT:    slli a0, a0, 2
2150; CHECK-NEXT:    addi a0, a0, -1
2151; CHECK-NEXT:    vsetivli zero, 1, e16, m8, ta, ma
2152; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2153; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
2154; CHECK-NEXT:    vslideup.vi v8, v16, 1
2155; CHECK-NEXT:    ret
2156  %res = call <vscale x 32 x half> @llvm.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -1)
2157  ret <vscale x 32 x half> %res
2158}
2159
2160define <vscale x 32 x half> @splice_nxv32f16_offset_min(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
2161; CHECK-LABEL: splice_nxv32f16_offset_min:
2162; CHECK:       # %bb.0:
2163; CHECK-NEXT:    csrr a0, vlenb
2164; CHECK-NEXT:    slli a0, a0, 2
2165; CHECK-NEXT:    addi a0, a0, -64
2166; CHECK-NEXT:    li a1, 64
2167; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
2168; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2169; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
2170; CHECK-NEXT:    vslideup.vx v8, v16, a1
2171; CHECK-NEXT:    ret
2172  %res = call <vscale x 32 x half> @llvm.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 -64)
2173  ret <vscale x 32 x half> %res
2174}
2175
2176define <vscale x 32 x half> @splice_nxv32f16_offset_max(<vscale x 32 x half> %a, <vscale x 32 x half> %b) #0 {
2177; CHECK-LABEL: splice_nxv32f16_offset_max:
2178; CHECK:       # %bb.0:
2179; CHECK-NEXT:    csrr a0, vlenb
2180; CHECK-NEXT:    slli a0, a0, 2
2181; CHECK-NEXT:    addi a0, a0, -63
2182; CHECK-NEXT:    li a1, 63
2183; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
2184; CHECK-NEXT:    vslidedown.vx v8, v8, a1
2185; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
2186; CHECK-NEXT:    vslideup.vx v8, v16, a0
2187; CHECK-NEXT:    ret
2188  %res = call <vscale x 32 x half> @llvm.vector.splice.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b, i32 63)
2189  ret <vscale x 32 x half> %res
2190}
2191
2192declare <vscale x 1 x float> @llvm.vector.splice.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>, i32)
2193
2194define <vscale x 1 x float> @splice_nxv1f32_offset_zero(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
2195; CHECK-LABEL: splice_nxv1f32_offset_zero:
2196; CHECK:       # %bb.0:
2197; CHECK-NEXT:    ret
2198  %res = call <vscale x 1 x float> @llvm.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 0)
2199  ret <vscale x 1 x float> %res
2200}
2201
2202define <vscale x 1 x float> @splice_nxv1f32_offset_negone(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
2203; CHECK-LABEL: splice_nxv1f32_offset_negone:
2204; CHECK:       # %bb.0:
2205; CHECK-NEXT:    csrr a0, vlenb
2206; CHECK-NEXT:    srli a0, a0, 3
2207; CHECK-NEXT:    addi a0, a0, -1
2208; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
2209; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2210; CHECK-NEXT:    vslideup.vi v8, v9, 1
2211; CHECK-NEXT:    ret
2212  %res = call <vscale x 1 x float> @llvm.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -1)
2213  ret <vscale x 1 x float> %res
2214}
2215
2216define <vscale x 1 x float> @splice_nxv1f32_offset_min(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
2217; CHECK-LABEL: splice_nxv1f32_offset_min:
2218; CHECK:       # %bb.0:
2219; CHECK-NEXT:    csrr a0, vlenb
2220; CHECK-NEXT:    srli a0, a0, 3
2221; CHECK-NEXT:    addi a0, a0, -2
2222; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
2223; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2224; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
2225; CHECK-NEXT:    vslideup.vi v8, v9, 2
2226; CHECK-NEXT:    ret
2227  %res = call <vscale x 1 x float> @llvm.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 -2)
2228  ret <vscale x 1 x float> %res
2229}
2230
2231define <vscale x 1 x float> @splice_nxv1f32_offset_max(<vscale x 1 x float> %a, <vscale x 1 x float> %b) #0 {
2232; CHECK-LABEL: splice_nxv1f32_offset_max:
2233; CHECK:       # %bb.0:
2234; CHECK-NEXT:    csrr a0, vlenb
2235; CHECK-NEXT:    srli a0, a0, 3
2236; CHECK-NEXT:    addi a0, a0, -1
2237; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
2238; CHECK-NEXT:    vslidedown.vi v8, v8, 1
2239; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
2240; CHECK-NEXT:    vslideup.vx v8, v9, a0
2241; CHECK-NEXT:    ret
2242  %res = call <vscale x 1 x float> @llvm.vector.splice.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b, i32 1)
2243  ret <vscale x 1 x float> %res
2244}
2245
2246declare <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32)
2247
2248define <vscale x 2 x float> @splice_nxv2f32_offset_zero(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
2249; CHECK-LABEL: splice_nxv2f32_offset_zero:
2250; CHECK:       # %bb.0:
2251; CHECK-NEXT:    ret
2252  %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 0)
2253  ret <vscale x 2 x float> %res
2254}
2255
2256define <vscale x 2 x float> @splice_nxv2f32_offset_negone(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
2257; CHECK-LABEL: splice_nxv2f32_offset_negone:
2258; CHECK:       # %bb.0:
2259; CHECK-NEXT:    csrr a0, vlenb
2260; CHECK-NEXT:    srli a0, a0, 2
2261; CHECK-NEXT:    addi a0, a0, -1
2262; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
2263; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2264; CHECK-NEXT:    vslideup.vi v8, v9, 1
2265; CHECK-NEXT:    ret
2266  %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -1)
2267  ret <vscale x 2 x float> %res
2268}
2269
2270define <vscale x 2 x float> @splice_nxv2f32_offset_min(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
2271; CHECK-LABEL: splice_nxv2f32_offset_min:
2272; CHECK:       # %bb.0:
2273; CHECK-NEXT:    csrr a0, vlenb
2274; CHECK-NEXT:    srli a0, a0, 2
2275; CHECK-NEXT:    addi a0, a0, -4
2276; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
2277; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2278; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
2279; CHECK-NEXT:    vslideup.vi v8, v9, 4
2280; CHECK-NEXT:    ret
2281  %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -4)
2282  ret <vscale x 2 x float> %res
2283}
2284
2285define <vscale x 2 x float> @splice_nxv2f32_offset_max(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
2286; CHECK-LABEL: splice_nxv2f32_offset_max:
2287; CHECK:       # %bb.0:
2288; CHECK-NEXT:    csrr a0, vlenb
2289; CHECK-NEXT:    srli a0, a0, 2
2290; CHECK-NEXT:    addi a0, a0, -3
2291; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
2292; CHECK-NEXT:    vslidedown.vi v8, v8, 3
2293; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
2294; CHECK-NEXT:    vslideup.vx v8, v9, a0
2295; CHECK-NEXT:    ret
2296  %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 3)
2297  ret <vscale x 2 x float> %res
2298}
2299
2300declare <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32)
2301
2302define <vscale x 4 x float> @splice_nxv4f32_offset_zero(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
2303; CHECK-LABEL: splice_nxv4f32_offset_zero:
2304; CHECK:       # %bb.0:
2305; CHECK-NEXT:    ret
2306  %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 0)
2307  ret <vscale x 4 x float> %res
2308}
2309
2310define <vscale x 4 x float> @splice_nxv4f32_offset_negone(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
2311; CHECK-LABEL: splice_nxv4f32_offset_negone:
2312; CHECK:       # %bb.0:
2313; CHECK-NEXT:    csrr a0, vlenb
2314; CHECK-NEXT:    srli a0, a0, 1
2315; CHECK-NEXT:    addi a0, a0, -1
2316; CHECK-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
2317; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2318; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
2319; CHECK-NEXT:    vslideup.vi v8, v10, 1
2320; CHECK-NEXT:    ret
2321  %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -1)
2322  ret <vscale x 4 x float> %res
2323}
2324
2325define <vscale x 4 x float> @splice_nxv4f32_offset_min(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
2326; CHECK-LABEL: splice_nxv4f32_offset_min:
2327; CHECK:       # %bb.0:
2328; CHECK-NEXT:    csrr a0, vlenb
2329; CHECK-NEXT:    srli a0, a0, 1
2330; CHECK-NEXT:    addi a0, a0, -8
2331; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
2332; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2333; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
2334; CHECK-NEXT:    vslideup.vi v8, v10, 8
2335; CHECK-NEXT:    ret
2336  %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -8)
2337  ret <vscale x 4 x float> %res
2338}
2339
2340define <vscale x 4 x float> @splice_nxv4f32_offset_max(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
2341; CHECK-LABEL: splice_nxv4f32_offset_max:
2342; CHECK:       # %bb.0:
2343; CHECK-NEXT:    csrr a0, vlenb
2344; CHECK-NEXT:    srli a0, a0, 1
2345; CHECK-NEXT:    addi a0, a0, -7
2346; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
2347; CHECK-NEXT:    vslidedown.vi v8, v8, 7
2348; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
2349; CHECK-NEXT:    vslideup.vx v8, v10, a0
2350; CHECK-NEXT:    ret
2351  %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 7)
2352  ret <vscale x 4 x float> %res
2353}
2354
2355declare <vscale x 8 x float> @llvm.vector.splice.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>, i32)
2356
2357define <vscale x 8 x float> @splice_nxv8f32_offset_zero(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
2358; CHECK-LABEL: splice_nxv8f32_offset_zero:
2359; CHECK:       # %bb.0:
2360; CHECK-NEXT:    ret
2361  %res = call <vscale x 8 x float> @llvm.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 0)
2362  ret <vscale x 8 x float> %res
2363}
2364
2365define <vscale x 8 x float> @splice_nxv8f32_offset_negone(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
2366; CHECK-LABEL: splice_nxv8f32_offset_negone:
2367; CHECK:       # %bb.0:
2368; CHECK-NEXT:    csrr a0, vlenb
2369; CHECK-NEXT:    addi a0, a0, -1
2370; CHECK-NEXT:    vsetivli zero, 1, e32, m4, ta, ma
2371; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2372; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
2373; CHECK-NEXT:    vslideup.vi v8, v12, 1
2374; CHECK-NEXT:    ret
2375  %res = call <vscale x 8 x float> @llvm.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -1)
2376  ret <vscale x 8 x float> %res
2377}
2378
2379define <vscale x 8 x float> @splice_nxv8f32_offset_min(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
2380; CHECK-LABEL: splice_nxv8f32_offset_min:
2381; CHECK:       # %bb.0:
2382; CHECK-NEXT:    csrr a0, vlenb
2383; CHECK-NEXT:    addi a0, a0, -16
2384; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
2385; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2386; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
2387; CHECK-NEXT:    vslideup.vi v8, v12, 16
2388; CHECK-NEXT:    ret
2389  %res = call <vscale x 8 x float> @llvm.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 -16)
2390  ret <vscale x 8 x float> %res
2391}
2392
2393define <vscale x 8 x float> @splice_nxv8f32_offset_max(<vscale x 8 x float> %a, <vscale x 8 x float> %b) #0 {
2394; CHECK-LABEL: splice_nxv8f32_offset_max:
2395; CHECK:       # %bb.0:
2396; CHECK-NEXT:    csrr a0, vlenb
2397; CHECK-NEXT:    addi a0, a0, -15
2398; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
2399; CHECK-NEXT:    vslidedown.vi v8, v8, 15
2400; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
2401; CHECK-NEXT:    vslideup.vx v8, v12, a0
2402; CHECK-NEXT:    ret
2403  %res = call <vscale x 8 x float> @llvm.vector.splice.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b, i32 15)
2404  ret <vscale x 8 x float> %res
2405}
2406
2407declare <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, i32)
2408
2409define <vscale x 16 x float> @splice_nxv16f32_offset_zero(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
2410; CHECK-LABEL: splice_nxv16f32_offset_zero:
2411; CHECK:       # %bb.0:
2412; CHECK-NEXT:    ret
2413  %res = call <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 0)
2414  ret <vscale x 16 x float> %res
2415}
2416
2417define <vscale x 16 x float> @splice_nxv16f32_offset_negone(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
2418; CHECK-LABEL: splice_nxv16f32_offset_negone:
2419; CHECK:       # %bb.0:
2420; CHECK-NEXT:    csrr a0, vlenb
2421; CHECK-NEXT:    slli a0, a0, 1
2422; CHECK-NEXT:    addi a0, a0, -1
2423; CHECK-NEXT:    vsetivli zero, 1, e32, m8, ta, ma
2424; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2425; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
2426; CHECK-NEXT:    vslideup.vi v8, v16, 1
2427; CHECK-NEXT:    ret
2428  %res = call <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -1)
2429  ret <vscale x 16 x float> %res
2430}
2431
2432define <vscale x 16 x float> @splice_nxv16f32_offset_min(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
2433; CHECK-LABEL: splice_nxv16f32_offset_min:
2434; CHECK:       # %bb.0:
2435; CHECK-NEXT:    csrr a0, vlenb
2436; CHECK-NEXT:    slli a0, a0, 1
2437; CHECK-NEXT:    addi a0, a0, -32
2438; CHECK-NEXT:    li a1, 32
2439; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
2440; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2441; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
2442; CHECK-NEXT:    vslideup.vx v8, v16, a1
2443; CHECK-NEXT:    ret
2444  %res = call <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -32)
2445  ret <vscale x 16 x float> %res
2446}
2447
2448define <vscale x 16 x float> @splice_nxv16f32_offset_max(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
2449; CHECK-LABEL: splice_nxv16f32_offset_max:
2450; CHECK:       # %bb.0:
2451; CHECK-NEXT:    csrr a0, vlenb
2452; CHECK-NEXT:    slli a0, a0, 1
2453; CHECK-NEXT:    addi a0, a0, -31
2454; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
2455; CHECK-NEXT:    vslidedown.vi v8, v8, 31
2456; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
2457; CHECK-NEXT:    vslideup.vx v8, v16, a0
2458; CHECK-NEXT:    ret
2459  %res = call <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 31)
2460  ret <vscale x 16 x float> %res
2461}
2462
2463declare <vscale x 1 x double> @llvm.vector.splice.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i32)
2464
2465define <vscale x 1 x double> @splice_nxv1f64_offset_zero(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
2466; CHECK-LABEL: splice_nxv1f64_offset_zero:
2467; CHECK:       # %bb.0:
2468; CHECK-NEXT:    ret
2469  %res = call <vscale x 1 x double> @llvm.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 0)
2470  ret <vscale x 1 x double> %res
2471}
2472
2473define <vscale x 1 x double> @splice_nxv1f64_offset_negone(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
2474; CHECK-LABEL: splice_nxv1f64_offset_negone:
2475; CHECK:       # %bb.0:
2476; CHECK-NEXT:    csrr a0, vlenb
2477; CHECK-NEXT:    srli a0, a0, 3
2478; CHECK-NEXT:    addi a0, a0, -1
2479; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
2480; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2481; CHECK-NEXT:    vslideup.vi v8, v9, 1
2482; CHECK-NEXT:    ret
2483  %res = call <vscale x 1 x double> @llvm.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -1)
2484  ret <vscale x 1 x double> %res
2485}
2486
2487define <vscale x 1 x double> @splice_nxv1f64_offset_min(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
2488; CHECK-LABEL: splice_nxv1f64_offset_min:
2489; CHECK:       # %bb.0:
2490; CHECK-NEXT:    csrr a0, vlenb
2491; CHECK-NEXT:    srli a0, a0, 3
2492; CHECK-NEXT:    addi a0, a0, -2
2493; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
2494; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2495; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
2496; CHECK-NEXT:    vslideup.vi v8, v9, 2
2497; CHECK-NEXT:    ret
2498  %res = call <vscale x 1 x double> @llvm.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 -2)
2499  ret <vscale x 1 x double> %res
2500}
2501
2502define <vscale x 1 x double> @splice_nxv1f64_offset_max(<vscale x 1 x double> %a, <vscale x 1 x double> %b) #0 {
2503; CHECK-LABEL: splice_nxv1f64_offset_max:
2504; CHECK:       # %bb.0:
2505; CHECK-NEXT:    csrr a0, vlenb
2506; CHECK-NEXT:    srli a0, a0, 3
2507; CHECK-NEXT:    addi a0, a0, -1
2508; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
2509; CHECK-NEXT:    vslidedown.vi v8, v8, 1
2510; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
2511; CHECK-NEXT:    vslideup.vx v8, v9, a0
2512; CHECK-NEXT:    ret
2513  %res = call <vscale x 1 x double> @llvm.vector.splice.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i32 1)
2514  ret <vscale x 1 x double> %res
2515}
2516
2517declare <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32)
2518
2519define <vscale x 2 x double> @splice_nxv2f64_offset_zero(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
2520; CHECK-LABEL: splice_nxv2f64_offset_zero:
2521; CHECK:       # %bb.0:
2522; CHECK-NEXT:    ret
2523  %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 0)
2524  ret <vscale x 2 x double> %res
2525}
2526
2527define <vscale x 2 x double> @splice_nxv2f64_offset_negone(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
2528; CHECK-LABEL: splice_nxv2f64_offset_negone:
2529; CHECK:       # %bb.0:
2530; CHECK-NEXT:    csrr a0, vlenb
2531; CHECK-NEXT:    srli a0, a0, 2
2532; CHECK-NEXT:    addi a0, a0, -1
2533; CHECK-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
2534; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2535; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
2536; CHECK-NEXT:    vslideup.vi v8, v10, 1
2537; CHECK-NEXT:    ret
2538  %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -1)
2539  ret <vscale x 2 x double> %res
2540}
2541
2542define <vscale x 2 x double> @splice_nxv2f64_offset_min(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
2543; CHECK-LABEL: splice_nxv2f64_offset_min:
2544; CHECK:       # %bb.0:
2545; CHECK-NEXT:    csrr a0, vlenb
2546; CHECK-NEXT:    srli a0, a0, 2
2547; CHECK-NEXT:    addi a0, a0, -4
2548; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
2549; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2550; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
2551; CHECK-NEXT:    vslideup.vi v8, v10, 4
2552; CHECK-NEXT:    ret
2553  %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -4)
2554  ret <vscale x 2 x double> %res
2555}
2556
2557define <vscale x 2 x double> @splice_nxv2f64_offset_max(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
2558; CHECK-LABEL: splice_nxv2f64_offset_max:
2559; CHECK:       # %bb.0:
2560; CHECK-NEXT:    csrr a0, vlenb
2561; CHECK-NEXT:    srli a0, a0, 2
2562; CHECK-NEXT:    addi a0, a0, -3
2563; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
2564; CHECK-NEXT:    vslidedown.vi v8, v8, 3
2565; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
2566; CHECK-NEXT:    vslideup.vx v8, v10, a0
2567; CHECK-NEXT:    ret
2568  %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 3)
2569  ret <vscale x 2 x double> %res
2570}
2571
2572declare <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>, i32)
2573
2574define <vscale x 4 x double> @splice_nxv4f64_offset_zero(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
2575; CHECK-LABEL: splice_nxv4f64_offset_zero:
2576; CHECK:       # %bb.0:
2577; CHECK-NEXT:    ret
2578  %res = call <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 0)
2579  ret <vscale x 4 x double> %res
2580}
2581
2582define <vscale x 4 x double> @splice_nxv4f64_offset_negone(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
2583; CHECK-LABEL: splice_nxv4f64_offset_negone:
2584; CHECK:       # %bb.0:
2585; CHECK-NEXT:    csrr a0, vlenb
2586; CHECK-NEXT:    srli a0, a0, 1
2587; CHECK-NEXT:    addi a0, a0, -1
2588; CHECK-NEXT:    vsetivli zero, 1, e64, m4, ta, ma
2589; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2590; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
2591; CHECK-NEXT:    vslideup.vi v8, v12, 1
2592; CHECK-NEXT:    ret
2593  %res = call <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -1)
2594  ret <vscale x 4 x double> %res
2595}
2596
2597define <vscale x 4 x double> @splice_nxv4f64_offset_min(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
2598; CHECK-LABEL: splice_nxv4f64_offset_min:
2599; CHECK:       # %bb.0:
2600; CHECK-NEXT:    csrr a0, vlenb
2601; CHECK-NEXT:    srli a0, a0, 1
2602; CHECK-NEXT:    addi a0, a0, -8
2603; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
2604; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2605; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
2606; CHECK-NEXT:    vslideup.vi v8, v12, 8
2607; CHECK-NEXT:    ret
2608  %res = call <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 -8)
2609  ret <vscale x 4 x double> %res
2610}
2611
2612define <vscale x 4 x double> @splice_nxv4f64_offset_max(<vscale x 4 x double> %a, <vscale x 4 x double> %b) #0 {
2613; CHECK-LABEL: splice_nxv4f64_offset_max:
2614; CHECK:       # %bb.0:
2615; CHECK-NEXT:    csrr a0, vlenb
2616; CHECK-NEXT:    srli a0, a0, 1
2617; CHECK-NEXT:    addi a0, a0, -7
2618; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
2619; CHECK-NEXT:    vslidedown.vi v8, v8, 7
2620; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
2621; CHECK-NEXT:    vslideup.vx v8, v12, a0
2622; CHECK-NEXT:    ret
2623  %res = call <vscale x 4 x double> @llvm.vector.splice.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b, i32 7)
2624  ret <vscale x 4 x double> %res
2625}
2626
2627declare <vscale x 8 x double> @llvm.vector.splice.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>, i32)
2628
2629define <vscale x 8 x double> @splice_nxv8f64_offset_zero(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
2630; CHECK-LABEL: splice_nxv8f64_offset_zero:
2631; CHECK:       # %bb.0:
2632; CHECK-NEXT:    ret
2633  %res = call <vscale x 8 x double> @llvm.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 0)
2634  ret <vscale x 8 x double> %res
2635}
2636
2637define <vscale x 8 x double> @splice_nxv8f64_offset_negone(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
2638; CHECK-LABEL: splice_nxv8f64_offset_negone:
2639; CHECK:       # %bb.0:
2640; CHECK-NEXT:    csrr a0, vlenb
2641; CHECK-NEXT:    addi a0, a0, -1
2642; CHECK-NEXT:    vsetivli zero, 1, e64, m8, ta, ma
2643; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2644; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
2645; CHECK-NEXT:    vslideup.vi v8, v16, 1
2646; CHECK-NEXT:    ret
2647  %res = call <vscale x 8 x double> @llvm.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -1)
2648  ret <vscale x 8 x double> %res
2649}
2650
2651define <vscale x 8 x double> @splice_nxv8f64_offset_min(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
2652; CHECK-LABEL: splice_nxv8f64_offset_min:
2653; CHECK:       # %bb.0:
2654; CHECK-NEXT:    csrr a0, vlenb
2655; CHECK-NEXT:    addi a0, a0, -16
2656; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
2657; CHECK-NEXT:    vslidedown.vx v8, v8, a0
2658; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
2659; CHECK-NEXT:    vslideup.vi v8, v16, 16
2660; CHECK-NEXT:    ret
2661  %res = call <vscale x 8 x double> @llvm.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 -16)
2662  ret <vscale x 8 x double> %res
2663}
2664
2665define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a, <vscale x 8 x double> %b) #0 {
2666; CHECK-LABEL: splice_nxv8f64_offset_max:
2667; CHECK:       # %bb.0:
2668; CHECK-NEXT:    csrr a0, vlenb
2669; CHECK-NEXT:    addi a0, a0, -15
2670; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
2671; CHECK-NEXT:    vslidedown.vi v8, v8, 15
2672; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
2673; CHECK-NEXT:    vslideup.vx v8, v16, a0
2674; CHECK-NEXT:    ret
2675  %res = call <vscale x 8 x double> @llvm.vector.splice.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b, i32 15)
2676  ret <vscale x 8 x double> %res
2677}
2678
2679attributes #0 = { vscale_range(2,0) }
2680