xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s
3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s
4
5; Integers
6
7define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
8; CHECK-LABEL: vector_deinterleave_v16i1_v32i1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
11; CHECK-NEXT:    vmv1r.v v8, v0
12; CHECK-NEXT:    vslidedown.vi v0, v0, 2
13; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
14; CHECK-NEXT:    vmv.v.i v10, 0
15; CHECK-NEXT:    vid.v v9
16; CHECK-NEXT:    li a0, -256
17; CHECK-NEXT:    vmerge.vim v11, v10, 1, v0
18; CHECK-NEXT:    vadd.vv v12, v9, v9
19; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
20; CHECK-NEXT:    vmv.s.x v9, a0
21; CHECK-NEXT:    vmv1r.v v0, v8
22; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
23; CHECK-NEXT:    vmerge.vim v8, v10, 1, v0
24; CHECK-NEXT:    vadd.vi v10, v12, -16
25; CHECK-NEXT:    vadd.vi v12, v12, -15
26; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
27; CHECK-NEXT:    vnsrl.wi v13, v8, 0
28; CHECK-NEXT:    vnsrl.wi v8, v8, 8
29; CHECK-NEXT:    vmv1r.v v0, v9
30; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
31; CHECK-NEXT:    vrgather.vv v13, v11, v10, v0.t
32; CHECK-NEXT:    vrgather.vv v8, v11, v12, v0.t
33; CHECK-NEXT:    vmsne.vi v0, v13, 0
34; CHECK-NEXT:    vmsne.vi v8, v8, 0
35; CHECK-NEXT:    ret
36%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)
37ret {<16 x i1>, <16 x i1>} %retval
38}
39
40define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) {
41; CHECK-LABEL: vector_deinterleave_v16i8_v32i8:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
44; CHECK-NEXT:    vnsrl.wi v10, v8, 0
45; CHECK-NEXT:    vnsrl.wi v11, v8, 8
46; CHECK-NEXT:    vmv.v.v v8, v10
47; CHECK-NEXT:    vmv.v.v v9, v11
48; CHECK-NEXT:    ret
49%retval = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec)
50ret {<16 x i8>, <16 x i8>} %retval
51}
52
53define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) {
54; CHECK-LABEL: vector_deinterleave_v8i16_v16i16:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
57; CHECK-NEXT:    vnsrl.wi v10, v8, 0
58; CHECK-NEXT:    vnsrl.wi v11, v8, 16
59; CHECK-NEXT:    vmv.v.v v8, v10
60; CHECK-NEXT:    vmv.v.v v9, v11
61; CHECK-NEXT:    ret
62%retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec)
63ret {<8 x i16>, <8 x i16>} %retval
64}
65
66define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_vv8i32(<8 x i32> %vec) {
67; CHECK-LABEL: vector_deinterleave_v4i32_vv8i32:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    li a0, 32
70; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
71; CHECK-NEXT:    vnsrl.wx v10, v8, a0
72; CHECK-NEXT:    vnsrl.wi v11, v8, 0
73; CHECK-NEXT:    vmv.v.v v8, v11
74; CHECK-NEXT:    vmv.v.v v9, v10
75; CHECK-NEXT:    ret
76%retval = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec)
77ret {<4 x i32>, <4 x i32>} %retval
78}
79
80define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
81; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetivli zero, 2, e64, m2, ta, ma
84; CHECK-NEXT:    vslidedown.vi v10, v8, 2
85; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
86; CHECK-NEXT:    vmv.v.i v0, 1
87; CHECK-NEXT:    vmv1r.v v9, v10
88; CHECK-NEXT:    vrgather.vi v9, v8, 1, v0.t
89; CHECK-NEXT:    vslideup.vi v8, v10, 1
90; CHECK-NEXT:    ret
91%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec)
92ret {<2 x i64>, <2 x i64>} %retval
93}
94
95define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
96; CHECK-LABEL: vector_deinterleave_v4i64_v8i64:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
99; CHECK-NEXT:    vmv.v.i v14, 5
100; CHECK-NEXT:    vid.v v15
101; CHECK-NEXT:    vsetivli zero, 4, e64, m4, ta, ma
102; CHECK-NEXT:    vslidedown.vi v16, v8, 4
103; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
104; CHECK-NEXT:    vmv.v.i v0, 12
105; CHECK-NEXT:    vmv.v.i v18, 10
106; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
107; CHECK-NEXT:    vcompress.vm v12, v8, v14
108; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
109; CHECK-NEXT:    vadd.vv v14, v15, v15
110; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
111; CHECK-NEXT:    vcompress.vm v10, v8, v18
112; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
113; CHECK-NEXT:    vadd.vi v8, v14, -4
114; CHECK-NEXT:    vadd.vi v9, v14, -3
115; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
116; CHECK-NEXT:    vrgatherei16.vv v12, v16, v8, v0.t
117; CHECK-NEXT:    vrgatherei16.vv v10, v16, v9, v0.t
118; CHECK-NEXT:    vmv.v.v v8, v12
119; CHECK-NEXT:    ret
120  %retval = call {<4 x i64>, <4 x i64>} @llvm.vector.deinterleave2.v8i64(<8 x i64> %vec)
121  ret {<4 x i64>, <4 x i64>} %retval
122}
123
124define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec) {
125; CHECK-LABEL: vector_deinterleave_v8i64_v16i64:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    li a0, 85
128; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
129; CHECK-NEXT:    vmv.v.i v0, -16
130; CHECK-NEXT:    vid.v v16
131; CHECK-NEXT:    vsetivli zero, 8, e64, m8, ta, ma
132; CHECK-NEXT:    vslidedown.vi v24, v8, 8
133; CHECK-NEXT:    vmv.s.x v12, a0
134; CHECK-NEXT:    li a0, 170
135; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
136; CHECK-NEXT:    vadd.vv v20, v16, v16
137; CHECK-NEXT:    vmv.s.x v21, a0
138; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
139; CHECK-NEXT:    vcompress.vm v16, v8, v12
140; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
141; CHECK-NEXT:    vadd.vi v22, v20, -8
142; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
143; CHECK-NEXT:    vcompress.vm v12, v8, v21
144; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
145; CHECK-NEXT:    vadd.vi v8, v20, -7
146; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
147; CHECK-NEXT:    vrgatherei16.vv v16, v24, v22, v0.t
148; CHECK-NEXT:    vrgatherei16.vv v12, v24, v8, v0.t
149; CHECK-NEXT:    vmv.v.v v8, v16
150; CHECK-NEXT:    ret
151  %retval = call {<8 x i64>, <8 x i64>} @llvm.vector.deinterleave2.v16i64(<16 x i64> %vec)
152  ret {<8 x i64>, <8 x i64>} %retval
153}
154
155declare {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1>)
156declare {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8>)
157declare {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16>)
158declare {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32>)
159declare {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64>)
160
161; Floats
162
163define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec) {
164; CHECK-LABEL: vector_deinterleave_v2f16_v4f16:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
167; CHECK-NEXT:    vnsrl.wi v10, v8, 0
168; CHECK-NEXT:    vnsrl.wi v9, v8, 16
169; CHECK-NEXT:    vmv1r.v v8, v10
170; CHECK-NEXT:    ret
171%retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec)
172ret {<2 x half>, <2 x half>} %retval
173}
174
175define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec) {
176; CHECK-LABEL: vector_deinterleave_v4f16_v8f16:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
179; CHECK-NEXT:    vnsrl.wi v10, v8, 0
180; CHECK-NEXT:    vnsrl.wi v9, v8, 16
181; CHECK-NEXT:    vmv1r.v v8, v10
182; CHECK-NEXT:    ret
183%retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec)
184ret {<4 x half>, <4 x half>} %retval
185}
186
187define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> %vec) {
188; CHECK-LABEL: vector_deinterleave_v2f32_v4f32:
189; CHECK:       # %bb.0:
190; CHECK-NEXT:    li a0, 32
191; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
192; CHECK-NEXT:    vnsrl.wx v9, v8, a0
193; CHECK-NEXT:    vnsrl.wi v8, v8, 0
194; CHECK-NEXT:    ret
195%retval = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec)
196ret {<2 x float>, <2 x float>} %retval
197}
198
199define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %vec) {
200; CHECK-LABEL: vector_deinterleave_v8f16_v16f16:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
203; CHECK-NEXT:    vnsrl.wi v10, v8, 0
204; CHECK-NEXT:    vnsrl.wi v11, v8, 16
205; CHECK-NEXT:    vmv.v.v v8, v10
206; CHECK-NEXT:    vmv.v.v v9, v11
207; CHECK-NEXT:    ret
208%retval = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec)
209ret {<8 x half>, <8 x half>} %retval
210}
211
212define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> %vec) {
213; CHECK-LABEL: vector_deinterleave_v4f32_v8f32:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    li a0, 32
216; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
217; CHECK-NEXT:    vnsrl.wx v10, v8, a0
218; CHECK-NEXT:    vnsrl.wi v11, v8, 0
219; CHECK-NEXT:    vmv.v.v v8, v11
220; CHECK-NEXT:    vmv.v.v v9, v10
221; CHECK-NEXT:    ret
222%retval = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec)
223ret  {<4 x float>, <4 x float>} %retval
224}
225
226define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
227; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    vsetivli zero, 2, e64, m2, ta, ma
230; CHECK-NEXT:    vslidedown.vi v10, v8, 2
231; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
232; CHECK-NEXT:    vmv.v.i v0, 1
233; CHECK-NEXT:    vmv1r.v v9, v10
234; CHECK-NEXT:    vrgather.vi v9, v8, 1, v0.t
235; CHECK-NEXT:    vslideup.vi v8, v10, 1
236; CHECK-NEXT:    ret
237%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec)
238ret {<2 x double>, <2 x double>} %retval
239}
240
241define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double> %vec) {
242; CHECK-LABEL: vector_deinterleave_v4f64_v8f64:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
245; CHECK-NEXT:    vmv.v.i v14, 5
246; CHECK-NEXT:    vid.v v15
247; CHECK-NEXT:    vsetivli zero, 4, e64, m4, ta, ma
248; CHECK-NEXT:    vslidedown.vi v16, v8, 4
249; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
250; CHECK-NEXT:    vmv.v.i v0, 12
251; CHECK-NEXT:    vmv.v.i v18, 10
252; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
253; CHECK-NEXT:    vcompress.vm v12, v8, v14
254; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
255; CHECK-NEXT:    vadd.vv v14, v15, v15
256; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
257; CHECK-NEXT:    vcompress.vm v10, v8, v18
258; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
259; CHECK-NEXT:    vadd.vi v8, v14, -4
260; CHECK-NEXT:    vadd.vi v9, v14, -3
261; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
262; CHECK-NEXT:    vrgatherei16.vv v12, v16, v8, v0.t
263; CHECK-NEXT:    vrgatherei16.vv v10, v16, v9, v0.t
264; CHECK-NEXT:    vmv.v.v v8, v12
265; CHECK-NEXT:    ret
266%retval = call {<4 x double>, <4 x double>} @llvm.vector.deinterleave2.v8f64(<8 x double> %vec)
267ret {<4 x double>, <4 x double>} %retval
268}
269
270declare {<2 x half>,<2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half>)
271declare {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half>)
272declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>)
273declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>)
274declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>)
275declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>)
276