xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/select-bf16.ll (revision 32597685574e594d745df1bb15dc0e626bd60566) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x bfloat> @select_nxv1bf16(i1 zeroext %c, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) {
8; CHECK-LABEL: select_nxv1bf16:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
11; CHECK-NEXT:    vmv.v.x v10, a0
12; CHECK-NEXT:    vmsne.vi v0, v10, 0
13; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
14; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
15; CHECK-NEXT:    ret
16  %v = select i1 %c, <vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b
17  ret <vscale x 1 x bfloat> %v
18}
19
20define <vscale x 1 x bfloat> @selectcc_nxv1bf16(bfloat %a, bfloat %b, <vscale x 1 x bfloat> %c, <vscale x 1 x bfloat> %d) {
21; CHECK-LABEL: selectcc_nxv1bf16:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
24; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
25; CHECK-NEXT:    feq.s a0, fa4, fa5
26; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
27; CHECK-NEXT:    vmv.v.x v10, a0
28; CHECK-NEXT:    vmsne.vi v0, v10, 0
29; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
30; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
31; CHECK-NEXT:    ret
32  %cmp = fcmp oeq bfloat %a, %b
33  %v = select i1 %cmp, <vscale x 1 x bfloat> %c, <vscale x 1 x bfloat> %d
34  ret <vscale x 1 x bfloat> %v
35}
36
37define <vscale x 2 x bfloat> @select_nxv2bf16(i1 zeroext %c, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
38; CHECK-LABEL: select_nxv2bf16:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
41; CHECK-NEXT:    vmv.v.x v10, a0
42; CHECK-NEXT:    vmsne.vi v0, v10, 0
43; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
44; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
45; CHECK-NEXT:    ret
46  %v = select i1 %c, <vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b
47  ret <vscale x 2 x bfloat> %v
48}
49
50define <vscale x 2 x bfloat> @selectcc_nxv2bf16(bfloat %a, bfloat %b, <vscale x 2 x bfloat> %c, <vscale x 2 x bfloat> %d) {
51; CHECK-LABEL: selectcc_nxv2bf16:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
54; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
55; CHECK-NEXT:    feq.s a0, fa4, fa5
56; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
57; CHECK-NEXT:    vmv.v.x v10, a0
58; CHECK-NEXT:    vmsne.vi v0, v10, 0
59; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
60; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
61; CHECK-NEXT:    ret
62  %cmp = fcmp oeq bfloat %a, %b
63  %v = select i1 %cmp, <vscale x 2 x bfloat> %c, <vscale x 2 x bfloat> %d
64  ret <vscale x 2 x bfloat> %v
65}
66
67define <vscale x 4 x bfloat> @select_nxv4bf16(i1 zeroext %c, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
68; CHECK-LABEL: select_nxv4bf16:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
71; CHECK-NEXT:    vmv.v.x v10, a0
72; CHECK-NEXT:    vmsne.vi v0, v10, 0
73; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
74; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
75; CHECK-NEXT:    ret
76  %v = select i1 %c, <vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b
77  ret <vscale x 4 x bfloat> %v
78}
79
80define <vscale x 4 x bfloat> @selectcc_nxv4bf16(bfloat %a, bfloat %b, <vscale x 4 x bfloat> %c, <vscale x 4 x bfloat> %d) {
81; CHECK-LABEL: selectcc_nxv4bf16:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
84; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
85; CHECK-NEXT:    feq.s a0, fa4, fa5
86; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
87; CHECK-NEXT:    vmv.v.x v10, a0
88; CHECK-NEXT:    vmsne.vi v0, v10, 0
89; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
90; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
91; CHECK-NEXT:    ret
92  %cmp = fcmp oeq bfloat %a, %b
93  %v = select i1 %cmp, <vscale x 4 x bfloat> %c, <vscale x 4 x bfloat> %d
94  ret <vscale x 4 x bfloat> %v
95}
96
97define <vscale x 8 x bfloat> @select_nxv8bf16(i1 zeroext %c, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
98; CHECK-LABEL: select_nxv8bf16:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
101; CHECK-NEXT:    vmv.v.x v12, a0
102; CHECK-NEXT:    vmsne.vi v0, v12, 0
103; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
104; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
105; CHECK-NEXT:    ret
106  %v = select i1 %c, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b
107  ret <vscale x 8 x bfloat> %v
108}
109
110define <vscale x 8 x bfloat> @selectcc_nxv8bf16(bfloat %a, bfloat %b, <vscale x 8 x bfloat> %c, <vscale x 8 x bfloat> %d) {
111; CHECK-LABEL: selectcc_nxv8bf16:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
114; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
115; CHECK-NEXT:    feq.s a0, fa4, fa5
116; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
117; CHECK-NEXT:    vmv.v.x v12, a0
118; CHECK-NEXT:    vmsne.vi v0, v12, 0
119; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
120; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
121; CHECK-NEXT:    ret
122  %cmp = fcmp oeq bfloat %a, %b
123  %v = select i1 %cmp, <vscale x 8 x bfloat> %c, <vscale x 8 x bfloat> %d
124  ret <vscale x 8 x bfloat> %v
125}
126
127define <vscale x 16 x bfloat> @select_nxv16bf16(i1 zeroext %c, <vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) {
128; CHECK-LABEL: select_nxv16bf16:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
131; CHECK-NEXT:    vmv.v.x v16, a0
132; CHECK-NEXT:    vmsne.vi v0, v16, 0
133; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
134; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
135; CHECK-NEXT:    ret
136  %v = select i1 %c, <vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b
137  ret <vscale x 16 x bfloat> %v
138}
139
140define <vscale x 16 x bfloat> @selectcc_nxv16bf16(bfloat %a, bfloat %b, <vscale x 16 x bfloat> %c, <vscale x 16 x bfloat> %d) {
141; CHECK-LABEL: selectcc_nxv16bf16:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
144; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
145; CHECK-NEXT:    feq.s a0, fa4, fa5
146; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
147; CHECK-NEXT:    vmv.v.x v16, a0
148; CHECK-NEXT:    vmsne.vi v0, v16, 0
149; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
150; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
151; CHECK-NEXT:    ret
152  %cmp = fcmp oeq bfloat %a, %b
153  %v = select i1 %cmp, <vscale x 16 x bfloat> %c, <vscale x 16 x bfloat> %d
154  ret <vscale x 16 x bfloat> %v
155}
156
157define <vscale x 32 x bfloat> @select_nxv32bf16(i1 zeroext %c, <vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) {
158; CHECK-LABEL: select_nxv32bf16:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
161; CHECK-NEXT:    vmv.v.x v24, a0
162; CHECK-NEXT:    vmsne.vi v0, v24, 0
163; CHECK-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
164; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
165; CHECK-NEXT:    ret
166  %v = select i1 %c, <vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b
167  ret <vscale x 32 x bfloat> %v
168}
169
170define <vscale x 32 x bfloat> @selectcc_nxv32bf16(bfloat %a, bfloat %b, <vscale x 32 x bfloat> %c, <vscale x 32 x bfloat> %d) {
171; CHECK-LABEL: selectcc_nxv32bf16:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    fcvt.s.bf16 fa5, fa1
174; CHECK-NEXT:    fcvt.s.bf16 fa4, fa0
175; CHECK-NEXT:    feq.s a0, fa4, fa5
176; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
177; CHECK-NEXT:    vmv.v.x v24, a0
178; CHECK-NEXT:    vmsne.vi v0, v24, 0
179; CHECK-NEXT:    vsetvli zero, zero, e16, m8, ta, ma
180; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
181; CHECK-NEXT:    ret
182  %cmp = fcmp oeq bfloat %a, %b
183  %v = select i1 %cmp, <vscale x 32 x bfloat> %c, <vscale x 32 x bfloat> %d
184  ret <vscale x 32 x bfloat> %v
185}
186