xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/localvar.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+v < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64IV
4
5define void @local_var_mf8() {
6; RV64IV-LABEL: local_var_mf8:
7; RV64IV:       # %bb.0:
8; RV64IV-NEXT:    addi sp, sp, -16
9; RV64IV-NEXT:    .cfi_def_cfa_offset 16
10; RV64IV-NEXT:    csrr a0, vlenb
11; RV64IV-NEXT:    slli a0, a0, 1
12; RV64IV-NEXT:    sub sp, sp, a0
13; RV64IV-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
14; RV64IV-NEXT:    csrr a0, vlenb
15; RV64IV-NEXT:    add a0, sp, a0
16; RV64IV-NEXT:    addi a0, a0, 16
17; RV64IV-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
18; RV64IV-NEXT:    vle8.v v8, (a0)
19; RV64IV-NEXT:    addi a0, sp, 16
20; RV64IV-NEXT:    vle8.v v8, (a0)
21; RV64IV-NEXT:    csrr a0, vlenb
22; RV64IV-NEXT:    slli a0, a0, 1
23; RV64IV-NEXT:    add sp, sp, a0
24; RV64IV-NEXT:    .cfi_def_cfa sp, 16
25; RV64IV-NEXT:    addi sp, sp, 16
26; RV64IV-NEXT:    .cfi_def_cfa_offset 0
27; RV64IV-NEXT:    ret
28  %local0 = alloca <vscale x 1 x i8>
29  %local1 = alloca <vscale x 1 x i8>
30  load volatile <vscale x 1 x i8>, ptr %local0
31  load volatile <vscale x 1 x i8>, ptr %local1
32  ret void
33}
34
35define void @local_var_m1() {
36; RV64IV-LABEL: local_var_m1:
37; RV64IV:       # %bb.0:
38; RV64IV-NEXT:    addi sp, sp, -16
39; RV64IV-NEXT:    .cfi_def_cfa_offset 16
40; RV64IV-NEXT:    csrr a0, vlenb
41; RV64IV-NEXT:    slli a0, a0, 1
42; RV64IV-NEXT:    sub sp, sp, a0
43; RV64IV-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
44; RV64IV-NEXT:    csrr a0, vlenb
45; RV64IV-NEXT:    add a0, sp, a0
46; RV64IV-NEXT:    addi a0, a0, 16
47; RV64IV-NEXT:    vl1r.v v8, (a0)
48; RV64IV-NEXT:    addi a0, sp, 16
49; RV64IV-NEXT:    vl1r.v v8, (a0)
50; RV64IV-NEXT:    csrr a0, vlenb
51; RV64IV-NEXT:    slli a0, a0, 1
52; RV64IV-NEXT:    add sp, sp, a0
53; RV64IV-NEXT:    .cfi_def_cfa sp, 16
54; RV64IV-NEXT:    addi sp, sp, 16
55; RV64IV-NEXT:    .cfi_def_cfa_offset 0
56; RV64IV-NEXT:    ret
57  %local0 = alloca <vscale x 8 x i8>
58  %local1 = alloca <vscale x 8 x i8>
59  load volatile <vscale x 8 x i8>, ptr %local0
60  load volatile <vscale x 8 x i8>, ptr %local1
61  ret void
62}
63
64define void @local_var_m2() {
65; RV64IV-LABEL: local_var_m2:
66; RV64IV:       # %bb.0:
67; RV64IV-NEXT:    addi sp, sp, -16
68; RV64IV-NEXT:    .cfi_def_cfa_offset 16
69; RV64IV-NEXT:    csrr a0, vlenb
70; RV64IV-NEXT:    slli a0, a0, 2
71; RV64IV-NEXT:    sub sp, sp, a0
72; RV64IV-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
73; RV64IV-NEXT:    csrr a0, vlenb
74; RV64IV-NEXT:    slli a0, a0, 1
75; RV64IV-NEXT:    add a0, sp, a0
76; RV64IV-NEXT:    addi a0, a0, 16
77; RV64IV-NEXT:    vl2r.v v8, (a0)
78; RV64IV-NEXT:    addi a0, sp, 16
79; RV64IV-NEXT:    vl2r.v v8, (a0)
80; RV64IV-NEXT:    csrr a0, vlenb
81; RV64IV-NEXT:    slli a0, a0, 2
82; RV64IV-NEXT:    add sp, sp, a0
83; RV64IV-NEXT:    .cfi_def_cfa sp, 16
84; RV64IV-NEXT:    addi sp, sp, 16
85; RV64IV-NEXT:    .cfi_def_cfa_offset 0
86; RV64IV-NEXT:    ret
87  %local0 = alloca <vscale x 16 x i8>
88  %local1 = alloca <vscale x 16 x i8>
89  load volatile <vscale x 16 x i8>, ptr %local0
90  load volatile <vscale x 16 x i8>, ptr %local1
91  ret void
92}
93
94define void @local_var_m4() {
95; RV64IV-LABEL: local_var_m4:
96; RV64IV:       # %bb.0:
97; RV64IV-NEXT:    addi sp, sp, -48
98; RV64IV-NEXT:    .cfi_def_cfa_offset 48
99; RV64IV-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
100; RV64IV-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
101; RV64IV-NEXT:    .cfi_offset ra, -8
102; RV64IV-NEXT:    .cfi_offset s0, -16
103; RV64IV-NEXT:    addi s0, sp, 48
104; RV64IV-NEXT:    .cfi_def_cfa s0, 0
105; RV64IV-NEXT:    csrr a0, vlenb
106; RV64IV-NEXT:    slli a0, a0, 3
107; RV64IV-NEXT:    sub sp, sp, a0
108; RV64IV-NEXT:    andi sp, sp, -32
109; RV64IV-NEXT:    csrr a0, vlenb
110; RV64IV-NEXT:    slli a0, a0, 2
111; RV64IV-NEXT:    add a0, sp, a0
112; RV64IV-NEXT:    addi a0, a0, 32
113; RV64IV-NEXT:    vl4r.v v8, (a0)
114; RV64IV-NEXT:    addi a0, sp, 32
115; RV64IV-NEXT:    vl4r.v v8, (a0)
116; RV64IV-NEXT:    addi sp, s0, -48
117; RV64IV-NEXT:    .cfi_def_cfa sp, 48
118; RV64IV-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
119; RV64IV-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
120; RV64IV-NEXT:    .cfi_restore ra
121; RV64IV-NEXT:    .cfi_restore s0
122; RV64IV-NEXT:    addi sp, sp, 48
123; RV64IV-NEXT:    .cfi_def_cfa_offset 0
124; RV64IV-NEXT:    ret
125  %local0 = alloca <vscale x 32 x i8>
126  %local1 = alloca <vscale x 32 x i8>
127  load volatile <vscale x 32 x i8>, ptr %local0
128  load volatile <vscale x 32 x i8>, ptr %local1
129  ret void
130}
131
132define void @local_var_m8() {
133; RV64IV-LABEL: local_var_m8:
134; RV64IV:       # %bb.0:
135; RV64IV-NEXT:    addi sp, sp, -80
136; RV64IV-NEXT:    .cfi_def_cfa_offset 80
137; RV64IV-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
138; RV64IV-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
139; RV64IV-NEXT:    .cfi_offset ra, -8
140; RV64IV-NEXT:    .cfi_offset s0, -16
141; RV64IV-NEXT:    addi s0, sp, 80
142; RV64IV-NEXT:    .cfi_def_cfa s0, 0
143; RV64IV-NEXT:    csrr a0, vlenb
144; RV64IV-NEXT:    slli a0, a0, 4
145; RV64IV-NEXT:    sub sp, sp, a0
146; RV64IV-NEXT:    andi sp, sp, -64
147; RV64IV-NEXT:    csrr a0, vlenb
148; RV64IV-NEXT:    slli a0, a0, 3
149; RV64IV-NEXT:    add a0, sp, a0
150; RV64IV-NEXT:    addi a0, a0, 64
151; RV64IV-NEXT:    vl8r.v v8, (a0)
152; RV64IV-NEXT:    addi a0, sp, 64
153; RV64IV-NEXT:    vl8r.v v8, (a0)
154; RV64IV-NEXT:    addi sp, s0, -80
155; RV64IV-NEXT:    .cfi_def_cfa sp, 80
156; RV64IV-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
157; RV64IV-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
158; RV64IV-NEXT:    .cfi_restore ra
159; RV64IV-NEXT:    .cfi_restore s0
160; RV64IV-NEXT:    addi sp, sp, 80
161; RV64IV-NEXT:    .cfi_def_cfa_offset 0
162; RV64IV-NEXT:    ret
163  %local0 = alloca <vscale x 64 x i8>
164  %local1 = alloca <vscale x 64 x i8>
165  load volatile <vscale x 64 x i8>, ptr %local0
166  load volatile <vscale x 64 x i8>, ptr %local1
167  ret void
168}
169
170define void @local_var_m2_mix_local_scalar() {
171; RV64IV-LABEL: local_var_m2_mix_local_scalar:
172; RV64IV:       # %bb.0:
173; RV64IV-NEXT:    addi sp, sp, -16
174; RV64IV-NEXT:    .cfi_def_cfa_offset 16
175; RV64IV-NEXT:    csrr a0, vlenb
176; RV64IV-NEXT:    slli a0, a0, 2
177; RV64IV-NEXT:    sub sp, sp, a0
178; RV64IV-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
179; RV64IV-NEXT:    lw zero, 12(sp)
180; RV64IV-NEXT:    csrr a0, vlenb
181; RV64IV-NEXT:    slli a0, a0, 1
182; RV64IV-NEXT:    add a0, sp, a0
183; RV64IV-NEXT:    addi a0, a0, 16
184; RV64IV-NEXT:    vl2r.v v8, (a0)
185; RV64IV-NEXT:    addi a0, sp, 16
186; RV64IV-NEXT:    vl2r.v v8, (a0)
187; RV64IV-NEXT:    lw zero, 8(sp)
188; RV64IV-NEXT:    csrr a0, vlenb
189; RV64IV-NEXT:    slli a0, a0, 2
190; RV64IV-NEXT:    add sp, sp, a0
191; RV64IV-NEXT:    .cfi_def_cfa sp, 16
192; RV64IV-NEXT:    addi sp, sp, 16
193; RV64IV-NEXT:    .cfi_def_cfa_offset 0
194; RV64IV-NEXT:    ret
195  %local_scalar0 = alloca i32
196  %local0 = alloca <vscale x 16 x i8>
197  %local1 = alloca <vscale x 16 x i8>
198  %local_scalar1 = alloca i32
199  load volatile i32, ptr %local_scalar0
200  load volatile <vscale x 16 x i8>, ptr %local0
201  load volatile <vscale x 16 x i8>, ptr %local1
202  load volatile i32, ptr %local_scalar1
203  ret void
204}
205
206define void @local_var_m2_with_varsize_object(i64 %n) {
207; RV64IV-LABEL: local_var_m2_with_varsize_object:
208; RV64IV:       # %bb.0:
209; RV64IV-NEXT:    addi sp, sp, -32
210; RV64IV-NEXT:    .cfi_def_cfa_offset 32
211; RV64IV-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
212; RV64IV-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
213; RV64IV-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
214; RV64IV-NEXT:    .cfi_offset ra, -8
215; RV64IV-NEXT:    .cfi_offset s0, -16
216; RV64IV-NEXT:    .cfi_offset s1, -24
217; RV64IV-NEXT:    addi s0, sp, 32
218; RV64IV-NEXT:    .cfi_def_cfa s0, 0
219; RV64IV-NEXT:    csrr a1, vlenb
220; RV64IV-NEXT:    slli a1, a1, 2
221; RV64IV-NEXT:    sub sp, sp, a1
222; RV64IV-NEXT:    addi a0, a0, 15
223; RV64IV-NEXT:    andi a0, a0, -16
224; RV64IV-NEXT:    sub a0, sp, a0
225; RV64IV-NEXT:    mv sp, a0
226; RV64IV-NEXT:    csrr a1, vlenb
227; RV64IV-NEXT:    slli a1, a1, 1
228; RV64IV-NEXT:    sub a1, s0, a1
229; RV64IV-NEXT:    addi a1, a1, -32
230; RV64IV-NEXT:    csrr s1, vlenb
231; RV64IV-NEXT:    slli s1, s1, 1
232; RV64IV-NEXT:    sub s1, s0, s1
233; RV64IV-NEXT:    addi s1, s1, -32
234; RV64IV-NEXT:    call notdead
235; RV64IV-NEXT:    vl2r.v v8, (s1)
236; RV64IV-NEXT:    csrr a0, vlenb
237; RV64IV-NEXT:    slli a0, a0, 2
238; RV64IV-NEXT:    sub a0, s0, a0
239; RV64IV-NEXT:    addi a0, a0, -32
240; RV64IV-NEXT:    vl2r.v v8, (a0)
241; RV64IV-NEXT:    addi sp, s0, -32
242; RV64IV-NEXT:    .cfi_def_cfa sp, 32
243; RV64IV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
244; RV64IV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
245; RV64IV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
246; RV64IV-NEXT:    .cfi_restore ra
247; RV64IV-NEXT:    .cfi_restore s0
248; RV64IV-NEXT:    .cfi_restore s1
249; RV64IV-NEXT:    addi sp, sp, 32
250; RV64IV-NEXT:    .cfi_def_cfa_offset 0
251; RV64IV-NEXT:    ret
252  %1 = alloca i8, i64 %n
253  %2 = alloca <vscale x 16 x i8>
254  %3 = alloca <vscale x 16 x i8>
255  call void @notdead(ptr %1, ptr %2)
256  load volatile <vscale x 16 x i8>, ptr %2
257  load volatile <vscale x 16 x i8>, ptr %3
258  ret void
259}
260
261define void @local_var_m2_with_bp(i64 %n) {
262; RV64IV-LABEL: local_var_m2_with_bp:
263; RV64IV:       # %bb.0:
264; RV64IV-NEXT:    addi sp, sp, -256
265; RV64IV-NEXT:    .cfi_def_cfa_offset 256
266; RV64IV-NEXT:    sd ra, 248(sp) # 8-byte Folded Spill
267; RV64IV-NEXT:    sd s0, 240(sp) # 8-byte Folded Spill
268; RV64IV-NEXT:    sd s1, 232(sp) # 8-byte Folded Spill
269; RV64IV-NEXT:    sd s2, 224(sp) # 8-byte Folded Spill
270; RV64IV-NEXT:    .cfi_offset ra, -8
271; RV64IV-NEXT:    .cfi_offset s0, -16
272; RV64IV-NEXT:    .cfi_offset s1, -24
273; RV64IV-NEXT:    .cfi_offset s2, -32
274; RV64IV-NEXT:    addi s0, sp, 256
275; RV64IV-NEXT:    .cfi_def_cfa s0, 0
276; RV64IV-NEXT:    csrr a1, vlenb
277; RV64IV-NEXT:    slli a1, a1, 2
278; RV64IV-NEXT:    sub sp, sp, a1
279; RV64IV-NEXT:    andi sp, sp, -128
280; RV64IV-NEXT:    mv s1, sp
281; RV64IV-NEXT:    addi a0, a0, 15
282; RV64IV-NEXT:    andi a0, a0, -16
283; RV64IV-NEXT:    sub a0, sp, a0
284; RV64IV-NEXT:    mv sp, a0
285; RV64IV-NEXT:    addi a1, s1, 128
286; RV64IV-NEXT:    csrr a2, vlenb
287; RV64IV-NEXT:    slli a2, a2, 1
288; RV64IV-NEXT:    add a2, s1, a2
289; RV64IV-NEXT:    addi a2, a2, 224
290; RV64IV-NEXT:    csrr s2, vlenb
291; RV64IV-NEXT:    slli s2, s2, 1
292; RV64IV-NEXT:    add s2, s1, s2
293; RV64IV-NEXT:    addi s2, s2, 224
294; RV64IV-NEXT:    call notdead2
295; RV64IV-NEXT:    lw zero, 124(s1)
296; RV64IV-NEXT:    vl2r.v v8, (s2)
297; RV64IV-NEXT:    addi a0, s1, 224
298; RV64IV-NEXT:    vl2r.v v8, (a0)
299; RV64IV-NEXT:    lw zero, 120(s1)
300; RV64IV-NEXT:    addi sp, s0, -256
301; RV64IV-NEXT:    .cfi_def_cfa sp, 256
302; RV64IV-NEXT:    ld ra, 248(sp) # 8-byte Folded Reload
303; RV64IV-NEXT:    ld s0, 240(sp) # 8-byte Folded Reload
304; RV64IV-NEXT:    ld s1, 232(sp) # 8-byte Folded Reload
305; RV64IV-NEXT:    ld s2, 224(sp) # 8-byte Folded Reload
306; RV64IV-NEXT:    .cfi_restore ra
307; RV64IV-NEXT:    .cfi_restore s0
308; RV64IV-NEXT:    .cfi_restore s1
309; RV64IV-NEXT:    .cfi_restore s2
310; RV64IV-NEXT:    addi sp, sp, 256
311; RV64IV-NEXT:    .cfi_def_cfa_offset 0
312; RV64IV-NEXT:    ret
313  %1 = alloca i8, i64 %n
314  %2 = alloca i32, align 128
315  %local_scalar0 = alloca i32
316  %local0 = alloca <vscale x 16 x i8>
317  %local1 = alloca <vscale x 16 x i8>
318  %local_scalar1 = alloca i32
319  call void @notdead2(ptr %1, ptr %2, ptr %local0)
320  load volatile i32, ptr %local_scalar0
321  load volatile <vscale x 16 x i8>, ptr %local0
322  load volatile <vscale x 16 x i8>, ptr %local1
323  load volatile i32, ptr %local_scalar1
324  ret void
325}
326
327define i64 @fixed_object(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) nounwind {
328; RV64IV-LABEL: fixed_object:
329; RV64IV:       # %bb.0:
330; RV64IV-NEXT:    addi sp, sp, -16
331; RV64IV-NEXT:    csrr a0, vlenb
332; RV64IV-NEXT:    slli a0, a0, 3
333; RV64IV-NEXT:    sub sp, sp, a0
334; RV64IV-NEXT:    csrr a0, vlenb
335; RV64IV-NEXT:    slli a0, a0, 3
336; RV64IV-NEXT:    add a0, sp, a0
337; RV64IV-NEXT:    ld a0, 16(a0)
338; RV64IV-NEXT:    csrr a1, vlenb
339; RV64IV-NEXT:    slli a1, a1, 3
340; RV64IV-NEXT:    add sp, sp, a1
341; RV64IV-NEXT:    addi sp, sp, 16
342; RV64IV-NEXT:    ret
343  %fixed_size = alloca i32
344  %rvv_vector = alloca <vscale x 8 x i64>, align 8
345  ret i64 %8
346}
347
348declare void @notdead(ptr, ptr)
349declare void @notdead2(ptr, ptr, ptr)
350