1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s 3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfbfmin -verify-machineinstrs | FileCheck %s 4 5define <vscale x 1 x bfloat> @load_nxv1bf16(ptr %p) { 6; CHECK-LABEL: load_nxv1bf16: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma 9; CHECK-NEXT: vle16.v v8, (a0) 10; CHECK-NEXT: ret 11 %x = load <vscale x 1 x bfloat>, ptr %p 12 ret <vscale x 1 x bfloat> %x 13} 14 15define <vscale x 2 x bfloat> @load_nxv2bf16(ptr %p) { 16; CHECK-LABEL: load_nxv2bf16: 17; CHECK: # %bb.0: 18; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma 19; CHECK-NEXT: vle16.v v8, (a0) 20; CHECK-NEXT: ret 21 %x = load <vscale x 2 x bfloat>, ptr %p 22 ret <vscale x 2 x bfloat> %x 23} 24 25define <vscale x 4 x bfloat> @load_nxv4bf16(ptr %p) { 26; CHECK-LABEL: load_nxv4bf16: 27; CHECK: # %bb.0: 28; CHECK-NEXT: vl1re16.v v8, (a0) 29; CHECK-NEXT: ret 30 %x = load <vscale x 4 x bfloat>, ptr %p 31 ret <vscale x 4 x bfloat> %x 32} 33 34define <vscale x 8 x bfloat> @load_nxv8bf16(ptr %p) { 35; CHECK-LABEL: load_nxv8bf16: 36; CHECK: # %bb.0: 37; CHECK-NEXT: vl2re16.v v8, (a0) 38; CHECK-NEXT: ret 39 %x = load <vscale x 8 x bfloat>, ptr %p 40 ret <vscale x 8 x bfloat> %x 41} 42 43define <vscale x 16 x bfloat> @load_nxv16bf16(ptr %p) { 44; CHECK-LABEL: load_nxv16bf16: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vl4re16.v v8, (a0) 47; CHECK-NEXT: ret 48 %x = load <vscale x 16 x bfloat>, ptr %p 49 ret <vscale x 16 x bfloat> %x 50} 51 52define <vscale x 32 x bfloat> @load_nxv32bf16(ptr %p) { 53; CHECK-LABEL: load_nxv32bf16: 54; CHECK: # %bb.0: 55; CHECK-NEXT: vl8re16.v v8, (a0) 56; CHECK-NEXT: ret 57 %x = load <vscale x 32 x bfloat>, ptr %p 58 ret <vscale x 32 x bfloat> %x 59} 60 61define <vscale x 4 x float> @extload(ptr %p) { 62; CHECK-LABEL: extload: 63; CHECK: # %bb.0: 64; CHECK-NEXT: vl1re16.v v10, (a0) 65; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma 66; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10 67; CHECK-NEXT: ret 68 %x = load <vscale x 4 x bfloat>, ptr %p 69 %y = fpext <vscale x 4 x bfloat> %x to <vscale x 4 x float> 70 ret <vscale x 4 x float> %y 71} 72