1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s 3 4; This test makes sure we match FrameIndex into the base address. 5; Done as a MIR test because eliminateFrameIndex will likely turn it 6; back into an addi. 7 8declare void @llvm.riscv.vse.nxv1i64( 9 <vscale x 1 x i64>, 10 ptr, 11 i64); 12 13define i64 @test(<vscale x 1 x i64> %0) nounwind { 14 ; CHECK-LABEL: name: test 15 ; CHECK: bb.0.entry: 16 ; CHECK-NEXT: liveins: $v8 17 ; CHECK-NEXT: {{ $}} 18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8 19 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.a, 0 20 ; CHECK-NEXT: PseudoVSE64_V_M1 [[COPY]], killed [[ADDI]], 1, 6 /* e64 */ 21 ; CHECK-NEXT: [[LD:%[0-9]+]]:gpr = LD %stack.0.a, 0 :: (dereferenceable load (s64) from %ir.a) 22 ; CHECK-NEXT: $x10 = COPY [[LD]] 23 ; CHECK-NEXT: PseudoRET implicit $x10 24entry: 25 %a = alloca i64 26 %b = bitcast ptr %a to ptr 27 call void @llvm.riscv.vse.nxv1i64( 28 <vscale x 1 x i64> %0, 29 ptr %b, 30 i64 1) 31 %c = load i64, ptr %a 32 ret i64 %c 33} 34