xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
3; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
5; RUN:   -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
6; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
7; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
9; RUN:   -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
10; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \
11; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
12; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \
13; RUN:   -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
14; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \
15; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
16; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \
17; RUN:   -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
18
19declare <vscale x 1 x bfloat> @llvm.minimum.nxv1bf16(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>)
20
21define <vscale x 1 x bfloat> @vfmin_nxv1bf16_vv(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b) {
22; CHECK-LABEL: vfmin_nxv1bf16_vv:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
25; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8
26; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
27; CHECK-NEXT:    vmfeq.vv v0, v10, v10
28; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
29; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v9
30; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
31; CHECK-NEXT:    vmerge.vvm v9, v10, v8, v0
32; CHECK-NEXT:    vmfeq.vv v0, v8, v8
33; CHECK-NEXT:    vmerge.vvm v8, v8, v10, v0
34; CHECK-NEXT:    vfmin.vv v9, v8, v9
35; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
36; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
37; CHECK-NEXT:    ret
38  %v = call <vscale x 1 x bfloat> @llvm.minimum.nxv1bf16(<vscale x 1 x bfloat> %a, <vscale x 1 x bfloat> %b)
39  ret <vscale x 1 x bfloat> %v
40}
41
42declare <vscale x 2 x bfloat> @llvm.minimum.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>)
43
44define <vscale x 2 x bfloat> @vfmin_nxv2bf16_vv(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) {
45; CHECK-LABEL: vfmin_nxv2bf16_vv:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
48; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8
49; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
50; CHECK-NEXT:    vmfeq.vv v0, v10, v10
51; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
52; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v9
53; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
54; CHECK-NEXT:    vmerge.vvm v9, v10, v8, v0
55; CHECK-NEXT:    vmfeq.vv v0, v8, v8
56; CHECK-NEXT:    vmerge.vvm v8, v8, v10, v0
57; CHECK-NEXT:    vfmin.vv v9, v8, v9
58; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
59; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
60; CHECK-NEXT:    ret
61  %v = call <vscale x 2 x bfloat> @llvm.minimum.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b)
62  ret <vscale x 2 x bfloat> %v
63}
64
65declare <vscale x 4 x bfloat> @llvm.minimum.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>)
66
67define <vscale x 4 x bfloat> @vfmin_nxv4bf16_vv(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) {
68; CHECK-LABEL: vfmin_nxv4bf16_vv:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
71; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8
72; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
73; CHECK-NEXT:    vmfeq.vv v0, v10, v10
74; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
75; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v9
76; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
77; CHECK-NEXT:    vmerge.vvm v8, v10, v12, v0
78; CHECK-NEXT:    vmfeq.vv v0, v12, v12
79; CHECK-NEXT:    vmerge.vvm v10, v12, v10, v0
80; CHECK-NEXT:    vfmin.vv v10, v10, v8
81; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
82; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
83; CHECK-NEXT:    ret
84  %v = call <vscale x 4 x bfloat> @llvm.minimum.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b)
85  ret <vscale x 4 x bfloat> %v
86}
87
88declare <vscale x 8 x bfloat> @llvm.minimum.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
89
90define <vscale x 8 x bfloat> @vfmin_nxv8bf16_vv(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {
91; CHECK-LABEL: vfmin_nxv8bf16_vv:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
94; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8
95; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
96; CHECK-NEXT:    vmfeq.vv v0, v12, v12
97; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
98; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v10
99; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
100; CHECK-NEXT:    vmerge.vvm v8, v12, v16, v0
101; CHECK-NEXT:    vmfeq.vv v0, v16, v16
102; CHECK-NEXT:    vmerge.vvm v12, v16, v12, v0
103; CHECK-NEXT:    vfmin.vv v12, v12, v8
104; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
105; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v12
106; CHECK-NEXT:    ret
107  %v = call <vscale x 8 x bfloat> @llvm.minimum.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)
108  ret <vscale x 8 x bfloat> %v
109}
110
111declare <vscale x 16 x bfloat> @llvm.minimum.nxv16bf16(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>)
112
113define <vscale x 16 x bfloat> @vfmin_nxv16bf16_vv(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b) {
114; CHECK-LABEL: vfmin_nxv16bf16_vv:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    addi sp, sp, -16
117; CHECK-NEXT:    .cfi_def_cfa_offset 16
118; CHECK-NEXT:    csrr a0, vlenb
119; CHECK-NEXT:    slli a0, a0, 3
120; CHECK-NEXT:    sub sp, sp, a0
121; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
122; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
123; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v12
124; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v8
125; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
126; CHECK-NEXT:    vmfeq.vv v0, v24, v24
127; CHECK-NEXT:    vmfeq.vv v7, v16, v16
128; CHECK-NEXT:    vmerge.vvm v8, v24, v16, v0
129; CHECK-NEXT:    addi a0, sp, 16
130; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
131; CHECK-NEXT:    vmv1r.v v0, v7
132; CHECK-NEXT:    vmerge.vvm v8, v16, v24, v0
133; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
134; CHECK-NEXT:    vfmin.vv v16, v8, v16
135; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
136; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16
137; CHECK-NEXT:    csrr a0, vlenb
138; CHECK-NEXT:    slli a0, a0, 3
139; CHECK-NEXT:    add sp, sp, a0
140; CHECK-NEXT:    .cfi_def_cfa sp, 16
141; CHECK-NEXT:    addi sp, sp, 16
142; CHECK-NEXT:    .cfi_def_cfa_offset 0
143; CHECK-NEXT:    ret
144  %v = call <vscale x 16 x bfloat> @llvm.minimum.nxv16bf16(<vscale x 16 x bfloat> %a, <vscale x 16 x bfloat> %b)
145  ret <vscale x 16 x bfloat> %v
146}
147
148declare <vscale x 32 x bfloat> @llvm.minimum.nxv32bf16(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>)
149
150define <vscale x 32 x bfloat> @vfmin_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b) nounwind {
151; ZVFH-LABEL: vfmin_nxv32bf16_vv:
152; ZVFH:       # %bb.0:
153; ZVFH-NEXT:    addi sp, sp, -16
154; ZVFH-NEXT:    csrr a0, vlenb
155; ZVFH-NEXT:    slli a0, a0, 3
156; ZVFH-NEXT:    mv a1, a0
157; ZVFH-NEXT:    slli a0, a0, 1
158; ZVFH-NEXT:    add a0, a0, a1
159; ZVFH-NEXT:    sub sp, sp, a0
160; ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
161; ZVFH-NEXT:    vmv8r.v v24, v16
162; ZVFH-NEXT:    csrr a0, vlenb
163; ZVFH-NEXT:    slli a0, a0, 3
164; ZVFH-NEXT:    add a0, sp, a0
165; ZVFH-NEXT:    addi a0, a0, 16
166; ZVFH-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
167; ZVFH-NEXT:    vmv8r.v v0, v8
168; ZVFH-NEXT:    vfwcvtbf16.f.f.v v16, v24
169; ZVFH-NEXT:    vfwcvtbf16.f.f.v v8, v0
170; ZVFH-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
171; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
172; ZVFH-NEXT:    vmfeq.vv v3, v16, v16
173; ZVFH-NEXT:    vmerge.vvm v24, v8, v16, v0
174; ZVFH-NEXT:    csrr a0, vlenb
175; ZVFH-NEXT:    slli a0, a0, 4
176; ZVFH-NEXT:    add a0, sp, a0
177; ZVFH-NEXT:    addi a0, a0, 16
178; ZVFH-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
179; ZVFH-NEXT:    vmv1r.v v0, v3
180; ZVFH-NEXT:    vmerge.vvm v8, v16, v8, v0
181; ZVFH-NEXT:    addi a0, sp, 16
182; ZVFH-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
183; ZVFH-NEXT:    csrr a0, vlenb
184; ZVFH-NEXT:    slli a0, a0, 3
185; ZVFH-NEXT:    add a0, sp, a0
186; ZVFH-NEXT:    addi a0, a0, 16
187; ZVFH-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
188; ZVFH-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
189; ZVFH-NEXT:    vfwcvtbf16.f.f.v v24, v12
190; ZVFH-NEXT:    vfwcvtbf16.f.f.v v8, v4
191; ZVFH-NEXT:    csrr a0, vlenb
192; ZVFH-NEXT:    slli a0, a0, 4
193; ZVFH-NEXT:    add a0, sp, a0
194; ZVFH-NEXT:    addi a0, a0, 16
195; ZVFH-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
196; ZVFH-NEXT:    addi a0, sp, 16
197; ZVFH-NEXT:    vl8r.v v0, (a0) # Unknown-size Folded Reload
198; ZVFH-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
199; ZVFH-NEXT:    vfmin.vv v16, v0, v16
200; ZVFH-NEXT:    csrr a0, vlenb
201; ZVFH-NEXT:    slli a0, a0, 4
202; ZVFH-NEXT:    add a0, sp, a0
203; ZVFH-NEXT:    addi a0, a0, 16
204; ZVFH-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
205; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
206; ZVFH-NEXT:    vmfeq.vv v7, v24, v24
207; ZVFH-NEXT:    vmerge.vvm v16, v8, v24, v0
208; ZVFH-NEXT:    vmv1r.v v0, v7
209; ZVFH-NEXT:    vmerge.vvm v8, v24, v8, v0
210; ZVFH-NEXT:    vfmin.vv v16, v8, v16
211; ZVFH-NEXT:    csrr a0, vlenb
212; ZVFH-NEXT:    slli a0, a0, 4
213; ZVFH-NEXT:    add a0, sp, a0
214; ZVFH-NEXT:    addi a0, a0, 16
215; ZVFH-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
216; ZVFH-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
217; ZVFH-NEXT:    vfncvtbf16.f.f.w v8, v24
218; ZVFH-NEXT:    vfncvtbf16.f.f.w v12, v16
219; ZVFH-NEXT:    csrr a0, vlenb
220; ZVFH-NEXT:    slli a0, a0, 3
221; ZVFH-NEXT:    mv a1, a0
222; ZVFH-NEXT:    slli a0, a0, 1
223; ZVFH-NEXT:    add a0, a0, a1
224; ZVFH-NEXT:    add sp, sp, a0
225; ZVFH-NEXT:    addi sp, sp, 16
226; ZVFH-NEXT:    ret
227;
228; ZVFHMIN-LABEL: vfmin_nxv32bf16_vv:
229; ZVFHMIN:       # %bb.0:
230; ZVFHMIN-NEXT:    addi sp, sp, -16
231; ZVFHMIN-NEXT:    csrr a0, vlenb
232; ZVFHMIN-NEXT:    li a1, 24
233; ZVFHMIN-NEXT:    mul a0, a0, a1
234; ZVFHMIN-NEXT:    sub sp, sp, a0
235; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
236; ZVFHMIN-NEXT:    vmv8r.v v24, v16
237; ZVFHMIN-NEXT:    csrr a0, vlenb
238; ZVFHMIN-NEXT:    slli a0, a0, 3
239; ZVFHMIN-NEXT:    add a0, sp, a0
240; ZVFHMIN-NEXT:    addi a0, a0, 16
241; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
242; ZVFHMIN-NEXT:    vmv8r.v v0, v8
243; ZVFHMIN-NEXT:    vfwcvtbf16.f.f.v v16, v24
244; ZVFHMIN-NEXT:    vfwcvtbf16.f.f.v v8, v0
245; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
246; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
247; ZVFHMIN-NEXT:    vmfeq.vv v3, v16, v16
248; ZVFHMIN-NEXT:    vmerge.vvm v24, v8, v16, v0
249; ZVFHMIN-NEXT:    csrr a0, vlenb
250; ZVFHMIN-NEXT:    slli a0, a0, 4
251; ZVFHMIN-NEXT:    add a0, sp, a0
252; ZVFHMIN-NEXT:    addi a0, a0, 16
253; ZVFHMIN-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
254; ZVFHMIN-NEXT:    vmv1r.v v0, v3
255; ZVFHMIN-NEXT:    vmerge.vvm v8, v16, v8, v0
256; ZVFHMIN-NEXT:    addi a0, sp, 16
257; ZVFHMIN-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
258; ZVFHMIN-NEXT:    csrr a0, vlenb
259; ZVFHMIN-NEXT:    slli a0, a0, 3
260; ZVFHMIN-NEXT:    add a0, sp, a0
261; ZVFHMIN-NEXT:    addi a0, a0, 16
262; ZVFHMIN-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
263; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
264; ZVFHMIN-NEXT:    vfwcvtbf16.f.f.v v24, v12
265; ZVFHMIN-NEXT:    vfwcvtbf16.f.f.v v8, v4
266; ZVFHMIN-NEXT:    csrr a0, vlenb
267; ZVFHMIN-NEXT:    slli a0, a0, 4
268; ZVFHMIN-NEXT:    add a0, sp, a0
269; ZVFHMIN-NEXT:    addi a0, a0, 16
270; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
271; ZVFHMIN-NEXT:    addi a0, sp, 16
272; ZVFHMIN-NEXT:    vl8r.v v0, (a0) # Unknown-size Folded Reload
273; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
274; ZVFHMIN-NEXT:    vfmin.vv v16, v0, v16
275; ZVFHMIN-NEXT:    csrr a0, vlenb
276; ZVFHMIN-NEXT:    slli a0, a0, 4
277; ZVFHMIN-NEXT:    add a0, sp, a0
278; ZVFHMIN-NEXT:    addi a0, a0, 16
279; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
280; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
281; ZVFHMIN-NEXT:    vmfeq.vv v7, v24, v24
282; ZVFHMIN-NEXT:    vmerge.vvm v16, v8, v24, v0
283; ZVFHMIN-NEXT:    vmv1r.v v0, v7
284; ZVFHMIN-NEXT:    vmerge.vvm v8, v24, v8, v0
285; ZVFHMIN-NEXT:    vfmin.vv v16, v8, v16
286; ZVFHMIN-NEXT:    csrr a0, vlenb
287; ZVFHMIN-NEXT:    slli a0, a0, 4
288; ZVFHMIN-NEXT:    add a0, sp, a0
289; ZVFHMIN-NEXT:    addi a0, a0, 16
290; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
291; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
292; ZVFHMIN-NEXT:    vfncvtbf16.f.f.w v8, v24
293; ZVFHMIN-NEXT:    vfncvtbf16.f.f.w v12, v16
294; ZVFHMIN-NEXT:    csrr a0, vlenb
295; ZVFHMIN-NEXT:    li a1, 24
296; ZVFHMIN-NEXT:    mul a0, a0, a1
297; ZVFHMIN-NEXT:    add sp, sp, a0
298; ZVFHMIN-NEXT:    addi sp, sp, 16
299; ZVFHMIN-NEXT:    ret
300  %v = call <vscale x 32 x bfloat> @llvm.minimum.nxv32bf16(<vscale x 32 x bfloat> %a, <vscale x 32 x bfloat> %b)
301  ret <vscale x 32 x bfloat> %v
302}
303
304declare <vscale x 1 x half> @llvm.minimum.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>)
305
306define <vscale x 1 x half> @vfmin_nxv1f16_vv(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
307; ZVFH-LABEL: vfmin_nxv1f16_vv:
308; ZVFH:       # %bb.0:
309; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
310; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
311; ZVFH-NEXT:    vmerge.vvm v10, v8, v9, v0
312; ZVFH-NEXT:    vmfeq.vv v0, v9, v9
313; ZVFH-NEXT:    vmerge.vvm v8, v9, v8, v0
314; ZVFH-NEXT:    vfmin.vv v8, v8, v10
315; ZVFH-NEXT:    ret
316;
317; ZVFHMIN-LABEL: vfmin_nxv1f16_vv:
318; ZVFHMIN:       # %bb.0:
319; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
320; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
321; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
322; ZVFHMIN-NEXT:    vmfeq.vv v0, v10, v10
323; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
324; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
325; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
326; ZVFHMIN-NEXT:    vmerge.vvm v9, v10, v8, v0
327; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
328; ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v10, v0
329; ZVFHMIN-NEXT:    vfmin.vv v9, v8, v9
330; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
331; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
332; ZVFHMIN-NEXT:    ret
333  %v = call <vscale x 1 x half> @llvm.minimum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b)
334  ret <vscale x 1 x half> %v
335}
336
337declare <vscale x 2 x half> @llvm.minimum.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>)
338
339define <vscale x 2 x half> @vfmin_nxv2f16_vv(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
340; ZVFH-LABEL: vfmin_nxv2f16_vv:
341; ZVFH:       # %bb.0:
342; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
343; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
344; ZVFH-NEXT:    vmerge.vvm v10, v8, v9, v0
345; ZVFH-NEXT:    vmfeq.vv v0, v9, v9
346; ZVFH-NEXT:    vmerge.vvm v8, v9, v8, v0
347; ZVFH-NEXT:    vfmin.vv v8, v8, v10
348; ZVFH-NEXT:    ret
349;
350; ZVFHMIN-LABEL: vfmin_nxv2f16_vv:
351; ZVFHMIN:       # %bb.0:
352; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
353; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
354; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
355; ZVFHMIN-NEXT:    vmfeq.vv v0, v10, v10
356; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
357; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
358; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
359; ZVFHMIN-NEXT:    vmerge.vvm v9, v10, v8, v0
360; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
361; ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v10, v0
362; ZVFHMIN-NEXT:    vfmin.vv v9, v8, v9
363; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
364; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
365; ZVFHMIN-NEXT:    ret
366  %v = call <vscale x 2 x half> @llvm.minimum.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b)
367  ret <vscale x 2 x half> %v
368}
369
370declare <vscale x 4 x half> @llvm.minimum.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>)
371
372define <vscale x 4 x half> @vfmin_nxv4f16_vv(<vscale x 4 x half> %a, <vscale x 4 x half> %b) {
373; ZVFH-LABEL: vfmin_nxv4f16_vv:
374; ZVFH:       # %bb.0:
375; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
376; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
377; ZVFH-NEXT:    vmerge.vvm v10, v8, v9, v0
378; ZVFH-NEXT:    vmfeq.vv v0, v9, v9
379; ZVFH-NEXT:    vmerge.vvm v8, v9, v8, v0
380; ZVFH-NEXT:    vfmin.vv v8, v8, v10
381; ZVFH-NEXT:    ret
382;
383; ZVFHMIN-LABEL: vfmin_nxv4f16_vv:
384; ZVFHMIN:       # %bb.0:
385; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
386; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
387; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
388; ZVFHMIN-NEXT:    vmfeq.vv v0, v10, v10
389; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
390; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v9
391; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
392; ZVFHMIN-NEXT:    vmerge.vvm v8, v10, v12, v0
393; ZVFHMIN-NEXT:    vmfeq.vv v0, v12, v12
394; ZVFHMIN-NEXT:    vmerge.vvm v10, v12, v10, v0
395; ZVFHMIN-NEXT:    vfmin.vv v10, v10, v8
396; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
397; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
398; ZVFHMIN-NEXT:    ret
399  %v = call <vscale x 4 x half> @llvm.minimum.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b)
400  ret <vscale x 4 x half> %v
401}
402
403declare <vscale x 8 x half> @llvm.minimum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>)
404
405define <vscale x 8 x half> @vfmin_nxv8f16_vv(<vscale x 8 x half> %a, <vscale x 8 x half> %b) {
406; ZVFH-LABEL: vfmin_nxv8f16_vv:
407; ZVFH:       # %bb.0:
408; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
409; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
410; ZVFH-NEXT:    vmerge.vvm v12, v8, v10, v0
411; ZVFH-NEXT:    vmfeq.vv v0, v10, v10
412; ZVFH-NEXT:    vmerge.vvm v8, v10, v8, v0
413; ZVFH-NEXT:    vfmin.vv v8, v8, v12
414; ZVFH-NEXT:    ret
415;
416; ZVFHMIN-LABEL: vfmin_nxv8f16_vv:
417; ZVFHMIN:       # %bb.0:
418; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
419; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8
420; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
421; ZVFHMIN-NEXT:    vmfeq.vv v0, v12, v12
422; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
423; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v10
424; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
425; ZVFHMIN-NEXT:    vmerge.vvm v8, v12, v16, v0
426; ZVFHMIN-NEXT:    vmfeq.vv v0, v16, v16
427; ZVFHMIN-NEXT:    vmerge.vvm v12, v16, v12, v0
428; ZVFHMIN-NEXT:    vfmin.vv v12, v12, v8
429; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
430; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12
431; ZVFHMIN-NEXT:    ret
432  %v = call <vscale x 8 x half> @llvm.minimum.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b)
433  ret <vscale x 8 x half> %v
434}
435
436declare <vscale x 16 x half> @llvm.minimum.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>)
437
438define <vscale x 16 x half> @vfmin_nxv16f16_vv(<vscale x 16 x half> %a, <vscale x 16 x half> %b) {
439; ZVFH-LABEL: vfmin_nxv16f16_vv:
440; ZVFH:       # %bb.0:
441; ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
442; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
443; ZVFH-NEXT:    vmerge.vvm v16, v8, v12, v0
444; ZVFH-NEXT:    vmfeq.vv v0, v12, v12
445; ZVFH-NEXT:    vmerge.vvm v8, v12, v8, v0
446; ZVFH-NEXT:    vfmin.vv v8, v8, v16
447; ZVFH-NEXT:    ret
448;
449; ZVFHMIN-LABEL: vfmin_nxv16f16_vv:
450; ZVFHMIN:       # %bb.0:
451; ZVFHMIN-NEXT:    addi sp, sp, -16
452; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
453; ZVFHMIN-NEXT:    csrr a0, vlenb
454; ZVFHMIN-NEXT:    slli a0, a0, 3
455; ZVFHMIN-NEXT:    sub sp, sp, a0
456; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
457; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
458; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12
459; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
460; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
461; ZVFHMIN-NEXT:    vmfeq.vv v0, v24, v24
462; ZVFHMIN-NEXT:    vmfeq.vv v7, v16, v16
463; ZVFHMIN-NEXT:    vmerge.vvm v8, v24, v16, v0
464; ZVFHMIN-NEXT:    addi a0, sp, 16
465; ZVFHMIN-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
466; ZVFHMIN-NEXT:    vmv1r.v v0, v7
467; ZVFHMIN-NEXT:    vmerge.vvm v8, v16, v24, v0
468; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
469; ZVFHMIN-NEXT:    vfmin.vv v16, v8, v16
470; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
471; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
472; ZVFHMIN-NEXT:    csrr a0, vlenb
473; ZVFHMIN-NEXT:    slli a0, a0, 3
474; ZVFHMIN-NEXT:    add sp, sp, a0
475; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
476; ZVFHMIN-NEXT:    addi sp, sp, 16
477; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
478; ZVFHMIN-NEXT:    ret
479  %v = call <vscale x 16 x half> @llvm.minimum.nxv16f16(<vscale x 16 x half> %a, <vscale x 16 x half> %b)
480  ret <vscale x 16 x half> %v
481}
482
483declare <vscale x 32 x half> @llvm.minimum.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>)
484
485define <vscale x 32 x half> @vfmin_nxv32f16_vv(<vscale x 32 x half> %a, <vscale x 32 x half> %b) nounwind {
486; ZVFH-LABEL: vfmin_nxv32f16_vv:
487; ZVFH:       # %bb.0:
488; ZVFH-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
489; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
490; ZVFH-NEXT:    vmfeq.vv v7, v16, v16
491; ZVFH-NEXT:    vmerge.vvm v24, v8, v16, v0
492; ZVFH-NEXT:    vmv1r.v v0, v7
493; ZVFH-NEXT:    vmerge.vvm v8, v16, v8, v0
494; ZVFH-NEXT:    vfmin.vv v8, v8, v24
495; ZVFH-NEXT:    ret
496;
497; ZVFHMIN-LABEL: vfmin_nxv32f16_vv:
498; ZVFHMIN:       # %bb.0:
499; ZVFHMIN-NEXT:    addi sp, sp, -16
500; ZVFHMIN-NEXT:    csrr a0, vlenb
501; ZVFHMIN-NEXT:    li a1, 24
502; ZVFHMIN-NEXT:    mul a0, a0, a1
503; ZVFHMIN-NEXT:    sub sp, sp, a0
504; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
505; ZVFHMIN-NEXT:    vmv8r.v v24, v16
506; ZVFHMIN-NEXT:    csrr a0, vlenb
507; ZVFHMIN-NEXT:    slli a0, a0, 3
508; ZVFHMIN-NEXT:    add a0, sp, a0
509; ZVFHMIN-NEXT:    addi a0, a0, 16
510; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
511; ZVFHMIN-NEXT:    vmv8r.v v0, v8
512; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
513; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v0
514; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
515; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
516; ZVFHMIN-NEXT:    vmfeq.vv v3, v16, v16
517; ZVFHMIN-NEXT:    vmerge.vvm v24, v8, v16, v0
518; ZVFHMIN-NEXT:    csrr a0, vlenb
519; ZVFHMIN-NEXT:    slli a0, a0, 4
520; ZVFHMIN-NEXT:    add a0, sp, a0
521; ZVFHMIN-NEXT:    addi a0, a0, 16
522; ZVFHMIN-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
523; ZVFHMIN-NEXT:    vmv1r.v v0, v3
524; ZVFHMIN-NEXT:    vmerge.vvm v8, v16, v8, v0
525; ZVFHMIN-NEXT:    addi a0, sp, 16
526; ZVFHMIN-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
527; ZVFHMIN-NEXT:    csrr a0, vlenb
528; ZVFHMIN-NEXT:    slli a0, a0, 3
529; ZVFHMIN-NEXT:    add a0, sp, a0
530; ZVFHMIN-NEXT:    addi a0, a0, 16
531; ZVFHMIN-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
532; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
533; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v12
534; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v4
535; ZVFHMIN-NEXT:    csrr a0, vlenb
536; ZVFHMIN-NEXT:    slli a0, a0, 4
537; ZVFHMIN-NEXT:    add a0, sp, a0
538; ZVFHMIN-NEXT:    addi a0, a0, 16
539; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
540; ZVFHMIN-NEXT:    addi a0, sp, 16
541; ZVFHMIN-NEXT:    vl8r.v v0, (a0) # Unknown-size Folded Reload
542; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
543; ZVFHMIN-NEXT:    vfmin.vv v16, v0, v16
544; ZVFHMIN-NEXT:    csrr a0, vlenb
545; ZVFHMIN-NEXT:    slli a0, a0, 4
546; ZVFHMIN-NEXT:    add a0, sp, a0
547; ZVFHMIN-NEXT:    addi a0, a0, 16
548; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
549; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
550; ZVFHMIN-NEXT:    vmfeq.vv v7, v24, v24
551; ZVFHMIN-NEXT:    vmerge.vvm v16, v8, v24, v0
552; ZVFHMIN-NEXT:    vmv1r.v v0, v7
553; ZVFHMIN-NEXT:    vmerge.vvm v8, v24, v8, v0
554; ZVFHMIN-NEXT:    vfmin.vv v16, v8, v16
555; ZVFHMIN-NEXT:    csrr a0, vlenb
556; ZVFHMIN-NEXT:    slli a0, a0, 4
557; ZVFHMIN-NEXT:    add a0, sp, a0
558; ZVFHMIN-NEXT:    addi a0, a0, 16
559; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
560; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
561; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v24
562; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v16
563; ZVFHMIN-NEXT:    csrr a0, vlenb
564; ZVFHMIN-NEXT:    li a1, 24
565; ZVFHMIN-NEXT:    mul a0, a0, a1
566; ZVFHMIN-NEXT:    add sp, sp, a0
567; ZVFHMIN-NEXT:    addi sp, sp, 16
568; ZVFHMIN-NEXT:    ret
569  %v = call <vscale x 32 x half> @llvm.minimum.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)
570  ret <vscale x 32 x half> %v
571}
572
573declare <vscale x 1 x float> @llvm.minimum.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>)
574
575define <vscale x 1 x float> @vfmin_nxv1f32_vv(<vscale x 1 x float> %a, <vscale x 1 x float> %b) {
576; CHECK-LABEL: vfmin_nxv1f32_vv:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
579; CHECK-NEXT:    vmfeq.vv v0, v8, v8
580; CHECK-NEXT:    vmerge.vvm v10, v8, v9, v0
581; CHECK-NEXT:    vmfeq.vv v0, v9, v9
582; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
583; CHECK-NEXT:    vfmin.vv v8, v8, v10
584; CHECK-NEXT:    ret
585  %v = call <vscale x 1 x float> @llvm.minimum.nxv1f32(<vscale x 1 x float> %a, <vscale x 1 x float> %b)
586  ret <vscale x 1 x float> %v
587}
588
589declare <vscale x 2 x float> @llvm.minimum.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>)
590
591define <vscale x 2 x float> @vfmin_nxv2f32_vv(<vscale x 2 x float> %a, <vscale x 2 x float> %b) {
592; CHECK-LABEL: vfmin_nxv2f32_vv:
593; CHECK:       # %bb.0:
594; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
595; CHECK-NEXT:    vmfeq.vv v0, v8, v8
596; CHECK-NEXT:    vmerge.vvm v10, v8, v9, v0
597; CHECK-NEXT:    vmfeq.vv v0, v9, v9
598; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
599; CHECK-NEXT:    vfmin.vv v8, v8, v10
600; CHECK-NEXT:    ret
601  %v = call <vscale x 2 x float> @llvm.minimum.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b)
602  ret <vscale x 2 x float> %v
603}
604
605declare <vscale x 4 x float> @llvm.minimum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
606
607define <vscale x 4 x float> @vfmin_nxv4f32_vv(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
608; CHECK-LABEL: vfmin_nxv4f32_vv:
609; CHECK:       # %bb.0:
610; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
611; CHECK-NEXT:    vmfeq.vv v0, v8, v8
612; CHECK-NEXT:    vmerge.vvm v12, v8, v10, v0
613; CHECK-NEXT:    vmfeq.vv v0, v10, v10
614; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
615; CHECK-NEXT:    vfmin.vv v8, v8, v12
616; CHECK-NEXT:    ret
617  %v = call <vscale x 4 x float> @llvm.minimum.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
618  ret <vscale x 4 x float> %v
619}
620
621declare <vscale x 8 x float> @llvm.minimum.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>)
622
623define <vscale x 8 x float> @vfmin_nxv8f32_vv(<vscale x 8 x float> %a, <vscale x 8 x float> %b) {
624; CHECK-LABEL: vfmin_nxv8f32_vv:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
627; CHECK-NEXT:    vmfeq.vv v0, v8, v8
628; CHECK-NEXT:    vmerge.vvm v16, v8, v12, v0
629; CHECK-NEXT:    vmfeq.vv v0, v12, v12
630; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
631; CHECK-NEXT:    vfmin.vv v8, v8, v16
632; CHECK-NEXT:    ret
633  %v = call <vscale x 8 x float> @llvm.minimum.nxv8f32(<vscale x 8 x float> %a, <vscale x 8 x float> %b)
634  ret <vscale x 8 x float> %v
635}
636
637declare <vscale x 16 x float> @llvm.minimum.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>)
638
639define <vscale x 16 x float> @vfmin_nxv16f32_vv(<vscale x 16 x float> %a, <vscale x 16 x float> %b) nounwind {
640; CHECK-LABEL: vfmin_nxv16f32_vv:
641; CHECK:       # %bb.0:
642; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
643; CHECK-NEXT:    vmfeq.vv v0, v8, v8
644; CHECK-NEXT:    vmfeq.vv v7, v16, v16
645; CHECK-NEXT:    vmerge.vvm v24, v8, v16, v0
646; CHECK-NEXT:    vmv1r.v v0, v7
647; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
648; CHECK-NEXT:    vfmin.vv v8, v8, v24
649; CHECK-NEXT:    ret
650  %v = call <vscale x 16 x float> @llvm.minimum.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)
651  ret <vscale x 16 x float> %v
652}
653
654declare <vscale x 1 x double> @llvm.minimum.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>)
655
656define <vscale x 1 x double> @vfmin_nxv1f64_vv(<vscale x 1 x double> %a, <vscale x 1 x double> %b) {
657; CHECK-LABEL: vfmin_nxv1f64_vv:
658; CHECK:       # %bb.0:
659; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
660; CHECK-NEXT:    vmfeq.vv v0, v8, v8
661; CHECK-NEXT:    vmerge.vvm v10, v8, v9, v0
662; CHECK-NEXT:    vmfeq.vv v0, v9, v9
663; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
664; CHECK-NEXT:    vfmin.vv v8, v8, v10
665; CHECK-NEXT:    ret
666  %v = call <vscale x 1 x double> @llvm.minimum.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b)
667  ret <vscale x 1 x double> %v
668}
669
670declare <vscale x 2 x double> @llvm.minimum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>)
671
672define <vscale x 2 x double> @vfmin_nxv2f64_vv(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
673; CHECK-LABEL: vfmin_nxv2f64_vv:
674; CHECK:       # %bb.0:
675; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
676; CHECK-NEXT:    vmfeq.vv v0, v8, v8
677; CHECK-NEXT:    vmerge.vvm v12, v8, v10, v0
678; CHECK-NEXT:    vmfeq.vv v0, v10, v10
679; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
680; CHECK-NEXT:    vfmin.vv v8, v8, v12
681; CHECK-NEXT:    ret
682  %v = call <vscale x 2 x double> @llvm.minimum.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
683  ret <vscale x 2 x double> %v
684}
685
686declare <vscale x 4 x double> @llvm.minimum.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>)
687
688define <vscale x 4 x double> @vfmin_nxv4f64_vv(<vscale x 4 x double> %a, <vscale x 4 x double> %b) {
689; CHECK-LABEL: vfmin_nxv4f64_vv:
690; CHECK:       # %bb.0:
691; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
692; CHECK-NEXT:    vmfeq.vv v0, v8, v8
693; CHECK-NEXT:    vmerge.vvm v16, v8, v12, v0
694; CHECK-NEXT:    vmfeq.vv v0, v12, v12
695; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
696; CHECK-NEXT:    vfmin.vv v8, v8, v16
697; CHECK-NEXT:    ret
698  %v = call <vscale x 4 x double> @llvm.minimum.nxv4f64(<vscale x 4 x double> %a, <vscale x 4 x double> %b)
699  ret <vscale x 4 x double> %v
700}
701
702declare <vscale x 8 x double> @llvm.minimum.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>)
703
704define <vscale x 8 x double> @vfmin_nxv8f64_vv(<vscale x 8 x double> %a, <vscale x 8 x double> %b) nounwind {
705; CHECK-LABEL: vfmin_nxv8f64_vv:
706; CHECK:       # %bb.0:
707; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
708; CHECK-NEXT:    vmfeq.vv v0, v8, v8
709; CHECK-NEXT:    vmfeq.vv v7, v16, v16
710; CHECK-NEXT:    vmerge.vvm v24, v8, v16, v0
711; CHECK-NEXT:    vmv1r.v v0, v7
712; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
713; CHECK-NEXT:    vfmin.vv v8, v8, v24
714; CHECK-NEXT:    ret
715  %v = call <vscale x 8 x double> @llvm.minimum.nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)
716  ret <vscale x 8 x double> %v
717}
718
719define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnan(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
720; ZVFH-LABEL: vfmin_nxv1f16_vv_nnan:
721; ZVFH:       # %bb.0:
722; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
723; ZVFH-NEXT:    vfmin.vv v8, v8, v9
724; ZVFH-NEXT:    ret
725;
726; ZVFHMIN-LABEL: vfmin_nxv1f16_vv_nnan:
727; ZVFHMIN:       # %bb.0:
728; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
729; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
730; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
731; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
732; ZVFHMIN-NEXT:    vfmin.vv v9, v9, v10
733; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
734; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
735; ZVFHMIN-NEXT:    ret
736  %v = call nnan <vscale x 1 x half> @llvm.minimum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %b)
737  ret <vscale x 1 x half> %v
738}
739
740define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
741; ZVFH-LABEL: vfmin_nxv1f16_vv_nnana:
742; ZVFH:       # %bb.0:
743; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
744; ZVFH-NEXT:    vmfeq.vv v0, v9, v9
745; ZVFH-NEXT:    vmv1r.v v10, v9
746; ZVFH-NEXT:    vfadd.vv v10, v8, v8, v0.t
747; ZVFH-NEXT:    vfmin.vv v8, v10, v9
748; ZVFH-NEXT:    ret
749;
750; ZVFHMIN-LABEL: vfmin_nxv1f16_vv_nnana:
751; ZVFHMIN:       # %bb.0:
752; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
753; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
754; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
755; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
756; ZVFHMIN-NEXT:    vfadd.vv v9, v10, v10
757; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
758; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
759; ZVFHMIN-NEXT:    vfncvt.f.f.w v10, v9
760; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v10
761; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
762; ZVFHMIN-NEXT:    vmerge.vvm v10, v8, v9, v0
763; ZVFHMIN-NEXT:    vmfeq.vv v0, v9, v9
764; ZVFHMIN-NEXT:    vmerge.vvm v8, v9, v8, v0
765; ZVFHMIN-NEXT:    vfmin.vv v9, v10, v8
766; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
767; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
768; ZVFHMIN-NEXT:    ret
769  %c = fadd nnan <vscale x 1 x half> %a, %a
770  %v = call <vscale x 1 x half> @llvm.minimum.nxv1f16(<vscale x 1 x half> %c, <vscale x 1 x half> %b)
771  ret <vscale x 1 x half> %v
772}
773
774define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vscale x 1 x half> %b) {
775; ZVFH-LABEL: vfmin_nxv1f16_vv_nnanb:
776; ZVFH:       # %bb.0:
777; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, mu
778; ZVFH-NEXT:    vmfeq.vv v0, v8, v8
779; ZVFH-NEXT:    vmv1r.v v10, v8
780; ZVFH-NEXT:    vfadd.vv v10, v9, v9, v0.t
781; ZVFH-NEXT:    vfmin.vv v8, v8, v10
782; ZVFH-NEXT:    ret
783;
784; ZVFHMIN-LABEL: vfmin_nxv1f16_vv_nnanb:
785; ZVFHMIN:       # %bb.0:
786; ZVFHMIN-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
787; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
788; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
789; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
790; ZVFHMIN-NEXT:    vfadd.vv v8, v10, v10
791; ZVFHMIN-NEXT:    vmfeq.vv v0, v9, v9
792; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
793; ZVFHMIN-NEXT:    vfncvt.f.f.w v10, v8
794; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v10
795; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
796; ZVFHMIN-NEXT:    vmerge.vvm v10, v9, v8, v0
797; ZVFHMIN-NEXT:    vmfeq.vv v0, v8, v8
798; ZVFHMIN-NEXT:    vmerge.vvm v8, v8, v9, v0
799; ZVFHMIN-NEXT:    vfmin.vv v9, v8, v10
800; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
801; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
802; ZVFHMIN-NEXT:    ret
803  %c = fadd nnan <vscale x 1 x half> %b, %b
804  %v = call <vscale x 1 x half> @llvm.minimum.nxv1f16(<vscale x 1 x half> %a, <vscale x 1 x half> %c)
805  ret <vscale x 1 x half> %v
806}
807