xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
8
9define <2 x i8> @ssub_v2i8_vv(<2 x i8> %va, <2 x i8> %b) {
10; CHECK-LABEL: ssub_v2i8_vv:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
13; CHECK-NEXT:    vssub.vv v8, v8, v9
14; CHECK-NEXT:    ret
15  %v = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b)
16  ret <2 x i8> %v
17}
18
19define <2 x i8> @ssub_v2i8_vx(<2 x i8> %va, i8 %b) {
20; CHECK-LABEL: ssub_v2i8_vx:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
23; CHECK-NEXT:    vssub.vx v8, v8, a0
24; CHECK-NEXT:    ret
25  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
26  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
27  %v = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb)
28  ret <2 x i8> %v
29}
30
31define <2 x i8> @ssub_v2i8_vi(<2 x i8> %va) {
32; CHECK-LABEL: ssub_v2i8_vi:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    li a0, 1
35; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
36; CHECK-NEXT:    vssub.vx v8, v8, a0
37; CHECK-NEXT:    ret
38  %v = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 1))
39  ret <2 x i8> %v
40}
41
42declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
43
44define <4 x i8> @ssub_v4i8_vv(<4 x i8> %va, <4 x i8> %b) {
45; CHECK-LABEL: ssub_v4i8_vv:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
48; CHECK-NEXT:    vssub.vv v8, v8, v9
49; CHECK-NEXT:    ret
50  %v = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b)
51  ret <4 x i8> %v
52}
53
54define <4 x i8> @ssub_v4i8_vx(<4 x i8> %va, i8 %b) {
55; CHECK-LABEL: ssub_v4i8_vx:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
58; CHECK-NEXT:    vssub.vx v8, v8, a0
59; CHECK-NEXT:    ret
60  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
61  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
62  %v = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb)
63  ret <4 x i8> %v
64}
65
66define <4 x i8> @ssub_v4i8_vi(<4 x i8> %va) {
67; CHECK-LABEL: ssub_v4i8_vi:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    li a0, 1
70; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
71; CHECK-NEXT:    vssub.vx v8, v8, a0
72; CHECK-NEXT:    ret
73  %v = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 1))
74  ret <4 x i8> %v
75}
76
77declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
78
79define <8 x i8> @ssub_v8i8_vv(<8 x i8> %va, <8 x i8> %b) {
80; CHECK-LABEL: ssub_v8i8_vv:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
83; CHECK-NEXT:    vssub.vv v8, v8, v9
84; CHECK-NEXT:    ret
85  %v = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b)
86  ret <8 x i8> %v
87}
88
89define <8 x i8> @ssub_v8i8_vx(<8 x i8> %va, i8 %b) {
90; CHECK-LABEL: ssub_v8i8_vx:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
93; CHECK-NEXT:    vssub.vx v8, v8, a0
94; CHECK-NEXT:    ret
95  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
96  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
97  %v = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb)
98  ret <8 x i8> %v
99}
100
101define <8 x i8> @ssub_v8i8_vi(<8 x i8> %va) {
102; CHECK-LABEL: ssub_v8i8_vi:
103; CHECK:       # %bb.0:
104; CHECK-NEXT:    li a0, 1
105; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
106; CHECK-NEXT:    vssub.vx v8, v8, a0
107; CHECK-NEXT:    ret
108  %v = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 1))
109  ret <8 x i8> %v
110}
111
112declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
113
114define <16 x i8> @ssub_v16i8_vv(<16 x i8> %va, <16 x i8> %b) {
115; CHECK-LABEL: ssub_v16i8_vv:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
118; CHECK-NEXT:    vssub.vv v8, v8, v9
119; CHECK-NEXT:    ret
120  %v = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b)
121  ret <16 x i8> %v
122}
123
124define <16 x i8> @ssub_v16i8_vx(<16 x i8> %va, i8 %b) {
125; CHECK-LABEL: ssub_v16i8_vx:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
128; CHECK-NEXT:    vssub.vx v8, v8, a0
129; CHECK-NEXT:    ret
130  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
131  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
132  %v = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb)
133  ret <16 x i8> %v
134}
135
136define <16 x i8> @ssub_v16i8_vi(<16 x i8> %va) {
137; CHECK-LABEL: ssub_v16i8_vi:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    li a0, 1
140; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
141; CHECK-NEXT:    vssub.vx v8, v8, a0
142; CHECK-NEXT:    ret
143  %v = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 1))
144  ret <16 x i8> %v
145}
146
147declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
148
149define <2 x i16> @ssub_v2i16_vv(<2 x i16> %va, <2 x i16> %b) {
150; CHECK-LABEL: ssub_v2i16_vv:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
153; CHECK-NEXT:    vssub.vv v8, v8, v9
154; CHECK-NEXT:    ret
155  %v = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b)
156  ret <2 x i16> %v
157}
158
159define <2 x i16> @ssub_v2i16_vx(<2 x i16> %va, i16 %b) {
160; CHECK-LABEL: ssub_v2i16_vx:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
163; CHECK-NEXT:    vssub.vx v8, v8, a0
164; CHECK-NEXT:    ret
165  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
166  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
167  %v = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb)
168  ret <2 x i16> %v
169}
170
171define <2 x i16> @ssub_v2i16_vi(<2 x i16> %va) {
172; CHECK-LABEL: ssub_v2i16_vi:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    li a0, 1
175; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
176; CHECK-NEXT:    vssub.vx v8, v8, a0
177; CHECK-NEXT:    ret
178  %v = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 1))
179  ret <2 x i16> %v
180}
181
182declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
183
184define <4 x i16> @ssub_v4i16_vv(<4 x i16> %va, <4 x i16> %b) {
185; CHECK-LABEL: ssub_v4i16_vv:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
188; CHECK-NEXT:    vssub.vv v8, v8, v9
189; CHECK-NEXT:    ret
190  %v = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b)
191  ret <4 x i16> %v
192}
193
194define <4 x i16> @ssub_v4i16_vx(<4 x i16> %va, i16 %b) {
195; CHECK-LABEL: ssub_v4i16_vx:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
198; CHECK-NEXT:    vssub.vx v8, v8, a0
199; CHECK-NEXT:    ret
200  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
201  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
202  %v = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb)
203  ret <4 x i16> %v
204}
205
206define <4 x i16> @ssub_v4i16_vi(<4 x i16> %va) {
207; CHECK-LABEL: ssub_v4i16_vi:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    li a0, 1
210; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
211; CHECK-NEXT:    vssub.vx v8, v8, a0
212; CHECK-NEXT:    ret
213  %v = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 1))
214  ret <4 x i16> %v
215}
216
217declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
218
219define <8 x i16> @ssub_v8i16_vv(<8 x i16> %va, <8 x i16> %b) {
220; CHECK-LABEL: ssub_v8i16_vv:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
223; CHECK-NEXT:    vssub.vv v8, v8, v9
224; CHECK-NEXT:    ret
225  %v = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b)
226  ret <8 x i16> %v
227}
228
229define <8 x i16> @ssub_v8i16_vx(<8 x i16> %va, i16 %b) {
230; CHECK-LABEL: ssub_v8i16_vx:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
233; CHECK-NEXT:    vssub.vx v8, v8, a0
234; CHECK-NEXT:    ret
235  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
236  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
237  %v = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb)
238  ret <8 x i16> %v
239}
240
241define <8 x i16> @ssub_v8i16_vi(<8 x i16> %va) {
242; CHECK-LABEL: ssub_v8i16_vi:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    li a0, 1
245; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
246; CHECK-NEXT:    vssub.vx v8, v8, a0
247; CHECK-NEXT:    ret
248  %v = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 1))
249  ret <8 x i16> %v
250}
251
252declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
253
254define <16 x i16> @ssub_v16i16_vv(<16 x i16> %va, <16 x i16> %b) {
255; CHECK-LABEL: ssub_v16i16_vv:
256; CHECK:       # %bb.0:
257; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
258; CHECK-NEXT:    vssub.vv v8, v8, v10
259; CHECK-NEXT:    ret
260  %v = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b)
261  ret <16 x i16> %v
262}
263
264define <16 x i16> @ssub_v16i16_vx(<16 x i16> %va, i16 %b) {
265; CHECK-LABEL: ssub_v16i16_vx:
266; CHECK:       # %bb.0:
267; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
268; CHECK-NEXT:    vssub.vx v8, v8, a0
269; CHECK-NEXT:    ret
270  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
271  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
272  %v = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb)
273  ret <16 x i16> %v
274}
275
276define <16 x i16> @ssub_v16i16_vi(<16 x i16> %va) {
277; CHECK-LABEL: ssub_v16i16_vi:
278; CHECK:       # %bb.0:
279; CHECK-NEXT:    li a0, 1
280; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
281; CHECK-NEXT:    vssub.vx v8, v8, a0
282; CHECK-NEXT:    ret
283  %v = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 1))
284  ret <16 x i16> %v
285}
286
287declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
288
289define <2 x i32> @ssub_v2i32_vv(<2 x i32> %va, <2 x i32> %b) {
290; CHECK-LABEL: ssub_v2i32_vv:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
293; CHECK-NEXT:    vssub.vv v8, v8, v9
294; CHECK-NEXT:    ret
295  %v = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b)
296  ret <2 x i32> %v
297}
298
299define <2 x i32> @ssub_v2i32_vx(<2 x i32> %va, i32 %b) {
300; CHECK-LABEL: ssub_v2i32_vx:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
303; CHECK-NEXT:    vssub.vx v8, v8, a0
304; CHECK-NEXT:    ret
305  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
306  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
307  %v = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb)
308  ret <2 x i32> %v
309}
310
311define <2 x i32> @ssub_v2i32_vi(<2 x i32> %va) {
312; CHECK-LABEL: ssub_v2i32_vi:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    li a0, 1
315; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
316; CHECK-NEXT:    vssub.vx v8, v8, a0
317; CHECK-NEXT:    ret
318  %v = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 1))
319  ret <2 x i32> %v
320}
321
322declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
323
324define <4 x i32> @ssub_v4i32_vv(<4 x i32> %va, <4 x i32> %b) {
325; CHECK-LABEL: ssub_v4i32_vv:
326; CHECK:       # %bb.0:
327; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
328; CHECK-NEXT:    vssub.vv v8, v8, v9
329; CHECK-NEXT:    ret
330  %v = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b)
331  ret <4 x i32> %v
332}
333
334define <4 x i32> @ssub_v4i32_vx(<4 x i32> %va, i32 %b) {
335; CHECK-LABEL: ssub_v4i32_vx:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
338; CHECK-NEXT:    vssub.vx v8, v8, a0
339; CHECK-NEXT:    ret
340  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
341  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
342  %v = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb)
343  ret <4 x i32> %v
344}
345
346define <4 x i32> @ssub_v4i32_vi(<4 x i32> %va) {
347; CHECK-LABEL: ssub_v4i32_vi:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    li a0, 1
350; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
351; CHECK-NEXT:    vssub.vx v8, v8, a0
352; CHECK-NEXT:    ret
353  %v = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 1))
354  ret <4 x i32> %v
355}
356
357declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
358
359define <8 x i32> @ssub_v8i32_vv(<8 x i32> %va, <8 x i32> %b) {
360; CHECK-LABEL: ssub_v8i32_vv:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
363; CHECK-NEXT:    vssub.vv v8, v8, v10
364; CHECK-NEXT:    ret
365  %v = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b)
366  ret <8 x i32> %v
367}
368
369define <8 x i32> @ssub_v8i32_vx(<8 x i32> %va, i32 %b) {
370; CHECK-LABEL: ssub_v8i32_vx:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
373; CHECK-NEXT:    vssub.vx v8, v8, a0
374; CHECK-NEXT:    ret
375  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
376  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
377  %v = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb)
378  ret <8 x i32> %v
379}
380
381define <8 x i32> @ssub_v8i32_vi(<8 x i32> %va) {
382; CHECK-LABEL: ssub_v8i32_vi:
383; CHECK:       # %bb.0:
384; CHECK-NEXT:    li a0, 1
385; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
386; CHECK-NEXT:    vssub.vx v8, v8, a0
387; CHECK-NEXT:    ret
388  %v = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 1))
389  ret <8 x i32> %v
390}
391
392declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
393
394define <16 x i32> @ssub_v16i32_vv(<16 x i32> %va, <16 x i32> %b) {
395; CHECK-LABEL: ssub_v16i32_vv:
396; CHECK:       # %bb.0:
397; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
398; CHECK-NEXT:    vssub.vv v8, v8, v12
399; CHECK-NEXT:    ret
400  %v = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b)
401  ret <16 x i32> %v
402}
403
404define <16 x i32> @ssub_v16i32_vx(<16 x i32> %va, i32 %b) {
405; CHECK-LABEL: ssub_v16i32_vx:
406; CHECK:       # %bb.0:
407; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
408; CHECK-NEXT:    vssub.vx v8, v8, a0
409; CHECK-NEXT:    ret
410  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
411  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
412  %v = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb)
413  ret <16 x i32> %v
414}
415
416define <16 x i32> @ssub_v16i32_vi(<16 x i32> %va) {
417; CHECK-LABEL: ssub_v16i32_vi:
418; CHECK:       # %bb.0:
419; CHECK-NEXT:    li a0, 1
420; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
421; CHECK-NEXT:    vssub.vx v8, v8, a0
422; CHECK-NEXT:    ret
423  %v = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 1))
424  ret <16 x i32> %v
425}
426
427declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
428
429define <2 x i64> @ssub_v2i64_vv(<2 x i64> %va, <2 x i64> %b) {
430; CHECK-LABEL: ssub_v2i64_vv:
431; CHECK:       # %bb.0:
432; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
433; CHECK-NEXT:    vssub.vv v8, v8, v9
434; CHECK-NEXT:    ret
435  %v = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b)
436  ret <2 x i64> %v
437}
438
439define <2 x i64> @ssub_v2i64_vx(<2 x i64> %va, i64 %b) {
440; RV32-LABEL: ssub_v2i64_vx:
441; RV32:       # %bb.0:
442; RV32-NEXT:    addi sp, sp, -16
443; RV32-NEXT:    .cfi_def_cfa_offset 16
444; RV32-NEXT:    sw a0, 8(sp)
445; RV32-NEXT:    sw a1, 12(sp)
446; RV32-NEXT:    addi a0, sp, 8
447; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
448; RV32-NEXT:    vlse64.v v9, (a0), zero
449; RV32-NEXT:    vssub.vv v8, v8, v9
450; RV32-NEXT:    addi sp, sp, 16
451; RV32-NEXT:    .cfi_def_cfa_offset 0
452; RV32-NEXT:    ret
453;
454; RV64-LABEL: ssub_v2i64_vx:
455; RV64:       # %bb.0:
456; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
457; RV64-NEXT:    vssub.vx v8, v8, a0
458; RV64-NEXT:    ret
459  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
460  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
461  %v = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb)
462  ret <2 x i64> %v
463}
464
465define <2 x i64> @ssub_v2i64_vi(<2 x i64> %va) {
466; CHECK-LABEL: ssub_v2i64_vi:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    li a0, 1
469; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
470; CHECK-NEXT:    vssub.vx v8, v8, a0
471; CHECK-NEXT:    ret
472  %v = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 1))
473  ret <2 x i64> %v
474}
475
476declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
477
478define <4 x i64> @ssub_v4i64_vv(<4 x i64> %va, <4 x i64> %b) {
479; CHECK-LABEL: ssub_v4i64_vv:
480; CHECK:       # %bb.0:
481; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
482; CHECK-NEXT:    vssub.vv v8, v8, v10
483; CHECK-NEXT:    ret
484  %v = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b)
485  ret <4 x i64> %v
486}
487
488define <4 x i64> @ssub_v4i64_vx(<4 x i64> %va, i64 %b) {
489; RV32-LABEL: ssub_v4i64_vx:
490; RV32:       # %bb.0:
491; RV32-NEXT:    addi sp, sp, -16
492; RV32-NEXT:    .cfi_def_cfa_offset 16
493; RV32-NEXT:    sw a0, 8(sp)
494; RV32-NEXT:    sw a1, 12(sp)
495; RV32-NEXT:    addi a0, sp, 8
496; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
497; RV32-NEXT:    vlse64.v v10, (a0), zero
498; RV32-NEXT:    vssub.vv v8, v8, v10
499; RV32-NEXT:    addi sp, sp, 16
500; RV32-NEXT:    .cfi_def_cfa_offset 0
501; RV32-NEXT:    ret
502;
503; RV64-LABEL: ssub_v4i64_vx:
504; RV64:       # %bb.0:
505; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
506; RV64-NEXT:    vssub.vx v8, v8, a0
507; RV64-NEXT:    ret
508  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
509  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
510  %v = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb)
511  ret <4 x i64> %v
512}
513
514define <4 x i64> @ssub_v4i64_vi(<4 x i64> %va) {
515; CHECK-LABEL: ssub_v4i64_vi:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    li a0, 1
518; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
519; CHECK-NEXT:    vssub.vx v8, v8, a0
520; CHECK-NEXT:    ret
521  %v = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 1))
522  ret <4 x i64> %v
523}
524
525declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
526
527define <8 x i64> @ssub_v8i64_vv(<8 x i64> %va, <8 x i64> %b) {
528; CHECK-LABEL: ssub_v8i64_vv:
529; CHECK:       # %bb.0:
530; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
531; CHECK-NEXT:    vssub.vv v8, v8, v12
532; CHECK-NEXT:    ret
533  %v = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b)
534  ret <8 x i64> %v
535}
536
537define <8 x i64> @ssub_v8i64_vx(<8 x i64> %va, i64 %b) {
538; RV32-LABEL: ssub_v8i64_vx:
539; RV32:       # %bb.0:
540; RV32-NEXT:    addi sp, sp, -16
541; RV32-NEXT:    .cfi_def_cfa_offset 16
542; RV32-NEXT:    sw a0, 8(sp)
543; RV32-NEXT:    sw a1, 12(sp)
544; RV32-NEXT:    addi a0, sp, 8
545; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
546; RV32-NEXT:    vlse64.v v12, (a0), zero
547; RV32-NEXT:    vssub.vv v8, v8, v12
548; RV32-NEXT:    addi sp, sp, 16
549; RV32-NEXT:    .cfi_def_cfa_offset 0
550; RV32-NEXT:    ret
551;
552; RV64-LABEL: ssub_v8i64_vx:
553; RV64:       # %bb.0:
554; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
555; RV64-NEXT:    vssub.vx v8, v8, a0
556; RV64-NEXT:    ret
557  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
558  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
559  %v = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb)
560  ret <8 x i64> %v
561}
562
563define <8 x i64> @ssub_v8i64_vi(<8 x i64> %va) {
564; CHECK-LABEL: ssub_v8i64_vi:
565; CHECK:       # %bb.0:
566; CHECK-NEXT:    li a0, 1
567; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
568; CHECK-NEXT:    vssub.vx v8, v8, a0
569; CHECK-NEXT:    ret
570  %v = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 1))
571  ret <8 x i64> %v
572}
573
574declare <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64>, <16 x i64>)
575
576define <16 x i64> @ssub_v16i64_vv(<16 x i64> %va, <16 x i64> %b) {
577; CHECK-LABEL: ssub_v16i64_vv:
578; CHECK:       # %bb.0:
579; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
580; CHECK-NEXT:    vssub.vv v8, v8, v16
581; CHECK-NEXT:    ret
582  %v = call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b)
583  ret <16 x i64> %v
584}
585
586define <16 x i64> @ssub_v16i64_vx(<16 x i64> %va, i64 %b) {
587; RV32-LABEL: ssub_v16i64_vx:
588; RV32:       # %bb.0:
589; RV32-NEXT:    addi sp, sp, -16
590; RV32-NEXT:    .cfi_def_cfa_offset 16
591; RV32-NEXT:    sw a0, 8(sp)
592; RV32-NEXT:    sw a1, 12(sp)
593; RV32-NEXT:    addi a0, sp, 8
594; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
595; RV32-NEXT:    vlse64.v v16, (a0), zero
596; RV32-NEXT:    vssub.vv v8, v8, v16
597; RV32-NEXT:    addi sp, sp, 16
598; RV32-NEXT:    .cfi_def_cfa_offset 0
599; RV32-NEXT:    ret
600;
601; RV64-LABEL: ssub_v16i64_vx:
602; RV64:       # %bb.0:
603; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
604; RV64-NEXT:    vssub.vx v8, v8, a0
605; RV64-NEXT:    ret
606  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
607  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
608  %v = call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb)
609  ret <16 x i64> %v
610}
611
612define <16 x i64> @ssub_v16i64_vi(<16 x i64> %va) {
613; CHECK-LABEL: ssub_v16i64_vi:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    li a0, 1
616; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
617; CHECK-NEXT:    vssub.vx v8, v8, a0
618; CHECK-NEXT:    ret
619  %v = call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 1))
620  ret <16 x i64> %v
621}
622