xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
8
9define <2 x i8> @sadd_v2i8_vv(<2 x i8> %va, <2 x i8> %b) {
10; CHECK-LABEL: sadd_v2i8_vv:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
13; CHECK-NEXT:    vsadd.vv v8, v8, v9
14; CHECK-NEXT:    ret
15  %v = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b)
16  ret <2 x i8> %v
17}
18
19define <2 x i8> @sadd_v2i8_vx(<2 x i8> %va, i8 %b) {
20; CHECK-LABEL: sadd_v2i8_vx:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
23; CHECK-NEXT:    vsadd.vx v8, v8, a0
24; CHECK-NEXT:    ret
25  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
26  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
27  %v = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb)
28  ret <2 x i8> %v
29}
30
31define <2 x i8> @sadd_v2i8_vi(<2 x i8> %va) {
32; CHECK-LABEL: sadd_v2i8_vi:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
35; CHECK-NEXT:    vsadd.vi v8, v8, 5
36; CHECK-NEXT:    ret
37  %v = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5))
38  ret <2 x i8> %v
39}
40
41declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>)
42
43define <4 x i8> @sadd_v4i8_vv(<4 x i8> %va, <4 x i8> %b) {
44; CHECK-LABEL: sadd_v4i8_vv:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
47; CHECK-NEXT:    vsadd.vv v8, v8, v9
48; CHECK-NEXT:    ret
49  %v = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b)
50  ret <4 x i8> %v
51}
52
53define <4 x i8> @sadd_v4i8_vx(<4 x i8> %va, i8 %b) {
54; CHECK-LABEL: sadd_v4i8_vx:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
57; CHECK-NEXT:    vsadd.vx v8, v8, a0
58; CHECK-NEXT:    ret
59  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
60  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
61  %v = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb)
62  ret <4 x i8> %v
63}
64
65define <4 x i8> @sadd_v4i8_vi(<4 x i8> %va) {
66; CHECK-LABEL: sadd_v4i8_vi:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
69; CHECK-NEXT:    vsadd.vi v8, v8, 5
70; CHECK-NEXT:    ret
71  %v = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5))
72  ret <4 x i8> %v
73}
74
75declare <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8>, <8 x i8>)
76
77define <8 x i8> @sadd_v8i8_vv(<8 x i8> %va, <8 x i8> %b) {
78; CHECK-LABEL: sadd_v8i8_vv:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
81; CHECK-NEXT:    vsadd.vv v8, v8, v9
82; CHECK-NEXT:    ret
83  %v = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b)
84  ret <8 x i8> %v
85}
86
87define <8 x i8> @sadd_v8i8_vx(<8 x i8> %va, i8 %b) {
88; CHECK-LABEL: sadd_v8i8_vx:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
91; CHECK-NEXT:    vsadd.vx v8, v8, a0
92; CHECK-NEXT:    ret
93  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
94  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
95  %v = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb)
96  ret <8 x i8> %v
97}
98
99define <8 x i8> @sadd_v8i8_vi(<8 x i8> %va) {
100; CHECK-LABEL: sadd_v8i8_vi:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
103; CHECK-NEXT:    vsadd.vi v8, v8, 5
104; CHECK-NEXT:    ret
105  %v = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5))
106  ret <8 x i8> %v
107}
108
109declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
110
111define <16 x i8> @sadd_v16i8_vv(<16 x i8> %va, <16 x i8> %b) {
112; CHECK-LABEL: sadd_v16i8_vv:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
115; CHECK-NEXT:    vsadd.vv v8, v8, v9
116; CHECK-NEXT:    ret
117  %v = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b)
118  ret <16 x i8> %v
119}
120
121define <16 x i8> @sadd_v16i8_vx(<16 x i8> %va, i8 %b) {
122; CHECK-LABEL: sadd_v16i8_vx:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
125; CHECK-NEXT:    vsadd.vx v8, v8, a0
126; CHECK-NEXT:    ret
127  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
128  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
129  %v = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb)
130  ret <16 x i8> %v
131}
132
133define <16 x i8> @sadd_v16i8_vi(<16 x i8> %va) {
134; CHECK-LABEL: sadd_v16i8_vi:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
137; CHECK-NEXT:    vsadd.vi v8, v8, 5
138; CHECK-NEXT:    ret
139  %v = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5))
140  ret <16 x i8> %v
141}
142
143declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
144
145define <2 x i16> @sadd_v2i16_vv(<2 x i16> %va, <2 x i16> %b) {
146; CHECK-LABEL: sadd_v2i16_vv:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
149; CHECK-NEXT:    vsadd.vv v8, v8, v9
150; CHECK-NEXT:    ret
151  %v = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b)
152  ret <2 x i16> %v
153}
154
155define <2 x i16> @sadd_v2i16_vx(<2 x i16> %va, i16 %b) {
156; CHECK-LABEL: sadd_v2i16_vx:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
159; CHECK-NEXT:    vsadd.vx v8, v8, a0
160; CHECK-NEXT:    ret
161  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
162  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
163  %v = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb)
164  ret <2 x i16> %v
165}
166
167define <2 x i16> @sadd_v2i16_vi(<2 x i16> %va) {
168; CHECK-LABEL: sadd_v2i16_vi:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
171; CHECK-NEXT:    vsadd.vi v8, v8, 5
172; CHECK-NEXT:    ret
173  %v = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5))
174  ret <2 x i16> %v
175}
176
177declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
178
179define <4 x i16> @sadd_v4i16_vv(<4 x i16> %va, <4 x i16> %b) {
180; CHECK-LABEL: sadd_v4i16_vv:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
183; CHECK-NEXT:    vsadd.vv v8, v8, v9
184; CHECK-NEXT:    ret
185  %v = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b)
186  ret <4 x i16> %v
187}
188
189define <4 x i16> @sadd_v4i16_vx(<4 x i16> %va, i16 %b) {
190; CHECK-LABEL: sadd_v4i16_vx:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
193; CHECK-NEXT:    vsadd.vx v8, v8, a0
194; CHECK-NEXT:    ret
195  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
196  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
197  %v = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb)
198  ret <4 x i16> %v
199}
200
201define <4 x i16> @sadd_v4i16_vi(<4 x i16> %va) {
202; CHECK-LABEL: sadd_v4i16_vi:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
205; CHECK-NEXT:    vsadd.vi v8, v8, 5
206; CHECK-NEXT:    ret
207  %v = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5))
208  ret <4 x i16> %v
209}
210
211declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
212
213define <8 x i16> @sadd_v8i16_vv(<8 x i16> %va, <8 x i16> %b) {
214; CHECK-LABEL: sadd_v8i16_vv:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
217; CHECK-NEXT:    vsadd.vv v8, v8, v9
218; CHECK-NEXT:    ret
219  %v = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b)
220  ret <8 x i16> %v
221}
222
223define <8 x i16> @sadd_v8i16_vx(<8 x i16> %va, i16 %b) {
224; CHECK-LABEL: sadd_v8i16_vx:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
227; CHECK-NEXT:    vsadd.vx v8, v8, a0
228; CHECK-NEXT:    ret
229  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
230  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
231  %v = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb)
232  ret <8 x i16> %v
233}
234
235define <8 x i16> @sadd_v8i16_vi(<8 x i16> %va) {
236; CHECK-LABEL: sadd_v8i16_vi:
237; CHECK:       # %bb.0:
238; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
239; CHECK-NEXT:    vsadd.vi v8, v8, 5
240; CHECK-NEXT:    ret
241  %v = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5))
242  ret <8 x i16> %v
243}
244
245declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
246
247define <16 x i16> @sadd_v16i16_vv(<16 x i16> %va, <16 x i16> %b) {
248; CHECK-LABEL: sadd_v16i16_vv:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
251; CHECK-NEXT:    vsadd.vv v8, v8, v10
252; CHECK-NEXT:    ret
253  %v = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b)
254  ret <16 x i16> %v
255}
256
257define <16 x i16> @sadd_v16i16_vx(<16 x i16> %va, i16 %b) {
258; CHECK-LABEL: sadd_v16i16_vx:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
261; CHECK-NEXT:    vsadd.vx v8, v8, a0
262; CHECK-NEXT:    ret
263  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
264  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
265  %v = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb)
266  ret <16 x i16> %v
267}
268
269define <16 x i16> @sadd_v16i16_vi(<16 x i16> %va) {
270; CHECK-LABEL: sadd_v16i16_vi:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
273; CHECK-NEXT:    vsadd.vi v8, v8, 5
274; CHECK-NEXT:    ret
275  %v = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5))
276  ret <16 x i16> %v
277}
278
279declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
280
281define <2 x i32> @sadd_v2i32_vv(<2 x i32> %va, <2 x i32> %b) {
282; CHECK-LABEL: sadd_v2i32_vv:
283; CHECK:       # %bb.0:
284; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
285; CHECK-NEXT:    vsadd.vv v8, v8, v9
286; CHECK-NEXT:    ret
287  %v = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b)
288  ret <2 x i32> %v
289}
290
291define <2 x i32> @sadd_v2i32_vx(<2 x i32> %va, i32 %b) {
292; CHECK-LABEL: sadd_v2i32_vx:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
295; CHECK-NEXT:    vsadd.vx v8, v8, a0
296; CHECK-NEXT:    ret
297  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
298  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
299  %v = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb)
300  ret <2 x i32> %v
301}
302
303define <2 x i32> @sadd_v2i32_vx_commute(<2 x i32> %va, i32 %b) {
304; CHECK-LABEL: sadd_v2i32_vx_commute:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
307; CHECK-NEXT:    vsadd.vx v8, v8, a0
308; CHECK-NEXT:    ret
309  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
310  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
311  %v = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %vb, <2 x i32> %va)
312  ret <2 x i32> %v
313}
314
315define <2 x i32> @sadd_v2i32_vi(<2 x i32> %va) {
316; CHECK-LABEL: sadd_v2i32_vi:
317; CHECK:       # %bb.0:
318; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
319; CHECK-NEXT:    vsadd.vi v8, v8, 5
320; CHECK-NEXT:    ret
321  %v = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5))
322  ret <2 x i32> %v
323}
324
325declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
326
327define <4 x i32> @sadd_v4i32_vv(<4 x i32> %va, <4 x i32> %b) {
328; CHECK-LABEL: sadd_v4i32_vv:
329; CHECK:       # %bb.0:
330; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
331; CHECK-NEXT:    vsadd.vv v8, v8, v9
332; CHECK-NEXT:    ret
333  %v = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b)
334  ret <4 x i32> %v
335}
336
337define <4 x i32> @sadd_v4i32_vx(<4 x i32> %va, i32 %b) {
338; CHECK-LABEL: sadd_v4i32_vx:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
341; CHECK-NEXT:    vsadd.vx v8, v8, a0
342; CHECK-NEXT:    ret
343  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
344  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
345  %v = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb)
346  ret <4 x i32> %v
347}
348
349define <4 x i32> @sadd_v4i32_vi(<4 x i32> %va) {
350; CHECK-LABEL: sadd_v4i32_vi:
351; CHECK:       # %bb.0:
352; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
353; CHECK-NEXT:    vsadd.vi v8, v8, 5
354; CHECK-NEXT:    ret
355  %v = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5))
356  ret <4 x i32> %v
357}
358
359declare <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32>, <8 x i32>)
360
361define <8 x i32> @sadd_v8i32_vv(<8 x i32> %va, <8 x i32> %b) {
362; CHECK-LABEL: sadd_v8i32_vv:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
365; CHECK-NEXT:    vsadd.vv v8, v8, v10
366; CHECK-NEXT:    ret
367  %v = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b)
368  ret <8 x i32> %v
369}
370
371define <8 x i32> @sadd_v8i32_vx(<8 x i32> %va, i32 %b) {
372; CHECK-LABEL: sadd_v8i32_vx:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
375; CHECK-NEXT:    vsadd.vx v8, v8, a0
376; CHECK-NEXT:    ret
377  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
378  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
379  %v = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb)
380  ret <8 x i32> %v
381}
382
383define <8 x i32> @sadd_v8i32_vi(<8 x i32> %va) {
384; CHECK-LABEL: sadd_v8i32_vi:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
387; CHECK-NEXT:    vsadd.vi v8, v8, 5
388; CHECK-NEXT:    ret
389  %v = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5))
390  ret <8 x i32> %v
391}
392
393declare <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32>, <16 x i32>)
394
395define <16 x i32> @sadd_v16i32_vv(<16 x i32> %va, <16 x i32> %b) {
396; CHECK-LABEL: sadd_v16i32_vv:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
399; CHECK-NEXT:    vsadd.vv v8, v8, v12
400; CHECK-NEXT:    ret
401  %v = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b)
402  ret <16 x i32> %v
403}
404
405define <16 x i32> @sadd_v16i32_vx(<16 x i32> %va, i32 %b) {
406; CHECK-LABEL: sadd_v16i32_vx:
407; CHECK:       # %bb.0:
408; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
409; CHECK-NEXT:    vsadd.vx v8, v8, a0
410; CHECK-NEXT:    ret
411  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
412  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
413  %v = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb)
414  ret <16 x i32> %v
415}
416
417define <16 x i32> @sadd_v16i32_vi(<16 x i32> %va) {
418; CHECK-LABEL: sadd_v16i32_vi:
419; CHECK:       # %bb.0:
420; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
421; CHECK-NEXT:    vsadd.vi v8, v8, 5
422; CHECK-NEXT:    ret
423  %v = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5))
424  ret <16 x i32> %v
425}
426
427declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>)
428
429define <2 x i64> @sadd_v2i64_vv(<2 x i64> %va, <2 x i64> %b) {
430; CHECK-LABEL: sadd_v2i64_vv:
431; CHECK:       # %bb.0:
432; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
433; CHECK-NEXT:    vsadd.vv v8, v8, v9
434; CHECK-NEXT:    ret
435  %v = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b)
436  ret <2 x i64> %v
437}
438
439define <2 x i64> @sadd_v2i64_vx(<2 x i64> %va, i64 %b) {
440; RV32-LABEL: sadd_v2i64_vx:
441; RV32:       # %bb.0:
442; RV32-NEXT:    addi sp, sp, -16
443; RV32-NEXT:    .cfi_def_cfa_offset 16
444; RV32-NEXT:    sw a0, 8(sp)
445; RV32-NEXT:    sw a1, 12(sp)
446; RV32-NEXT:    addi a0, sp, 8
447; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
448; RV32-NEXT:    vlse64.v v9, (a0), zero
449; RV32-NEXT:    vsadd.vv v8, v8, v9
450; RV32-NEXT:    addi sp, sp, 16
451; RV32-NEXT:    .cfi_def_cfa_offset 0
452; RV32-NEXT:    ret
453;
454; RV64-LABEL: sadd_v2i64_vx:
455; RV64:       # %bb.0:
456; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
457; RV64-NEXT:    vsadd.vx v8, v8, a0
458; RV64-NEXT:    ret
459  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
460  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
461  %v = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb)
462  ret <2 x i64> %v
463}
464
465define <2 x i64> @sadd_v2i64_vi(<2 x i64> %va) {
466; CHECK-LABEL: sadd_v2i64_vi:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
469; CHECK-NEXT:    vsadd.vi v8, v8, 5
470; CHECK-NEXT:    ret
471  %v = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5))
472  ret <2 x i64> %v
473}
474
475declare <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64>, <4 x i64>)
476
477define <4 x i64> @sadd_v4i64_vv(<4 x i64> %va, <4 x i64> %b) {
478; CHECK-LABEL: sadd_v4i64_vv:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
481; CHECK-NEXT:    vsadd.vv v8, v8, v10
482; CHECK-NEXT:    ret
483  %v = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b)
484  ret <4 x i64> %v
485}
486
487define <4 x i64> @sadd_v4i64_vx(<4 x i64> %va, i64 %b) {
488; RV32-LABEL: sadd_v4i64_vx:
489; RV32:       # %bb.0:
490; RV32-NEXT:    addi sp, sp, -16
491; RV32-NEXT:    .cfi_def_cfa_offset 16
492; RV32-NEXT:    sw a0, 8(sp)
493; RV32-NEXT:    sw a1, 12(sp)
494; RV32-NEXT:    addi a0, sp, 8
495; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
496; RV32-NEXT:    vlse64.v v10, (a0), zero
497; RV32-NEXT:    vsadd.vv v8, v8, v10
498; RV32-NEXT:    addi sp, sp, 16
499; RV32-NEXT:    .cfi_def_cfa_offset 0
500; RV32-NEXT:    ret
501;
502; RV64-LABEL: sadd_v4i64_vx:
503; RV64:       # %bb.0:
504; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
505; RV64-NEXT:    vsadd.vx v8, v8, a0
506; RV64-NEXT:    ret
507  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
508  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
509  %v = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb)
510  ret <4 x i64> %v
511}
512
513define <4 x i64> @sadd_v4i64_vi(<4 x i64> %va) {
514; CHECK-LABEL: sadd_v4i64_vi:
515; CHECK:       # %bb.0:
516; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
517; CHECK-NEXT:    vsadd.vi v8, v8, 5
518; CHECK-NEXT:    ret
519  %v = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5))
520  ret <4 x i64> %v
521}
522
523declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
524
525define <8 x i64> @sadd_v8i64_vv(<8 x i64> %va, <8 x i64> %b) {
526; CHECK-LABEL: sadd_v8i64_vv:
527; CHECK:       # %bb.0:
528; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
529; CHECK-NEXT:    vsadd.vv v8, v8, v12
530; CHECK-NEXT:    ret
531  %v = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b)
532  ret <8 x i64> %v
533}
534
535define <8 x i64> @sadd_v8i64_vx(<8 x i64> %va, i64 %b) {
536; RV32-LABEL: sadd_v8i64_vx:
537; RV32:       # %bb.0:
538; RV32-NEXT:    addi sp, sp, -16
539; RV32-NEXT:    .cfi_def_cfa_offset 16
540; RV32-NEXT:    sw a0, 8(sp)
541; RV32-NEXT:    sw a1, 12(sp)
542; RV32-NEXT:    addi a0, sp, 8
543; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
544; RV32-NEXT:    vlse64.v v12, (a0), zero
545; RV32-NEXT:    vsadd.vv v8, v8, v12
546; RV32-NEXT:    addi sp, sp, 16
547; RV32-NEXT:    .cfi_def_cfa_offset 0
548; RV32-NEXT:    ret
549;
550; RV64-LABEL: sadd_v8i64_vx:
551; RV64:       # %bb.0:
552; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
553; RV64-NEXT:    vsadd.vx v8, v8, a0
554; RV64-NEXT:    ret
555  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
556  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
557  %v = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb)
558  ret <8 x i64> %v
559}
560
561define <8 x i64> @sadd_v8i64_vi(<8 x i64> %va) {
562; CHECK-LABEL: sadd_v8i64_vi:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
565; CHECK-NEXT:    vsadd.vi v8, v8, 5
566; CHECK-NEXT:    ret
567  %v = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5))
568  ret <8 x i64> %v
569}
570
571declare <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64>, <16 x i64>)
572
573define <16 x i64> @sadd_v16i64_vv(<16 x i64> %va, <16 x i64> %b) {
574; CHECK-LABEL: sadd_v16i64_vv:
575; CHECK:       # %bb.0:
576; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
577; CHECK-NEXT:    vsadd.vv v8, v8, v16
578; CHECK-NEXT:    ret
579  %v = call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b)
580  ret <16 x i64> %v
581}
582
583define <16 x i64> @sadd_v16i64_vx(<16 x i64> %va, i64 %b) {
584; RV32-LABEL: sadd_v16i64_vx:
585; RV32:       # %bb.0:
586; RV32-NEXT:    addi sp, sp, -16
587; RV32-NEXT:    .cfi_def_cfa_offset 16
588; RV32-NEXT:    sw a0, 8(sp)
589; RV32-NEXT:    sw a1, 12(sp)
590; RV32-NEXT:    addi a0, sp, 8
591; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
592; RV32-NEXT:    vlse64.v v16, (a0), zero
593; RV32-NEXT:    vsadd.vv v8, v8, v16
594; RV32-NEXT:    addi sp, sp, 16
595; RV32-NEXT:    .cfi_def_cfa_offset 0
596; RV32-NEXT:    ret
597;
598; RV64-LABEL: sadd_v16i64_vx:
599; RV64:       # %bb.0:
600; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
601; RV64-NEXT:    vsadd.vx v8, v8, a0
602; RV64-NEXT:    ret
603  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
604  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
605  %v = call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb)
606  ret <16 x i64> %v
607}
608
609define <16 x i64> @sadd_v16i64_vi(<16 x i64> %va) {
610; CHECK-LABEL: sadd_v16i64_vi:
611; CHECK:       # %bb.0:
612; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
613; CHECK-NEXT:    vsadd.vi v8, v8, 5
614; CHECK-NEXT:    ret
615  %v = call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5))
616  ret <16 x i64> %v
617}
618