xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.sadd.sat.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vsadd_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vsadd_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
13; CHECK-NEXT:    vadd.vv v9, v9, v9
14; CHECK-NEXT:    vadd.vv v8, v8, v8
15; CHECK-NEXT:    li a1, 63
16; CHECK-NEXT:    vsra.vi v9, v9, 1
17; CHECK-NEXT:    vsra.vi v8, v8, 1
18; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
19; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
20; CHECK-NEXT:    vmin.vx v8, v8, a1, v0.t
21; CHECK-NEXT:    li a0, 192
22; CHECK-NEXT:    vmax.vx v8, v8, a0, v0.t
23; CHECK-NEXT:    ret
24  %v = call <8 x i7> @llvm.vp.sadd.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
25  ret <8 x i7> %v
26}
27
28declare <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
29
30define <2 x i8> @vsadd_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
31; CHECK-LABEL: vsadd_vv_v2i8:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
34; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
35; CHECK-NEXT:    ret
36  %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
37  ret <2 x i8> %v
38}
39
40define <2 x i8> @vsadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
41; CHECK-LABEL: vsadd_vv_v2i8_unmasked:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
44; CHECK-NEXT:    vsadd.vv v8, v8, v9
45; CHECK-NEXT:    ret
46  %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
47  ret <2 x i8> %v
48}
49
50define <2 x i8> @vsadd_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
51; CHECK-LABEL: vsadd_vx_v2i8:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
54; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
55; CHECK-NEXT:    ret
56  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
57  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
58  %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
59  ret <2 x i8> %v
60}
61
62define <2 x i8> @vsadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
63; CHECK-LABEL: vsadd_vx_v2i8_unmasked:
64; CHECK:       # %bb.0:
65; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
66; CHECK-NEXT:    vsadd.vx v8, v8, a0
67; CHECK-NEXT:    ret
68  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
69  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
70  %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
71  ret <2 x i8> %v
72}
73
74define <2 x i8> @vsadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
75; CHECK-LABEL: vsadd_vi_v2i8:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
78; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
79; CHECK-NEXT:    ret
80  %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
81  ret <2 x i8> %v
82}
83
84define <2 x i8> @vsadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
85; CHECK-LABEL: vsadd_vi_v2i8_unmasked:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
88; CHECK-NEXT:    vsadd.vi v8, v8, -1
89; CHECK-NEXT:    ret
90  %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
91  ret <2 x i8> %v
92}
93
94declare <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
95
96define <4 x i8> @vsadd_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
97; CHECK-LABEL: vsadd_vv_v4i8:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
100; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
101; CHECK-NEXT:    ret
102  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
103  ret <4 x i8> %v
104}
105
106define <4 x i8> @vsadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
107; CHECK-LABEL: vsadd_vv_v4i8_unmasked:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
110; CHECK-NEXT:    vsadd.vv v8, v8, v9
111; CHECK-NEXT:    ret
112  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
113  ret <4 x i8> %v
114}
115
116define <4 x i8> @vsadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
117; CHECK-LABEL: vsadd_vx_v4i8:
118; CHECK:       # %bb.0:
119; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
120; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
121; CHECK-NEXT:    ret
122  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
123  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
124  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
125  ret <4 x i8> %v
126}
127
128define <4 x i8> @vsadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
129; CHECK-LABEL: vsadd_vx_v4i8_commute:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
132; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
133; CHECK-NEXT:    ret
134  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
135  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
136  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
137  ret <4 x i8> %v
138}
139
140define <4 x i8> @vsadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
141; CHECK-LABEL: vsadd_vx_v4i8_unmasked:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
144; CHECK-NEXT:    vsadd.vx v8, v8, a0
145; CHECK-NEXT:    ret
146  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
147  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
148  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
149  ret <4 x i8> %v
150}
151
152define <4 x i8> @vsadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
153; CHECK-LABEL: vsadd_vi_v4i8:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
156; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
157; CHECK-NEXT:    ret
158  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
159  ret <4 x i8> %v
160}
161
162define <4 x i8> @vsadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
163; CHECK-LABEL: vsadd_vi_v4i8_unmasked:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
166; CHECK-NEXT:    vsadd.vi v8, v8, -1
167; CHECK-NEXT:    ret
168  %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
169  ret <4 x i8> %v
170}
171
172declare <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8>, <5 x i8>, <5 x i1>, i32)
173
174define <5 x i8> @vsadd_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
175; CHECK-LABEL: vsadd_vv_v5i8:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
178; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
179; CHECK-NEXT:    ret
180  %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
181  ret <5 x i8> %v
182}
183
184define <5 x i8> @vsadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
185; CHECK-LABEL: vsadd_vv_v5i8_unmasked:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
188; CHECK-NEXT:    vsadd.vv v8, v8, v9
189; CHECK-NEXT:    ret
190  %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
191  ret <5 x i8> %v
192}
193
194define <5 x i8> @vsadd_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
195; CHECK-LABEL: vsadd_vx_v5i8:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
198; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
199; CHECK-NEXT:    ret
200  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
201  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
202  %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)
203  ret <5 x i8> %v
204}
205
206define <5 x i8> @vsadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
207; CHECK-LABEL: vsadd_vx_v5i8_unmasked:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
210; CHECK-NEXT:    vsadd.vx v8, v8, a0
211; CHECK-NEXT:    ret
212  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
213  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
214  %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)
215  ret <5 x i8> %v
216}
217
218define <5 x i8> @vsadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
219; CHECK-LABEL: vsadd_vi_v5i8:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
222; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
223; CHECK-NEXT:    ret
224  %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
225  ret <5 x i8> %v
226}
227
228define <5 x i8> @vsadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
229; CHECK-LABEL: vsadd_vi_v5i8_unmasked:
230; CHECK:       # %bb.0:
231; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
232; CHECK-NEXT:    vsadd.vi v8, v8, -1
233; CHECK-NEXT:    ret
234  %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
235  ret <5 x i8> %v
236}
237
238declare <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
239
240define <8 x i8> @vsadd_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
241; CHECK-LABEL: vsadd_vv_v8i8:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
244; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
245; CHECK-NEXT:    ret
246  %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
247  ret <8 x i8> %v
248}
249
250define <8 x i8> @vsadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
251; CHECK-LABEL: vsadd_vv_v8i8_unmasked:
252; CHECK:       # %bb.0:
253; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
254; CHECK-NEXT:    vsadd.vv v8, v8, v9
255; CHECK-NEXT:    ret
256  %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
257  ret <8 x i8> %v
258}
259
260define <8 x i8> @vsadd_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
261; CHECK-LABEL: vsadd_vx_v8i8:
262; CHECK:       # %bb.0:
263; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
264; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
265; CHECK-NEXT:    ret
266  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
267  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
268  %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
269  ret <8 x i8> %v
270}
271
272define <8 x i8> @vsadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
273; CHECK-LABEL: vsadd_vx_v8i8_unmasked:
274; CHECK:       # %bb.0:
275; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
276; CHECK-NEXT:    vsadd.vx v8, v8, a0
277; CHECK-NEXT:    ret
278  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
279  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
280  %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
281  ret <8 x i8> %v
282}
283
284define <8 x i8> @vsadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
285; CHECK-LABEL: vsadd_vi_v8i8:
286; CHECK:       # %bb.0:
287; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
288; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
289; CHECK-NEXT:    ret
290  %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
291  ret <8 x i8> %v
292}
293
294define <8 x i8> @vsadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
295; CHECK-LABEL: vsadd_vi_v8i8_unmasked:
296; CHECK:       # %bb.0:
297; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
298; CHECK-NEXT:    vsadd.vi v8, v8, -1
299; CHECK-NEXT:    ret
300  %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
301  ret <8 x i8> %v
302}
303
304declare <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
305
306define <16 x i8> @vsadd_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
307; CHECK-LABEL: vsadd_vv_v16i8:
308; CHECK:       # %bb.0:
309; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
310; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
311; CHECK-NEXT:    ret
312  %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
313  ret <16 x i8> %v
314}
315
316define <16 x i8> @vsadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
317; CHECK-LABEL: vsadd_vv_v16i8_unmasked:
318; CHECK:       # %bb.0:
319; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
320; CHECK-NEXT:    vsadd.vv v8, v8, v9
321; CHECK-NEXT:    ret
322  %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
323  ret <16 x i8> %v
324}
325
326define <16 x i8> @vsadd_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
327; CHECK-LABEL: vsadd_vx_v16i8:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
330; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
331; CHECK-NEXT:    ret
332  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
333  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
334  %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
335  ret <16 x i8> %v
336}
337
338define <16 x i8> @vsadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
339; CHECK-LABEL: vsadd_vx_v16i8_unmasked:
340; CHECK:       # %bb.0:
341; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
342; CHECK-NEXT:    vsadd.vx v8, v8, a0
343; CHECK-NEXT:    ret
344  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
345  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
346  %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
347  ret <16 x i8> %v
348}
349
350define <16 x i8> @vsadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
351; CHECK-LABEL: vsadd_vi_v16i8:
352; CHECK:       # %bb.0:
353; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
354; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
355; CHECK-NEXT:    ret
356  %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
357  ret <16 x i8> %v
358}
359
360define <16 x i8> @vsadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
361; CHECK-LABEL: vsadd_vi_v16i8_unmasked:
362; CHECK:       # %bb.0:
363; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
364; CHECK-NEXT:    vsadd.vi v8, v8, -1
365; CHECK-NEXT:    ret
366  %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
367  ret <16 x i8> %v
368}
369
370declare <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8>, <256 x i8>, <256 x i1>, i32)
371
372define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
373; CHECK-LABEL: vsadd_vi_v258i8:
374; CHECK:       # %bb.0:
375; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
376; CHECK-NEXT:    vmv1r.v v24, v0
377; CHECK-NEXT:    li a2, 128
378; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
379; CHECK-NEXT:    vlm.v v0, (a0)
380; CHECK-NEXT:    addi a0, a1, -128
381; CHECK-NEXT:    sltu a3, a1, a0
382; CHECK-NEXT:    addi a3, a3, -1
383; CHECK-NEXT:    and a0, a3, a0
384; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
385; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t
386; CHECK-NEXT:    bltu a1, a2, .LBB32_2
387; CHECK-NEXT:  # %bb.1:
388; CHECK-NEXT:    li a1, 128
389; CHECK-NEXT:  .LBB32_2:
390; CHECK-NEXT:    vmv1r.v v0, v24
391; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
392; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
393; CHECK-NEXT:    ret
394  %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
395  ret <256 x i8> %v
396}
397
398define <256 x i8> @vsadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
399; CHECK-LABEL: vsadd_vi_v258i8_unmasked:
400; CHECK:       # %bb.0:
401; CHECK-NEXT:    li a2, 128
402; CHECK-NEXT:    mv a1, a0
403; CHECK-NEXT:    bltu a0, a2, .LBB33_2
404; CHECK-NEXT:  # %bb.1:
405; CHECK-NEXT:    li a1, 128
406; CHECK-NEXT:  .LBB33_2:
407; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
408; CHECK-NEXT:    vsadd.vi v8, v8, -1
409; CHECK-NEXT:    addi a1, a0, -128
410; CHECK-NEXT:    sltu a0, a0, a1
411; CHECK-NEXT:    addi a0, a0, -1
412; CHECK-NEXT:    and a0, a0, a1
413; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
414; CHECK-NEXT:    vsadd.vi v16, v16, -1
415; CHECK-NEXT:    ret
416  %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
417  ret <256 x i8> %v
418}
419
420; Test splitting when the %evl is a known constant.
421
422define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
423; CHECK-LABEL: vsadd_vi_v258i8_evl129:
424; CHECK:       # %bb.0:
425; CHECK-NEXT:    li a1, 128
426; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
427; CHECK-NEXT:    vlm.v v24, (a0)
428; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
429; CHECK-NEXT:    vmv1r.v v0, v24
430; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
431; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t
432; CHECK-NEXT:    ret
433  %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
434  ret <256 x i8> %v
435}
436
437; FIXME: The upper half is doing nothing.
438
439define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
440; CHECK-LABEL: vsadd_vi_v258i8_evl128:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    li a1, 128
443; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
444; CHECK-NEXT:    vlm.v v24, (a0)
445; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
446; CHECK-NEXT:    vmv1r.v v0, v24
447; CHECK-NEXT:    vsetivli zero, 0, e8, m8, ta, ma
448; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t
449; CHECK-NEXT:    ret
450  %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
451  ret <256 x i8> %v
452}
453
454declare <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
455
456define <2 x i16> @vsadd_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
457; CHECK-LABEL: vsadd_vv_v2i16:
458; CHECK:       # %bb.0:
459; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
460; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
461; CHECK-NEXT:    ret
462  %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
463  ret <2 x i16> %v
464}
465
466define <2 x i16> @vsadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
467; CHECK-LABEL: vsadd_vv_v2i16_unmasked:
468; CHECK:       # %bb.0:
469; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
470; CHECK-NEXT:    vsadd.vv v8, v8, v9
471; CHECK-NEXT:    ret
472  %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
473  ret <2 x i16> %v
474}
475
476define <2 x i16> @vsadd_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
477; CHECK-LABEL: vsadd_vx_v2i16:
478; CHECK:       # %bb.0:
479; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
480; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
481; CHECK-NEXT:    ret
482  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
483  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
484  %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
485  ret <2 x i16> %v
486}
487
488define <2 x i16> @vsadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
489; CHECK-LABEL: vsadd_vx_v2i16_unmasked:
490; CHECK:       # %bb.0:
491; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
492; CHECK-NEXT:    vsadd.vx v8, v8, a0
493; CHECK-NEXT:    ret
494  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
495  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
496  %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
497  ret <2 x i16> %v
498}
499
500define <2 x i16> @vsadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
501; CHECK-LABEL: vsadd_vi_v2i16:
502; CHECK:       # %bb.0:
503; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
504; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
505; CHECK-NEXT:    ret
506  %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
507  ret <2 x i16> %v
508}
509
510define <2 x i16> @vsadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
511; CHECK-LABEL: vsadd_vi_v2i16_unmasked:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
514; CHECK-NEXT:    vsadd.vi v8, v8, -1
515; CHECK-NEXT:    ret
516  %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
517  ret <2 x i16> %v
518}
519
520declare <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
521
522define <4 x i16> @vsadd_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
523; CHECK-LABEL: vsadd_vv_v4i16:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
526; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
527; CHECK-NEXT:    ret
528  %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
529  ret <4 x i16> %v
530}
531
532define <4 x i16> @vsadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
533; CHECK-LABEL: vsadd_vv_v4i16_unmasked:
534; CHECK:       # %bb.0:
535; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
536; CHECK-NEXT:    vsadd.vv v8, v8, v9
537; CHECK-NEXT:    ret
538  %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
539  ret <4 x i16> %v
540}
541
542define <4 x i16> @vsadd_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
543; CHECK-LABEL: vsadd_vx_v4i16:
544; CHECK:       # %bb.0:
545; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
546; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
547; CHECK-NEXT:    ret
548  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
549  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
550  %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
551  ret <4 x i16> %v
552}
553
554define <4 x i16> @vsadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
555; CHECK-LABEL: vsadd_vx_v4i16_unmasked:
556; CHECK:       # %bb.0:
557; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
558; CHECK-NEXT:    vsadd.vx v8, v8, a0
559; CHECK-NEXT:    ret
560  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
561  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
562  %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
563  ret <4 x i16> %v
564}
565
566define <4 x i16> @vsadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
567; CHECK-LABEL: vsadd_vi_v4i16:
568; CHECK:       # %bb.0:
569; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
570; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
571; CHECK-NEXT:    ret
572  %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
573  ret <4 x i16> %v
574}
575
576define <4 x i16> @vsadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
577; CHECK-LABEL: vsadd_vi_v4i16_unmasked:
578; CHECK:       # %bb.0:
579; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
580; CHECK-NEXT:    vsadd.vi v8, v8, -1
581; CHECK-NEXT:    ret
582  %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
583  ret <4 x i16> %v
584}
585
586declare <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
587
588define <8 x i16> @vsadd_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
589; CHECK-LABEL: vsadd_vv_v8i16:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
592; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
593; CHECK-NEXT:    ret
594  %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
595  ret <8 x i16> %v
596}
597
598define <8 x i16> @vsadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
599; CHECK-LABEL: vsadd_vv_v8i16_unmasked:
600; CHECK:       # %bb.0:
601; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
602; CHECK-NEXT:    vsadd.vv v8, v8, v9
603; CHECK-NEXT:    ret
604  %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
605  ret <8 x i16> %v
606}
607
608define <8 x i16> @vsadd_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
609; CHECK-LABEL: vsadd_vx_v8i16:
610; CHECK:       # %bb.0:
611; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
612; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
613; CHECK-NEXT:    ret
614  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
615  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
616  %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
617  ret <8 x i16> %v
618}
619
620define <8 x i16> @vsadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
621; CHECK-LABEL: vsadd_vx_v8i16_unmasked:
622; CHECK:       # %bb.0:
623; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
624; CHECK-NEXT:    vsadd.vx v8, v8, a0
625; CHECK-NEXT:    ret
626  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
627  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
628  %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
629  ret <8 x i16> %v
630}
631
632define <8 x i16> @vsadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
633; CHECK-LABEL: vsadd_vi_v8i16:
634; CHECK:       # %bb.0:
635; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
636; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
637; CHECK-NEXT:    ret
638  %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
639  ret <8 x i16> %v
640}
641
642define <8 x i16> @vsadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
643; CHECK-LABEL: vsadd_vi_v8i16_unmasked:
644; CHECK:       # %bb.0:
645; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
646; CHECK-NEXT:    vsadd.vi v8, v8, -1
647; CHECK-NEXT:    ret
648  %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
649  ret <8 x i16> %v
650}
651
652declare <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
653
654define <16 x i16> @vsadd_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
655; CHECK-LABEL: vsadd_vv_v16i16:
656; CHECK:       # %bb.0:
657; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
658; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t
659; CHECK-NEXT:    ret
660  %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
661  ret <16 x i16> %v
662}
663
664define <16 x i16> @vsadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
665; CHECK-LABEL: vsadd_vv_v16i16_unmasked:
666; CHECK:       # %bb.0:
667; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
668; CHECK-NEXT:    vsadd.vv v8, v8, v10
669; CHECK-NEXT:    ret
670  %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
671  ret <16 x i16> %v
672}
673
674define <16 x i16> @vsadd_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
675; CHECK-LABEL: vsadd_vx_v16i16:
676; CHECK:       # %bb.0:
677; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
678; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
679; CHECK-NEXT:    ret
680  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
681  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
682  %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
683  ret <16 x i16> %v
684}
685
686define <16 x i16> @vsadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
687; CHECK-LABEL: vsadd_vx_v16i16_unmasked:
688; CHECK:       # %bb.0:
689; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
690; CHECK-NEXT:    vsadd.vx v8, v8, a0
691; CHECK-NEXT:    ret
692  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
693  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
694  %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
695  ret <16 x i16> %v
696}
697
698define <16 x i16> @vsadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
699; CHECK-LABEL: vsadd_vi_v16i16:
700; CHECK:       # %bb.0:
701; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
702; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
703; CHECK-NEXT:    ret
704  %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
705  ret <16 x i16> %v
706}
707
708define <16 x i16> @vsadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
709; CHECK-LABEL: vsadd_vi_v16i16_unmasked:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
712; CHECK-NEXT:    vsadd.vi v8, v8, -1
713; CHECK-NEXT:    ret
714  %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
715  ret <16 x i16> %v
716}
717
718declare <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
719
720define <2 x i32> @vsadd_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
721; CHECK-LABEL: vsadd_vv_v2i32:
722; CHECK:       # %bb.0:
723; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
724; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
725; CHECK-NEXT:    ret
726  %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
727  ret <2 x i32> %v
728}
729
730define <2 x i32> @vsadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
731; CHECK-LABEL: vsadd_vv_v2i32_unmasked:
732; CHECK:       # %bb.0:
733; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
734; CHECK-NEXT:    vsadd.vv v8, v8, v9
735; CHECK-NEXT:    ret
736  %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
737  ret <2 x i32> %v
738}
739
740define <2 x i32> @vsadd_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
741; CHECK-LABEL: vsadd_vx_v2i32:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
744; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
745; CHECK-NEXT:    ret
746  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
747  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
748  %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
749  ret <2 x i32> %v
750}
751
752define <2 x i32> @vsadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
753; CHECK-LABEL: vsadd_vx_v2i32_unmasked:
754; CHECK:       # %bb.0:
755; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
756; CHECK-NEXT:    vsadd.vx v8, v8, a0
757; CHECK-NEXT:    ret
758  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
759  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
760  %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
761  ret <2 x i32> %v
762}
763
764define <2 x i32> @vsadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
765; CHECK-LABEL: vsadd_vi_v2i32:
766; CHECK:       # %bb.0:
767; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
768; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
769; CHECK-NEXT:    ret
770  %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
771  ret <2 x i32> %v
772}
773
774define <2 x i32> @vsadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
775; CHECK-LABEL: vsadd_vi_v2i32_unmasked:
776; CHECK:       # %bb.0:
777; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
778; CHECK-NEXT:    vsadd.vi v8, v8, -1
779; CHECK-NEXT:    ret
780  %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
781  ret <2 x i32> %v
782}
783
784declare <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
785
786define <4 x i32> @vsadd_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
787; CHECK-LABEL: vsadd_vv_v4i32:
788; CHECK:       # %bb.0:
789; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
790; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
791; CHECK-NEXT:    ret
792  %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
793  ret <4 x i32> %v
794}
795
796define <4 x i32> @vsadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
797; CHECK-LABEL: vsadd_vv_v4i32_unmasked:
798; CHECK:       # %bb.0:
799; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
800; CHECK-NEXT:    vsadd.vv v8, v8, v9
801; CHECK-NEXT:    ret
802  %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
803  ret <4 x i32> %v
804}
805
806define <4 x i32> @vsadd_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
807; CHECK-LABEL: vsadd_vx_v4i32:
808; CHECK:       # %bb.0:
809; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
810; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
811; CHECK-NEXT:    ret
812  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
813  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
814  %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
815  ret <4 x i32> %v
816}
817
818define <4 x i32> @vsadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
819; CHECK-LABEL: vsadd_vx_v4i32_unmasked:
820; CHECK:       # %bb.0:
821; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
822; CHECK-NEXT:    vsadd.vx v8, v8, a0
823; CHECK-NEXT:    ret
824  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
825  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
826  %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
827  ret <4 x i32> %v
828}
829
830define <4 x i32> @vsadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
831; CHECK-LABEL: vsadd_vi_v4i32:
832; CHECK:       # %bb.0:
833; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
834; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
835; CHECK-NEXT:    ret
836  %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
837  ret <4 x i32> %v
838}
839
840define <4 x i32> @vsadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
841; CHECK-LABEL: vsadd_vi_v4i32_unmasked:
842; CHECK:       # %bb.0:
843; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
844; CHECK-NEXT:    vsadd.vi v8, v8, -1
845; CHECK-NEXT:    ret
846  %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
847  ret <4 x i32> %v
848}
849
850declare <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
851
852define <8 x i32> @vsadd_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
853; CHECK-LABEL: vsadd_vv_v8i32:
854; CHECK:       # %bb.0:
855; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
856; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t
857; CHECK-NEXT:    ret
858  %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
859  ret <8 x i32> %v
860}
861
862define <8 x i32> @vsadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
863; CHECK-LABEL: vsadd_vv_v8i32_unmasked:
864; CHECK:       # %bb.0:
865; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
866; CHECK-NEXT:    vsadd.vv v8, v8, v10
867; CHECK-NEXT:    ret
868  %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
869  ret <8 x i32> %v
870}
871
872define <8 x i32> @vsadd_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
873; CHECK-LABEL: vsadd_vx_v8i32:
874; CHECK:       # %bb.0:
875; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
876; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
877; CHECK-NEXT:    ret
878  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
879  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
880  %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
881  ret <8 x i32> %v
882}
883
884define <8 x i32> @vsadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
885; CHECK-LABEL: vsadd_vx_v8i32_unmasked:
886; CHECK:       # %bb.0:
887; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
888; CHECK-NEXT:    vsadd.vx v8, v8, a0
889; CHECK-NEXT:    ret
890  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
891  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
892  %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
893  ret <8 x i32> %v
894}
895
896define <8 x i32> @vsadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
897; CHECK-LABEL: vsadd_vi_v8i32:
898; CHECK:       # %bb.0:
899; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
900; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
901; CHECK-NEXT:    ret
902  %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
903  ret <8 x i32> %v
904}
905
906define <8 x i32> @vsadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
907; CHECK-LABEL: vsadd_vi_v8i32_unmasked:
908; CHECK:       # %bb.0:
909; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
910; CHECK-NEXT:    vsadd.vi v8, v8, -1
911; CHECK-NEXT:    ret
912  %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
913  ret <8 x i32> %v
914}
915
916declare <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
917
918define <16 x i32> @vsadd_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
919; CHECK-LABEL: vsadd_vv_v16i32:
920; CHECK:       # %bb.0:
921; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
922; CHECK-NEXT:    vsadd.vv v8, v8, v12, v0.t
923; CHECK-NEXT:    ret
924  %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
925  ret <16 x i32> %v
926}
927
928define <16 x i32> @vsadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
929; CHECK-LABEL: vsadd_vv_v16i32_unmasked:
930; CHECK:       # %bb.0:
931; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
932; CHECK-NEXT:    vsadd.vv v8, v8, v12
933; CHECK-NEXT:    ret
934  %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
935  ret <16 x i32> %v
936}
937
938define <16 x i32> @vsadd_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
939; CHECK-LABEL: vsadd_vx_v16i32:
940; CHECK:       # %bb.0:
941; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
942; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t
943; CHECK-NEXT:    ret
944  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
945  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
946  %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
947  ret <16 x i32> %v
948}
949
950define <16 x i32> @vsadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
951; CHECK-LABEL: vsadd_vx_v16i32_unmasked:
952; CHECK:       # %bb.0:
953; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
954; CHECK-NEXT:    vsadd.vx v8, v8, a0
955; CHECK-NEXT:    ret
956  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
957  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
958  %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
959  ret <16 x i32> %v
960}
961
962define <16 x i32> @vsadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
963; CHECK-LABEL: vsadd_vi_v16i32:
964; CHECK:       # %bb.0:
965; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
966; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
967; CHECK-NEXT:    ret
968  %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
969  ret <16 x i32> %v
970}
971
972define <16 x i32> @vsadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
973; CHECK-LABEL: vsadd_vi_v16i32_unmasked:
974; CHECK:       # %bb.0:
975; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
976; CHECK-NEXT:    vsadd.vi v8, v8, -1
977; CHECK-NEXT:    ret
978  %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
979  ret <16 x i32> %v
980}
981
982declare <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
983
984define <2 x i64> @vsadd_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
985; CHECK-LABEL: vsadd_vv_v2i64:
986; CHECK:       # %bb.0:
987; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
988; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t
989; CHECK-NEXT:    ret
990  %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
991  ret <2 x i64> %v
992}
993
994define <2 x i64> @vsadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
995; CHECK-LABEL: vsadd_vv_v2i64_unmasked:
996; CHECK:       # %bb.0:
997; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
998; CHECK-NEXT:    vsadd.vv v8, v8, v9
999; CHECK-NEXT:    ret
1000  %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
1001  ret <2 x i64> %v
1002}
1003
1004define <2 x i64> @vsadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
1005; RV32-LABEL: vsadd_vx_v2i64:
1006; RV32:       # %bb.0:
1007; RV32-NEXT:    addi sp, sp, -16
1008; RV32-NEXT:    .cfi_def_cfa_offset 16
1009; RV32-NEXT:    sw a0, 8(sp)
1010; RV32-NEXT:    sw a1, 12(sp)
1011; RV32-NEXT:    addi a0, sp, 8
1012; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1013; RV32-NEXT:    vlse64.v v9, (a0), zero
1014; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1015; RV32-NEXT:    vsadd.vv v8, v8, v9, v0.t
1016; RV32-NEXT:    addi sp, sp, 16
1017; RV32-NEXT:    .cfi_def_cfa_offset 0
1018; RV32-NEXT:    ret
1019;
1020; RV64-LABEL: vsadd_vx_v2i64:
1021; RV64:       # %bb.0:
1022; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1023; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t
1024; RV64-NEXT:    ret
1025  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1026  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1027  %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
1028  ret <2 x i64> %v
1029}
1030
1031define <2 x i64> @vsadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
1032; RV32-LABEL: vsadd_vx_v2i64_unmasked:
1033; RV32:       # %bb.0:
1034; RV32-NEXT:    addi sp, sp, -16
1035; RV32-NEXT:    .cfi_def_cfa_offset 16
1036; RV32-NEXT:    sw a0, 8(sp)
1037; RV32-NEXT:    sw a1, 12(sp)
1038; RV32-NEXT:    addi a0, sp, 8
1039; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1040; RV32-NEXT:    vlse64.v v9, (a0), zero
1041; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1042; RV32-NEXT:    vsadd.vv v8, v8, v9
1043; RV32-NEXT:    addi sp, sp, 16
1044; RV32-NEXT:    .cfi_def_cfa_offset 0
1045; RV32-NEXT:    ret
1046;
1047; RV64-LABEL: vsadd_vx_v2i64_unmasked:
1048; RV64:       # %bb.0:
1049; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1050; RV64-NEXT:    vsadd.vx v8, v8, a0
1051; RV64-NEXT:    ret
1052  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1053  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1054  %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
1055  ret <2 x i64> %v
1056}
1057
1058define <2 x i64> @vsadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
1059; CHECK-LABEL: vsadd_vi_v2i64:
1060; CHECK:       # %bb.0:
1061; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1062; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1063; CHECK-NEXT:    ret
1064  %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
1065  ret <2 x i64> %v
1066}
1067
1068define <2 x i64> @vsadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
1069; CHECK-LABEL: vsadd_vi_v2i64_unmasked:
1070; CHECK:       # %bb.0:
1071; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1072; CHECK-NEXT:    vsadd.vi v8, v8, -1
1073; CHECK-NEXT:    ret
1074  %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
1075  ret <2 x i64> %v
1076}
1077
1078declare <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
1079
1080define <4 x i64> @vsadd_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
1081; CHECK-LABEL: vsadd_vv_v4i64:
1082; CHECK:       # %bb.0:
1083; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1084; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t
1085; CHECK-NEXT:    ret
1086  %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1087  ret <4 x i64> %v
1088}
1089
1090define <4 x i64> @vsadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
1091; CHECK-LABEL: vsadd_vv_v4i64_unmasked:
1092; CHECK:       # %bb.0:
1093; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1094; CHECK-NEXT:    vsadd.vv v8, v8, v10
1095; CHECK-NEXT:    ret
1096  %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
1097  ret <4 x i64> %v
1098}
1099
1100define <4 x i64> @vsadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1101; RV32-LABEL: vsadd_vx_v4i64:
1102; RV32:       # %bb.0:
1103; RV32-NEXT:    addi sp, sp, -16
1104; RV32-NEXT:    .cfi_def_cfa_offset 16
1105; RV32-NEXT:    sw a0, 8(sp)
1106; RV32-NEXT:    sw a1, 12(sp)
1107; RV32-NEXT:    addi a0, sp, 8
1108; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1109; RV32-NEXT:    vlse64.v v10, (a0), zero
1110; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1111; RV32-NEXT:    vsadd.vv v8, v8, v10, v0.t
1112; RV32-NEXT:    addi sp, sp, 16
1113; RV32-NEXT:    .cfi_def_cfa_offset 0
1114; RV32-NEXT:    ret
1115;
1116; RV64-LABEL: vsadd_vx_v4i64:
1117; RV64:       # %bb.0:
1118; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1119; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t
1120; RV64-NEXT:    ret
1121  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1122  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1123  %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1124  ret <4 x i64> %v
1125}
1126
1127define <4 x i64> @vsadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1128; RV32-LABEL: vsadd_vx_v4i64_unmasked:
1129; RV32:       # %bb.0:
1130; RV32-NEXT:    addi sp, sp, -16
1131; RV32-NEXT:    .cfi_def_cfa_offset 16
1132; RV32-NEXT:    sw a0, 8(sp)
1133; RV32-NEXT:    sw a1, 12(sp)
1134; RV32-NEXT:    addi a0, sp, 8
1135; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1136; RV32-NEXT:    vlse64.v v10, (a0), zero
1137; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1138; RV32-NEXT:    vsadd.vv v8, v8, v10
1139; RV32-NEXT:    addi sp, sp, 16
1140; RV32-NEXT:    .cfi_def_cfa_offset 0
1141; RV32-NEXT:    ret
1142;
1143; RV64-LABEL: vsadd_vx_v4i64_unmasked:
1144; RV64:       # %bb.0:
1145; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1146; RV64-NEXT:    vsadd.vx v8, v8, a0
1147; RV64-NEXT:    ret
1148  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1149  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1150  %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
1151  ret <4 x i64> %v
1152}
1153
1154define <4 x i64> @vsadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1155; CHECK-LABEL: vsadd_vi_v4i64:
1156; CHECK:       # %bb.0:
1157; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1158; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1159; CHECK-NEXT:    ret
1160  %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
1161  ret <4 x i64> %v
1162}
1163
1164define <4 x i64> @vsadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1165; CHECK-LABEL: vsadd_vi_v4i64_unmasked:
1166; CHECK:       # %bb.0:
1167; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1168; CHECK-NEXT:    vsadd.vi v8, v8, -1
1169; CHECK-NEXT:    ret
1170  %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
1171  ret <4 x i64> %v
1172}
1173
1174declare <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1175
1176define <8 x i64> @vsadd_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1177; CHECK-LABEL: vsadd_vv_v8i64:
1178; CHECK:       # %bb.0:
1179; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1180; CHECK-NEXT:    vsadd.vv v8, v8, v12, v0.t
1181; CHECK-NEXT:    ret
1182  %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1183  ret <8 x i64> %v
1184}
1185
1186define <8 x i64> @vsadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1187; CHECK-LABEL: vsadd_vv_v8i64_unmasked:
1188; CHECK:       # %bb.0:
1189; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1190; CHECK-NEXT:    vsadd.vv v8, v8, v12
1191; CHECK-NEXT:    ret
1192  %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
1193  ret <8 x i64> %v
1194}
1195
1196define <8 x i64> @vsadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1197; RV32-LABEL: vsadd_vx_v8i64:
1198; RV32:       # %bb.0:
1199; RV32-NEXT:    addi sp, sp, -16
1200; RV32-NEXT:    .cfi_def_cfa_offset 16
1201; RV32-NEXT:    sw a0, 8(sp)
1202; RV32-NEXT:    sw a1, 12(sp)
1203; RV32-NEXT:    addi a0, sp, 8
1204; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1205; RV32-NEXT:    vlse64.v v12, (a0), zero
1206; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1207; RV32-NEXT:    vsadd.vv v8, v8, v12, v0.t
1208; RV32-NEXT:    addi sp, sp, 16
1209; RV32-NEXT:    .cfi_def_cfa_offset 0
1210; RV32-NEXT:    ret
1211;
1212; RV64-LABEL: vsadd_vx_v8i64:
1213; RV64:       # %bb.0:
1214; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1215; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t
1216; RV64-NEXT:    ret
1217  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1218  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1219  %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1220  ret <8 x i64> %v
1221}
1222
1223define <8 x i64> @vsadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1224; RV32-LABEL: vsadd_vx_v8i64_unmasked:
1225; RV32:       # %bb.0:
1226; RV32-NEXT:    addi sp, sp, -16
1227; RV32-NEXT:    .cfi_def_cfa_offset 16
1228; RV32-NEXT:    sw a0, 8(sp)
1229; RV32-NEXT:    sw a1, 12(sp)
1230; RV32-NEXT:    addi a0, sp, 8
1231; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1232; RV32-NEXT:    vlse64.v v12, (a0), zero
1233; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1234; RV32-NEXT:    vsadd.vv v8, v8, v12
1235; RV32-NEXT:    addi sp, sp, 16
1236; RV32-NEXT:    .cfi_def_cfa_offset 0
1237; RV32-NEXT:    ret
1238;
1239; RV64-LABEL: vsadd_vx_v8i64_unmasked:
1240; RV64:       # %bb.0:
1241; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1242; RV64-NEXT:    vsadd.vx v8, v8, a0
1243; RV64-NEXT:    ret
1244  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1245  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1246  %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
1247  ret <8 x i64> %v
1248}
1249
1250define <8 x i64> @vsadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1251; CHECK-LABEL: vsadd_vi_v8i64:
1252; CHECK:       # %bb.0:
1253; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1254; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1255; CHECK-NEXT:    ret
1256  %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
1257  ret <8 x i64> %v
1258}
1259
1260define <8 x i64> @vsadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1261; CHECK-LABEL: vsadd_vi_v8i64_unmasked:
1262; CHECK:       # %bb.0:
1263; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1264; CHECK-NEXT:    vsadd.vi v8, v8, -1
1265; CHECK-NEXT:    ret
1266  %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
1267  ret <8 x i64> %v
1268}
1269
1270declare <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1271
1272define <16 x i64> @vsadd_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1273; CHECK-LABEL: vsadd_vv_v16i64:
1274; CHECK:       # %bb.0:
1275; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1276; CHECK-NEXT:    vsadd.vv v8, v8, v16, v0.t
1277; CHECK-NEXT:    ret
1278  %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1279  ret <16 x i64> %v
1280}
1281
1282define <16 x i64> @vsadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1283; CHECK-LABEL: vsadd_vv_v16i64_unmasked:
1284; CHECK:       # %bb.0:
1285; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1286; CHECK-NEXT:    vsadd.vv v8, v8, v16
1287; CHECK-NEXT:    ret
1288  %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
1289  ret <16 x i64> %v
1290}
1291
1292define <16 x i64> @vsadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1293; RV32-LABEL: vsadd_vx_v16i64:
1294; RV32:       # %bb.0:
1295; RV32-NEXT:    addi sp, sp, -16
1296; RV32-NEXT:    .cfi_def_cfa_offset 16
1297; RV32-NEXT:    sw a0, 8(sp)
1298; RV32-NEXT:    sw a1, 12(sp)
1299; RV32-NEXT:    addi a0, sp, 8
1300; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1301; RV32-NEXT:    vlse64.v v16, (a0), zero
1302; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1303; RV32-NEXT:    vsadd.vv v8, v8, v16, v0.t
1304; RV32-NEXT:    addi sp, sp, 16
1305; RV32-NEXT:    .cfi_def_cfa_offset 0
1306; RV32-NEXT:    ret
1307;
1308; RV64-LABEL: vsadd_vx_v16i64:
1309; RV64:       # %bb.0:
1310; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1311; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t
1312; RV64-NEXT:    ret
1313  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1314  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1315  %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1316  ret <16 x i64> %v
1317}
1318
1319define <16 x i64> @vsadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1320; RV32-LABEL: vsadd_vx_v16i64_unmasked:
1321; RV32:       # %bb.0:
1322; RV32-NEXT:    addi sp, sp, -16
1323; RV32-NEXT:    .cfi_def_cfa_offset 16
1324; RV32-NEXT:    sw a0, 8(sp)
1325; RV32-NEXT:    sw a1, 12(sp)
1326; RV32-NEXT:    addi a0, sp, 8
1327; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1328; RV32-NEXT:    vlse64.v v16, (a0), zero
1329; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1330; RV32-NEXT:    vsadd.vv v8, v8, v16
1331; RV32-NEXT:    addi sp, sp, 16
1332; RV32-NEXT:    .cfi_def_cfa_offset 0
1333; RV32-NEXT:    ret
1334;
1335; RV64-LABEL: vsadd_vx_v16i64_unmasked:
1336; RV64:       # %bb.0:
1337; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1338; RV64-NEXT:    vsadd.vx v8, v8, a0
1339; RV64-NEXT:    ret
1340  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1341  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1342  %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1343  ret <16 x i64> %v
1344}
1345
1346define <16 x i64> @vsadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1347; CHECK-LABEL: vsadd_vi_v16i64:
1348; CHECK:       # %bb.0:
1349; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1350; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1351; CHECK-NEXT:    ret
1352  %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
1353  ret <16 x i64> %v
1354}
1355
1356define <16 x i64> @vsadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1357; CHECK-LABEL: vsadd_vi_v16i64_unmasked:
1358; CHECK:       # %bb.0:
1359; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1360; CHECK-NEXT:    vsadd.vi v8, v8, -1
1361; CHECK-NEXT:    ret
1362  %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
1363  ret <16 x i64> %v
1364}
1365
1366; Test that split-legalization works as expected.
1367
1368declare <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
1369
1370define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
1371; CHECK-LABEL: vsadd_vx_v32i64:
1372; CHECK:       # %bb.0:
1373; CHECK-NEXT:    li a2, 16
1374; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1375; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1376; CHECK-NEXT:    mv a1, a0
1377; CHECK-NEXT:    bltu a0, a2, .LBB108_2
1378; CHECK-NEXT:  # %bb.1:
1379; CHECK-NEXT:    li a1, 16
1380; CHECK-NEXT:  .LBB108_2:
1381; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1382; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1383; CHECK-NEXT:    addi a1, a0, -16
1384; CHECK-NEXT:    sltu a0, a0, a1
1385; CHECK-NEXT:    addi a0, a0, -1
1386; CHECK-NEXT:    and a0, a0, a1
1387; CHECK-NEXT:    vmv1r.v v0, v24
1388; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1389; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t
1390; CHECK-NEXT:    ret
1391  %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
1392  ret <32 x i64> %v
1393}
1394
1395define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
1396; CHECK-LABEL: vsadd_vi_v32i64_unmasked:
1397; CHECK:       # %bb.0:
1398; CHECK-NEXT:    li a2, 16
1399; CHECK-NEXT:    mv a1, a0
1400; CHECK-NEXT:    bltu a0, a2, .LBB109_2
1401; CHECK-NEXT:  # %bb.1:
1402; CHECK-NEXT:    li a1, 16
1403; CHECK-NEXT:  .LBB109_2:
1404; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1405; CHECK-NEXT:    vsadd.vi v8, v8, -1
1406; CHECK-NEXT:    addi a1, a0, -16
1407; CHECK-NEXT:    sltu a0, a0, a1
1408; CHECK-NEXT:    addi a0, a0, -1
1409; CHECK-NEXT:    and a0, a0, a1
1410; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1411; CHECK-NEXT:    vsadd.vi v16, v16, -1
1412; CHECK-NEXT:    ret
1413  %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
1414  ret <32 x i64> %v
1415}
1416
1417define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
1418; CHECK-LABEL: vsadd_vx_v32i64_evl12:
1419; CHECK:       # %bb.0:
1420; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1421; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1422; CHECK-NEXT:    vsetivli zero, 12, e64, m8, ta, ma
1423; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1424; CHECK-NEXT:    vmv1r.v v0, v24
1425; CHECK-NEXT:    vsetivli zero, 0, e64, m8, ta, ma
1426; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t
1427; CHECK-NEXT:    ret
1428  %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
1429  ret <32 x i64> %v
1430}
1431
1432define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
1433; CHECK-LABEL: vsadd_vx_v32i64_evl27:
1434; CHECK:       # %bb.0:
1435; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1436; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1437; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1438; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t
1439; CHECK-NEXT:    vmv1r.v v0, v24
1440; CHECK-NEXT:    vsetivli zero, 11, e64, m8, ta, ma
1441; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t
1442; CHECK-NEXT:    ret
1443  %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
1444  ret <32 x i64> %v
1445}
1446