xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
6
7declare <1 x i8> @llvm.fshr.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
8declare <1 x i8> @llvm.fshl.v1i8(<1 x i8>, <1 x i8>, <1 x i8>)
9
10define <1 x i8> @vror_vv_v1i8(<1 x i8> %a, <1 x i8> %b) {
11; CHECK-LABEL: vror_vv_v1i8:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
14; CHECK-NEXT:    vand.vi v10, v9, 7
15; CHECK-NEXT:    vrsub.vi v9, v9, 0
16; CHECK-NEXT:    vsrl.vv v10, v8, v10
17; CHECK-NEXT:    vand.vi v9, v9, 7
18; CHECK-NEXT:    vsll.vv v8, v8, v9
19; CHECK-NEXT:    vor.vv v8, v10, v8
20; CHECK-NEXT:    ret
21;
22; CHECK-ZVKB-LABEL: vror_vv_v1i8:
23; CHECK-ZVKB:       # %bb.0:
24; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
25; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
26; CHECK-ZVKB-NEXT:    ret
27  %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b)
28  ret <1 x i8> %x
29}
30
31define <1 x i8> @vror_vx_v1i8(<1 x i8> %a, i8 %b) {
32; CHECK-LABEL: vror_vx_v1i8:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
35; CHECK-NEXT:    vmv.s.x v9, a0
36; CHECK-NEXT:    vand.vi v10, v9, 7
37; CHECK-NEXT:    vrsub.vi v9, v9, 0
38; CHECK-NEXT:    vsrl.vv v10, v8, v10
39; CHECK-NEXT:    vand.vi v9, v9, 7
40; CHECK-NEXT:    vsll.vv v8, v8, v9
41; CHECK-NEXT:    vor.vv v8, v10, v8
42; CHECK-NEXT:    ret
43;
44; CHECK-ZVKB-LABEL: vror_vx_v1i8:
45; CHECK-ZVKB:       # %bb.0:
46; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
47; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
48; CHECK-ZVKB-NEXT:    ret
49  %b.head = insertelement <1 x i8> poison, i8 %b, i32 0
50  %b.splat = shufflevector <1 x i8> %b.head, <1 x i8> poison, <1 x i32> zeroinitializer
51  %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> %b.splat)
52  ret <1 x i8> %x
53}
54
55define <1 x i8> @vror_vi_v1i8(<1 x i8> %a) {
56; CHECK-LABEL: vror_vi_v1i8:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
59; CHECK-NEXT:    vsll.vi v9, v8, 7
60; CHECK-NEXT:    vsrl.vi v8, v8, 1
61; CHECK-NEXT:    vor.vv v8, v8, v9
62; CHECK-NEXT:    ret
63;
64; CHECK-ZVKB-LABEL: vror_vi_v1i8:
65; CHECK-ZVKB:       # %bb.0:
66; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
67; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
68; CHECK-ZVKB-NEXT:    ret
69  %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> splat (i8 1))
70  ret <1 x i8> %x
71}
72
73define <1 x i8> @vror_vi_rotl_v1i8(<1 x i8> %a) {
74; CHECK-LABEL: vror_vi_rotl_v1i8:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
77; CHECK-NEXT:    vsrl.vi v9, v8, 7
78; CHECK-NEXT:    vadd.vv v8, v8, v8
79; CHECK-NEXT:    vor.vv v8, v8, v9
80; CHECK-NEXT:    ret
81;
82; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i8:
83; CHECK-ZVKB:       # %bb.0:
84; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
85; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
86; CHECK-ZVKB-NEXT:    ret
87  %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> splat (i8 1))
88  ret <1 x i8> %x
89}
90
91declare <2 x i8> @llvm.fshr.v2i8(<2 x i8>, <2 x i8>, <2 x i8>)
92declare <2 x i8> @llvm.fshl.v2i8(<2 x i8>, <2 x i8>, <2 x i8>)
93
94define <2 x i8> @vror_vv_v2i8(<2 x i8> %a, <2 x i8> %b) {
95; CHECK-LABEL: vror_vv_v2i8:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
98; CHECK-NEXT:    vand.vi v10, v9, 7
99; CHECK-NEXT:    vrsub.vi v9, v9, 0
100; CHECK-NEXT:    vsrl.vv v10, v8, v10
101; CHECK-NEXT:    vand.vi v9, v9, 7
102; CHECK-NEXT:    vsll.vv v8, v8, v9
103; CHECK-NEXT:    vor.vv v8, v10, v8
104; CHECK-NEXT:    ret
105;
106; CHECK-ZVKB-LABEL: vror_vv_v2i8:
107; CHECK-ZVKB:       # %bb.0:
108; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
109; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
110; CHECK-ZVKB-NEXT:    ret
111  %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b)
112  ret <2 x i8> %x
113}
114
115define <2 x i8> @vror_vx_v2i8(<2 x i8> %a, i8 %b) {
116; CHECK-LABEL: vror_vx_v2i8:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
119; CHECK-NEXT:    vmv.v.x v9, a0
120; CHECK-NEXT:    vand.vi v10, v9, 7
121; CHECK-NEXT:    vrsub.vi v9, v9, 0
122; CHECK-NEXT:    vsrl.vv v10, v8, v10
123; CHECK-NEXT:    vand.vi v9, v9, 7
124; CHECK-NEXT:    vsll.vv v8, v8, v9
125; CHECK-NEXT:    vor.vv v8, v10, v8
126; CHECK-NEXT:    ret
127;
128; CHECK-ZVKB-LABEL: vror_vx_v2i8:
129; CHECK-ZVKB:       # %bb.0:
130; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
131; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
132; CHECK-ZVKB-NEXT:    ret
133  %b.head = insertelement <2 x i8> poison, i8 %b, i32 0
134  %b.splat = shufflevector <2 x i8> %b.head, <2 x i8> poison, <2 x i32> zeroinitializer
135  %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> %b.splat)
136  ret <2 x i8> %x
137}
138
139define <2 x i8> @vror_vi_v2i8(<2 x i8> %a) {
140; CHECK-LABEL: vror_vi_v2i8:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
143; CHECK-NEXT:    vsll.vi v9, v8, 7
144; CHECK-NEXT:    vsrl.vi v8, v8, 1
145; CHECK-NEXT:    vor.vv v8, v8, v9
146; CHECK-NEXT:    ret
147;
148; CHECK-ZVKB-LABEL: vror_vi_v2i8:
149; CHECK-ZVKB:       # %bb.0:
150; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
151; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
152; CHECK-ZVKB-NEXT:    ret
153  %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> splat (i8 1))
154  ret <2 x i8> %x
155}
156
157define <2 x i8> @vror_vi_rotl_v2i8(<2 x i8> %a) {
158; CHECK-LABEL: vror_vi_rotl_v2i8:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
161; CHECK-NEXT:    vsrl.vi v9, v8, 7
162; CHECK-NEXT:    vadd.vv v8, v8, v8
163; CHECK-NEXT:    vor.vv v8, v8, v9
164; CHECK-NEXT:    ret
165;
166; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i8:
167; CHECK-ZVKB:       # %bb.0:
168; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
169; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
170; CHECK-ZVKB-NEXT:    ret
171  %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> splat (i8 1))
172  ret <2 x i8> %x
173}
174
175declare <4 x i8> @llvm.fshr.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
176declare <4 x i8> @llvm.fshl.v4i8(<4 x i8>, <4 x i8>, <4 x i8>)
177
178define <4 x i8> @vror_vv_v4i8(<4 x i8> %a, <4 x i8> %b) {
179; CHECK-LABEL: vror_vv_v4i8:
180; CHECK:       # %bb.0:
181; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
182; CHECK-NEXT:    vand.vi v10, v9, 7
183; CHECK-NEXT:    vrsub.vi v9, v9, 0
184; CHECK-NEXT:    vsrl.vv v10, v8, v10
185; CHECK-NEXT:    vand.vi v9, v9, 7
186; CHECK-NEXT:    vsll.vv v8, v8, v9
187; CHECK-NEXT:    vor.vv v8, v10, v8
188; CHECK-NEXT:    ret
189;
190; CHECK-ZVKB-LABEL: vror_vv_v4i8:
191; CHECK-ZVKB:       # %bb.0:
192; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
193; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
194; CHECK-ZVKB-NEXT:    ret
195  %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b)
196  ret <4 x i8> %x
197}
198
199define <4 x i8> @vror_vx_v4i8(<4 x i8> %a, i8 %b) {
200; CHECK-LABEL: vror_vx_v4i8:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
203; CHECK-NEXT:    vmv.v.x v9, a0
204; CHECK-NEXT:    vand.vi v10, v9, 7
205; CHECK-NEXT:    vrsub.vi v9, v9, 0
206; CHECK-NEXT:    vsrl.vv v10, v8, v10
207; CHECK-NEXT:    vand.vi v9, v9, 7
208; CHECK-NEXT:    vsll.vv v8, v8, v9
209; CHECK-NEXT:    vor.vv v8, v10, v8
210; CHECK-NEXT:    ret
211;
212; CHECK-ZVKB-LABEL: vror_vx_v4i8:
213; CHECK-ZVKB:       # %bb.0:
214; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
215; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
216; CHECK-ZVKB-NEXT:    ret
217  %b.head = insertelement <4 x i8> poison, i8 %b, i32 0
218  %b.splat = shufflevector <4 x i8> %b.head, <4 x i8> poison, <4 x i32> zeroinitializer
219  %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> %b.splat)
220  ret <4 x i8> %x
221}
222
223define <4 x i8> @vror_vi_v4i8(<4 x i8> %a) {
224; CHECK-LABEL: vror_vi_v4i8:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
227; CHECK-NEXT:    vsll.vi v9, v8, 7
228; CHECK-NEXT:    vsrl.vi v8, v8, 1
229; CHECK-NEXT:    vor.vv v8, v8, v9
230; CHECK-NEXT:    ret
231;
232; CHECK-ZVKB-LABEL: vror_vi_v4i8:
233; CHECK-ZVKB:       # %bb.0:
234; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
235; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
236; CHECK-ZVKB-NEXT:    ret
237  %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> splat (i8 1))
238  ret <4 x i8> %x
239}
240
241define <4 x i8> @vror_vi_rotl_v4i8(<4 x i8> %a) {
242; CHECK-LABEL: vror_vi_rotl_v4i8:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
245; CHECK-NEXT:    vsrl.vi v9, v8, 7
246; CHECK-NEXT:    vadd.vv v8, v8, v8
247; CHECK-NEXT:    vor.vv v8, v8, v9
248; CHECK-NEXT:    ret
249;
250; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i8:
251; CHECK-ZVKB:       # %bb.0:
252; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
253; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
254; CHECK-ZVKB-NEXT:    ret
255  %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> splat (i8 1))
256  ret <4 x i8> %x
257}
258
259declare <8 x i8> @llvm.fshr.v8i8(<8 x i8>, <8 x i8>, <8 x i8>)
260declare <8 x i8> @llvm.fshl.v8i8(<8 x i8>, <8 x i8>, <8 x i8>)
261
262define <8 x i8> @vror_vv_v8i8(<8 x i8> %a, <8 x i8> %b) {
263; CHECK-LABEL: vror_vv_v8i8:
264; CHECK:       # %bb.0:
265; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
266; CHECK-NEXT:    vand.vi v10, v9, 7
267; CHECK-NEXT:    vrsub.vi v9, v9, 0
268; CHECK-NEXT:    vsrl.vv v10, v8, v10
269; CHECK-NEXT:    vand.vi v9, v9, 7
270; CHECK-NEXT:    vsll.vv v8, v8, v9
271; CHECK-NEXT:    vor.vv v8, v10, v8
272; CHECK-NEXT:    ret
273;
274; CHECK-ZVKB-LABEL: vror_vv_v8i8:
275; CHECK-ZVKB:       # %bb.0:
276; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
277; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
278; CHECK-ZVKB-NEXT:    ret
279  %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b)
280  ret <8 x i8> %x
281}
282
283define <8 x i8> @vror_vx_v8i8(<8 x i8> %a, i8 %b) {
284; CHECK-LABEL: vror_vx_v8i8:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
287; CHECK-NEXT:    vmv.v.x v9, a0
288; CHECK-NEXT:    vand.vi v10, v9, 7
289; CHECK-NEXT:    vrsub.vi v9, v9, 0
290; CHECK-NEXT:    vsrl.vv v10, v8, v10
291; CHECK-NEXT:    vand.vi v9, v9, 7
292; CHECK-NEXT:    vsll.vv v8, v8, v9
293; CHECK-NEXT:    vor.vv v8, v10, v8
294; CHECK-NEXT:    ret
295;
296; CHECK-ZVKB-LABEL: vror_vx_v8i8:
297; CHECK-ZVKB:       # %bb.0:
298; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
299; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
300; CHECK-ZVKB-NEXT:    ret
301  %b.head = insertelement <8 x i8> poison, i8 %b, i32 0
302  %b.splat = shufflevector <8 x i8> %b.head, <8 x i8> poison, <8 x i32> zeroinitializer
303  %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> %b.splat)
304  ret <8 x i8> %x
305}
306
307define <8 x i8> @vror_vi_v8i8(<8 x i8> %a) {
308; CHECK-LABEL: vror_vi_v8i8:
309; CHECK:       # %bb.0:
310; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
311; CHECK-NEXT:    vsll.vi v9, v8, 7
312; CHECK-NEXT:    vsrl.vi v8, v8, 1
313; CHECK-NEXT:    vor.vv v8, v8, v9
314; CHECK-NEXT:    ret
315;
316; CHECK-ZVKB-LABEL: vror_vi_v8i8:
317; CHECK-ZVKB:       # %bb.0:
318; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
319; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
320; CHECK-ZVKB-NEXT:    ret
321  %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> splat (i8 1))
322  ret <8 x i8> %x
323}
324
325define <8 x i8> @vror_vi_rotl_v8i8(<8 x i8> %a) {
326; CHECK-LABEL: vror_vi_rotl_v8i8:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
329; CHECK-NEXT:    vsrl.vi v9, v8, 7
330; CHECK-NEXT:    vadd.vv v8, v8, v8
331; CHECK-NEXT:    vor.vv v8, v8, v9
332; CHECK-NEXT:    ret
333;
334; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i8:
335; CHECK-ZVKB:       # %bb.0:
336; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
337; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
338; CHECK-ZVKB-NEXT:    ret
339  %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> splat (i8 1))
340  ret <8 x i8> %x
341}
342
343declare <16 x i8> @llvm.fshr.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
344declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
345
346define <16 x i8> @vror_vv_v16i8(<16 x i8> %a, <16 x i8> %b) {
347; CHECK-LABEL: vror_vv_v16i8:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
350; CHECK-NEXT:    vand.vi v10, v9, 7
351; CHECK-NEXT:    vrsub.vi v9, v9, 0
352; CHECK-NEXT:    vsrl.vv v10, v8, v10
353; CHECK-NEXT:    vand.vi v9, v9, 7
354; CHECK-NEXT:    vsll.vv v8, v8, v9
355; CHECK-NEXT:    vor.vv v8, v10, v8
356; CHECK-NEXT:    ret
357;
358; CHECK-ZVKB-LABEL: vror_vv_v16i8:
359; CHECK-ZVKB:       # %bb.0:
360; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
361; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
362; CHECK-ZVKB-NEXT:    ret
363  %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b)
364  ret <16 x i8> %x
365}
366
367define <16 x i8> @vror_vx_v16i8(<16 x i8> %a, i8 %b) {
368; CHECK-LABEL: vror_vx_v16i8:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
371; CHECK-NEXT:    vmv.v.x v9, a0
372; CHECK-NEXT:    vand.vi v10, v9, 7
373; CHECK-NEXT:    vrsub.vi v9, v9, 0
374; CHECK-NEXT:    vsrl.vv v10, v8, v10
375; CHECK-NEXT:    vand.vi v9, v9, 7
376; CHECK-NEXT:    vsll.vv v8, v8, v9
377; CHECK-NEXT:    vor.vv v8, v10, v8
378; CHECK-NEXT:    ret
379;
380; CHECK-ZVKB-LABEL: vror_vx_v16i8:
381; CHECK-ZVKB:       # %bb.0:
382; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
383; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
384; CHECK-ZVKB-NEXT:    ret
385  %b.head = insertelement <16 x i8> poison, i8 %b, i32 0
386  %b.splat = shufflevector <16 x i8> %b.head, <16 x i8> poison, <16 x i32> zeroinitializer
387  %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> %b.splat)
388  ret <16 x i8> %x
389}
390
391define <16 x i8> @vror_vi_v16i8(<16 x i8> %a) {
392; CHECK-LABEL: vror_vi_v16i8:
393; CHECK:       # %bb.0:
394; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
395; CHECK-NEXT:    vsll.vi v9, v8, 7
396; CHECK-NEXT:    vsrl.vi v8, v8, 1
397; CHECK-NEXT:    vor.vv v8, v8, v9
398; CHECK-NEXT:    ret
399;
400; CHECK-ZVKB-LABEL: vror_vi_v16i8:
401; CHECK-ZVKB:       # %bb.0:
402; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
403; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
404; CHECK-ZVKB-NEXT:    ret
405  %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 1))
406  ret <16 x i8> %x
407}
408
409define <16 x i8> @vror_vi_rotl_v16i8(<16 x i8> %a) {
410; CHECK-LABEL: vror_vi_rotl_v16i8:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
413; CHECK-NEXT:    vsrl.vi v9, v8, 7
414; CHECK-NEXT:    vadd.vv v8, v8, v8
415; CHECK-NEXT:    vor.vv v8, v8, v9
416; CHECK-NEXT:    ret
417;
418; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i8:
419; CHECK-ZVKB:       # %bb.0:
420; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
421; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
422; CHECK-ZVKB-NEXT:    ret
423  %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 1))
424  ret <16 x i8> %x
425}
426
427declare <32 x i8> @llvm.fshr.v32i8(<32 x i8>, <32 x i8>, <32 x i8>)
428declare <32 x i8> @llvm.fshl.v32i8(<32 x i8>, <32 x i8>, <32 x i8>)
429
430define <32 x i8> @vror_vv_v32i8(<32 x i8> %a, <32 x i8> %b) {
431; CHECK-LABEL: vror_vv_v32i8:
432; CHECK:       # %bb.0:
433; CHECK-NEXT:    li a0, 32
434; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
435; CHECK-NEXT:    vand.vi v12, v10, 7
436; CHECK-NEXT:    vrsub.vi v10, v10, 0
437; CHECK-NEXT:    vsrl.vv v12, v8, v12
438; CHECK-NEXT:    vand.vi v10, v10, 7
439; CHECK-NEXT:    vsll.vv v8, v8, v10
440; CHECK-NEXT:    vor.vv v8, v12, v8
441; CHECK-NEXT:    ret
442;
443; CHECK-ZVKB-LABEL: vror_vv_v32i8:
444; CHECK-ZVKB:       # %bb.0:
445; CHECK-ZVKB-NEXT:    li a0, 32
446; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
447; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
448; CHECK-ZVKB-NEXT:    ret
449  %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b)
450  ret <32 x i8> %x
451}
452
453define <32 x i8> @vror_vx_v32i8(<32 x i8> %a, i8 %b) {
454; CHECK-LABEL: vror_vx_v32i8:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    li a1, 32
457; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
458; CHECK-NEXT:    vmv.v.x v10, a0
459; CHECK-NEXT:    vand.vi v12, v10, 7
460; CHECK-NEXT:    vrsub.vi v10, v10, 0
461; CHECK-NEXT:    vsrl.vv v12, v8, v12
462; CHECK-NEXT:    vand.vi v10, v10, 7
463; CHECK-NEXT:    vsll.vv v8, v8, v10
464; CHECK-NEXT:    vor.vv v8, v12, v8
465; CHECK-NEXT:    ret
466;
467; CHECK-ZVKB-LABEL: vror_vx_v32i8:
468; CHECK-ZVKB:       # %bb.0:
469; CHECK-ZVKB-NEXT:    li a1, 32
470; CHECK-ZVKB-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
471; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
472; CHECK-ZVKB-NEXT:    ret
473  %b.head = insertelement <32 x i8> poison, i8 %b, i32 0
474  %b.splat = shufflevector <32 x i8> %b.head, <32 x i8> poison, <32 x i32> zeroinitializer
475  %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> %b.splat)
476  ret <32 x i8> %x
477}
478
479define <32 x i8> @vror_vi_v32i8(<32 x i8> %a) {
480; CHECK-LABEL: vror_vi_v32i8:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    li a0, 32
483; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
484; CHECK-NEXT:    vsll.vi v10, v8, 7
485; CHECK-NEXT:    vsrl.vi v8, v8, 1
486; CHECK-NEXT:    vor.vv v8, v8, v10
487; CHECK-NEXT:    ret
488;
489; CHECK-ZVKB-LABEL: vror_vi_v32i8:
490; CHECK-ZVKB:       # %bb.0:
491; CHECK-ZVKB-NEXT:    li a0, 32
492; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
493; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
494; CHECK-ZVKB-NEXT:    ret
495  %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> splat (i8 1))
496  ret <32 x i8> %x
497}
498
499define <32 x i8> @vror_vi_rotl_v32i8(<32 x i8> %a) {
500; CHECK-LABEL: vror_vi_rotl_v32i8:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    li a0, 32
503; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
504; CHECK-NEXT:    vsrl.vi v10, v8, 7
505; CHECK-NEXT:    vadd.vv v8, v8, v8
506; CHECK-NEXT:    vor.vv v8, v8, v10
507; CHECK-NEXT:    ret
508;
509; CHECK-ZVKB-LABEL: vror_vi_rotl_v32i8:
510; CHECK-ZVKB:       # %bb.0:
511; CHECK-ZVKB-NEXT:    li a0, 32
512; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
513; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
514; CHECK-ZVKB-NEXT:    ret
515  %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> splat (i8 1))
516  ret <32 x i8> %x
517}
518
519declare <64 x i8> @llvm.fshr.v64i8(<64 x i8>, <64 x i8>, <64 x i8>)
520declare <64 x i8> @llvm.fshl.v64i8(<64 x i8>, <64 x i8>, <64 x i8>)
521
522define <64 x i8> @vror_vv_v64i8(<64 x i8> %a, <64 x i8> %b) {
523; CHECK-LABEL: vror_vv_v64i8:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    li a0, 64
526; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
527; CHECK-NEXT:    vand.vi v16, v12, 7
528; CHECK-NEXT:    vrsub.vi v12, v12, 0
529; CHECK-NEXT:    vsrl.vv v16, v8, v16
530; CHECK-NEXT:    vand.vi v12, v12, 7
531; CHECK-NEXT:    vsll.vv v8, v8, v12
532; CHECK-NEXT:    vor.vv v8, v16, v8
533; CHECK-NEXT:    ret
534;
535; CHECK-ZVKB-LABEL: vror_vv_v64i8:
536; CHECK-ZVKB:       # %bb.0:
537; CHECK-ZVKB-NEXT:    li a0, 64
538; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
539; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
540; CHECK-ZVKB-NEXT:    ret
541  %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b)
542  ret <64 x i8> %x
543}
544
545define <64 x i8> @vror_vx_v64i8(<64 x i8> %a, i8 %b) {
546; CHECK-LABEL: vror_vx_v64i8:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    li a1, 64
549; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
550; CHECK-NEXT:    vmv.v.x v12, a0
551; CHECK-NEXT:    vand.vi v16, v12, 7
552; CHECK-NEXT:    vrsub.vi v12, v12, 0
553; CHECK-NEXT:    vsrl.vv v16, v8, v16
554; CHECK-NEXT:    vand.vi v12, v12, 7
555; CHECK-NEXT:    vsll.vv v8, v8, v12
556; CHECK-NEXT:    vor.vv v8, v16, v8
557; CHECK-NEXT:    ret
558;
559; CHECK-ZVKB-LABEL: vror_vx_v64i8:
560; CHECK-ZVKB:       # %bb.0:
561; CHECK-ZVKB-NEXT:    li a1, 64
562; CHECK-ZVKB-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
563; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
564; CHECK-ZVKB-NEXT:    ret
565  %b.head = insertelement <64 x i8> poison, i8 %b, i32 0
566  %b.splat = shufflevector <64 x i8> %b.head, <64 x i8> poison, <64 x i32> zeroinitializer
567  %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> %b.splat)
568  ret <64 x i8> %x
569}
570
571define <64 x i8> @vror_vi_v64i8(<64 x i8> %a) {
572; CHECK-LABEL: vror_vi_v64i8:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    li a0, 64
575; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
576; CHECK-NEXT:    vsll.vi v12, v8, 7
577; CHECK-NEXT:    vsrl.vi v8, v8, 1
578; CHECK-NEXT:    vor.vv v8, v8, v12
579; CHECK-NEXT:    ret
580;
581; CHECK-ZVKB-LABEL: vror_vi_v64i8:
582; CHECK-ZVKB:       # %bb.0:
583; CHECK-ZVKB-NEXT:    li a0, 64
584; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
585; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
586; CHECK-ZVKB-NEXT:    ret
587  %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> splat (i8 1))
588  ret <64 x i8> %x
589}
590
591define <64 x i8> @vror_vi_rotl_v64i8(<64 x i8> %a) {
592; CHECK-LABEL: vror_vi_rotl_v64i8:
593; CHECK:       # %bb.0:
594; CHECK-NEXT:    li a0, 64
595; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
596; CHECK-NEXT:    vsrl.vi v12, v8, 7
597; CHECK-NEXT:    vadd.vv v8, v8, v8
598; CHECK-NEXT:    vor.vv v8, v8, v12
599; CHECK-NEXT:    ret
600;
601; CHECK-ZVKB-LABEL: vror_vi_rotl_v64i8:
602; CHECK-ZVKB:       # %bb.0:
603; CHECK-ZVKB-NEXT:    li a0, 64
604; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
605; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 7
606; CHECK-ZVKB-NEXT:    ret
607  %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> splat (i8 1))
608  ret <64 x i8> %x
609}
610
611declare <1 x i16> @llvm.fshr.v1i16(<1 x i16>, <1 x i16>, <1 x i16>)
612declare <1 x i16> @llvm.fshl.v1i16(<1 x i16>, <1 x i16>, <1 x i16>)
613
614define <1 x i16> @vror_vv_v1i16(<1 x i16> %a, <1 x i16> %b) {
615; CHECK-LABEL: vror_vv_v1i16:
616; CHECK:       # %bb.0:
617; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
618; CHECK-NEXT:    vand.vi v10, v9, 15
619; CHECK-NEXT:    vrsub.vi v9, v9, 0
620; CHECK-NEXT:    vsrl.vv v10, v8, v10
621; CHECK-NEXT:    vand.vi v9, v9, 15
622; CHECK-NEXT:    vsll.vv v8, v8, v9
623; CHECK-NEXT:    vor.vv v8, v10, v8
624; CHECK-NEXT:    ret
625;
626; CHECK-ZVKB-LABEL: vror_vv_v1i16:
627; CHECK-ZVKB:       # %bb.0:
628; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
629; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
630; CHECK-ZVKB-NEXT:    ret
631  %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b)
632  ret <1 x i16> %x
633}
634
635define <1 x i16> @vror_vx_v1i16(<1 x i16> %a, i16 %b) {
636; CHECK-LABEL: vror_vx_v1i16:
637; CHECK:       # %bb.0:
638; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
639; CHECK-NEXT:    vmv.s.x v9, a0
640; CHECK-NEXT:    vand.vi v10, v9, 15
641; CHECK-NEXT:    vrsub.vi v9, v9, 0
642; CHECK-NEXT:    vsrl.vv v10, v8, v10
643; CHECK-NEXT:    vand.vi v9, v9, 15
644; CHECK-NEXT:    vsll.vv v8, v8, v9
645; CHECK-NEXT:    vor.vv v8, v10, v8
646; CHECK-NEXT:    ret
647;
648; CHECK-ZVKB-LABEL: vror_vx_v1i16:
649; CHECK-ZVKB:       # %bb.0:
650; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
651; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
652; CHECK-ZVKB-NEXT:    ret
653  %b.head = insertelement <1 x i16> poison, i16 %b, i32 0
654  %b.splat = shufflevector <1 x i16> %b.head, <1 x i16> poison, <1 x i32> zeroinitializer
655  %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> %b.splat)
656  ret <1 x i16> %x
657}
658
659define <1 x i16> @vror_vi_v1i16(<1 x i16> %a) {
660; CHECK-LABEL: vror_vi_v1i16:
661; CHECK:       # %bb.0:
662; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
663; CHECK-NEXT:    vsll.vi v9, v8, 15
664; CHECK-NEXT:    vsrl.vi v8, v8, 1
665; CHECK-NEXT:    vor.vv v8, v8, v9
666; CHECK-NEXT:    ret
667;
668; CHECK-ZVKB-LABEL: vror_vi_v1i16:
669; CHECK-ZVKB:       # %bb.0:
670; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
671; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
672; CHECK-ZVKB-NEXT:    ret
673  %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> splat (i16 1))
674  ret <1 x i16> %x
675}
676
677define <1 x i16> @vror_vi_rotl_v1i16(<1 x i16> %a) {
678; CHECK-LABEL: vror_vi_rotl_v1i16:
679; CHECK:       # %bb.0:
680; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
681; CHECK-NEXT:    vsrl.vi v9, v8, 15
682; CHECK-NEXT:    vadd.vv v8, v8, v8
683; CHECK-NEXT:    vor.vv v8, v8, v9
684; CHECK-NEXT:    ret
685;
686; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i16:
687; CHECK-ZVKB:       # %bb.0:
688; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
689; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
690; CHECK-ZVKB-NEXT:    ret
691  %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> splat (i16 1))
692  ret <1 x i16> %x
693}
694
695declare <2 x i16> @llvm.fshr.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
696declare <2 x i16> @llvm.fshl.v2i16(<2 x i16>, <2 x i16>, <2 x i16>)
697
698define <2 x i16> @vror_vv_v2i16(<2 x i16> %a, <2 x i16> %b) {
699; CHECK-LABEL: vror_vv_v2i16:
700; CHECK:       # %bb.0:
701; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
702; CHECK-NEXT:    vand.vi v10, v9, 15
703; CHECK-NEXT:    vrsub.vi v9, v9, 0
704; CHECK-NEXT:    vsrl.vv v10, v8, v10
705; CHECK-NEXT:    vand.vi v9, v9, 15
706; CHECK-NEXT:    vsll.vv v8, v8, v9
707; CHECK-NEXT:    vor.vv v8, v10, v8
708; CHECK-NEXT:    ret
709;
710; CHECK-ZVKB-LABEL: vror_vv_v2i16:
711; CHECK-ZVKB:       # %bb.0:
712; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
713; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
714; CHECK-ZVKB-NEXT:    ret
715  %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b)
716  ret <2 x i16> %x
717}
718
719define <2 x i16> @vror_vx_v2i16(<2 x i16> %a, i16 %b) {
720; CHECK-LABEL: vror_vx_v2i16:
721; CHECK:       # %bb.0:
722; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
723; CHECK-NEXT:    vmv.v.x v9, a0
724; CHECK-NEXT:    vand.vi v10, v9, 15
725; CHECK-NEXT:    vrsub.vi v9, v9, 0
726; CHECK-NEXT:    vsrl.vv v10, v8, v10
727; CHECK-NEXT:    vand.vi v9, v9, 15
728; CHECK-NEXT:    vsll.vv v8, v8, v9
729; CHECK-NEXT:    vor.vv v8, v10, v8
730; CHECK-NEXT:    ret
731;
732; CHECK-ZVKB-LABEL: vror_vx_v2i16:
733; CHECK-ZVKB:       # %bb.0:
734; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
735; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
736; CHECK-ZVKB-NEXT:    ret
737  %b.head = insertelement <2 x i16> poison, i16 %b, i32 0
738  %b.splat = shufflevector <2 x i16> %b.head, <2 x i16> poison, <2 x i32> zeroinitializer
739  %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> %b.splat)
740  ret <2 x i16> %x
741}
742
743define <2 x i16> @vror_vi_v2i16(<2 x i16> %a) {
744; CHECK-LABEL: vror_vi_v2i16:
745; CHECK:       # %bb.0:
746; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
747; CHECK-NEXT:    vsll.vi v9, v8, 15
748; CHECK-NEXT:    vsrl.vi v8, v8, 1
749; CHECK-NEXT:    vor.vv v8, v8, v9
750; CHECK-NEXT:    ret
751;
752; CHECK-ZVKB-LABEL: vror_vi_v2i16:
753; CHECK-ZVKB:       # %bb.0:
754; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
755; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
756; CHECK-ZVKB-NEXT:    ret
757  %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> splat (i16 1))
758  ret <2 x i16> %x
759}
760
761define <2 x i16> @vror_vi_rotl_v2i16(<2 x i16> %a) {
762; CHECK-LABEL: vror_vi_rotl_v2i16:
763; CHECK:       # %bb.0:
764; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
765; CHECK-NEXT:    vsrl.vi v9, v8, 15
766; CHECK-NEXT:    vadd.vv v8, v8, v8
767; CHECK-NEXT:    vor.vv v8, v8, v9
768; CHECK-NEXT:    ret
769;
770; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i16:
771; CHECK-ZVKB:       # %bb.0:
772; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
773; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
774; CHECK-ZVKB-NEXT:    ret
775  %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> splat (i16 1))
776  ret <2 x i16> %x
777}
778
779declare <4 x i16> @llvm.fshr.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
780declare <4 x i16> @llvm.fshl.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
781
782define <4 x i16> @vror_vv_v4i16(<4 x i16> %a, <4 x i16> %b) {
783; CHECK-LABEL: vror_vv_v4i16:
784; CHECK:       # %bb.0:
785; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
786; CHECK-NEXT:    vand.vi v10, v9, 15
787; CHECK-NEXT:    vrsub.vi v9, v9, 0
788; CHECK-NEXT:    vsrl.vv v10, v8, v10
789; CHECK-NEXT:    vand.vi v9, v9, 15
790; CHECK-NEXT:    vsll.vv v8, v8, v9
791; CHECK-NEXT:    vor.vv v8, v10, v8
792; CHECK-NEXT:    ret
793;
794; CHECK-ZVKB-LABEL: vror_vv_v4i16:
795; CHECK-ZVKB:       # %bb.0:
796; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
797; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
798; CHECK-ZVKB-NEXT:    ret
799  %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b)
800  ret <4 x i16> %x
801}
802
803define <4 x i16> @vror_vx_v4i16(<4 x i16> %a, i16 %b) {
804; CHECK-LABEL: vror_vx_v4i16:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
807; CHECK-NEXT:    vmv.v.x v9, a0
808; CHECK-NEXT:    vand.vi v10, v9, 15
809; CHECK-NEXT:    vrsub.vi v9, v9, 0
810; CHECK-NEXT:    vsrl.vv v10, v8, v10
811; CHECK-NEXT:    vand.vi v9, v9, 15
812; CHECK-NEXT:    vsll.vv v8, v8, v9
813; CHECK-NEXT:    vor.vv v8, v10, v8
814; CHECK-NEXT:    ret
815;
816; CHECK-ZVKB-LABEL: vror_vx_v4i16:
817; CHECK-ZVKB:       # %bb.0:
818; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
819; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
820; CHECK-ZVKB-NEXT:    ret
821  %b.head = insertelement <4 x i16> poison, i16 %b, i32 0
822  %b.splat = shufflevector <4 x i16> %b.head, <4 x i16> poison, <4 x i32> zeroinitializer
823  %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> %b.splat)
824  ret <4 x i16> %x
825}
826
827define <4 x i16> @vror_vi_v4i16(<4 x i16> %a) {
828; CHECK-LABEL: vror_vi_v4i16:
829; CHECK:       # %bb.0:
830; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
831; CHECK-NEXT:    vsll.vi v9, v8, 15
832; CHECK-NEXT:    vsrl.vi v8, v8, 1
833; CHECK-NEXT:    vor.vv v8, v8, v9
834; CHECK-NEXT:    ret
835;
836; CHECK-ZVKB-LABEL: vror_vi_v4i16:
837; CHECK-ZVKB:       # %bb.0:
838; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
839; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
840; CHECK-ZVKB-NEXT:    ret
841  %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> splat (i16 1))
842  ret <4 x i16> %x
843}
844
845define <4 x i16> @vror_vi_rotl_v4i16(<4 x i16> %a) {
846; CHECK-LABEL: vror_vi_rotl_v4i16:
847; CHECK:       # %bb.0:
848; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
849; CHECK-NEXT:    vsrl.vi v9, v8, 15
850; CHECK-NEXT:    vadd.vv v8, v8, v8
851; CHECK-NEXT:    vor.vv v8, v8, v9
852; CHECK-NEXT:    ret
853;
854; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i16:
855; CHECK-ZVKB:       # %bb.0:
856; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
857; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
858; CHECK-ZVKB-NEXT:    ret
859  %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> splat (i16 1))
860  ret <4 x i16> %x
861}
862
863declare <8 x i16> @llvm.fshr.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
864declare <8 x i16> @llvm.fshl.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
865
866define <8 x i16> @vror_vv_v8i16(<8 x i16> %a, <8 x i16> %b) {
867; CHECK-LABEL: vror_vv_v8i16:
868; CHECK:       # %bb.0:
869; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
870; CHECK-NEXT:    vand.vi v10, v9, 15
871; CHECK-NEXT:    vrsub.vi v9, v9, 0
872; CHECK-NEXT:    vsrl.vv v10, v8, v10
873; CHECK-NEXT:    vand.vi v9, v9, 15
874; CHECK-NEXT:    vsll.vv v8, v8, v9
875; CHECK-NEXT:    vor.vv v8, v10, v8
876; CHECK-NEXT:    ret
877;
878; CHECK-ZVKB-LABEL: vror_vv_v8i16:
879; CHECK-ZVKB:       # %bb.0:
880; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
881; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
882; CHECK-ZVKB-NEXT:    ret
883  %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b)
884  ret <8 x i16> %x
885}
886
887define <8 x i16> @vror_vx_v8i16(<8 x i16> %a, i16 %b) {
888; CHECK-LABEL: vror_vx_v8i16:
889; CHECK:       # %bb.0:
890; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
891; CHECK-NEXT:    vmv.v.x v9, a0
892; CHECK-NEXT:    vand.vi v10, v9, 15
893; CHECK-NEXT:    vrsub.vi v9, v9, 0
894; CHECK-NEXT:    vsrl.vv v10, v8, v10
895; CHECK-NEXT:    vand.vi v9, v9, 15
896; CHECK-NEXT:    vsll.vv v8, v8, v9
897; CHECK-NEXT:    vor.vv v8, v10, v8
898; CHECK-NEXT:    ret
899;
900; CHECK-ZVKB-LABEL: vror_vx_v8i16:
901; CHECK-ZVKB:       # %bb.0:
902; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
903; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
904; CHECK-ZVKB-NEXT:    ret
905  %b.head = insertelement <8 x i16> poison, i16 %b, i32 0
906  %b.splat = shufflevector <8 x i16> %b.head, <8 x i16> poison, <8 x i32> zeroinitializer
907  %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> %b.splat)
908  ret <8 x i16> %x
909}
910
911define <8 x i16> @vror_vi_v8i16(<8 x i16> %a) {
912; CHECK-LABEL: vror_vi_v8i16:
913; CHECK:       # %bb.0:
914; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
915; CHECK-NEXT:    vsll.vi v9, v8, 15
916; CHECK-NEXT:    vsrl.vi v8, v8, 1
917; CHECK-NEXT:    vor.vv v8, v8, v9
918; CHECK-NEXT:    ret
919;
920; CHECK-ZVKB-LABEL: vror_vi_v8i16:
921; CHECK-ZVKB:       # %bb.0:
922; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
923; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
924; CHECK-ZVKB-NEXT:    ret
925  %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 1))
926  ret <8 x i16> %x
927}
928
929define <8 x i16> @vror_vi_rotl_v8i16(<8 x i16> %a) {
930; CHECK-LABEL: vror_vi_rotl_v8i16:
931; CHECK:       # %bb.0:
932; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
933; CHECK-NEXT:    vsrl.vi v9, v8, 15
934; CHECK-NEXT:    vadd.vv v8, v8, v8
935; CHECK-NEXT:    vor.vv v8, v8, v9
936; CHECK-NEXT:    ret
937;
938; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i16:
939; CHECK-ZVKB:       # %bb.0:
940; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
941; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
942; CHECK-ZVKB-NEXT:    ret
943  %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 1))
944  ret <8 x i16> %x
945}
946
947declare <16 x i16> @llvm.fshr.v16i16(<16 x i16>, <16 x i16>, <16 x i16>)
948declare <16 x i16> @llvm.fshl.v16i16(<16 x i16>, <16 x i16>, <16 x i16>)
949
950define <16 x i16> @vror_vv_v16i16(<16 x i16> %a, <16 x i16> %b) {
951; CHECK-LABEL: vror_vv_v16i16:
952; CHECK:       # %bb.0:
953; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
954; CHECK-NEXT:    vand.vi v12, v10, 15
955; CHECK-NEXT:    vrsub.vi v10, v10, 0
956; CHECK-NEXT:    vsrl.vv v12, v8, v12
957; CHECK-NEXT:    vand.vi v10, v10, 15
958; CHECK-NEXT:    vsll.vv v8, v8, v10
959; CHECK-NEXT:    vor.vv v8, v12, v8
960; CHECK-NEXT:    ret
961;
962; CHECK-ZVKB-LABEL: vror_vv_v16i16:
963; CHECK-ZVKB:       # %bb.0:
964; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
965; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
966; CHECK-ZVKB-NEXT:    ret
967  %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b)
968  ret <16 x i16> %x
969}
970
971define <16 x i16> @vror_vx_v16i16(<16 x i16> %a, i16 %b) {
972; CHECK-LABEL: vror_vx_v16i16:
973; CHECK:       # %bb.0:
974; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
975; CHECK-NEXT:    vmv.v.x v10, a0
976; CHECK-NEXT:    vand.vi v12, v10, 15
977; CHECK-NEXT:    vrsub.vi v10, v10, 0
978; CHECK-NEXT:    vsrl.vv v12, v8, v12
979; CHECK-NEXT:    vand.vi v10, v10, 15
980; CHECK-NEXT:    vsll.vv v8, v8, v10
981; CHECK-NEXT:    vor.vv v8, v12, v8
982; CHECK-NEXT:    ret
983;
984; CHECK-ZVKB-LABEL: vror_vx_v16i16:
985; CHECK-ZVKB:       # %bb.0:
986; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
987; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
988; CHECK-ZVKB-NEXT:    ret
989  %b.head = insertelement <16 x i16> poison, i16 %b, i32 0
990  %b.splat = shufflevector <16 x i16> %b.head, <16 x i16> poison, <16 x i32> zeroinitializer
991  %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> %b.splat)
992  ret <16 x i16> %x
993}
994
995define <16 x i16> @vror_vi_v16i16(<16 x i16> %a) {
996; CHECK-LABEL: vror_vi_v16i16:
997; CHECK:       # %bb.0:
998; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
999; CHECK-NEXT:    vsll.vi v10, v8, 15
1000; CHECK-NEXT:    vsrl.vi v8, v8, 1
1001; CHECK-NEXT:    vor.vv v8, v8, v10
1002; CHECK-NEXT:    ret
1003;
1004; CHECK-ZVKB-LABEL: vror_vi_v16i16:
1005; CHECK-ZVKB:       # %bb.0:
1006; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
1007; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1008; CHECK-ZVKB-NEXT:    ret
1009  %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> splat (i16 1))
1010  ret <16 x i16> %x
1011}
1012
1013define <16 x i16> @vror_vi_rotl_v16i16(<16 x i16> %a) {
1014; CHECK-LABEL: vror_vi_rotl_v16i16:
1015; CHECK:       # %bb.0:
1016; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
1017; CHECK-NEXT:    vsrl.vi v10, v8, 15
1018; CHECK-NEXT:    vadd.vv v8, v8, v8
1019; CHECK-NEXT:    vor.vv v8, v8, v10
1020; CHECK-NEXT:    ret
1021;
1022; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i16:
1023; CHECK-ZVKB:       # %bb.0:
1024; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
1025; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
1026; CHECK-ZVKB-NEXT:    ret
1027  %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> splat (i16 1))
1028  ret <16 x i16> %x
1029}
1030
1031declare <32 x i16> @llvm.fshr.v32i16(<32 x i16>, <32 x i16>, <32 x i16>)
1032declare <32 x i16> @llvm.fshl.v32i16(<32 x i16>, <32 x i16>, <32 x i16>)
1033
1034define <32 x i16> @vror_vv_v32i16(<32 x i16> %a, <32 x i16> %b) {
1035; CHECK-LABEL: vror_vv_v32i16:
1036; CHECK:       # %bb.0:
1037; CHECK-NEXT:    li a0, 32
1038; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1039; CHECK-NEXT:    vand.vi v16, v12, 15
1040; CHECK-NEXT:    vrsub.vi v12, v12, 0
1041; CHECK-NEXT:    vsrl.vv v16, v8, v16
1042; CHECK-NEXT:    vand.vi v12, v12, 15
1043; CHECK-NEXT:    vsll.vv v8, v8, v12
1044; CHECK-NEXT:    vor.vv v8, v16, v8
1045; CHECK-NEXT:    ret
1046;
1047; CHECK-ZVKB-LABEL: vror_vv_v32i16:
1048; CHECK-ZVKB:       # %bb.0:
1049; CHECK-ZVKB-NEXT:    li a0, 32
1050; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1051; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
1052; CHECK-ZVKB-NEXT:    ret
1053  %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b)
1054  ret <32 x i16> %x
1055}
1056
1057define <32 x i16> @vror_vx_v32i16(<32 x i16> %a, i16 %b) {
1058; CHECK-LABEL: vror_vx_v32i16:
1059; CHECK:       # %bb.0:
1060; CHECK-NEXT:    li a1, 32
1061; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
1062; CHECK-NEXT:    vmv.v.x v12, a0
1063; CHECK-NEXT:    vand.vi v16, v12, 15
1064; CHECK-NEXT:    vrsub.vi v12, v12, 0
1065; CHECK-NEXT:    vsrl.vv v16, v8, v16
1066; CHECK-NEXT:    vand.vi v12, v12, 15
1067; CHECK-NEXT:    vsll.vv v8, v8, v12
1068; CHECK-NEXT:    vor.vv v8, v16, v8
1069; CHECK-NEXT:    ret
1070;
1071; CHECK-ZVKB-LABEL: vror_vx_v32i16:
1072; CHECK-ZVKB:       # %bb.0:
1073; CHECK-ZVKB-NEXT:    li a1, 32
1074; CHECK-ZVKB-NEXT:    vsetvli zero, a1, e16, m4, ta, ma
1075; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1076; CHECK-ZVKB-NEXT:    ret
1077  %b.head = insertelement <32 x i16> poison, i16 %b, i32 0
1078  %b.splat = shufflevector <32 x i16> %b.head, <32 x i16> poison, <32 x i32> zeroinitializer
1079  %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> %b.splat)
1080  ret <32 x i16> %x
1081}
1082
1083define <32 x i16> @vror_vi_v32i16(<32 x i16> %a) {
1084; CHECK-LABEL: vror_vi_v32i16:
1085; CHECK:       # %bb.0:
1086; CHECK-NEXT:    li a0, 32
1087; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1088; CHECK-NEXT:    vsll.vi v12, v8, 15
1089; CHECK-NEXT:    vsrl.vi v8, v8, 1
1090; CHECK-NEXT:    vor.vv v8, v8, v12
1091; CHECK-NEXT:    ret
1092;
1093; CHECK-ZVKB-LABEL: vror_vi_v32i16:
1094; CHECK-ZVKB:       # %bb.0:
1095; CHECK-ZVKB-NEXT:    li a0, 32
1096; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1097; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1098; CHECK-ZVKB-NEXT:    ret
1099  %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> splat (i16 1))
1100  ret <32 x i16> %x
1101}
1102
1103define <32 x i16> @vror_vi_rotl_v32i16(<32 x i16> %a) {
1104; CHECK-LABEL: vror_vi_rotl_v32i16:
1105; CHECK:       # %bb.0:
1106; CHECK-NEXT:    li a0, 32
1107; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1108; CHECK-NEXT:    vsrl.vi v12, v8, 15
1109; CHECK-NEXT:    vadd.vv v8, v8, v8
1110; CHECK-NEXT:    vor.vv v8, v8, v12
1111; CHECK-NEXT:    ret
1112;
1113; CHECK-ZVKB-LABEL: vror_vi_rotl_v32i16:
1114; CHECK-ZVKB:       # %bb.0:
1115; CHECK-ZVKB-NEXT:    li a0, 32
1116; CHECK-ZVKB-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
1117; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 15
1118; CHECK-ZVKB-NEXT:    ret
1119  %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> splat (i16 1))
1120  ret <32 x i16> %x
1121}
1122
1123declare <1 x i32> @llvm.fshr.v1i32(<1 x i32>, <1 x i32>, <1 x i32>)
1124declare <1 x i32> @llvm.fshl.v1i32(<1 x i32>, <1 x i32>, <1 x i32>)
1125
1126define <1 x i32> @vror_vv_v1i32(<1 x i32> %a, <1 x i32> %b) {
1127; CHECK-LABEL: vror_vv_v1i32:
1128; CHECK:       # %bb.0:
1129; CHECK-NEXT:    li a0, 31
1130; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1131; CHECK-NEXT:    vrsub.vi v10, v9, 0
1132; CHECK-NEXT:    vand.vx v9, v9, a0
1133; CHECK-NEXT:    vand.vx v10, v10, a0
1134; CHECK-NEXT:    vsrl.vv v9, v8, v9
1135; CHECK-NEXT:    vsll.vv v8, v8, v10
1136; CHECK-NEXT:    vor.vv v8, v9, v8
1137; CHECK-NEXT:    ret
1138;
1139; CHECK-ZVKB-LABEL: vror_vv_v1i32:
1140; CHECK-ZVKB:       # %bb.0:
1141; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1142; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1143; CHECK-ZVKB-NEXT:    ret
1144  %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b)
1145  ret <1 x i32> %x
1146}
1147
1148define <1 x i32> @vror_vx_v1i32(<1 x i32> %a, i32 %b) {
1149; CHECK-LABEL: vror_vx_v1i32:
1150; CHECK:       # %bb.0:
1151; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1152; CHECK-NEXT:    vmv.s.x v9, a0
1153; CHECK-NEXT:    li a0, 31
1154; CHECK-NEXT:    vand.vx v10, v9, a0
1155; CHECK-NEXT:    vrsub.vi v9, v9, 0
1156; CHECK-NEXT:    vsrl.vv v10, v8, v10
1157; CHECK-NEXT:    vand.vx v9, v9, a0
1158; CHECK-NEXT:    vsll.vv v8, v8, v9
1159; CHECK-NEXT:    vor.vv v8, v10, v8
1160; CHECK-NEXT:    ret
1161;
1162; CHECK-ZVKB-LABEL: vror_vx_v1i32:
1163; CHECK-ZVKB:       # %bb.0:
1164; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1165; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1166; CHECK-ZVKB-NEXT:    ret
1167  %b.head = insertelement <1 x i32> poison, i32 %b, i32 0
1168  %b.splat = shufflevector <1 x i32> %b.head, <1 x i32> poison, <1 x i32> zeroinitializer
1169  %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> %b.splat)
1170  ret <1 x i32> %x
1171}
1172
1173define <1 x i32> @vror_vi_v1i32(<1 x i32> %a) {
1174; CHECK-LABEL: vror_vi_v1i32:
1175; CHECK:       # %bb.0:
1176; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1177; CHECK-NEXT:    vsll.vi v9, v8, 31
1178; CHECK-NEXT:    vsrl.vi v8, v8, 1
1179; CHECK-NEXT:    vor.vv v8, v8, v9
1180; CHECK-NEXT:    ret
1181;
1182; CHECK-ZVKB-LABEL: vror_vi_v1i32:
1183; CHECK-ZVKB:       # %bb.0:
1184; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1185; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1186; CHECK-ZVKB-NEXT:    ret
1187  %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> splat (i32 1))
1188  ret <1 x i32> %x
1189}
1190
1191define <1 x i32> @vror_vi_rotl_v1i32(<1 x i32> %a) {
1192; CHECK-LABEL: vror_vi_rotl_v1i32:
1193; CHECK:       # %bb.0:
1194; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1195; CHECK-NEXT:    vsrl.vi v9, v8, 31
1196; CHECK-NEXT:    vadd.vv v8, v8, v8
1197; CHECK-NEXT:    vor.vv v8, v8, v9
1198; CHECK-NEXT:    ret
1199;
1200; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i32:
1201; CHECK-ZVKB:       # %bb.0:
1202; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
1203; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1204; CHECK-ZVKB-NEXT:    ret
1205  %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> splat (i32 1))
1206  ret <1 x i32> %x
1207}
1208
1209declare <2 x i32> @llvm.fshr.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
1210declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>)
1211
1212define <2 x i32> @vror_vv_v2i32(<2 x i32> %a, <2 x i32> %b) {
1213; CHECK-LABEL: vror_vv_v2i32:
1214; CHECK:       # %bb.0:
1215; CHECK-NEXT:    li a0, 31
1216; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1217; CHECK-NEXT:    vrsub.vi v10, v9, 0
1218; CHECK-NEXT:    vand.vx v9, v9, a0
1219; CHECK-NEXT:    vand.vx v10, v10, a0
1220; CHECK-NEXT:    vsrl.vv v9, v8, v9
1221; CHECK-NEXT:    vsll.vv v8, v8, v10
1222; CHECK-NEXT:    vor.vv v8, v9, v8
1223; CHECK-NEXT:    ret
1224;
1225; CHECK-ZVKB-LABEL: vror_vv_v2i32:
1226; CHECK-ZVKB:       # %bb.0:
1227; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1228; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1229; CHECK-ZVKB-NEXT:    ret
1230  %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b)
1231  ret <2 x i32> %x
1232}
1233
1234define <2 x i32> @vror_vx_v2i32(<2 x i32> %a, i32 %b) {
1235; CHECK-LABEL: vror_vx_v2i32:
1236; CHECK:       # %bb.0:
1237; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1238; CHECK-NEXT:    vmv.v.x v9, a0
1239; CHECK-NEXT:    li a0, 31
1240; CHECK-NEXT:    vand.vx v10, v9, a0
1241; CHECK-NEXT:    vrsub.vi v9, v9, 0
1242; CHECK-NEXT:    vsrl.vv v10, v8, v10
1243; CHECK-NEXT:    vand.vx v9, v9, a0
1244; CHECK-NEXT:    vsll.vv v8, v8, v9
1245; CHECK-NEXT:    vor.vv v8, v10, v8
1246; CHECK-NEXT:    ret
1247;
1248; CHECK-ZVKB-LABEL: vror_vx_v2i32:
1249; CHECK-ZVKB:       # %bb.0:
1250; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1251; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1252; CHECK-ZVKB-NEXT:    ret
1253  %b.head = insertelement <2 x i32> poison, i32 %b, i32 0
1254  %b.splat = shufflevector <2 x i32> %b.head, <2 x i32> poison, <2 x i32> zeroinitializer
1255  %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> %b.splat)
1256  ret <2 x i32> %x
1257}
1258
1259define <2 x i32> @vror_vi_v2i32(<2 x i32> %a) {
1260; CHECK-LABEL: vror_vi_v2i32:
1261; CHECK:       # %bb.0:
1262; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1263; CHECK-NEXT:    vsll.vi v9, v8, 31
1264; CHECK-NEXT:    vsrl.vi v8, v8, 1
1265; CHECK-NEXT:    vor.vv v8, v8, v9
1266; CHECK-NEXT:    ret
1267;
1268; CHECK-ZVKB-LABEL: vror_vi_v2i32:
1269; CHECK-ZVKB:       # %bb.0:
1270; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1271; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1272; CHECK-ZVKB-NEXT:    ret
1273  %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> splat (i32 1))
1274  ret <2 x i32> %x
1275}
1276
1277define <2 x i32> @vror_vi_rotl_v2i32(<2 x i32> %a) {
1278; CHECK-LABEL: vror_vi_rotl_v2i32:
1279; CHECK:       # %bb.0:
1280; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1281; CHECK-NEXT:    vsrl.vi v9, v8, 31
1282; CHECK-NEXT:    vadd.vv v8, v8, v8
1283; CHECK-NEXT:    vor.vv v8, v8, v9
1284; CHECK-NEXT:    ret
1285;
1286; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i32:
1287; CHECK-ZVKB:       # %bb.0:
1288; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1289; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1290; CHECK-ZVKB-NEXT:    ret
1291  %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> splat (i32 1))
1292  ret <2 x i32> %x
1293}
1294
1295declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
1296declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
1297
1298define <4 x i32> @vror_vv_v4i32(<4 x i32> %a, <4 x i32> %b) {
1299; CHECK-LABEL: vror_vv_v4i32:
1300; CHECK:       # %bb.0:
1301; CHECK-NEXT:    li a0, 31
1302; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1303; CHECK-NEXT:    vrsub.vi v10, v9, 0
1304; CHECK-NEXT:    vand.vx v9, v9, a0
1305; CHECK-NEXT:    vand.vx v10, v10, a0
1306; CHECK-NEXT:    vsrl.vv v9, v8, v9
1307; CHECK-NEXT:    vsll.vv v8, v8, v10
1308; CHECK-NEXT:    vor.vv v8, v9, v8
1309; CHECK-NEXT:    ret
1310;
1311; CHECK-ZVKB-LABEL: vror_vv_v4i32:
1312; CHECK-ZVKB:       # %bb.0:
1313; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1314; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1315; CHECK-ZVKB-NEXT:    ret
1316  %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b)
1317  ret <4 x i32> %x
1318}
1319
1320define <4 x i32> @vror_vx_v4i32(<4 x i32> %a, i32 %b) {
1321; CHECK-LABEL: vror_vx_v4i32:
1322; CHECK:       # %bb.0:
1323; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1324; CHECK-NEXT:    vmv.v.x v9, a0
1325; CHECK-NEXT:    li a0, 31
1326; CHECK-NEXT:    vand.vx v10, v9, a0
1327; CHECK-NEXT:    vrsub.vi v9, v9, 0
1328; CHECK-NEXT:    vsrl.vv v10, v8, v10
1329; CHECK-NEXT:    vand.vx v9, v9, a0
1330; CHECK-NEXT:    vsll.vv v8, v8, v9
1331; CHECK-NEXT:    vor.vv v8, v10, v8
1332; CHECK-NEXT:    ret
1333;
1334; CHECK-ZVKB-LABEL: vror_vx_v4i32:
1335; CHECK-ZVKB:       # %bb.0:
1336; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1337; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1338; CHECK-ZVKB-NEXT:    ret
1339  %b.head = insertelement <4 x i32> poison, i32 %b, i32 0
1340  %b.splat = shufflevector <4 x i32> %b.head, <4 x i32> poison, <4 x i32> zeroinitializer
1341  %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> %b.splat)
1342  ret <4 x i32> %x
1343}
1344
1345define <4 x i32> @vror_vi_v4i32(<4 x i32> %a) {
1346; CHECK-LABEL: vror_vi_v4i32:
1347; CHECK:       # %bb.0:
1348; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1349; CHECK-NEXT:    vsll.vi v9, v8, 31
1350; CHECK-NEXT:    vsrl.vi v8, v8, 1
1351; CHECK-NEXT:    vor.vv v8, v8, v9
1352; CHECK-NEXT:    ret
1353;
1354; CHECK-ZVKB-LABEL: vror_vi_v4i32:
1355; CHECK-ZVKB:       # %bb.0:
1356; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1357; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1358; CHECK-ZVKB-NEXT:    ret
1359  %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 1))
1360  ret <4 x i32> %x
1361}
1362
1363define <4 x i32> @vror_vi_rotl_v4i32(<4 x i32> %a) {
1364; CHECK-LABEL: vror_vi_rotl_v4i32:
1365; CHECK:       # %bb.0:
1366; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1367; CHECK-NEXT:    vsrl.vi v9, v8, 31
1368; CHECK-NEXT:    vadd.vv v8, v8, v8
1369; CHECK-NEXT:    vor.vv v8, v8, v9
1370; CHECK-NEXT:    ret
1371;
1372; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i32:
1373; CHECK-ZVKB:       # %bb.0:
1374; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1375; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1376; CHECK-ZVKB-NEXT:    ret
1377  %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 1))
1378  ret <4 x i32> %x
1379}
1380
1381declare <8 x i32> @llvm.fshr.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
1382declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
1383
1384define <8 x i32> @vror_vv_v8i32(<8 x i32> %a, <8 x i32> %b) {
1385; CHECK-LABEL: vror_vv_v8i32:
1386; CHECK:       # %bb.0:
1387; CHECK-NEXT:    li a0, 31
1388; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1389; CHECK-NEXT:    vrsub.vi v12, v10, 0
1390; CHECK-NEXT:    vand.vx v10, v10, a0
1391; CHECK-NEXT:    vand.vx v12, v12, a0
1392; CHECK-NEXT:    vsrl.vv v10, v8, v10
1393; CHECK-NEXT:    vsll.vv v8, v8, v12
1394; CHECK-NEXT:    vor.vv v8, v10, v8
1395; CHECK-NEXT:    ret
1396;
1397; CHECK-ZVKB-LABEL: vror_vv_v8i32:
1398; CHECK-ZVKB:       # %bb.0:
1399; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1400; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
1401; CHECK-ZVKB-NEXT:    ret
1402  %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b)
1403  ret <8 x i32> %x
1404}
1405
1406define <8 x i32> @vror_vx_v8i32(<8 x i32> %a, i32 %b) {
1407; CHECK-LABEL: vror_vx_v8i32:
1408; CHECK:       # %bb.0:
1409; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1410; CHECK-NEXT:    vmv.v.x v10, a0
1411; CHECK-NEXT:    li a0, 31
1412; CHECK-NEXT:    vand.vx v12, v10, a0
1413; CHECK-NEXT:    vrsub.vi v10, v10, 0
1414; CHECK-NEXT:    vsrl.vv v12, v8, v12
1415; CHECK-NEXT:    vand.vx v10, v10, a0
1416; CHECK-NEXT:    vsll.vv v8, v8, v10
1417; CHECK-NEXT:    vor.vv v8, v12, v8
1418; CHECK-NEXT:    ret
1419;
1420; CHECK-ZVKB-LABEL: vror_vx_v8i32:
1421; CHECK-ZVKB:       # %bb.0:
1422; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1423; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1424; CHECK-ZVKB-NEXT:    ret
1425  %b.head = insertelement <8 x i32> poison, i32 %b, i32 0
1426  %b.splat = shufflevector <8 x i32> %b.head, <8 x i32> poison, <8 x i32> zeroinitializer
1427  %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> %b.splat)
1428  ret <8 x i32> %x
1429}
1430
1431define <8 x i32> @vror_vi_v8i32(<8 x i32> %a) {
1432; CHECK-LABEL: vror_vi_v8i32:
1433; CHECK:       # %bb.0:
1434; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1435; CHECK-NEXT:    vsll.vi v10, v8, 31
1436; CHECK-NEXT:    vsrl.vi v8, v8, 1
1437; CHECK-NEXT:    vor.vv v8, v8, v10
1438; CHECK-NEXT:    ret
1439;
1440; CHECK-ZVKB-LABEL: vror_vi_v8i32:
1441; CHECK-ZVKB:       # %bb.0:
1442; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1443; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1444; CHECK-ZVKB-NEXT:    ret
1445  %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> splat (i32 1))
1446  ret <8 x i32> %x
1447}
1448
1449define <8 x i32> @vror_vi_rotl_v8i32(<8 x i32> %a) {
1450; CHECK-LABEL: vror_vi_rotl_v8i32:
1451; CHECK:       # %bb.0:
1452; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1453; CHECK-NEXT:    vsrl.vi v10, v8, 31
1454; CHECK-NEXT:    vadd.vv v8, v8, v8
1455; CHECK-NEXT:    vor.vv v8, v8, v10
1456; CHECK-NEXT:    ret
1457;
1458; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i32:
1459; CHECK-ZVKB:       # %bb.0:
1460; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
1461; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1462; CHECK-ZVKB-NEXT:    ret
1463  %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> splat (i32 1))
1464  ret <8 x i32> %x
1465}
1466
1467declare <16 x i32> @llvm.fshr.v16i32(<16 x i32>, <16 x i32>, <16 x i32>)
1468declare <16 x i32> @llvm.fshl.v16i32(<16 x i32>, <16 x i32>, <16 x i32>)
1469
1470define <16 x i32> @vror_vv_v16i32(<16 x i32> %a, <16 x i32> %b) {
1471; CHECK-LABEL: vror_vv_v16i32:
1472; CHECK:       # %bb.0:
1473; CHECK-NEXT:    li a0, 31
1474; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1475; CHECK-NEXT:    vrsub.vi v16, v12, 0
1476; CHECK-NEXT:    vand.vx v12, v12, a0
1477; CHECK-NEXT:    vand.vx v16, v16, a0
1478; CHECK-NEXT:    vsrl.vv v12, v8, v12
1479; CHECK-NEXT:    vsll.vv v8, v8, v16
1480; CHECK-NEXT:    vor.vv v8, v12, v8
1481; CHECK-NEXT:    ret
1482;
1483; CHECK-ZVKB-LABEL: vror_vv_v16i32:
1484; CHECK-ZVKB:       # %bb.0:
1485; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1486; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
1487; CHECK-ZVKB-NEXT:    ret
1488  %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b)
1489  ret <16 x i32> %x
1490}
1491
1492define <16 x i32> @vror_vx_v16i32(<16 x i32> %a, i32 %b) {
1493; CHECK-LABEL: vror_vx_v16i32:
1494; CHECK:       # %bb.0:
1495; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1496; CHECK-NEXT:    vmv.v.x v12, a0
1497; CHECK-NEXT:    li a0, 31
1498; CHECK-NEXT:    vand.vx v16, v12, a0
1499; CHECK-NEXT:    vrsub.vi v12, v12, 0
1500; CHECK-NEXT:    vsrl.vv v16, v8, v16
1501; CHECK-NEXT:    vand.vx v12, v12, a0
1502; CHECK-NEXT:    vsll.vv v8, v8, v12
1503; CHECK-NEXT:    vor.vv v8, v16, v8
1504; CHECK-NEXT:    ret
1505;
1506; CHECK-ZVKB-LABEL: vror_vx_v16i32:
1507; CHECK-ZVKB:       # %bb.0:
1508; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1509; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1510; CHECK-ZVKB-NEXT:    ret
1511  %b.head = insertelement <16 x i32> poison, i32 %b, i32 0
1512  %b.splat = shufflevector <16 x i32> %b.head, <16 x i32> poison, <16 x i32> zeroinitializer
1513  %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> %b.splat)
1514  ret <16 x i32> %x
1515}
1516
1517define <16 x i32> @vror_vi_v16i32(<16 x i32> %a) {
1518; CHECK-LABEL: vror_vi_v16i32:
1519; CHECK:       # %bb.0:
1520; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1521; CHECK-NEXT:    vsll.vi v12, v8, 31
1522; CHECK-NEXT:    vsrl.vi v8, v8, 1
1523; CHECK-NEXT:    vor.vv v8, v8, v12
1524; CHECK-NEXT:    ret
1525;
1526; CHECK-ZVKB-LABEL: vror_vi_v16i32:
1527; CHECK-ZVKB:       # %bb.0:
1528; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1529; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1530; CHECK-ZVKB-NEXT:    ret
1531  %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> splat (i32 1))
1532  ret <16 x i32> %x
1533}
1534
1535define <16 x i32> @vror_vi_rotl_v16i32(<16 x i32> %a) {
1536; CHECK-LABEL: vror_vi_rotl_v16i32:
1537; CHECK:       # %bb.0:
1538; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1539; CHECK-NEXT:    vsrl.vi v12, v8, 31
1540; CHECK-NEXT:    vadd.vv v8, v8, v8
1541; CHECK-NEXT:    vor.vv v8, v8, v12
1542; CHECK-NEXT:    ret
1543;
1544; CHECK-ZVKB-LABEL: vror_vi_rotl_v16i32:
1545; CHECK-ZVKB:       # %bb.0:
1546; CHECK-ZVKB-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
1547; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 31
1548; CHECK-ZVKB-NEXT:    ret
1549  %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> splat (i32 1))
1550  ret <16 x i32> %x
1551}
1552
1553declare <1 x i64> @llvm.fshr.v1i64(<1 x i64>, <1 x i64>, <1 x i64>)
1554declare <1 x i64> @llvm.fshl.v1i64(<1 x i64>, <1 x i64>, <1 x i64>)
1555
1556define <1 x i64> @vror_vv_v1i64(<1 x i64> %a, <1 x i64> %b) {
1557; CHECK-LABEL: vror_vv_v1i64:
1558; CHECK:       # %bb.0:
1559; CHECK-NEXT:    li a0, 63
1560; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1561; CHECK-NEXT:    vrsub.vi v10, v9, 0
1562; CHECK-NEXT:    vand.vx v9, v9, a0
1563; CHECK-NEXT:    vand.vx v10, v10, a0
1564; CHECK-NEXT:    vsrl.vv v9, v8, v9
1565; CHECK-NEXT:    vsll.vv v8, v8, v10
1566; CHECK-NEXT:    vor.vv v8, v9, v8
1567; CHECK-NEXT:    ret
1568;
1569; CHECK-ZVKB-LABEL: vror_vv_v1i64:
1570; CHECK-ZVKB:       # %bb.0:
1571; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1572; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1573; CHECK-ZVKB-NEXT:    ret
1574  %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)
1575  ret <1 x i64> %x
1576}
1577
1578define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) {
1579; CHECK-LABEL: vror_vx_v1i64:
1580; CHECK:       # %bb.0:
1581; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1582; CHECK-NEXT:    vmv.s.x v9, a0
1583; CHECK-NEXT:    li a0, 63
1584; CHECK-NEXT:    vand.vx v10, v9, a0
1585; CHECK-NEXT:    vrsub.vi v9, v9, 0
1586; CHECK-NEXT:    vsrl.vv v10, v8, v10
1587; CHECK-NEXT:    vand.vx v9, v9, a0
1588; CHECK-NEXT:    vsll.vv v8, v8, v9
1589; CHECK-NEXT:    vor.vv v8, v10, v8
1590; CHECK-NEXT:    ret
1591;
1592; CHECK-ZVKB-LABEL: vror_vx_v1i64:
1593; CHECK-ZVKB:       # %bb.0:
1594; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1595; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1596; CHECK-ZVKB-NEXT:    ret
1597  %b.head = insertelement <1 x i64> poison, i64 %b, i32 0
1598  %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer
1599  %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)
1600  ret <1 x i64> %x
1601}
1602
1603define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) {
1604; CHECK-RV32-LABEL: vror_vi_v1i64:
1605; CHECK-RV32:       # %bb.0:
1606; CHECK-RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1607; CHECK-RV32-NEXT:    vmv.v.i v9, 1
1608; CHECK-RV32-NEXT:    li a0, 63
1609; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
1610; CHECK-RV32-NEXT:    vmv.s.x v10, a0
1611; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
1612; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
1613; CHECK-RV32-NEXT:    vsll.vv v9, v8, v9
1614; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
1615; CHECK-RV32-NEXT:    vor.vv v8, v8, v9
1616; CHECK-RV32-NEXT:    ret
1617;
1618; CHECK-RV64-LABEL: vror_vi_v1i64:
1619; CHECK-RV64:       # %bb.0:
1620; CHECK-RV64-NEXT:    li a0, 63
1621; CHECK-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1622; CHECK-RV64-NEXT:    vsll.vx v9, v8, a0
1623; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
1624; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
1625; CHECK-RV64-NEXT:    ret
1626;
1627; CHECK-ZVKB-LABEL: vror_vi_v1i64:
1628; CHECK-ZVKB:       # %bb.0:
1629; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1630; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1631; CHECK-ZVKB-NEXT:    ret
1632  %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> splat (i64 1))
1633  ret <1 x i64> %x
1634}
1635
1636define <1 x i64> @vror_vi_rotl_v1i64(<1 x i64> %a) {
1637; CHECK-RV32-LABEL: vror_vi_rotl_v1i64:
1638; CHECK-RV32:       # %bb.0:
1639; CHECK-RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1640; CHECK-RV32-NEXT:    vmv.v.i v9, 1
1641; CHECK-RV32-NEXT:    li a0, 63
1642; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
1643; CHECK-RV32-NEXT:    vmv.s.x v10, a0
1644; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
1645; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
1646; CHECK-RV32-NEXT:    vsrl.vv v9, v8, v9
1647; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
1648; CHECK-RV32-NEXT:    vor.vv v8, v8, v9
1649; CHECK-RV32-NEXT:    ret
1650;
1651; CHECK-RV64-LABEL: vror_vi_rotl_v1i64:
1652; CHECK-RV64:       # %bb.0:
1653; CHECK-RV64-NEXT:    li a0, 63
1654; CHECK-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1655; CHECK-RV64-NEXT:    vsrl.vx v9, v8, a0
1656; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
1657; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
1658; CHECK-RV64-NEXT:    ret
1659;
1660; CHECK-ZVKB-LABEL: vror_vi_rotl_v1i64:
1661; CHECK-ZVKB:       # %bb.0:
1662; CHECK-ZVKB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
1663; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1664; CHECK-ZVKB-NEXT:    ret
1665  %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> splat (i64 1))
1666  ret <1 x i64> %x
1667}
1668
1669declare <2 x i64> @llvm.fshr.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
1670declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
1671
1672define <2 x i64> @vror_vv_v2i64(<2 x i64> %a, <2 x i64> %b) {
1673; CHECK-LABEL: vror_vv_v2i64:
1674; CHECK:       # %bb.0:
1675; CHECK-NEXT:    li a0, 63
1676; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1677; CHECK-NEXT:    vrsub.vi v10, v9, 0
1678; CHECK-NEXT:    vand.vx v9, v9, a0
1679; CHECK-NEXT:    vand.vx v10, v10, a0
1680; CHECK-NEXT:    vsrl.vv v9, v8, v9
1681; CHECK-NEXT:    vsll.vv v8, v8, v10
1682; CHECK-NEXT:    vor.vv v8, v9, v8
1683; CHECK-NEXT:    ret
1684;
1685; CHECK-ZVKB-LABEL: vror_vv_v2i64:
1686; CHECK-ZVKB:       # %bb.0:
1687; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1688; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v9
1689; CHECK-ZVKB-NEXT:    ret
1690  %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b)
1691  ret <2 x i64> %x
1692}
1693
1694define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) {
1695; CHECK-RV32-LABEL: vror_vx_v2i64:
1696; CHECK-RV32:       # %bb.0:
1697; CHECK-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1698; CHECK-RV32-NEXT:    vmv.v.x v9, a0
1699; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
1700; CHECK-RV32-NEXT:    vmv.v.i v10, 0
1701; CHECK-RV32-NEXT:    vwsub.vx v11, v10, a0
1702; CHECK-RV32-NEXT:    li a0, 63
1703; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
1704; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
1705; CHECK-RV32-NEXT:    vand.vx v10, v11, a0
1706; CHECK-RV32-NEXT:    vsll.vv v10, v8, v10
1707; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v9
1708; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
1709; CHECK-RV32-NEXT:    ret
1710;
1711; CHECK-RV64-LABEL: vror_vx_v2i64:
1712; CHECK-RV64:       # %bb.0:
1713; CHECK-RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1714; CHECK-RV64-NEXT:    vmv.v.x v9, a0
1715; CHECK-RV64-NEXT:    li a0, 63
1716; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
1717; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
1718; CHECK-RV64-NEXT:    vsrl.vv v10, v8, v10
1719; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
1720; CHECK-RV64-NEXT:    vsll.vv v8, v8, v9
1721; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
1722; CHECK-RV64-NEXT:    ret
1723;
1724; CHECK-ZVKB-LABEL: vror_vx_v2i64:
1725; CHECK-ZVKB:       # %bb.0:
1726; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1727; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1728; CHECK-ZVKB-NEXT:    ret
1729  %b.head = insertelement <2 x i64> poison, i64 %b, i32 0
1730  %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer
1731  %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)
1732  ret <2 x i64> %x
1733}
1734
1735define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {
1736; CHECK-RV32-LABEL: vror_vi_v2i64:
1737; CHECK-RV32:       # %bb.0:
1738; CHECK-RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1739; CHECK-RV32-NEXT:    vmv.v.i v9, 0
1740; CHECK-RV32-NEXT:    li a0, 1
1741; CHECK-RV32-NEXT:    vwsubu.vx v10, v9, a0
1742; CHECK-RV32-NEXT:    li a0, 63
1743; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
1744; CHECK-RV32-NEXT:    vmv.v.x v9, a0
1745; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
1746; CHECK-RV32-NEXT:    vand.vi v9, v9, 1
1747; CHECK-RV32-NEXT:    vsll.vv v10, v8, v10
1748; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v9
1749; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
1750; CHECK-RV32-NEXT:    ret
1751;
1752; CHECK-RV64-LABEL: vror_vi_v2i64:
1753; CHECK-RV64:       # %bb.0:
1754; CHECK-RV64-NEXT:    li a0, 63
1755; CHECK-RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1756; CHECK-RV64-NEXT:    vsll.vx v9, v8, a0
1757; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
1758; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
1759; CHECK-RV64-NEXT:    ret
1760;
1761; CHECK-ZVKB-LABEL: vror_vi_v2i64:
1762; CHECK-ZVKB:       # %bb.0:
1763; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1764; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1765; CHECK-ZVKB-NEXT:    ret
1766  %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1))
1767  ret <2 x i64> %x
1768}
1769
1770define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) {
1771; CHECK-RV32-LABEL: vror_vi_rotl_v2i64:
1772; CHECK-RV32:       # %bb.0:
1773; CHECK-RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
1774; CHECK-RV32-NEXT:    vmv.v.i v9, 0
1775; CHECK-RV32-NEXT:    li a0, 1
1776; CHECK-RV32-NEXT:    vwsubu.vx v10, v9, a0
1777; CHECK-RV32-NEXT:    li a0, 63
1778; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
1779; CHECK-RV32-NEXT:    vmv.v.x v9, a0
1780; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
1781; CHECK-RV32-NEXT:    vand.vi v9, v9, 1
1782; CHECK-RV32-NEXT:    vsrl.vv v10, v8, v10
1783; CHECK-RV32-NEXT:    vsll.vv v8, v8, v9
1784; CHECK-RV32-NEXT:    vor.vv v8, v8, v10
1785; CHECK-RV32-NEXT:    ret
1786;
1787; CHECK-RV64-LABEL: vror_vi_rotl_v2i64:
1788; CHECK-RV64:       # %bb.0:
1789; CHECK-RV64-NEXT:    li a0, 63
1790; CHECK-RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1791; CHECK-RV64-NEXT:    vsrl.vx v9, v8, a0
1792; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
1793; CHECK-RV64-NEXT:    vor.vv v8, v8, v9
1794; CHECK-RV64-NEXT:    ret
1795;
1796; CHECK-ZVKB-LABEL: vror_vi_rotl_v2i64:
1797; CHECK-ZVKB:       # %bb.0:
1798; CHECK-ZVKB-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1799; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1800; CHECK-ZVKB-NEXT:    ret
1801  %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1))
1802  ret <2 x i64> %x
1803}
1804
1805declare <4 x i64> @llvm.fshr.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
1806declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
1807
1808define <4 x i64> @vror_vv_v4i64(<4 x i64> %a, <4 x i64> %b) {
1809; CHECK-LABEL: vror_vv_v4i64:
1810; CHECK:       # %bb.0:
1811; CHECK-NEXT:    li a0, 63
1812; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1813; CHECK-NEXT:    vrsub.vi v12, v10, 0
1814; CHECK-NEXT:    vand.vx v10, v10, a0
1815; CHECK-NEXT:    vand.vx v12, v12, a0
1816; CHECK-NEXT:    vsrl.vv v10, v8, v10
1817; CHECK-NEXT:    vsll.vv v8, v8, v12
1818; CHECK-NEXT:    vor.vv v8, v10, v8
1819; CHECK-NEXT:    ret
1820;
1821; CHECK-ZVKB-LABEL: vror_vv_v4i64:
1822; CHECK-ZVKB:       # %bb.0:
1823; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1824; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v10
1825; CHECK-ZVKB-NEXT:    ret
1826  %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b)
1827  ret <4 x i64> %x
1828}
1829
1830define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) {
1831; CHECK-RV32-LABEL: vror_vx_v4i64:
1832; CHECK-RV32:       # %bb.0:
1833; CHECK-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1834; CHECK-RV32-NEXT:    vmv.v.x v10, a0
1835; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
1836; CHECK-RV32-NEXT:    vmv.v.i v12, 0
1837; CHECK-RV32-NEXT:    vwsub.vx v14, v12, a0
1838; CHECK-RV32-NEXT:    li a0, 63
1839; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1840; CHECK-RV32-NEXT:    vand.vx v10, v10, a0
1841; CHECK-RV32-NEXT:    vand.vx v12, v14, a0
1842; CHECK-RV32-NEXT:    vsll.vv v12, v8, v12
1843; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
1844; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
1845; CHECK-RV32-NEXT:    ret
1846;
1847; CHECK-RV64-LABEL: vror_vx_v4i64:
1848; CHECK-RV64:       # %bb.0:
1849; CHECK-RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1850; CHECK-RV64-NEXT:    vmv.v.x v10, a0
1851; CHECK-RV64-NEXT:    li a0, 63
1852; CHECK-RV64-NEXT:    vand.vx v12, v10, a0
1853; CHECK-RV64-NEXT:    vrsub.vi v10, v10, 0
1854; CHECK-RV64-NEXT:    vsrl.vv v12, v8, v12
1855; CHECK-RV64-NEXT:    vand.vx v10, v10, a0
1856; CHECK-RV64-NEXT:    vsll.vv v8, v8, v10
1857; CHECK-RV64-NEXT:    vor.vv v8, v12, v8
1858; CHECK-RV64-NEXT:    ret
1859;
1860; CHECK-ZVKB-LABEL: vror_vx_v4i64:
1861; CHECK-ZVKB:       # %bb.0:
1862; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1863; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
1864; CHECK-ZVKB-NEXT:    ret
1865  %b.head = insertelement <4 x i64> poison, i64 %b, i32 0
1866  %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer
1867  %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)
1868  ret <4 x i64> %x
1869}
1870
1871define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {
1872; CHECK-RV32-LABEL: vror_vi_v4i64:
1873; CHECK-RV32:       # %bb.0:
1874; CHECK-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1875; CHECK-RV32-NEXT:    vmv.v.i v10, 0
1876; CHECK-RV32-NEXT:    li a0, 1
1877; CHECK-RV32-NEXT:    vwsubu.vx v12, v10, a0
1878; CHECK-RV32-NEXT:    li a0, 63
1879; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1880; CHECK-RV32-NEXT:    vmv.v.x v10, a0
1881; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
1882; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
1883; CHECK-RV32-NEXT:    vsll.vv v12, v8, v12
1884; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
1885; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
1886; CHECK-RV32-NEXT:    ret
1887;
1888; CHECK-RV64-LABEL: vror_vi_v4i64:
1889; CHECK-RV64:       # %bb.0:
1890; CHECK-RV64-NEXT:    li a0, 63
1891; CHECK-RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1892; CHECK-RV64-NEXT:    vsll.vx v10, v8, a0
1893; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
1894; CHECK-RV64-NEXT:    vor.vv v8, v8, v10
1895; CHECK-RV64-NEXT:    ret
1896;
1897; CHECK-ZVKB-LABEL: vror_vi_v4i64:
1898; CHECK-ZVKB:       # %bb.0:
1899; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1900; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
1901; CHECK-ZVKB-NEXT:    ret
1902  %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> splat (i64 1))
1903  ret <4 x i64> %x
1904}
1905
1906define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) {
1907; CHECK-RV32-LABEL: vror_vi_rotl_v4i64:
1908; CHECK-RV32:       # %bb.0:
1909; CHECK-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
1910; CHECK-RV32-NEXT:    vmv.v.i v10, 0
1911; CHECK-RV32-NEXT:    li a0, 1
1912; CHECK-RV32-NEXT:    vwsubu.vx v12, v10, a0
1913; CHECK-RV32-NEXT:    li a0, 63
1914; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
1915; CHECK-RV32-NEXT:    vmv.v.x v10, a0
1916; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
1917; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
1918; CHECK-RV32-NEXT:    vsrl.vv v12, v8, v12
1919; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
1920; CHECK-RV32-NEXT:    vor.vv v8, v8, v12
1921; CHECK-RV32-NEXT:    ret
1922;
1923; CHECK-RV64-LABEL: vror_vi_rotl_v4i64:
1924; CHECK-RV64:       # %bb.0:
1925; CHECK-RV64-NEXT:    li a0, 63
1926; CHECK-RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1927; CHECK-RV64-NEXT:    vsrl.vx v10, v8, a0
1928; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
1929; CHECK-RV64-NEXT:    vor.vv v8, v8, v10
1930; CHECK-RV64-NEXT:    ret
1931;
1932; CHECK-ZVKB-LABEL: vror_vi_rotl_v4i64:
1933; CHECK-ZVKB:       # %bb.0:
1934; CHECK-ZVKB-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1935; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
1936; CHECK-ZVKB-NEXT:    ret
1937  %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> splat (i64 1))
1938  ret <4 x i64> %x
1939}
1940
1941declare <8 x i64> @llvm.fshr.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
1942declare <8 x i64> @llvm.fshl.v8i64(<8 x i64>, <8 x i64>, <8 x i64>)
1943
1944define <8 x i64> @vror_vv_v8i64(<8 x i64> %a, <8 x i64> %b) {
1945; CHECK-LABEL: vror_vv_v8i64:
1946; CHECK:       # %bb.0:
1947; CHECK-NEXT:    li a0, 63
1948; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1949; CHECK-NEXT:    vrsub.vi v16, v12, 0
1950; CHECK-NEXT:    vand.vx v12, v12, a0
1951; CHECK-NEXT:    vand.vx v16, v16, a0
1952; CHECK-NEXT:    vsrl.vv v12, v8, v12
1953; CHECK-NEXT:    vsll.vv v8, v8, v16
1954; CHECK-NEXT:    vor.vv v8, v12, v8
1955; CHECK-NEXT:    ret
1956;
1957; CHECK-ZVKB-LABEL: vror_vv_v8i64:
1958; CHECK-ZVKB:       # %bb.0:
1959; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1960; CHECK-ZVKB-NEXT:    vror.vv v8, v8, v12
1961; CHECK-ZVKB-NEXT:    ret
1962  %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b)
1963  ret <8 x i64> %x
1964}
1965
1966define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) {
1967; CHECK-RV32-LABEL: vror_vx_v8i64:
1968; CHECK-RV32:       # %bb.0:
1969; CHECK-RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1970; CHECK-RV32-NEXT:    vmv.v.x v12, a0
1971; CHECK-RV32-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
1972; CHECK-RV32-NEXT:    vmv.v.i v16, 0
1973; CHECK-RV32-NEXT:    vwsub.vx v20, v16, a0
1974; CHECK-RV32-NEXT:    li a0, 63
1975; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
1976; CHECK-RV32-NEXT:    vand.vx v12, v12, a0
1977; CHECK-RV32-NEXT:    vand.vx v16, v20, a0
1978; CHECK-RV32-NEXT:    vsll.vv v16, v8, v16
1979; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v12
1980; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
1981; CHECK-RV32-NEXT:    ret
1982;
1983; CHECK-RV64-LABEL: vror_vx_v8i64:
1984; CHECK-RV64:       # %bb.0:
1985; CHECK-RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1986; CHECK-RV64-NEXT:    vmv.v.x v12, a0
1987; CHECK-RV64-NEXT:    li a0, 63
1988; CHECK-RV64-NEXT:    vand.vx v16, v12, a0
1989; CHECK-RV64-NEXT:    vrsub.vi v12, v12, 0
1990; CHECK-RV64-NEXT:    vsrl.vv v16, v8, v16
1991; CHECK-RV64-NEXT:    vand.vx v12, v12, a0
1992; CHECK-RV64-NEXT:    vsll.vv v8, v8, v12
1993; CHECK-RV64-NEXT:    vor.vv v8, v16, v8
1994; CHECK-RV64-NEXT:    ret
1995;
1996; CHECK-ZVKB-LABEL: vror_vx_v8i64:
1997; CHECK-ZVKB:       # %bb.0:
1998; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1999; CHECK-ZVKB-NEXT:    vror.vx v8, v8, a0
2000; CHECK-ZVKB-NEXT:    ret
2001  %b.head = insertelement <8 x i64> poison, i64 %b, i32 0
2002  %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer
2003  %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
2004  ret <8 x i64> %x
2005}
2006
2007define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {
2008; CHECK-RV32-LABEL: vror_vi_v8i64:
2009; CHECK-RV32:       # %bb.0:
2010; CHECK-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
2011; CHECK-RV32-NEXT:    vmv.v.i v12, 0
2012; CHECK-RV32-NEXT:    li a0, 1
2013; CHECK-RV32-NEXT:    vwsubu.vx v16, v12, a0
2014; CHECK-RV32-NEXT:    li a0, 63
2015; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
2016; CHECK-RV32-NEXT:    vmv.v.x v12, a0
2017; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
2018; CHECK-RV32-NEXT:    vand.vi v12, v12, 1
2019; CHECK-RV32-NEXT:    vsll.vv v16, v8, v16
2020; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v12
2021; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
2022; CHECK-RV32-NEXT:    ret
2023;
2024; CHECK-RV64-LABEL: vror_vi_v8i64:
2025; CHECK-RV64:       # %bb.0:
2026; CHECK-RV64-NEXT:    li a0, 63
2027; CHECK-RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
2028; CHECK-RV64-NEXT:    vsll.vx v12, v8, a0
2029; CHECK-RV64-NEXT:    vsrl.vi v8, v8, 1
2030; CHECK-RV64-NEXT:    vor.vv v8, v8, v12
2031; CHECK-RV64-NEXT:    ret
2032;
2033; CHECK-ZVKB-LABEL: vror_vi_v8i64:
2034; CHECK-ZVKB:       # %bb.0:
2035; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
2036; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 1
2037; CHECK-ZVKB-NEXT:    ret
2038  %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> splat (i64 1))
2039  ret <8 x i64> %x
2040}
2041
2042define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) {
2043; CHECK-RV32-LABEL: vror_vi_rotl_v8i64:
2044; CHECK-RV32:       # %bb.0:
2045; CHECK-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
2046; CHECK-RV32-NEXT:    vmv.v.i v12, 0
2047; CHECK-RV32-NEXT:    li a0, 1
2048; CHECK-RV32-NEXT:    vwsubu.vx v16, v12, a0
2049; CHECK-RV32-NEXT:    li a0, 63
2050; CHECK-RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
2051; CHECK-RV32-NEXT:    vmv.v.x v12, a0
2052; CHECK-RV32-NEXT:    vand.vx v16, v16, a0
2053; CHECK-RV32-NEXT:    vand.vi v12, v12, 1
2054; CHECK-RV32-NEXT:    vsrl.vv v16, v8, v16
2055; CHECK-RV32-NEXT:    vsll.vv v8, v8, v12
2056; CHECK-RV32-NEXT:    vor.vv v8, v8, v16
2057; CHECK-RV32-NEXT:    ret
2058;
2059; CHECK-RV64-LABEL: vror_vi_rotl_v8i64:
2060; CHECK-RV64:       # %bb.0:
2061; CHECK-RV64-NEXT:    li a0, 63
2062; CHECK-RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
2063; CHECK-RV64-NEXT:    vsrl.vx v12, v8, a0
2064; CHECK-RV64-NEXT:    vadd.vv v8, v8, v8
2065; CHECK-RV64-NEXT:    vor.vv v8, v8, v12
2066; CHECK-RV64-NEXT:    ret
2067;
2068; CHECK-ZVKB-LABEL: vror_vi_rotl_v8i64:
2069; CHECK-ZVKB:       # %bb.0:
2070; CHECK-ZVKB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
2071; CHECK-ZVKB-NEXT:    vror.vi v8, v8, 63
2072; CHECK-ZVKB-NEXT:    ret
2073  %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> splat (i64 1))
2074  ret <8 x i64> %x
2075}
2076