xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.add.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vadd_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vadd_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
13; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
14; CHECK-NEXT:    ret
15  %v = call <8 x i7> @llvm.vp.add.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
16  ret <8 x i7> %v
17}
18
19declare <2 x i8> @llvm.vp.add.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
20
21define <2 x i8> @vadd_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
22; CHECK-LABEL: vadd_vv_v2i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
25; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
26; CHECK-NEXT:    ret
27  %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
28  ret <2 x i8> %v
29}
30
31define <2 x i8> @vadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
32; CHECK-LABEL: vadd_vv_v2i8_unmasked:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
35; CHECK-NEXT:    vadd.vv v8, v8, v9
36; CHECK-NEXT:    ret
37  %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
38  ret <2 x i8> %v
39}
40
41define <2 x i8> @vadd_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
42; CHECK-LABEL: vadd_vx_v2i8:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
45; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
46; CHECK-NEXT:    ret
47  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
48  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
49  %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
50  ret <2 x i8> %v
51}
52
53define <2 x i8> @vadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
54; CHECK-LABEL: vadd_vx_v2i8_unmasked:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
57; CHECK-NEXT:    vadd.vx v8, v8, a0
58; CHECK-NEXT:    ret
59  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
60  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
61  %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
62  ret <2 x i8> %v
63}
64
65define <2 x i8> @vadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
66; CHECK-LABEL: vadd_vi_v2i8:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
69; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
70; CHECK-NEXT:    ret
71  %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
72  ret <2 x i8> %v
73}
74
75define <2 x i8> @vadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
76; CHECK-LABEL: vadd_vi_v2i8_unmasked:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
79; CHECK-NEXT:    vadd.vi v8, v8, -1
80; CHECK-NEXT:    ret
81  %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
82  ret <2 x i8> %v
83}
84
85declare <4 x i8> @llvm.vp.add.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
86
87define <4 x i8> @vadd_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
88; CHECK-LABEL: vadd_vv_v4i8:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
91; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
92; CHECK-NEXT:    ret
93  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
94  ret <4 x i8> %v
95}
96
97define <4 x i8> @vadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
98; CHECK-LABEL: vadd_vv_v4i8_unmasked:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
101; CHECK-NEXT:    vadd.vv v8, v8, v9
102; CHECK-NEXT:    ret
103  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
104  ret <4 x i8> %v
105}
106
107define <4 x i8> @vadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
108; CHECK-LABEL: vadd_vx_v4i8:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
111; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
112; CHECK-NEXT:    ret
113  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
114  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
115  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
116  ret <4 x i8> %v
117}
118
119define <4 x i8> @vadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
120; CHECK-LABEL: vadd_vx_v4i8_commute:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
123; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
124; CHECK-NEXT:    ret
125  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
126  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
127  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
128  ret <4 x i8> %v
129}
130
131define <4 x i8> @vadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
132; CHECK-LABEL: vadd_vx_v4i8_unmasked:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
135; CHECK-NEXT:    vadd.vx v8, v8, a0
136; CHECK-NEXT:    ret
137  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
138  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
139  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
140  ret <4 x i8> %v
141}
142
143define <4 x i8> @vadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
144; CHECK-LABEL: vadd_vi_v4i8:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
147; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
148; CHECK-NEXT:    ret
149  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
150  ret <4 x i8> %v
151}
152
153define <4 x i8> @vadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
154; CHECK-LABEL: vadd_vi_v4i8_unmasked:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
157; CHECK-NEXT:    vadd.vi v8, v8, -1
158; CHECK-NEXT:    ret
159  %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
160  ret <4 x i8> %v
161}
162
163declare <5 x i8> @llvm.vp.add.v5i8(<5 x i8>, <5 x i8>, <5 x i1>, i32)
164
165define <5 x i8> @vadd_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
166; CHECK-LABEL: vadd_vv_v5i8:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
169; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
170; CHECK-NEXT:    ret
171  %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
172  ret <5 x i8> %v
173}
174
175define <5 x i8> @vadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
176; CHECK-LABEL: vadd_vv_v5i8_unmasked:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
179; CHECK-NEXT:    vadd.vv v8, v8, v9
180; CHECK-NEXT:    ret
181  %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
182  ret <5 x i8> %v
183}
184
185define <5 x i8> @vadd_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
186; CHECK-LABEL: vadd_vx_v5i8:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
189; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
190; CHECK-NEXT:    ret
191  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
192  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
193  %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)
194  ret <5 x i8> %v
195}
196
197define <5 x i8> @vadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
198; CHECK-LABEL: vadd_vx_v5i8_unmasked:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
201; CHECK-NEXT:    vadd.vx v8, v8, a0
202; CHECK-NEXT:    ret
203  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
204  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
205  %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)
206  ret <5 x i8> %v
207}
208
209define <5 x i8> @vadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
210; CHECK-LABEL: vadd_vi_v5i8:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
213; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
214; CHECK-NEXT:    ret
215  %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
216  ret <5 x i8> %v
217}
218
219define <5 x i8> @vadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
220; CHECK-LABEL: vadd_vi_v5i8_unmasked:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
223; CHECK-NEXT:    vadd.vi v8, v8, -1
224; CHECK-NEXT:    ret
225  %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
226  ret <5 x i8> %v
227}
228
229declare <8 x i8> @llvm.vp.add.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
230
231define <8 x i8> @vadd_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
232; CHECK-LABEL: vadd_vv_v8i8:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
235; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
236; CHECK-NEXT:    ret
237  %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
238  ret <8 x i8> %v
239}
240
241define <8 x i8> @vadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
242; CHECK-LABEL: vadd_vv_v8i8_unmasked:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
245; CHECK-NEXT:    vadd.vv v8, v8, v9
246; CHECK-NEXT:    ret
247  %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
248  ret <8 x i8> %v
249}
250
251define <8 x i8> @vadd_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
252; CHECK-LABEL: vadd_vx_v8i8:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
255; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
256; CHECK-NEXT:    ret
257  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
258  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
259  %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
260  ret <8 x i8> %v
261}
262
263define <8 x i8> @vadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
264; CHECK-LABEL: vadd_vx_v8i8_unmasked:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
267; CHECK-NEXT:    vadd.vx v8, v8, a0
268; CHECK-NEXT:    ret
269  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
270  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
271  %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
272  ret <8 x i8> %v
273}
274
275define <8 x i8> @vadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
276; CHECK-LABEL: vadd_vi_v8i8:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
279; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
280; CHECK-NEXT:    ret
281  %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
282  ret <8 x i8> %v
283}
284
285define <8 x i8> @vadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
286; CHECK-LABEL: vadd_vi_v8i8_unmasked:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
289; CHECK-NEXT:    vadd.vi v8, v8, -1
290; CHECK-NEXT:    ret
291  %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
292  ret <8 x i8> %v
293}
294
295declare <16 x i8> @llvm.vp.add.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
296
297define <16 x i8> @vadd_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
298; CHECK-LABEL: vadd_vv_v16i8:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
301; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
302; CHECK-NEXT:    ret
303  %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
304  ret <16 x i8> %v
305}
306
307define <16 x i8> @vadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
308; CHECK-LABEL: vadd_vv_v16i8_unmasked:
309; CHECK:       # %bb.0:
310; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
311; CHECK-NEXT:    vadd.vv v8, v8, v9
312; CHECK-NEXT:    ret
313  %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
314  ret <16 x i8> %v
315}
316
317define <16 x i8> @vadd_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
318; CHECK-LABEL: vadd_vx_v16i8:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
321; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
322; CHECK-NEXT:    ret
323  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
324  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
325  %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
326  ret <16 x i8> %v
327}
328
329define <16 x i8> @vadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
330; CHECK-LABEL: vadd_vx_v16i8_unmasked:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
333; CHECK-NEXT:    vadd.vx v8, v8, a0
334; CHECK-NEXT:    ret
335  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
336  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
337  %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
338  ret <16 x i8> %v
339}
340
341define <16 x i8> @vadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
342; CHECK-LABEL: vadd_vi_v16i8:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
345; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
346; CHECK-NEXT:    ret
347  %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
348  ret <16 x i8> %v
349}
350
351define <16 x i8> @vadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
352; CHECK-LABEL: vadd_vi_v16i8_unmasked:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
355; CHECK-NEXT:    vadd.vi v8, v8, -1
356; CHECK-NEXT:    ret
357  %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
358  ret <16 x i8> %v
359}
360
361declare <256 x i8> @llvm.vp.add.v258i8(<256 x i8>, <256 x i8>, <256 x i1>, i32)
362
363define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
364; CHECK-LABEL: vadd_vi_v258i8:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
367; CHECK-NEXT:    vmv1r.v v24, v0
368; CHECK-NEXT:    li a2, 128
369; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
370; CHECK-NEXT:    vlm.v v0, (a0)
371; CHECK-NEXT:    addi a0, a1, -128
372; CHECK-NEXT:    sltu a3, a1, a0
373; CHECK-NEXT:    addi a3, a3, -1
374; CHECK-NEXT:    and a0, a3, a0
375; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
376; CHECK-NEXT:    vadd.vi v16, v16, -1, v0.t
377; CHECK-NEXT:    bltu a1, a2, .LBB32_2
378; CHECK-NEXT:  # %bb.1:
379; CHECK-NEXT:    li a1, 128
380; CHECK-NEXT:  .LBB32_2:
381; CHECK-NEXT:    vmv1r.v v0, v24
382; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
383; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
384; CHECK-NEXT:    ret
385  %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
386  ret <256 x i8> %v
387}
388
389define <256 x i8> @vadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
390; CHECK-LABEL: vadd_vi_v258i8_unmasked:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    li a2, 128
393; CHECK-NEXT:    mv a1, a0
394; CHECK-NEXT:    bltu a0, a2, .LBB33_2
395; CHECK-NEXT:  # %bb.1:
396; CHECK-NEXT:    li a1, 128
397; CHECK-NEXT:  .LBB33_2:
398; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
399; CHECK-NEXT:    vadd.vi v8, v8, -1
400; CHECK-NEXT:    addi a1, a0, -128
401; CHECK-NEXT:    sltu a0, a0, a1
402; CHECK-NEXT:    addi a0, a0, -1
403; CHECK-NEXT:    and a0, a0, a1
404; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
405; CHECK-NEXT:    vadd.vi v16, v16, -1
406; CHECK-NEXT:    ret
407  %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
408  ret <256 x i8> %v
409}
410
411; Test splitting when the %evl is a known constant.
412
413define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
414; CHECK-LABEL: vadd_vi_v258i8_evl129:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    li a1, 128
417; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
418; CHECK-NEXT:    vlm.v v24, (a0)
419; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
420; CHECK-NEXT:    vmv1r.v v0, v24
421; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
422; CHECK-NEXT:    vadd.vi v16, v16, -1, v0.t
423; CHECK-NEXT:    ret
424  %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
425  ret <256 x i8> %v
426}
427
428; FIXME: The upper half is doing nothing.
429
430define <256 x i8> @vadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
431; CHECK-LABEL: vadd_vi_v258i8_evl128:
432; CHECK:       # %bb.0:
433; CHECK-NEXT:    li a0, 128
434; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
435; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
436; CHECK-NEXT:    ret
437  %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
438  ret <256 x i8> %v
439}
440
441declare <2 x i16> @llvm.vp.add.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
442
443define <2 x i16> @vadd_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
444; CHECK-LABEL: vadd_vv_v2i16:
445; CHECK:       # %bb.0:
446; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
447; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
448; CHECK-NEXT:    ret
449  %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
450  ret <2 x i16> %v
451}
452
453define <2 x i16> @vadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
454; CHECK-LABEL: vadd_vv_v2i16_unmasked:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
457; CHECK-NEXT:    vadd.vv v8, v8, v9
458; CHECK-NEXT:    ret
459  %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
460  ret <2 x i16> %v
461}
462
463define <2 x i16> @vadd_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
464; CHECK-LABEL: vadd_vx_v2i16:
465; CHECK:       # %bb.0:
466; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
467; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
468; CHECK-NEXT:    ret
469  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
470  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
471  %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
472  ret <2 x i16> %v
473}
474
475define <2 x i16> @vadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
476; CHECK-LABEL: vadd_vx_v2i16_unmasked:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
479; CHECK-NEXT:    vadd.vx v8, v8, a0
480; CHECK-NEXT:    ret
481  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
482  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
483  %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
484  ret <2 x i16> %v
485}
486
487define <2 x i16> @vadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
488; CHECK-LABEL: vadd_vi_v2i16:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
491; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
492; CHECK-NEXT:    ret
493  %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
494  ret <2 x i16> %v
495}
496
497define <2 x i16> @vadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
498; CHECK-LABEL: vadd_vi_v2i16_unmasked:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
501; CHECK-NEXT:    vadd.vi v8, v8, -1
502; CHECK-NEXT:    ret
503  %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
504  ret <2 x i16> %v
505}
506
507declare <4 x i16> @llvm.vp.add.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
508
509define <4 x i16> @vadd_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
510; CHECK-LABEL: vadd_vv_v4i16:
511; CHECK:       # %bb.0:
512; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
513; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
514; CHECK-NEXT:    ret
515  %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
516  ret <4 x i16> %v
517}
518
519define <4 x i16> @vadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
520; CHECK-LABEL: vadd_vv_v4i16_unmasked:
521; CHECK:       # %bb.0:
522; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
523; CHECK-NEXT:    vadd.vv v8, v8, v9
524; CHECK-NEXT:    ret
525  %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
526  ret <4 x i16> %v
527}
528
529define <4 x i16> @vadd_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
530; CHECK-LABEL: vadd_vx_v4i16:
531; CHECK:       # %bb.0:
532; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
533; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
534; CHECK-NEXT:    ret
535  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
536  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
537  %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
538  ret <4 x i16> %v
539}
540
541define <4 x i16> @vadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
542; CHECK-LABEL: vadd_vx_v4i16_unmasked:
543; CHECK:       # %bb.0:
544; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
545; CHECK-NEXT:    vadd.vx v8, v8, a0
546; CHECK-NEXT:    ret
547  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
548  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
549  %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
550  ret <4 x i16> %v
551}
552
553define <4 x i16> @vadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
554; CHECK-LABEL: vadd_vi_v4i16:
555; CHECK:       # %bb.0:
556; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
557; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
558; CHECK-NEXT:    ret
559  %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
560  ret <4 x i16> %v
561}
562
563define <4 x i16> @vadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
564; CHECK-LABEL: vadd_vi_v4i16_unmasked:
565; CHECK:       # %bb.0:
566; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
567; CHECK-NEXT:    vadd.vi v8, v8, -1
568; CHECK-NEXT:    ret
569  %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
570  ret <4 x i16> %v
571}
572
573declare <8 x i16> @llvm.vp.add.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
574
575define <8 x i16> @vadd_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
576; CHECK-LABEL: vadd_vv_v8i16:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
579; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
580; CHECK-NEXT:    ret
581  %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
582  ret <8 x i16> %v
583}
584
585define <8 x i16> @vadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
586; CHECK-LABEL: vadd_vv_v8i16_unmasked:
587; CHECK:       # %bb.0:
588; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
589; CHECK-NEXT:    vadd.vv v8, v8, v9
590; CHECK-NEXT:    ret
591  %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
592  ret <8 x i16> %v
593}
594
595define <8 x i16> @vadd_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
596; CHECK-LABEL: vadd_vx_v8i16:
597; CHECK:       # %bb.0:
598; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
599; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
600; CHECK-NEXT:    ret
601  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
602  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
603  %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
604  ret <8 x i16> %v
605}
606
607define <8 x i16> @vadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
608; CHECK-LABEL: vadd_vx_v8i16_unmasked:
609; CHECK:       # %bb.0:
610; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
611; CHECK-NEXT:    vadd.vx v8, v8, a0
612; CHECK-NEXT:    ret
613  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
614  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
615  %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
616  ret <8 x i16> %v
617}
618
619define <8 x i16> @vadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
620; CHECK-LABEL: vadd_vi_v8i16:
621; CHECK:       # %bb.0:
622; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
623; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
624; CHECK-NEXT:    ret
625  %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
626  ret <8 x i16> %v
627}
628
629define <8 x i16> @vadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
630; CHECK-LABEL: vadd_vi_v8i16_unmasked:
631; CHECK:       # %bb.0:
632; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
633; CHECK-NEXT:    vadd.vi v8, v8, -1
634; CHECK-NEXT:    ret
635  %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
636  ret <8 x i16> %v
637}
638
639declare <16 x i16> @llvm.vp.add.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
640
641define <16 x i16> @vadd_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
642; CHECK-LABEL: vadd_vv_v16i16:
643; CHECK:       # %bb.0:
644; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
645; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t
646; CHECK-NEXT:    ret
647  %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
648  ret <16 x i16> %v
649}
650
651define <16 x i16> @vadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
652; CHECK-LABEL: vadd_vv_v16i16_unmasked:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
655; CHECK-NEXT:    vadd.vv v8, v8, v10
656; CHECK-NEXT:    ret
657  %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
658  ret <16 x i16> %v
659}
660
661define <16 x i16> @vadd_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
662; CHECK-LABEL: vadd_vx_v16i16:
663; CHECK:       # %bb.0:
664; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
665; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
666; CHECK-NEXT:    ret
667  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
668  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
669  %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
670  ret <16 x i16> %v
671}
672
673define <16 x i16> @vadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
674; CHECK-LABEL: vadd_vx_v16i16_unmasked:
675; CHECK:       # %bb.0:
676; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
677; CHECK-NEXT:    vadd.vx v8, v8, a0
678; CHECK-NEXT:    ret
679  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
680  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
681  %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
682  ret <16 x i16> %v
683}
684
685define <16 x i16> @vadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
686; CHECK-LABEL: vadd_vi_v16i16:
687; CHECK:       # %bb.0:
688; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
689; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
690; CHECK-NEXT:    ret
691  %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
692  ret <16 x i16> %v
693}
694
695define <16 x i16> @vadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
696; CHECK-LABEL: vadd_vi_v16i16_unmasked:
697; CHECK:       # %bb.0:
698; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
699; CHECK-NEXT:    vadd.vi v8, v8, -1
700; CHECK-NEXT:    ret
701  %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
702  ret <16 x i16> %v
703}
704
705declare <2 x i32> @llvm.vp.add.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
706
707define <2 x i32> @vadd_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
708; CHECK-LABEL: vadd_vv_v2i32:
709; CHECK:       # %bb.0:
710; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
711; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
712; CHECK-NEXT:    ret
713  %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
714  ret <2 x i32> %v
715}
716
717define <2 x i32> @vadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
718; CHECK-LABEL: vadd_vv_v2i32_unmasked:
719; CHECK:       # %bb.0:
720; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
721; CHECK-NEXT:    vadd.vv v8, v8, v9
722; CHECK-NEXT:    ret
723  %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
724  ret <2 x i32> %v
725}
726
727define <2 x i32> @vadd_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
728; CHECK-LABEL: vadd_vx_v2i32:
729; CHECK:       # %bb.0:
730; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
731; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
732; CHECK-NEXT:    ret
733  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
734  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
735  %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
736  ret <2 x i32> %v
737}
738
739define <2 x i32> @vadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
740; CHECK-LABEL: vadd_vx_v2i32_unmasked:
741; CHECK:       # %bb.0:
742; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
743; CHECK-NEXT:    vadd.vx v8, v8, a0
744; CHECK-NEXT:    ret
745  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
746  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
747  %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
748  ret <2 x i32> %v
749}
750
751define <2 x i32> @vadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
752; CHECK-LABEL: vadd_vi_v2i32:
753; CHECK:       # %bb.0:
754; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
755; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
756; CHECK-NEXT:    ret
757  %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
758  ret <2 x i32> %v
759}
760
761define <2 x i32> @vadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
762; CHECK-LABEL: vadd_vi_v2i32_unmasked:
763; CHECK:       # %bb.0:
764; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
765; CHECK-NEXT:    vadd.vi v8, v8, -1
766; CHECK-NEXT:    ret
767  %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
768  ret <2 x i32> %v
769}
770
771declare <4 x i32> @llvm.vp.add.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
772
773define <4 x i32> @vadd_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
774; CHECK-LABEL: vadd_vv_v4i32:
775; CHECK:       # %bb.0:
776; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
777; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
778; CHECK-NEXT:    ret
779  %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
780  ret <4 x i32> %v
781}
782
783define <4 x i32> @vadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
784; CHECK-LABEL: vadd_vv_v4i32_unmasked:
785; CHECK:       # %bb.0:
786; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
787; CHECK-NEXT:    vadd.vv v8, v8, v9
788; CHECK-NEXT:    ret
789  %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
790  ret <4 x i32> %v
791}
792
793define <4 x i32> @vadd_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
794; CHECK-LABEL: vadd_vx_v4i32:
795; CHECK:       # %bb.0:
796; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
797; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
798; CHECK-NEXT:    ret
799  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
800  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
801  %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
802  ret <4 x i32> %v
803}
804
805define <4 x i32> @vadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
806; CHECK-LABEL: vadd_vx_v4i32_unmasked:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
809; CHECK-NEXT:    vadd.vx v8, v8, a0
810; CHECK-NEXT:    ret
811  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
812  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
813  %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
814  ret <4 x i32> %v
815}
816
817define <4 x i32> @vadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
818; CHECK-LABEL: vadd_vi_v4i32:
819; CHECK:       # %bb.0:
820; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
821; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
822; CHECK-NEXT:    ret
823  %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
824  ret <4 x i32> %v
825}
826
827define <4 x i32> @vadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
828; CHECK-LABEL: vadd_vi_v4i32_unmasked:
829; CHECK:       # %bb.0:
830; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
831; CHECK-NEXT:    vadd.vi v8, v8, -1
832; CHECK-NEXT:    ret
833  %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
834  ret <4 x i32> %v
835}
836
837declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
838
839define <8 x i32> @vadd_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
840; CHECK-LABEL: vadd_vv_v8i32:
841; CHECK:       # %bb.0:
842; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
843; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t
844; CHECK-NEXT:    ret
845  %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
846  ret <8 x i32> %v
847}
848
849define <8 x i32> @vadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
850; CHECK-LABEL: vadd_vv_v8i32_unmasked:
851; CHECK:       # %bb.0:
852; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
853; CHECK-NEXT:    vadd.vv v8, v8, v10
854; CHECK-NEXT:    ret
855  %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
856  ret <8 x i32> %v
857}
858
859define <8 x i32> @vadd_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
860; CHECK-LABEL: vadd_vx_v8i32:
861; CHECK:       # %bb.0:
862; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
863; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
864; CHECK-NEXT:    ret
865  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
866  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
867  %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
868  ret <8 x i32> %v
869}
870
871define <8 x i32> @vadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
872; CHECK-LABEL: vadd_vx_v8i32_unmasked:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
875; CHECK-NEXT:    vadd.vx v8, v8, a0
876; CHECK-NEXT:    ret
877  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
878  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
879  %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
880  ret <8 x i32> %v
881}
882
883define <8 x i32> @vadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
884; CHECK-LABEL: vadd_vi_v8i32:
885; CHECK:       # %bb.0:
886; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
887; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
888; CHECK-NEXT:    ret
889  %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
890  ret <8 x i32> %v
891}
892
893define <8 x i32> @vadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
894; CHECK-LABEL: vadd_vi_v8i32_unmasked:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
897; CHECK-NEXT:    vadd.vi v8, v8, -1
898; CHECK-NEXT:    ret
899  %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
900  ret <8 x i32> %v
901}
902
903declare <16 x i32> @llvm.vp.add.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
904
905define <16 x i32> @vadd_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
906; CHECK-LABEL: vadd_vv_v16i32:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
909; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t
910; CHECK-NEXT:    ret
911  %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
912  ret <16 x i32> %v
913}
914
915define <16 x i32> @vadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
916; CHECK-LABEL: vadd_vv_v16i32_unmasked:
917; CHECK:       # %bb.0:
918; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
919; CHECK-NEXT:    vadd.vv v8, v8, v12
920; CHECK-NEXT:    ret
921  %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
922  ret <16 x i32> %v
923}
924
925define <16 x i32> @vadd_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
926; CHECK-LABEL: vadd_vx_v16i32:
927; CHECK:       # %bb.0:
928; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
929; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
930; CHECK-NEXT:    ret
931  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
932  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
933  %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
934  ret <16 x i32> %v
935}
936
937define <16 x i32> @vadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
938; CHECK-LABEL: vadd_vx_v16i32_unmasked:
939; CHECK:       # %bb.0:
940; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
941; CHECK-NEXT:    vadd.vx v8, v8, a0
942; CHECK-NEXT:    ret
943  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
944  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
945  %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
946  ret <16 x i32> %v
947}
948
949define <16 x i32> @vadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
950; CHECK-LABEL: vadd_vi_v16i32:
951; CHECK:       # %bb.0:
952; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
953; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
954; CHECK-NEXT:    ret
955  %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
956  ret <16 x i32> %v
957}
958
959define <16 x i32> @vadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
960; CHECK-LABEL: vadd_vi_v16i32_unmasked:
961; CHECK:       # %bb.0:
962; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
963; CHECK-NEXT:    vadd.vi v8, v8, -1
964; CHECK-NEXT:    ret
965  %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
966  ret <16 x i32> %v
967}
968
969declare <2 x i64> @llvm.vp.add.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
970
971define <2 x i64> @vadd_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
972; CHECK-LABEL: vadd_vv_v2i64:
973; CHECK:       # %bb.0:
974; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
975; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
976; CHECK-NEXT:    ret
977  %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
978  ret <2 x i64> %v
979}
980
981define <2 x i64> @vadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
982; CHECK-LABEL: vadd_vv_v2i64_unmasked:
983; CHECK:       # %bb.0:
984; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
985; CHECK-NEXT:    vadd.vv v8, v8, v9
986; CHECK-NEXT:    ret
987  %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
988  ret <2 x i64> %v
989}
990
991define <2 x i64> @vadd_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
992; RV32-LABEL: vadd_vx_v2i64:
993; RV32:       # %bb.0:
994; RV32-NEXT:    addi sp, sp, -16
995; RV32-NEXT:    .cfi_def_cfa_offset 16
996; RV32-NEXT:    sw a0, 8(sp)
997; RV32-NEXT:    sw a1, 12(sp)
998; RV32-NEXT:    addi a0, sp, 8
999; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1000; RV32-NEXT:    vlse64.v v9, (a0), zero
1001; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1002; RV32-NEXT:    vadd.vv v8, v8, v9, v0.t
1003; RV32-NEXT:    addi sp, sp, 16
1004; RV32-NEXT:    .cfi_def_cfa_offset 0
1005; RV32-NEXT:    ret
1006;
1007; RV64-LABEL: vadd_vx_v2i64:
1008; RV64:       # %bb.0:
1009; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1010; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t
1011; RV64-NEXT:    ret
1012  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1013  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1014  %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
1015  ret <2 x i64> %v
1016}
1017
1018define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
1019; RV32-LABEL: vadd_vx_v2i64_unmasked:
1020; RV32:       # %bb.0:
1021; RV32-NEXT:    addi sp, sp, -16
1022; RV32-NEXT:    .cfi_def_cfa_offset 16
1023; RV32-NEXT:    sw a0, 8(sp)
1024; RV32-NEXT:    sw a1, 12(sp)
1025; RV32-NEXT:    addi a0, sp, 8
1026; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1027; RV32-NEXT:    vlse64.v v9, (a0), zero
1028; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1029; RV32-NEXT:    vadd.vv v8, v8, v9
1030; RV32-NEXT:    addi sp, sp, 16
1031; RV32-NEXT:    .cfi_def_cfa_offset 0
1032; RV32-NEXT:    ret
1033;
1034; RV64-LABEL: vadd_vx_v2i64_unmasked:
1035; RV64:       # %bb.0:
1036; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1037; RV64-NEXT:    vadd.vx v8, v8, a0
1038; RV64-NEXT:    ret
1039  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1040  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1041  %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
1042  ret <2 x i64> %v
1043}
1044
1045define <2 x i64> @vadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
1046; CHECK-LABEL: vadd_vi_v2i64:
1047; CHECK:       # %bb.0:
1048; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1049; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1050; CHECK-NEXT:    ret
1051  %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
1052  ret <2 x i64> %v
1053}
1054
1055define <2 x i64> @vadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
1056; CHECK-LABEL: vadd_vi_v2i64_unmasked:
1057; CHECK:       # %bb.0:
1058; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1059; CHECK-NEXT:    vadd.vi v8, v8, -1
1060; CHECK-NEXT:    ret
1061  %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
1062  ret <2 x i64> %v
1063}
1064
1065declare <4 x i64> @llvm.vp.add.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
1066
1067define <4 x i64> @vadd_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
1068; CHECK-LABEL: vadd_vv_v4i64:
1069; CHECK:       # %bb.0:
1070; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1071; CHECK-NEXT:    vadd.vv v8, v8, v10, v0.t
1072; CHECK-NEXT:    ret
1073  %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1074  ret <4 x i64> %v
1075}
1076
1077define <4 x i64> @vadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
1078; CHECK-LABEL: vadd_vv_v4i64_unmasked:
1079; CHECK:       # %bb.0:
1080; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1081; CHECK-NEXT:    vadd.vv v8, v8, v10
1082; CHECK-NEXT:    ret
1083  %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
1084  ret <4 x i64> %v
1085}
1086
1087define <4 x i64> @vadd_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1088; RV32-LABEL: vadd_vx_v4i64:
1089; RV32:       # %bb.0:
1090; RV32-NEXT:    addi sp, sp, -16
1091; RV32-NEXT:    .cfi_def_cfa_offset 16
1092; RV32-NEXT:    sw a0, 8(sp)
1093; RV32-NEXT:    sw a1, 12(sp)
1094; RV32-NEXT:    addi a0, sp, 8
1095; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1096; RV32-NEXT:    vlse64.v v10, (a0), zero
1097; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1098; RV32-NEXT:    vadd.vv v8, v8, v10, v0.t
1099; RV32-NEXT:    addi sp, sp, 16
1100; RV32-NEXT:    .cfi_def_cfa_offset 0
1101; RV32-NEXT:    ret
1102;
1103; RV64-LABEL: vadd_vx_v4i64:
1104; RV64:       # %bb.0:
1105; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1106; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t
1107; RV64-NEXT:    ret
1108  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1109  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1110  %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1111  ret <4 x i64> %v
1112}
1113
1114define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1115; RV32-LABEL: vadd_vx_v4i64_unmasked:
1116; RV32:       # %bb.0:
1117; RV32-NEXT:    addi sp, sp, -16
1118; RV32-NEXT:    .cfi_def_cfa_offset 16
1119; RV32-NEXT:    sw a0, 8(sp)
1120; RV32-NEXT:    sw a1, 12(sp)
1121; RV32-NEXT:    addi a0, sp, 8
1122; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1123; RV32-NEXT:    vlse64.v v10, (a0), zero
1124; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1125; RV32-NEXT:    vadd.vv v8, v8, v10
1126; RV32-NEXT:    addi sp, sp, 16
1127; RV32-NEXT:    .cfi_def_cfa_offset 0
1128; RV32-NEXT:    ret
1129;
1130; RV64-LABEL: vadd_vx_v4i64_unmasked:
1131; RV64:       # %bb.0:
1132; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1133; RV64-NEXT:    vadd.vx v8, v8, a0
1134; RV64-NEXT:    ret
1135  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1136  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1137  %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
1138  ret <4 x i64> %v
1139}
1140
1141define <4 x i64> @vadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1142; CHECK-LABEL: vadd_vi_v4i64:
1143; CHECK:       # %bb.0:
1144; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1145; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1146; CHECK-NEXT:    ret
1147  %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
1148  ret <4 x i64> %v
1149}
1150
1151define <4 x i64> @vadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1152; CHECK-LABEL: vadd_vi_v4i64_unmasked:
1153; CHECK:       # %bb.0:
1154; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1155; CHECK-NEXT:    vadd.vi v8, v8, -1
1156; CHECK-NEXT:    ret
1157  %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
1158  ret <4 x i64> %v
1159}
1160
1161declare <8 x i64> @llvm.vp.add.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1162
1163define <8 x i64> @vadd_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1164; CHECK-LABEL: vadd_vv_v8i64:
1165; CHECK:       # %bb.0:
1166; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1167; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t
1168; CHECK-NEXT:    ret
1169  %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1170  ret <8 x i64> %v
1171}
1172
1173define <8 x i64> @vadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1174; CHECK-LABEL: vadd_vv_v8i64_unmasked:
1175; CHECK:       # %bb.0:
1176; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1177; CHECK-NEXT:    vadd.vv v8, v8, v12
1178; CHECK-NEXT:    ret
1179  %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
1180  ret <8 x i64> %v
1181}
1182
1183define <8 x i64> @vadd_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1184; RV32-LABEL: vadd_vx_v8i64:
1185; RV32:       # %bb.0:
1186; RV32-NEXT:    addi sp, sp, -16
1187; RV32-NEXT:    .cfi_def_cfa_offset 16
1188; RV32-NEXT:    sw a0, 8(sp)
1189; RV32-NEXT:    sw a1, 12(sp)
1190; RV32-NEXT:    addi a0, sp, 8
1191; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1192; RV32-NEXT:    vlse64.v v12, (a0), zero
1193; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1194; RV32-NEXT:    vadd.vv v8, v8, v12, v0.t
1195; RV32-NEXT:    addi sp, sp, 16
1196; RV32-NEXT:    .cfi_def_cfa_offset 0
1197; RV32-NEXT:    ret
1198;
1199; RV64-LABEL: vadd_vx_v8i64:
1200; RV64:       # %bb.0:
1201; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1202; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t
1203; RV64-NEXT:    ret
1204  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1205  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1206  %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1207  ret <8 x i64> %v
1208}
1209
1210define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1211; RV32-LABEL: vadd_vx_v8i64_unmasked:
1212; RV32:       # %bb.0:
1213; RV32-NEXT:    addi sp, sp, -16
1214; RV32-NEXT:    .cfi_def_cfa_offset 16
1215; RV32-NEXT:    sw a0, 8(sp)
1216; RV32-NEXT:    sw a1, 12(sp)
1217; RV32-NEXT:    addi a0, sp, 8
1218; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1219; RV32-NEXT:    vlse64.v v12, (a0), zero
1220; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1221; RV32-NEXT:    vadd.vv v8, v8, v12
1222; RV32-NEXT:    addi sp, sp, 16
1223; RV32-NEXT:    .cfi_def_cfa_offset 0
1224; RV32-NEXT:    ret
1225;
1226; RV64-LABEL: vadd_vx_v8i64_unmasked:
1227; RV64:       # %bb.0:
1228; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1229; RV64-NEXT:    vadd.vx v8, v8, a0
1230; RV64-NEXT:    ret
1231  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1232  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1233  %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
1234  ret <8 x i64> %v
1235}
1236
1237define <8 x i64> @vadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1238; CHECK-LABEL: vadd_vi_v8i64:
1239; CHECK:       # %bb.0:
1240; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1241; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1242; CHECK-NEXT:    ret
1243  %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
1244  ret <8 x i64> %v
1245}
1246
1247define <8 x i64> @vadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1248; CHECK-LABEL: vadd_vi_v8i64_unmasked:
1249; CHECK:       # %bb.0:
1250; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1251; CHECK-NEXT:    vadd.vi v8, v8, -1
1252; CHECK-NEXT:    ret
1253  %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
1254  ret <8 x i64> %v
1255}
1256
1257declare <16 x i64> @llvm.vp.add.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1258
1259define <16 x i64> @vadd_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1260; CHECK-LABEL: vadd_vv_v16i64:
1261; CHECK:       # %bb.0:
1262; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1263; CHECK-NEXT:    vadd.vv v8, v8, v16, v0.t
1264; CHECK-NEXT:    ret
1265  %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1266  ret <16 x i64> %v
1267}
1268
1269define <16 x i64> @vadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1270; CHECK-LABEL: vadd_vv_v16i64_unmasked:
1271; CHECK:       # %bb.0:
1272; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1273; CHECK-NEXT:    vadd.vv v8, v8, v16
1274; CHECK-NEXT:    ret
1275  %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
1276  ret <16 x i64> %v
1277}
1278
1279define <16 x i64> @vadd_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1280; RV32-LABEL: vadd_vx_v16i64:
1281; RV32:       # %bb.0:
1282; RV32-NEXT:    addi sp, sp, -16
1283; RV32-NEXT:    .cfi_def_cfa_offset 16
1284; RV32-NEXT:    sw a0, 8(sp)
1285; RV32-NEXT:    sw a1, 12(sp)
1286; RV32-NEXT:    addi a0, sp, 8
1287; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1288; RV32-NEXT:    vlse64.v v16, (a0), zero
1289; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1290; RV32-NEXT:    vadd.vv v8, v8, v16, v0.t
1291; RV32-NEXT:    addi sp, sp, 16
1292; RV32-NEXT:    .cfi_def_cfa_offset 0
1293; RV32-NEXT:    ret
1294;
1295; RV64-LABEL: vadd_vx_v16i64:
1296; RV64:       # %bb.0:
1297; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1298; RV64-NEXT:    vadd.vx v8, v8, a0, v0.t
1299; RV64-NEXT:    ret
1300  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1301  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1302  %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1303  ret <16 x i64> %v
1304}
1305
1306define <16 x i64> @vadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1307; RV32-LABEL: vadd_vx_v16i64_unmasked:
1308; RV32:       # %bb.0:
1309; RV32-NEXT:    addi sp, sp, -16
1310; RV32-NEXT:    .cfi_def_cfa_offset 16
1311; RV32-NEXT:    sw a0, 8(sp)
1312; RV32-NEXT:    sw a1, 12(sp)
1313; RV32-NEXT:    addi a0, sp, 8
1314; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1315; RV32-NEXT:    vlse64.v v16, (a0), zero
1316; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1317; RV32-NEXT:    vadd.vv v8, v8, v16
1318; RV32-NEXT:    addi sp, sp, 16
1319; RV32-NEXT:    .cfi_def_cfa_offset 0
1320; RV32-NEXT:    ret
1321;
1322; RV64-LABEL: vadd_vx_v16i64_unmasked:
1323; RV64:       # %bb.0:
1324; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1325; RV64-NEXT:    vadd.vx v8, v8, a0
1326; RV64-NEXT:    ret
1327  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1328  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1329  %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1330  ret <16 x i64> %v
1331}
1332
1333define <16 x i64> @vadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1334; CHECK-LABEL: vadd_vi_v16i64:
1335; CHECK:       # %bb.0:
1336; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1337; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1338; CHECK-NEXT:    ret
1339  %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
1340  ret <16 x i64> %v
1341}
1342
1343define <16 x i64> @vadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1344; CHECK-LABEL: vadd_vi_v16i64_unmasked:
1345; CHECK:       # %bb.0:
1346; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1347; CHECK-NEXT:    vadd.vi v8, v8, -1
1348; CHECK-NEXT:    ret
1349  %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
1350  ret <16 x i64> %v
1351}
1352
1353; Test that split-legalization works as expected.
1354
1355declare <32 x i64> @llvm.vp.add.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
1356
1357define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
1358; CHECK-LABEL: vadd_vx_v32i64:
1359; CHECK:       # %bb.0:
1360; CHECK-NEXT:    li a2, 16
1361; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1362; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1363; CHECK-NEXT:    mv a1, a0
1364; CHECK-NEXT:    bltu a0, a2, .LBB108_2
1365; CHECK-NEXT:  # %bb.1:
1366; CHECK-NEXT:    li a1, 16
1367; CHECK-NEXT:  .LBB108_2:
1368; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1369; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1370; CHECK-NEXT:    addi a1, a0, -16
1371; CHECK-NEXT:    sltu a0, a0, a1
1372; CHECK-NEXT:    addi a0, a0, -1
1373; CHECK-NEXT:    and a0, a0, a1
1374; CHECK-NEXT:    vmv1r.v v0, v24
1375; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1376; CHECK-NEXT:    vadd.vi v16, v16, -1, v0.t
1377; CHECK-NEXT:    ret
1378  %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
1379  ret <32 x i64> %v
1380}
1381
1382define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
1383; CHECK-LABEL: vadd_vi_v32i64_unmasked:
1384; CHECK:       # %bb.0:
1385; CHECK-NEXT:    li a2, 16
1386; CHECK-NEXT:    mv a1, a0
1387; CHECK-NEXT:    bltu a0, a2, .LBB109_2
1388; CHECK-NEXT:  # %bb.1:
1389; CHECK-NEXT:    li a1, 16
1390; CHECK-NEXT:  .LBB109_2:
1391; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1392; CHECK-NEXT:    vadd.vi v8, v8, -1
1393; CHECK-NEXT:    addi a1, a0, -16
1394; CHECK-NEXT:    sltu a0, a0, a1
1395; CHECK-NEXT:    addi a0, a0, -1
1396; CHECK-NEXT:    and a0, a0, a1
1397; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1398; CHECK-NEXT:    vadd.vi v16, v16, -1
1399; CHECK-NEXT:    ret
1400  %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
1401  ret <32 x i64> %v
1402}
1403
1404define <32 x i64> @vadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
1405; CHECK-LABEL: vadd_vx_v32i64_evl12:
1406; CHECK:       # %bb.0:
1407; CHECK-NEXT:    vsetivli zero, 12, e64, m8, ta, ma
1408; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1409; CHECK-NEXT:    ret
1410  %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
1411  ret <32 x i64> %v
1412}
1413
1414define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
1415; CHECK-LABEL: vadd_vx_v32i64_evl27:
1416; CHECK:       # %bb.0:
1417; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1418; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1419; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1420; CHECK-NEXT:    vadd.vi v8, v8, -1, v0.t
1421; CHECK-NEXT:    vmv1r.v v0, v24
1422; CHECK-NEXT:    vsetivli zero, 11, e64, m8, ta, ma
1423; CHECK-NEXT:    vadd.vi v16, v16, -1, v0.t
1424; CHECK-NEXT:    ret
1425  %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
1426  ret <32 x i64> %v
1427}
1428