xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
4
5define void @store_v5i8(ptr %p, <5 x i8> %v) {
6; CHECK-LABEL: store_v5i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
9; CHECK-NEXT:    vse8.v v8, (a0)
10; CHECK-NEXT:    ret
11  store <5 x i8> %v, ptr %p
12  ret void
13}
14
15define void @store_v5i8_align1(ptr %p, <5 x i8> %v) {
16; CHECK-LABEL: store_v5i8_align1:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
19; CHECK-NEXT:    vse8.v v8, (a0)
20; CHECK-NEXT:    ret
21  store <5 x i8> %v, ptr %p, align 1
22  ret void
23}
24
25
26define void @store_v6i8(ptr %p, <6 x i8> %v) {
27; CHECK-LABEL: store_v6i8:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    vsetivli zero, 6, e8, mf2, ta, ma
30; CHECK-NEXT:    vse8.v v8, (a0)
31; CHECK-NEXT:    ret
32  store <6 x i8> %v, ptr %p
33  ret void
34}
35
36define void @store_v12i8(ptr %p, <12 x i8> %v) {
37; CHECK-LABEL: store_v12i8:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    vsetivli zero, 12, e8, m1, ta, ma
40; CHECK-NEXT:    vse8.v v8, (a0)
41; CHECK-NEXT:    ret
42  store <12 x i8> %v, ptr %p
43  ret void
44}
45
46define void @store_v6i16(ptr %p, <6 x i16> %v) {
47; CHECK-LABEL: store_v6i16:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
50; CHECK-NEXT:    vse16.v v8, (a0)
51; CHECK-NEXT:    ret
52  store <6 x i16> %v, ptr %p
53  ret void
54}
55
56define void @store_v6f16(ptr %p, <6 x half> %v) {
57; CHECK-LABEL: store_v6f16:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
60; CHECK-NEXT:    vse16.v v8, (a0)
61; CHECK-NEXT:    ret
62  store <6 x half> %v, ptr %p
63  ret void
64}
65
66define void @store_v6f32(ptr %p, <6 x float> %v) {
67; CHECK-LABEL: store_v6f32:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
70; CHECK-NEXT:    vse32.v v8, (a0)
71; CHECK-NEXT:    ret
72  store <6 x float> %v, ptr %p
73  ret void
74}
75
76define void @store_v6f64(ptr %p, <6 x double> %v) {
77; CHECK-LABEL: store_v6f64:
78; CHECK:       # %bb.0:
79; CHECK-NEXT:    vsetivli zero, 6, e64, m4, ta, ma
80; CHECK-NEXT:    vse64.v v8, (a0)
81; CHECK-NEXT:    ret
82  store <6 x double> %v, ptr %p
83  ret void
84}
85
86define void @store_v6i1(ptr %p, <6 x i1> %v) {
87; CHECK-LABEL: store_v6i1:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
90; CHECK-NEXT:    vfirst.m a1, v0
91; CHECK-NEXT:    vmv.x.s a2, v0
92; CHECK-NEXT:    seqz a1, a1
93; CHECK-NEXT:    andi a3, a2, 2
94; CHECK-NEXT:    andi a4, a2, 4
95; CHECK-NEXT:    or a1, a1, a3
96; CHECK-NEXT:    andi a3, a2, 8
97; CHECK-NEXT:    or a3, a4, a3
98; CHECK-NEXT:    andi a4, a2, 16
99; CHECK-NEXT:    andi a2, a2, -32
100; CHECK-NEXT:    or a1, a1, a3
101; CHECK-NEXT:    or a2, a4, a2
102; CHECK-NEXT:    or a1, a1, a2
103; CHECK-NEXT:    andi a1, a1, 63
104; CHECK-NEXT:    sb a1, 0(a0)
105; CHECK-NEXT:    ret
106  store <6 x i1> %v, ptr %p
107  ret void
108}
109
110define void @store_constant_v2i8(ptr %p) {
111; CHECK-LABEL: store_constant_v2i8:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    li a1, 1539
114; CHECK-NEXT:    sh a1, 0(a0)
115; CHECK-NEXT:    ret
116  store <2 x i8> <i8 3, i8 6>, ptr %p
117  ret void
118}
119
120define void @store_constant_v2i16(ptr %p) {
121; CHECK-LABEL: store_constant_v2i16:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    lui a1, 96
124; CHECK-NEXT:    addi a1, a1, 3
125; CHECK-NEXT:    sw a1, 0(a0)
126; CHECK-NEXT:    ret
127  store <2 x i16> <i16 3, i16 6>, ptr %p
128  ret void
129}
130
131define void @store_constant_v2i32(ptr %p) {
132; CHECK-LABEL: store_constant_v2i32:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
135; CHECK-NEXT:    vmv.v.i v8, 3
136; CHECK-NEXT:    vid.v v9
137; CHECK-NEXT:    li a1, 3
138; CHECK-NEXT:    vmadd.vx v9, a1, v8
139; CHECK-NEXT:    vse32.v v9, (a0)
140; CHECK-NEXT:    ret
141  store <2 x i32> <i32 3, i32 6>, ptr %p
142  ret void
143}
144
145define void @store_constant_v4i8(ptr %p) {
146; CHECK-LABEL: store_constant_v4i8:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    lui a1, 4176
149; CHECK-NEXT:    addi a1, a1, 1539
150; CHECK-NEXT:    sw a1, 0(a0)
151; CHECK-NEXT:    ret
152  store <4 x i8> <i8 3, i8 6, i8 5, i8 1>, ptr %p
153  ret void
154}
155
156define void @store_constant_v4i16(ptr %p) {
157; CHECK-LABEL: store_constant_v4i16:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    lui a1, 4176
160; CHECK-NEXT:    addi a1, a1, 1539
161; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
162; CHECK-NEXT:    vmv.s.x v8, a1
163; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
164; CHECK-NEXT:    vsext.vf2 v9, v8
165; CHECK-NEXT:    vse16.v v9, (a0)
166; CHECK-NEXT:    ret
167  store <4 x i16> <i16 3, i16 6, i16 5, i16 1>, ptr %p
168  ret void
169}
170
171define void @store_constant_v4i32(ptr %p) {
172; CHECK-LABEL: store_constant_v4i32:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    lui a1, 4176
175; CHECK-NEXT:    addi a1, a1, 1539
176; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
177; CHECK-NEXT:    vmv.s.x v8, a1
178; CHECK-NEXT:    vsext.vf4 v9, v8
179; CHECK-NEXT:    vse32.v v9, (a0)
180; CHECK-NEXT:    ret
181  store <4 x i32> <i32 3, i32 6, i32 5, i32 1>, ptr %p
182  ret void
183}
184
185define void @store_id_v4i8(ptr %p) {
186; CHECK-LABEL: store_id_v4i8:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    lui a1, 12320
189; CHECK-NEXT:    addi a1, a1, 256
190; CHECK-NEXT:    sw a1, 0(a0)
191; CHECK-NEXT:    ret
192  store <4 x i8> <i8 0, i8 1, i8 2, i8 3>, ptr %p
193  ret void
194}
195
196define void @store_constant_v2i8_align1(ptr %p) {
197; CHECK-LABEL: store_constant_v2i8_align1:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
200; CHECK-NEXT:    vmv.v.i v8, 3
201; CHECK-NEXT:    vid.v v9
202; CHECK-NEXT:    li a1, 3
203; CHECK-NEXT:    vmadd.vx v9, a1, v8
204; CHECK-NEXT:    vse8.v v9, (a0)
205; CHECK-NEXT:    ret
206  store <2 x i8> <i8 3, i8 6>, ptr %p, align 1
207  ret void
208}
209
210define void @store_constant_splat_v2i8(ptr %p) {
211; CHECK-LABEL: store_constant_splat_v2i8:
212; CHECK:       # %bb.0:
213; CHECK-NEXT:    li a1, 771
214; CHECK-NEXT:    sh a1, 0(a0)
215; CHECK-NEXT:    ret
216  store <2 x i8> <i8 3, i8 3>, ptr %p
217  ret void
218}
219
220define void @store_constant_undef_v2i8(ptr %p) {
221; CHECK-LABEL: store_constant_undef_v2i8:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    li a1, 768
224; CHECK-NEXT:    sh a1, 0(a0)
225; CHECK-NEXT:    ret
226  store <2 x i8> <i8 undef, i8 3>, ptr %p
227  ret void
228}
229
230define void @store_constant_v2i8_volatile(ptr %p) {
231; CHECK-LABEL: store_constant_v2i8_volatile:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
234; CHECK-NEXT:    vmv.v.i v8, 1
235; CHECK-NEXT:    vse8.v v8, (a0)
236; CHECK-NEXT:    ret
237  store volatile <2 x i8> <i8 1, i8 1>, ptr %p
238  ret void
239}
240
241
242define void @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {
243; CHECK-LABEL: exact_vlen_i32_m1:
244; CHECK:       # %bb.0:
245; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
246; CHECK-NEXT:    vmv.v.i v8, 0
247; CHECK-NEXT:    vs1r.v v8, (a0)
248; CHECK-NEXT:    ret
249  store <4 x i32> zeroinitializer, ptr %p
250  ret void
251}
252
253define void @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {
254; CHECK-LABEL: exact_vlen_i8_m1:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
257; CHECK-NEXT:    vmv.v.i v8, 0
258; CHECK-NEXT:    vs1r.v v8, (a0)
259; CHECK-NEXT:    ret
260  store <16 x i8> zeroinitializer, ptr %p
261  ret void
262}
263
264define void @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {
265; CHECK-LABEL: exact_vlen_i8_m2:
266; CHECK:       # %bb.0:
267; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
268; CHECK-NEXT:    vmv.v.i v8, 0
269; CHECK-NEXT:    vs2r.v v8, (a0)
270; CHECK-NEXT:    ret
271  store <32 x i8> zeroinitializer, ptr %p
272  ret void
273}
274
275define void @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {
276; CHECK-LABEL: exact_vlen_i8_m8:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
279; CHECK-NEXT:    vmv.v.i v8, 0
280; CHECK-NEXT:    vs8r.v v8, (a0)
281; CHECK-NEXT:    ret
282  store <128 x i8> zeroinitializer, ptr %p
283  ret void
284}
285
286define void @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
287; CHECK-LABEL: exact_vlen_i64_m8:
288; CHECK:       # %bb.0:
289; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
290; CHECK-NEXT:    vmv.v.i v8, 0
291; CHECK-NEXT:    vs8r.v v8, (a0)
292; CHECK-NEXT:    ret
293  store <16 x i64> zeroinitializer, ptr %p
294  ret void
295}
296
297define void @store_v6bf16(ptr %p, <6 x bfloat> %v) {
298; CHECK-LABEL: store_v6bf16:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
301; CHECK-NEXT:    vse16.v v8, (a0)
302; CHECK-NEXT:    ret
303  store <6 x bfloat> %v, ptr %p
304  ret void
305}
306
307;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
308; RV32: {{.*}}
309; RV64: {{.*}}
310