1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+v | FileCheck %s 3 4; This test loads to values and stores them in reversed order. This previously 5; asserted because part of DAGCombiner::tryStoreMerge thinks we can use an i64 6; rotate, but the loads aren't sufficiently aligned. So then it tried to use 7; a vector type, but that can't handle the swapped case. 8 9@foo = global [2 x i32] zeroinitializer, align 4 10@bar = global [2 x i32] zeroinitializer, align 4 11 12define void @baz() nounwind { 13; CHECK-LABEL: baz: 14; CHECK: # %bb.0: # %entry 15; CHECK-NEXT: lui a0, %hi(foo) 16; CHECK-NEXT: addi a1, a0, %lo(foo) 17; CHECK-NEXT: lw a1, 4(a1) 18; CHECK-NEXT: lw a0, %lo(foo)(a0) 19; CHECK-NEXT: lui a2, %hi(bar) 20; CHECK-NEXT: sw a1, %lo(bar)(a2) 21; CHECK-NEXT: addi a1, a2, %lo(bar) 22; CHECK-NEXT: sw a0, 4(a1) 23; CHECK-NEXT: ret 24entry: 25 %0 = load i32, ptr getelementptr inbounds ([2 x i32], ptr @foo, i64 0, i64 1), align 4 26 store i32 %0, ptr @bar, align 4 27 %1 = load i32, ptr @foo, align 4 28 store i32 %1, ptr getelementptr inbounds ([2 x i32], ptr @bar, i64 0, i64 1), align 4 29 ret void 30} 31