xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll (revision 74f985b793bf4005e49736f8c2cef8b5cbf7c1ab) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) {
8; CHECK-LABEL: select_v1i1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
11; CHECK-NEXT:    vmv.s.x v9, a0
12; CHECK-NEXT:    vmsne.vi v9, v9, 0
13; CHECK-NEXT:    vmandn.mm v8, v8, v9
14; CHECK-NEXT:    vmand.mm v9, v0, v9
15; CHECK-NEXT:    vmor.mm v0, v9, v8
16; CHECK-NEXT:    ret
17  %v = select i1 %c, <1 x i1> %a, <1 x i1> %b
18  ret <1 x i1> %v
19}
20
21define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i1> %d) {
22; CHECK-LABEL: selectcc_v1i1:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    xor a0, a0, a1
25; CHECK-NEXT:    andi a0, a0, 1
26; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
27; CHECK-NEXT:    vmv.s.x v9, a0
28; CHECK-NEXT:    vmsne.vi v9, v9, 0
29; CHECK-NEXT:    vmandn.mm v8, v8, v9
30; CHECK-NEXT:    vmand.mm v9, v0, v9
31; CHECK-NEXT:    vmor.mm v0, v9, v8
32; CHECK-NEXT:    ret
33  %cmp = icmp ne i1 %a, %b
34  %v = select i1 %cmp, <1 x i1> %c, <1 x i1> %d
35  ret <1 x i1> %v
36}
37
38define <2 x i1> @select_v2i1(i1 zeroext %c, <2 x i1> %a, <2 x i1> %b) {
39; CHECK-LABEL: select_v2i1:
40; CHECK:       # %bb.0:
41; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
42; CHECK-NEXT:    vmv.v.x v9, a0
43; CHECK-NEXT:    vmsne.vi v9, v9, 0
44; CHECK-NEXT:    vmandn.mm v8, v8, v9
45; CHECK-NEXT:    vmand.mm v9, v0, v9
46; CHECK-NEXT:    vmor.mm v0, v9, v8
47; CHECK-NEXT:    ret
48  %v = select i1 %c, <2 x i1> %a, <2 x i1> %b
49  ret <2 x i1> %v
50}
51
52define <2 x i1> @selectcc_v2i1(i1 signext %a, i1 signext %b, <2 x i1> %c, <2 x i1> %d) {
53; CHECK-LABEL: selectcc_v2i1:
54; CHECK:       # %bb.0:
55; CHECK-NEXT:    xor a0, a0, a1
56; CHECK-NEXT:    andi a0, a0, 1
57; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
58; CHECK-NEXT:    vmv.v.x v9, a0
59; CHECK-NEXT:    vmsne.vi v9, v9, 0
60; CHECK-NEXT:    vmandn.mm v8, v8, v9
61; CHECK-NEXT:    vmand.mm v9, v0, v9
62; CHECK-NEXT:    vmor.mm v0, v9, v8
63; CHECK-NEXT:    ret
64  %cmp = icmp ne i1 %a, %b
65  %v = select i1 %cmp, <2 x i1> %c, <2 x i1> %d
66  ret <2 x i1> %v
67}
68
69define <4 x i1> @select_v4i1(i1 zeroext %c, <4 x i1> %a, <4 x i1> %b) {
70; CHECK-LABEL: select_v4i1:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
73; CHECK-NEXT:    vmv.v.x v9, a0
74; CHECK-NEXT:    vmsne.vi v9, v9, 0
75; CHECK-NEXT:    vmandn.mm v8, v8, v9
76; CHECK-NEXT:    vmand.mm v9, v0, v9
77; CHECK-NEXT:    vmor.mm v0, v9, v8
78; CHECK-NEXT:    ret
79  %v = select i1 %c, <4 x i1> %a, <4 x i1> %b
80  ret <4 x i1> %v
81}
82
83define <4 x i1> @selectcc_v4i1(i1 signext %a, i1 signext %b, <4 x i1> %c, <4 x i1> %d) {
84; CHECK-LABEL: selectcc_v4i1:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    xor a0, a0, a1
87; CHECK-NEXT:    andi a0, a0, 1
88; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
89; CHECK-NEXT:    vmv.v.x v9, a0
90; CHECK-NEXT:    vmsne.vi v9, v9, 0
91; CHECK-NEXT:    vmandn.mm v8, v8, v9
92; CHECK-NEXT:    vmand.mm v9, v0, v9
93; CHECK-NEXT:    vmor.mm v0, v9, v8
94; CHECK-NEXT:    ret
95  %cmp = icmp ne i1 %a, %b
96  %v = select i1 %cmp, <4 x i1> %c, <4 x i1> %d
97  ret <4 x i1> %v
98}
99
100define <8 x i1> @select_v8i1(i1 zeroext %c, <8 x i1> %a, <8 x i1> %b) {
101; CHECK-LABEL: select_v8i1:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
104; CHECK-NEXT:    vmv.v.x v9, a0
105; CHECK-NEXT:    vmsne.vi v9, v9, 0
106; CHECK-NEXT:    vmandn.mm v8, v8, v9
107; CHECK-NEXT:    vmand.mm v9, v0, v9
108; CHECK-NEXT:    vmor.mm v0, v9, v8
109; CHECK-NEXT:    ret
110  %v = select i1 %c, <8 x i1> %a, <8 x i1> %b
111  ret <8 x i1> %v
112}
113
114define <8 x i1> @selectcc_v8i1(i1 signext %a, i1 signext %b, <8 x i1> %c, <8 x i1> %d) {
115; CHECK-LABEL: selectcc_v8i1:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    xor a0, a0, a1
118; CHECK-NEXT:    andi a0, a0, 1
119; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
120; CHECK-NEXT:    vmv.v.x v9, a0
121; CHECK-NEXT:    vmsne.vi v9, v9, 0
122; CHECK-NEXT:    vmandn.mm v8, v8, v9
123; CHECK-NEXT:    vmand.mm v9, v0, v9
124; CHECK-NEXT:    vmor.mm v0, v9, v8
125; CHECK-NEXT:    ret
126  %cmp = icmp ne i1 %a, %b
127  %v = select i1 %cmp, <8 x i1> %c, <8 x i1> %d
128  ret <8 x i1> %v
129}
130
131define <16 x i1> @select_v16i1(i1 zeroext %c, <16 x i1> %a, <16 x i1> %b) {
132; CHECK-LABEL: select_v16i1:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
135; CHECK-NEXT:    vmv.v.x v9, a0
136; CHECK-NEXT:    vmsne.vi v9, v9, 0
137; CHECK-NEXT:    vmandn.mm v8, v8, v9
138; CHECK-NEXT:    vmand.mm v9, v0, v9
139; CHECK-NEXT:    vmor.mm v0, v9, v8
140; CHECK-NEXT:    ret
141  %v = select i1 %c, <16 x i1> %a, <16 x i1> %b
142  ret <16 x i1> %v
143}
144
145define <16 x i1> @selectcc_v16i1(i1 signext %a, i1 signext %b, <16 x i1> %c, <16 x i1> %d) {
146; CHECK-LABEL: selectcc_v16i1:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    xor a0, a0, a1
149; CHECK-NEXT:    andi a0, a0, 1
150; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
151; CHECK-NEXT:    vmv.v.x v9, a0
152; CHECK-NEXT:    vmsne.vi v9, v9, 0
153; CHECK-NEXT:    vmandn.mm v8, v8, v9
154; CHECK-NEXT:    vmand.mm v9, v0, v9
155; CHECK-NEXT:    vmor.mm v0, v9, v8
156; CHECK-NEXT:    ret
157  %cmp = icmp ne i1 %a, %b
158  %v = select i1 %cmp, <16 x i1> %c, <16 x i1> %d
159  ret <16 x i1> %v
160}
161
162define <2 x i8> @select_v2i8(i1 zeroext %c, <2 x i8> %a, <2 x i8> %b) {
163; CHECK-LABEL: select_v2i8:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
166; CHECK-NEXT:    vmv.v.x v10, a0
167; CHECK-NEXT:    vmsne.vi v0, v10, 0
168; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
169; CHECK-NEXT:    ret
170  %v = select i1 %c, <2 x i8> %a, <2 x i8> %b
171  ret <2 x i8> %v
172}
173
174define <2 x i8> @selectcc_v2i8(i8 signext %a, i8 signext %b, <2 x i8> %c, <2 x i8> %d) {
175; CHECK-LABEL: selectcc_v2i8:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    xor a0, a0, a1
178; CHECK-NEXT:    snez a0, a0
179; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
180; CHECK-NEXT:    vmv.v.x v10, a0
181; CHECK-NEXT:    vmsne.vi v0, v10, 0
182; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
183; CHECK-NEXT:    ret
184  %cmp = icmp ne i8 %a, %b
185  %v = select i1 %cmp, <2 x i8> %c, <2 x i8> %d
186  ret <2 x i8> %v
187}
188
189define <4 x i8> @select_v4i8(i1 zeroext %c, <4 x i8> %a, <4 x i8> %b) {
190; CHECK-LABEL: select_v4i8:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
193; CHECK-NEXT:    vmv.v.x v10, a0
194; CHECK-NEXT:    vmsne.vi v0, v10, 0
195; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
196; CHECK-NEXT:    ret
197  %v = select i1 %c, <4 x i8> %a, <4 x i8> %b
198  ret <4 x i8> %v
199}
200
201define <4 x i8> @selectcc_v4i8(i8 signext %a, i8 signext %b, <4 x i8> %c, <4 x i8> %d) {
202; CHECK-LABEL: selectcc_v4i8:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    xor a0, a0, a1
205; CHECK-NEXT:    snez a0, a0
206; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
207; CHECK-NEXT:    vmv.v.x v10, a0
208; CHECK-NEXT:    vmsne.vi v0, v10, 0
209; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
210; CHECK-NEXT:    ret
211  %cmp = icmp ne i8 %a, %b
212  %v = select i1 %cmp, <4 x i8> %c, <4 x i8> %d
213  ret <4 x i8> %v
214}
215
216define <8 x i8> @select_v8i8(i1 zeroext %c, <8 x i8> %a, <8 x i8> %b) {
217; CHECK-LABEL: select_v8i8:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
220; CHECK-NEXT:    vmv.v.x v10, a0
221; CHECK-NEXT:    vmsne.vi v0, v10, 0
222; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
223; CHECK-NEXT:    ret
224  %v = select i1 %c, <8 x i8> %a, <8 x i8> %b
225  ret <8 x i8> %v
226}
227
228define <8 x i8> @selectcc_v8i8(i8 signext %a, i8 signext %b, <8 x i8> %c, <8 x i8> %d) {
229; CHECK-LABEL: selectcc_v8i8:
230; CHECK:       # %bb.0:
231; CHECK-NEXT:    xor a0, a0, a1
232; CHECK-NEXT:    snez a0, a0
233; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
234; CHECK-NEXT:    vmv.v.x v10, a0
235; CHECK-NEXT:    vmsne.vi v0, v10, 0
236; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
237; CHECK-NEXT:    ret
238  %cmp = icmp ne i8 %a, %b
239  %v = select i1 %cmp, <8 x i8> %c, <8 x i8> %d
240  ret <8 x i8> %v
241}
242
243define <16 x i8> @select_v16i8(i1 zeroext %c, <16 x i8> %a, <16 x i8> %b) {
244; CHECK-LABEL: select_v16i8:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
247; CHECK-NEXT:    vmv.v.x v10, a0
248; CHECK-NEXT:    vmsne.vi v0, v10, 0
249; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
250; CHECK-NEXT:    ret
251  %v = select i1 %c, <16 x i8> %a, <16 x i8> %b
252  ret <16 x i8> %v
253}
254
255define <16 x i8> @selectcc_v16i8(i8 signext %a, i8 signext %b, <16 x i8> %c, <16 x i8> %d) {
256; CHECK-LABEL: selectcc_v16i8:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    xor a0, a0, a1
259; CHECK-NEXT:    snez a0, a0
260; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
261; CHECK-NEXT:    vmv.v.x v10, a0
262; CHECK-NEXT:    vmsne.vi v0, v10, 0
263; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
264; CHECK-NEXT:    ret
265  %cmp = icmp ne i8 %a, %b
266  %v = select i1 %cmp, <16 x i8> %c, <16 x i8> %d
267  ret <16 x i8> %v
268}
269
270define <2 x i16> @select_v2i16(i1 zeroext %c, <2 x i16> %a, <2 x i16> %b) {
271; CHECK-LABEL: select_v2i16:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
274; CHECK-NEXT:    vmv.v.x v10, a0
275; CHECK-NEXT:    vmsne.vi v0, v10, 0
276; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
277; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
278; CHECK-NEXT:    ret
279  %v = select i1 %c, <2 x i16> %a, <2 x i16> %b
280  ret <2 x i16> %v
281}
282
283define <2 x i16> @selectcc_v2i16(i16 signext %a, i16 signext %b, <2 x i16> %c, <2 x i16> %d) {
284; CHECK-LABEL: selectcc_v2i16:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    xor a0, a0, a1
287; CHECK-NEXT:    snez a0, a0
288; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
289; CHECK-NEXT:    vmv.v.x v10, a0
290; CHECK-NEXT:    vmsne.vi v0, v10, 0
291; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
292; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
293; CHECK-NEXT:    ret
294  %cmp = icmp ne i16 %a, %b
295  %v = select i1 %cmp, <2 x i16> %c, <2 x i16> %d
296  ret <2 x i16> %v
297}
298
299define <4 x i16> @select_v4i16(i1 zeroext %c, <4 x i16> %a, <4 x i16> %b) {
300; CHECK-LABEL: select_v4i16:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
303; CHECK-NEXT:    vmv.v.x v10, a0
304; CHECK-NEXT:    vmsne.vi v0, v10, 0
305; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
306; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
307; CHECK-NEXT:    ret
308  %v = select i1 %c, <4 x i16> %a, <4 x i16> %b
309  ret <4 x i16> %v
310}
311
312define <4 x i16> @selectcc_v4i16(i16 signext %a, i16 signext %b, <4 x i16> %c, <4 x i16> %d) {
313; CHECK-LABEL: selectcc_v4i16:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    xor a0, a0, a1
316; CHECK-NEXT:    snez a0, a0
317; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
318; CHECK-NEXT:    vmv.v.x v10, a0
319; CHECK-NEXT:    vmsne.vi v0, v10, 0
320; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
321; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
322; CHECK-NEXT:    ret
323  %cmp = icmp ne i16 %a, %b
324  %v = select i1 %cmp, <4 x i16> %c, <4 x i16> %d
325  ret <4 x i16> %v
326}
327
328define <8 x i16> @select_v8i16(i1 zeroext %c, <8 x i16> %a, <8 x i16> %b) {
329; CHECK-LABEL: select_v8i16:
330; CHECK:       # %bb.0:
331; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
332; CHECK-NEXT:    vmv.v.x v10, a0
333; CHECK-NEXT:    vmsne.vi v0, v10, 0
334; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
335; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
336; CHECK-NEXT:    ret
337  %v = select i1 %c, <8 x i16> %a, <8 x i16> %b
338  ret <8 x i16> %v
339}
340
341define <8 x i16> @selectcc_v8i16(i16 signext %a, i16 signext %b, <8 x i16> %c, <8 x i16> %d) {
342; CHECK-LABEL: selectcc_v8i16:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    xor a0, a0, a1
345; CHECK-NEXT:    snez a0, a0
346; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
347; CHECK-NEXT:    vmv.v.x v10, a0
348; CHECK-NEXT:    vmsne.vi v0, v10, 0
349; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
350; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
351; CHECK-NEXT:    ret
352  %cmp = icmp ne i16 %a, %b
353  %v = select i1 %cmp, <8 x i16> %c, <8 x i16> %d
354  ret <8 x i16> %v
355}
356
357define <16 x i16> @select_v16i16(i1 zeroext %c, <16 x i16> %a, <16 x i16> %b) {
358; CHECK-LABEL: select_v16i16:
359; CHECK:       # %bb.0:
360; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
361; CHECK-NEXT:    vmv.v.x v12, a0
362; CHECK-NEXT:    vmsne.vi v0, v12, 0
363; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
364; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
365; CHECK-NEXT:    ret
366  %v = select i1 %c, <16 x i16> %a, <16 x i16> %b
367  ret <16 x i16> %v
368}
369
370define <16 x i16> @selectcc_v16i16(i16 signext %a, i16 signext %b, <16 x i16> %c, <16 x i16> %d) {
371; CHECK-LABEL: selectcc_v16i16:
372; CHECK:       # %bb.0:
373; CHECK-NEXT:    xor a0, a0, a1
374; CHECK-NEXT:    snez a0, a0
375; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
376; CHECK-NEXT:    vmv.v.x v12, a0
377; CHECK-NEXT:    vmsne.vi v0, v12, 0
378; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
379; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
380; CHECK-NEXT:    ret
381  %cmp = icmp ne i16 %a, %b
382  %v = select i1 %cmp, <16 x i16> %c, <16 x i16> %d
383  ret <16 x i16> %v
384}
385
386define <2 x i32> @select_v2i32(i1 zeroext %c, <2 x i32> %a, <2 x i32> %b) {
387; CHECK-LABEL: select_v2i32:
388; CHECK:       # %bb.0:
389; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
390; CHECK-NEXT:    vmv.v.x v10, a0
391; CHECK-NEXT:    vmsne.vi v0, v10, 0
392; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
393; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
394; CHECK-NEXT:    ret
395  %v = select i1 %c, <2 x i32> %a, <2 x i32> %b
396  ret <2 x i32> %v
397}
398
399define <2 x i32> @selectcc_v2i32(i32 signext %a, i32 signext %b, <2 x i32> %c, <2 x i32> %d) {
400; CHECK-LABEL: selectcc_v2i32:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    xor a0, a0, a1
403; CHECK-NEXT:    snez a0, a0
404; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
405; CHECK-NEXT:    vmv.v.x v10, a0
406; CHECK-NEXT:    vmsne.vi v0, v10, 0
407; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
408; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
409; CHECK-NEXT:    ret
410  %cmp = icmp ne i32 %a, %b
411  %v = select i1 %cmp, <2 x i32> %c, <2 x i32> %d
412  ret <2 x i32> %v
413}
414
415define <4 x i32> @select_v4i32(i1 zeroext %c, <4 x i32> %a, <4 x i32> %b) {
416; CHECK-LABEL: select_v4i32:
417; CHECK:       # %bb.0:
418; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
419; CHECK-NEXT:    vmv.v.x v10, a0
420; CHECK-NEXT:    vmsne.vi v0, v10, 0
421; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
422; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
423; CHECK-NEXT:    ret
424  %v = select i1 %c, <4 x i32> %a, <4 x i32> %b
425  ret <4 x i32> %v
426}
427
428define <4 x i32> @selectcc_v4i32(i32 signext %a, i32 signext %b, <4 x i32> %c, <4 x i32> %d) {
429; CHECK-LABEL: selectcc_v4i32:
430; CHECK:       # %bb.0:
431; CHECK-NEXT:    xor a0, a0, a1
432; CHECK-NEXT:    snez a0, a0
433; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
434; CHECK-NEXT:    vmv.v.x v10, a0
435; CHECK-NEXT:    vmsne.vi v0, v10, 0
436; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
437; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
438; CHECK-NEXT:    ret
439  %cmp = icmp ne i32 %a, %b
440  %v = select i1 %cmp, <4 x i32> %c, <4 x i32> %d
441  ret <4 x i32> %v
442}
443
444define <8 x i32> @select_v8i32(i1 zeroext %c, <8 x i32> %a, <8 x i32> %b) {
445; CHECK-LABEL: select_v8i32:
446; CHECK:       # %bb.0:
447; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
448; CHECK-NEXT:    vmv.v.x v12, a0
449; CHECK-NEXT:    vmsne.vi v0, v12, 0
450; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
451; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
452; CHECK-NEXT:    ret
453  %v = select i1 %c, <8 x i32> %a, <8 x i32> %b
454  ret <8 x i32> %v
455}
456
457define <8 x i32> @selectcc_v8i32(i32 signext %a, i32 signext %b, <8 x i32> %c, <8 x i32> %d) {
458; CHECK-LABEL: selectcc_v8i32:
459; CHECK:       # %bb.0:
460; CHECK-NEXT:    xor a0, a0, a1
461; CHECK-NEXT:    snez a0, a0
462; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
463; CHECK-NEXT:    vmv.v.x v12, a0
464; CHECK-NEXT:    vmsne.vi v0, v12, 0
465; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
466; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
467; CHECK-NEXT:    ret
468  %cmp = icmp ne i32 %a, %b
469  %v = select i1 %cmp, <8 x i32> %c, <8 x i32> %d
470  ret <8 x i32> %v
471}
472
473define <16 x i32> @select_v16i32(i1 zeroext %c, <16 x i32> %a, <16 x i32> %b) {
474; CHECK-LABEL: select_v16i32:
475; CHECK:       # %bb.0:
476; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
477; CHECK-NEXT:    vmv.v.x v16, a0
478; CHECK-NEXT:    vmsne.vi v0, v16, 0
479; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
480; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
481; CHECK-NEXT:    ret
482  %v = select i1 %c, <16 x i32> %a, <16 x i32> %b
483  ret <16 x i32> %v
484}
485
486define <16 x i32> @selectcc_v16i32(i32 signext %a, i32 signext %b, <16 x i32> %c, <16 x i32> %d) {
487; CHECK-LABEL: selectcc_v16i32:
488; CHECK:       # %bb.0:
489; CHECK-NEXT:    xor a0, a0, a1
490; CHECK-NEXT:    snez a0, a0
491; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
492; CHECK-NEXT:    vmv.v.x v16, a0
493; CHECK-NEXT:    vmsne.vi v0, v16, 0
494; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
495; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
496; CHECK-NEXT:    ret
497  %cmp = icmp ne i32 %a, %b
498  %v = select i1 %cmp, <16 x i32> %c, <16 x i32> %d
499  ret <16 x i32> %v
500}
501
502define <2 x i64> @select_v2i64(i1 zeroext %c, <2 x i64> %a, <2 x i64> %b) {
503; CHECK-LABEL: select_v2i64:
504; CHECK:       # %bb.0:
505; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
506; CHECK-NEXT:    vmv.v.x v10, a0
507; CHECK-NEXT:    vmsne.vi v0, v10, 0
508; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
509; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
510; CHECK-NEXT:    ret
511  %v = select i1 %c, <2 x i64> %a, <2 x i64> %b
512  ret <2 x i64> %v
513}
514
515define <2 x i64> @selectcc_v2i64(i64 signext %a, i64 signext %b, <2 x i64> %c, <2 x i64> %d) {
516; RV32-LABEL: selectcc_v2i64:
517; RV32:       # %bb.0:
518; RV32-NEXT:    xor a1, a1, a3
519; RV32-NEXT:    xor a0, a0, a2
520; RV32-NEXT:    or a0, a0, a1
521; RV32-NEXT:    snez a0, a0
522; RV32-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
523; RV32-NEXT:    vmv.v.x v10, a0
524; RV32-NEXT:    vmsne.vi v0, v10, 0
525; RV32-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
526; RV32-NEXT:    vmerge.vvm v8, v9, v8, v0
527; RV32-NEXT:    ret
528;
529; RV64-LABEL: selectcc_v2i64:
530; RV64:       # %bb.0:
531; RV64-NEXT:    xor a0, a0, a1
532; RV64-NEXT:    snez a0, a0
533; RV64-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
534; RV64-NEXT:    vmv.v.x v10, a0
535; RV64-NEXT:    vmsne.vi v0, v10, 0
536; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
537; RV64-NEXT:    vmerge.vvm v8, v9, v8, v0
538; RV64-NEXT:    ret
539  %cmp = icmp ne i64 %a, %b
540  %v = select i1 %cmp, <2 x i64> %c, <2 x i64> %d
541  ret <2 x i64> %v
542}
543
544define <4 x i64> @select_v4i64(i1 zeroext %c, <4 x i64> %a, <4 x i64> %b) {
545; CHECK-LABEL: select_v4i64:
546; CHECK:       # %bb.0:
547; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
548; CHECK-NEXT:    vmv.v.x v12, a0
549; CHECK-NEXT:    vmsne.vi v0, v12, 0
550; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
551; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
552; CHECK-NEXT:    ret
553  %v = select i1 %c, <4 x i64> %a, <4 x i64> %b
554  ret <4 x i64> %v
555}
556
557define <4 x i64> @selectcc_v4i64(i64 signext %a, i64 signext %b, <4 x i64> %c, <4 x i64> %d) {
558; RV32-LABEL: selectcc_v4i64:
559; RV32:       # %bb.0:
560; RV32-NEXT:    xor a1, a1, a3
561; RV32-NEXT:    xor a0, a0, a2
562; RV32-NEXT:    or a0, a0, a1
563; RV32-NEXT:    snez a0, a0
564; RV32-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
565; RV32-NEXT:    vmv.v.x v12, a0
566; RV32-NEXT:    vmsne.vi v0, v12, 0
567; RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
568; RV32-NEXT:    vmerge.vvm v8, v10, v8, v0
569; RV32-NEXT:    ret
570;
571; RV64-LABEL: selectcc_v4i64:
572; RV64:       # %bb.0:
573; RV64-NEXT:    xor a0, a0, a1
574; RV64-NEXT:    snez a0, a0
575; RV64-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
576; RV64-NEXT:    vmv.v.x v12, a0
577; RV64-NEXT:    vmsne.vi v0, v12, 0
578; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
579; RV64-NEXT:    vmerge.vvm v8, v10, v8, v0
580; RV64-NEXT:    ret
581  %cmp = icmp ne i64 %a, %b
582  %v = select i1 %cmp, <4 x i64> %c, <4 x i64> %d
583  ret <4 x i64> %v
584}
585
586define <8 x i64> @select_v8i64(i1 zeroext %c, <8 x i64> %a, <8 x i64> %b) {
587; CHECK-LABEL: select_v8i64:
588; CHECK:       # %bb.0:
589; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
590; CHECK-NEXT:    vmv.v.x v16, a0
591; CHECK-NEXT:    vmsne.vi v0, v16, 0
592; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
593; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
594; CHECK-NEXT:    ret
595  %v = select i1 %c, <8 x i64> %a, <8 x i64> %b
596  ret <8 x i64> %v
597}
598
599define <8 x i64> @selectcc_v8i64(i64 signext %a, i64 signext %b, <8 x i64> %c, <8 x i64> %d) {
600; RV32-LABEL: selectcc_v8i64:
601; RV32:       # %bb.0:
602; RV32-NEXT:    xor a1, a1, a3
603; RV32-NEXT:    xor a0, a0, a2
604; RV32-NEXT:    or a0, a0, a1
605; RV32-NEXT:    snez a0, a0
606; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
607; RV32-NEXT:    vmv.v.x v16, a0
608; RV32-NEXT:    vmsne.vi v0, v16, 0
609; RV32-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
610; RV32-NEXT:    vmerge.vvm v8, v12, v8, v0
611; RV32-NEXT:    ret
612;
613; RV64-LABEL: selectcc_v8i64:
614; RV64:       # %bb.0:
615; RV64-NEXT:    xor a0, a0, a1
616; RV64-NEXT:    snez a0, a0
617; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
618; RV64-NEXT:    vmv.v.x v16, a0
619; RV64-NEXT:    vmsne.vi v0, v16, 0
620; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
621; RV64-NEXT:    vmerge.vvm v8, v12, v8, v0
622; RV64-NEXT:    ret
623  %cmp = icmp ne i64 %a, %b
624  %v = select i1 %cmp, <8 x i64> %c, <8 x i64> %d
625  ret <8 x i64> %v
626}
627
628define <16 x i64> @select_v16i64(i1 zeroext %c, <16 x i64> %a, <16 x i64> %b) {
629; CHECK-LABEL: select_v16i64:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
632; CHECK-NEXT:    vmv.v.x v24, a0
633; CHECK-NEXT:    vmsne.vi v0, v24, 0
634; CHECK-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
635; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
636; CHECK-NEXT:    ret
637  %v = select i1 %c, <16 x i64> %a, <16 x i64> %b
638  ret <16 x i64> %v
639}
640
641define <16 x i64> @selectcc_v16i64(i64 signext %a, i64 signext %b, <16 x i64> %c, <16 x i64> %d) {
642; RV32-LABEL: selectcc_v16i64:
643; RV32:       # %bb.0:
644; RV32-NEXT:    xor a1, a1, a3
645; RV32-NEXT:    xor a0, a0, a2
646; RV32-NEXT:    or a0, a0, a1
647; RV32-NEXT:    snez a0, a0
648; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
649; RV32-NEXT:    vmv.v.x v24, a0
650; RV32-NEXT:    vmsne.vi v0, v24, 0
651; RV32-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
652; RV32-NEXT:    vmerge.vvm v8, v16, v8, v0
653; RV32-NEXT:    ret
654;
655; RV64-LABEL: selectcc_v16i64:
656; RV64:       # %bb.0:
657; RV64-NEXT:    xor a0, a0, a1
658; RV64-NEXT:    snez a0, a0
659; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
660; RV64-NEXT:    vmv.v.x v24, a0
661; RV64-NEXT:    vmsne.vi v0, v24, 0
662; RV64-NEXT:    vsetvli zero, zero, e64, m8, ta, ma
663; RV64-NEXT:    vmerge.vvm v8, v16, v8, v0
664; RV64-NEXT:    ret
665  %cmp = icmp ne i64 %a, %b
666  %v = select i1 %cmp, <16 x i64> %c, <16 x i64> %d
667  ret <16 x i64> %v
668}
669