1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=ilp32d \ 3; RUN: -verify-machineinstrs < %s | FileCheck %s 4; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zfbfmin,+zvfbfmin -target-abi=lp64d \ 5; RUN: -verify-machineinstrs < %s | FileCheck %s 6 7define <2 x bfloat> @select_v2bf16(i1 zeroext %c, <2 x bfloat> %a, <2 x bfloat> %b) { 8; CHECK-LABEL: select_v2bf16: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 11; CHECK-NEXT: vmv.v.x v10, a0 12; CHECK-NEXT: vmsne.vi v0, v10, 0 13; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma 14; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 15; CHECK-NEXT: ret 16 %v = select i1 %c, <2 x bfloat> %a, <2 x bfloat> %b 17 ret <2 x bfloat> %v 18} 19 20define <2 x bfloat> @selectcc_v2bf16(bfloat %a, bfloat %b, <2 x bfloat> %c, <2 x bfloat> %d) { 21; CHECK-LABEL: selectcc_v2bf16: 22; CHECK: # %bb.0: 23; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 24; CHECK-NEXT: fcvt.s.bf16 fa4, fa0 25; CHECK-NEXT: feq.s a0, fa4, fa5 26; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 27; CHECK-NEXT: vmv.v.x v10, a0 28; CHECK-NEXT: vmsne.vi v0, v10, 0 29; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma 30; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 31; CHECK-NEXT: ret 32 %cmp = fcmp oeq bfloat %a, %b 33 %v = select i1 %cmp, <2 x bfloat> %c, <2 x bfloat> %d 34 ret <2 x bfloat> %v 35} 36 37define <4 x bfloat> @select_v4bf16(i1 zeroext %c, <4 x bfloat> %a, <4 x bfloat> %b) { 38; CHECK-LABEL: select_v4bf16: 39; CHECK: # %bb.0: 40; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 41; CHECK-NEXT: vmv.v.x v10, a0 42; CHECK-NEXT: vmsne.vi v0, v10, 0 43; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma 44; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 45; CHECK-NEXT: ret 46 %v = select i1 %c, <4 x bfloat> %a, <4 x bfloat> %b 47 ret <4 x bfloat> %v 48} 49 50define <4 x bfloat> @selectcc_v4bf16(bfloat %a, bfloat %b, <4 x bfloat> %c, <4 x bfloat> %d) { 51; CHECK-LABEL: selectcc_v4bf16: 52; CHECK: # %bb.0: 53; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 54; CHECK-NEXT: fcvt.s.bf16 fa4, fa0 55; CHECK-NEXT: feq.s a0, fa4, fa5 56; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 57; CHECK-NEXT: vmv.v.x v10, a0 58; CHECK-NEXT: vmsne.vi v0, v10, 0 59; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma 60; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 61; CHECK-NEXT: ret 62 %cmp = fcmp oeq bfloat %a, %b 63 %v = select i1 %cmp, <4 x bfloat> %c, <4 x bfloat> %d 64 ret <4 x bfloat> %v 65} 66 67define <8 x bfloat> @select_v8bf16(i1 zeroext %c, <8 x bfloat> %a, <8 x bfloat> %b) { 68; CHECK-LABEL: select_v8bf16: 69; CHECK: # %bb.0: 70; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 71; CHECK-NEXT: vmv.v.x v10, a0 72; CHECK-NEXT: vmsne.vi v0, v10, 0 73; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma 74; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 75; CHECK-NEXT: ret 76 %v = select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b 77 ret <8 x bfloat> %v 78} 79 80define <8 x bfloat> @selectcc_v8bf16(bfloat %a, bfloat %b, <8 x bfloat> %c, <8 x bfloat> %d) { 81; CHECK-LABEL: selectcc_v8bf16: 82; CHECK: # %bb.0: 83; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 84; CHECK-NEXT: fcvt.s.bf16 fa4, fa0 85; CHECK-NEXT: feq.s a0, fa4, fa5 86; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 87; CHECK-NEXT: vmv.v.x v10, a0 88; CHECK-NEXT: vmsne.vi v0, v10, 0 89; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma 90; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 91; CHECK-NEXT: ret 92 %cmp = fcmp oeq bfloat %a, %b 93 %v = select i1 %cmp, <8 x bfloat> %c, <8 x bfloat> %d 94 ret <8 x bfloat> %v 95} 96 97define <16 x bfloat> @select_v16bf16(i1 zeroext %c, <16 x bfloat> %a, <16 x bfloat> %b) { 98; CHECK-LABEL: select_v16bf16: 99; CHECK: # %bb.0: 100; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 101; CHECK-NEXT: vmv.v.x v12, a0 102; CHECK-NEXT: vmsne.vi v0, v12, 0 103; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 104; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 105; CHECK-NEXT: ret 106 %v = select i1 %c, <16 x bfloat> %a, <16 x bfloat> %b 107 ret <16 x bfloat> %v 108} 109 110define <16 x bfloat> @selectcc_v16bf16(bfloat %a, bfloat %b, <16 x bfloat> %c, <16 x bfloat> %d) { 111; CHECK-LABEL: selectcc_v16bf16: 112; CHECK: # %bb.0: 113; CHECK-NEXT: fcvt.s.bf16 fa5, fa1 114; CHECK-NEXT: fcvt.s.bf16 fa4, fa0 115; CHECK-NEXT: feq.s a0, fa4, fa5 116; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 117; CHECK-NEXT: vmv.v.x v12, a0 118; CHECK-NEXT: vmsne.vi v0, v12, 0 119; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 120; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 121; CHECK-NEXT: ret 122 %cmp = fcmp oeq bfloat %a, %b 123 %v = select i1 %cmp, <16 x bfloat> %c, <16 x bfloat> %d 124 ret <16 x bfloat> %v 125} 126