1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 4; Test with ELEN limited 5; RUN: llc -mtriple=riscv32 -mattr=+f,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVE32F 6; RUN: llc -mtriple=riscv64 -mattr=+f,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVE32F 7 8define <1 x i1> @buildvec_mask_nonconst_v1i1(i1 %x) { 9; CHECK-LABEL: buildvec_mask_nonconst_v1i1: 10; CHECK: # %bb.0: 11; CHECK-NEXT: andi a0, a0, 1 12; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma 13; CHECK-NEXT: vmv.s.x v8, a0 14; CHECK-NEXT: vmsne.vi v0, v8, 0 15; CHECK-NEXT: ret 16; 17; ZVE32F-LABEL: buildvec_mask_nonconst_v1i1: 18; ZVE32F: # %bb.0: 19; ZVE32F-NEXT: andi a0, a0, 1 20; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma 21; ZVE32F-NEXT: vmv.s.x v8, a0 22; ZVE32F-NEXT: vmsne.vi v0, v8, 0 23; ZVE32F-NEXT: ret 24 %1 = insertelement <1 x i1> poison, i1 %x, i32 0 25 ret <1 x i1> %1 26} 27 28define <1 x i1> @buildvec_mask_optsize_nonconst_v1i1(i1 %x) optsize { 29; CHECK-LABEL: buildvec_mask_optsize_nonconst_v1i1: 30; CHECK: # %bb.0: 31; CHECK-NEXT: andi a0, a0, 1 32; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma 33; CHECK-NEXT: vmv.s.x v8, a0 34; CHECK-NEXT: vmsne.vi v0, v8, 0 35; CHECK-NEXT: ret 36; 37; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v1i1: 38; ZVE32F: # %bb.0: 39; ZVE32F-NEXT: andi a0, a0, 1 40; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma 41; ZVE32F-NEXT: vmv.s.x v8, a0 42; ZVE32F-NEXT: vmsne.vi v0, v8, 0 43; ZVE32F-NEXT: ret 44 %1 = insertelement <1 x i1> poison, i1 %x, i32 0 45 ret <1 x i1> %1 46} 47 48define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) { 49; CHECK-LABEL: buildvec_mask_nonconst_v2i1: 50; CHECK: # %bb.0: 51; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 52; CHECK-NEXT: vmv.v.x v8, a0 53; CHECK-NEXT: vslide1down.vx v8, v8, a1 54; CHECK-NEXT: vand.vi v8, v8, 1 55; CHECK-NEXT: vmsne.vi v0, v8, 0 56; CHECK-NEXT: ret 57; 58; ZVE32F-LABEL: buildvec_mask_nonconst_v2i1: 59; ZVE32F: # %bb.0: 60; ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma 61; ZVE32F-NEXT: vmv.v.x v8, a0 62; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 63; ZVE32F-NEXT: vand.vi v8, v8, 1 64; ZVE32F-NEXT: vmsne.vi v0, v8, 0 65; ZVE32F-NEXT: ret 66 %1 = insertelement <2 x i1> poison, i1 %x, i32 0 67 %2 = insertelement <2 x i1> %1, i1 %y, i32 1 68 ret <2 x i1> %2 69} 70 71; FIXME: optsize isn't smaller than the code above 72define <2 x i1> @buildvec_mask_optsize_nonconst_v2i1(i1 %x, i1 %y) optsize { 73; CHECK-LABEL: buildvec_mask_optsize_nonconst_v2i1: 74; CHECK: # %bb.0: 75; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 76; CHECK-NEXT: vmv.v.x v8, a0 77; CHECK-NEXT: vslide1down.vx v8, v8, a1 78; CHECK-NEXT: vand.vi v8, v8, 1 79; CHECK-NEXT: vmsne.vi v0, v8, 0 80; CHECK-NEXT: ret 81; 82; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v2i1: 83; ZVE32F: # %bb.0: 84; ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma 85; ZVE32F-NEXT: vmv.v.x v8, a0 86; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 87; ZVE32F-NEXT: vand.vi v8, v8, 1 88; ZVE32F-NEXT: vmsne.vi v0, v8, 0 89; ZVE32F-NEXT: ret 90 %1 = insertelement <2 x i1> poison, i1 %x, i32 0 91 %2 = insertelement <2 x i1> %1, i1 %y, i32 1 92 ret <2 x i1> %2 93} 94 95define <3 x i1> @buildvec_mask_v1i1() { 96; CHECK-LABEL: buildvec_mask_v1i1: 97; CHECK: # %bb.0: 98; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma 99; CHECK-NEXT: vmv.v.i v0, 2 100; CHECK-NEXT: ret 101; 102; ZVE32F-LABEL: buildvec_mask_v1i1: 103; ZVE32F: # %bb.0: 104; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma 105; ZVE32F-NEXT: vmv.v.i v0, 2 106; ZVE32F-NEXT: ret 107 ret <3 x i1> <i1 0, i1 1, i1 0> 108} 109 110define <3 x i1> @buildvec_mask_optsize_v1i1() optsize { 111; CHECK-LABEL: buildvec_mask_optsize_v1i1: 112; CHECK: # %bb.0: 113; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma 114; CHECK-NEXT: vmv.v.i v0, 2 115; CHECK-NEXT: ret 116; 117; ZVE32F-LABEL: buildvec_mask_optsize_v1i1: 118; ZVE32F: # %bb.0: 119; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma 120; ZVE32F-NEXT: vmv.v.i v0, 2 121; ZVE32F-NEXT: ret 122 ret <3 x i1> <i1 0, i1 1, i1 0> 123} 124 125define <4 x i1> @buildvec_mask_v4i1() { 126; CHECK-LABEL: buildvec_mask_v4i1: 127; CHECK: # %bb.0: 128; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma 129; CHECK-NEXT: vmv.v.i v0, 6 130; CHECK-NEXT: ret 131; 132; ZVE32F-LABEL: buildvec_mask_v4i1: 133; ZVE32F: # %bb.0: 134; ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma 135; ZVE32F-NEXT: vmv.v.i v0, 6 136; ZVE32F-NEXT: ret 137 ret <4 x i1> <i1 0, i1 1, i1 1, i1 0> 138} 139 140define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) { 141; CHECK-LABEL: buildvec_mask_nonconst_v4i1: 142; CHECK: # %bb.0: 143; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 144; CHECK-NEXT: vmv.v.i v0, 3 145; CHECK-NEXT: vmv.v.x v8, a1 146; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 147; CHECK-NEXT: vand.vi v8, v8, 1 148; CHECK-NEXT: vmsne.vi v0, v8, 0 149; CHECK-NEXT: ret 150; 151; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1: 152; ZVE32F: # %bb.0: 153; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 154; ZVE32F-NEXT: vmv.v.i v0, 3 155; ZVE32F-NEXT: vmv.v.x v8, a1 156; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0 157; ZVE32F-NEXT: vand.vi v8, v8, 1 158; ZVE32F-NEXT: vmsne.vi v0, v8, 0 159; ZVE32F-NEXT: ret 160 %1 = insertelement <4 x i1> poison, i1 %x, i32 0 161 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 162 %3 = insertelement <4 x i1> %2, i1 %y, i32 2 163 %4 = insertelement <4 x i1> %3, i1 %y, i32 3 164 ret <4 x i1> %4 165} 166 167; FIXME: optsize isn't smaller than the code above 168define <4 x i1> @buildvec_mask_optsize_nonconst_v4i1(i1 %x, i1 %y) optsize { 169; CHECK-LABEL: buildvec_mask_optsize_nonconst_v4i1: 170; CHECK: # %bb.0: 171; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 172; CHECK-NEXT: vmv.v.x v8, a0 173; CHECK-NEXT: vslide1down.vx v8, v8, a0 174; CHECK-NEXT: vslide1down.vx v8, v8, a1 175; CHECK-NEXT: vslide1down.vx v8, v8, a1 176; CHECK-NEXT: vand.vi v8, v8, 1 177; CHECK-NEXT: vmsne.vi v0, v8, 0 178; CHECK-NEXT: ret 179; 180; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v4i1: 181; ZVE32F: # %bb.0: 182; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 183; ZVE32F-NEXT: vmv.v.x v8, a0 184; ZVE32F-NEXT: vslide1down.vx v8, v8, a0 185; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 186; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 187; ZVE32F-NEXT: vand.vi v8, v8, 1 188; ZVE32F-NEXT: vmsne.vi v0, v8, 0 189; ZVE32F-NEXT: ret 190 %1 = insertelement <4 x i1> poison, i1 %x, i32 0 191 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 192 %3 = insertelement <4 x i1> %2, i1 %y, i32 2 193 %4 = insertelement <4 x i1> %3, i1 %y, i32 3 194 ret <4 x i1> %4 195} 196 197define <4 x i1> @buildvec_mask_nonconst_v4i1_2(i1 %x, i1 %y) { 198; CHECK-LABEL: buildvec_mask_nonconst_v4i1_2: 199; CHECK: # %bb.0: 200; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 201; CHECK-NEXT: vmv.v.i v8, 0 202; CHECK-NEXT: vslide1down.vx v8, v8, a0 203; CHECK-NEXT: li a0, 1 204; CHECK-NEXT: vslide1down.vx v8, v8, a0 205; CHECK-NEXT: vslide1down.vx v8, v8, a1 206; CHECK-NEXT: vand.vi v8, v8, 1 207; CHECK-NEXT: vmsne.vi v0, v8, 0 208; CHECK-NEXT: ret 209; 210; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1_2: 211; ZVE32F: # %bb.0: 212; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 213; ZVE32F-NEXT: vmv.v.i v8, 0 214; ZVE32F-NEXT: vslide1down.vx v8, v8, a0 215; ZVE32F-NEXT: li a0, 1 216; ZVE32F-NEXT: vslide1down.vx v8, v8, a0 217; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 218; ZVE32F-NEXT: vand.vi v8, v8, 1 219; ZVE32F-NEXT: vmsne.vi v0, v8, 0 220; ZVE32F-NEXT: ret 221 %1 = insertelement <4 x i1> poison, i1 0, i32 0 222 %2 = insertelement <4 x i1> %1, i1 %x, i32 1 223 %3 = insertelement <4 x i1> %2, i1 1, i32 2 224 %4 = insertelement <4 x i1> %3, i1 %y, i32 3 225 ret <4 x i1> %4 226} 227 228define <8 x i1> @buildvec_mask_v8i1() { 229; CHECK-LABEL: buildvec_mask_v8i1: 230; CHECK: # %bb.0: 231; CHECK-NEXT: li a0, 182 232; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma 233; CHECK-NEXT: vmv.s.x v0, a0 234; CHECK-NEXT: ret 235; 236; ZVE32F-LABEL: buildvec_mask_v8i1: 237; ZVE32F: # %bb.0: 238; ZVE32F-NEXT: li a0, 182 239; ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma 240; ZVE32F-NEXT: vmv.s.x v0, a0 241; ZVE32F-NEXT: ret 242 ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> 243} 244 245define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) { 246; CHECK-LABEL: buildvec_mask_nonconst_v8i1: 247; CHECK: # %bb.0: 248; CHECK-NEXT: li a2, 19 249; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 250; CHECK-NEXT: vmv.s.x v0, a2 251; CHECK-NEXT: vmv.v.x v8, a1 252; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 253; CHECK-NEXT: vand.vi v8, v8, 1 254; CHECK-NEXT: vmsne.vi v0, v8, 0 255; CHECK-NEXT: ret 256; 257; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1: 258; ZVE32F: # %bb.0: 259; ZVE32F-NEXT: li a2, 19 260; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 261; ZVE32F-NEXT: vmv.s.x v0, a2 262; ZVE32F-NEXT: vmv.v.x v8, a1 263; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0 264; ZVE32F-NEXT: vand.vi v8, v8, 1 265; ZVE32F-NEXT: vmsne.vi v0, v8, 0 266; ZVE32F-NEXT: ret 267 %1 = insertelement <8 x i1> poison, i1 %x, i32 0 268 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 269 %3 = insertelement <8 x i1> %2, i1 %y, i32 2 270 %4 = insertelement <8 x i1> %3, i1 %y, i32 3 271 %5 = insertelement <8 x i1> %4, i1 %x, i32 4 272 %6 = insertelement <8 x i1> %5, i1 %y, i32 5 273 %7 = insertelement <8 x i1> %6, i1 %y, i32 6 274 %8 = insertelement <8 x i1> %7, i1 %y, i32 7 275 ret <8 x i1> %8 276} 277 278define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) { 279; CHECK-LABEL: buildvec_mask_nonconst_v8i1_2: 280; CHECK: # %bb.0: 281; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 282; CHECK-NEXT: vmv.v.x v8, a0 283; CHECK-NEXT: vslide1down.vx v9, v8, a0 284; CHECK-NEXT: li a0, 1 285; CHECK-NEXT: vmv.v.i v0, 15 286; CHECK-NEXT: vslide1down.vx v8, v8, a3 287; CHECK-NEXT: vslide1down.vx v9, v9, a0 288; CHECK-NEXT: vslide1down.vx v8, v8, zero 289; CHECK-NEXT: vslide1down.vx v9, v9, a1 290; CHECK-NEXT: vslide1down.vx v8, v8, a2 291; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t 292; CHECK-NEXT: vand.vi v8, v8, 1 293; CHECK-NEXT: vmsne.vi v0, v8, 0 294; CHECK-NEXT: ret 295; 296; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1_2: 297; ZVE32F: # %bb.0: 298; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 299; ZVE32F-NEXT: vmv.v.x v8, a0 300; ZVE32F-NEXT: vslide1down.vx v9, v8, a0 301; ZVE32F-NEXT: li a0, 1 302; ZVE32F-NEXT: vmv.v.i v0, 15 303; ZVE32F-NEXT: vslide1down.vx v8, v8, a3 304; ZVE32F-NEXT: vslide1down.vx v9, v9, a0 305; ZVE32F-NEXT: vslide1down.vx v8, v8, zero 306; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 307; ZVE32F-NEXT: vslide1down.vx v8, v8, a2 308; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t 309; ZVE32F-NEXT: vand.vi v8, v8, 1 310; ZVE32F-NEXT: vmsne.vi v0, v8, 0 311; ZVE32F-NEXT: ret 312 %1 = insertelement <8 x i1> poison, i1 %x, i32 0 313 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 314 %3 = insertelement <8 x i1> %2, i1 1, i32 2 315 %4 = insertelement <8 x i1> %3, i1 %y, i32 3 316 %5 = insertelement <8 x i1> %4, i1 %x, i32 4 317 %6 = insertelement <8 x i1> %5, i1 %w, i32 5 318 %7 = insertelement <8 x i1> %6, i1 0, i32 6 319 %8 = insertelement <8 x i1> %7, i1 %z, i32 7 320 ret <8 x i1> %8 321} 322 323define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) optsize { 324; CHECK-LABEL: buildvec_mask_optsize_nonconst_v8i1_2: 325; CHECK: # %bb.0: 326; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 327; CHECK-NEXT: vmv.v.x v8, a0 328; CHECK-NEXT: vslide1down.vx v9, v8, a0 329; CHECK-NEXT: li a0, 1 330; CHECK-NEXT: vmv.v.i v0, 15 331; CHECK-NEXT: vslide1down.vx v8, v8, a3 332; CHECK-NEXT: vslide1down.vx v9, v9, a0 333; CHECK-NEXT: vslide1down.vx v8, v8, zero 334; CHECK-NEXT: vslide1down.vx v9, v9, a1 335; CHECK-NEXT: vslide1down.vx v8, v8, a2 336; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t 337; CHECK-NEXT: vand.vi v8, v8, 1 338; CHECK-NEXT: vmsne.vi v0, v8, 0 339; CHECK-NEXT: ret 340; 341; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1_2: 342; ZVE32F: # %bb.0: 343; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 344; ZVE32F-NEXT: vmv.v.x v8, a0 345; ZVE32F-NEXT: vslide1down.vx v9, v8, a0 346; ZVE32F-NEXT: li a0, 1 347; ZVE32F-NEXT: vmv.v.i v0, 15 348; ZVE32F-NEXT: vslide1down.vx v8, v8, a3 349; ZVE32F-NEXT: vslide1down.vx v9, v9, a0 350; ZVE32F-NEXT: vslide1down.vx v8, v8, zero 351; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 352; ZVE32F-NEXT: vslide1down.vx v8, v8, a2 353; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t 354; ZVE32F-NEXT: vand.vi v8, v8, 1 355; ZVE32F-NEXT: vmsne.vi v0, v8, 0 356; ZVE32F-NEXT: ret 357 %1 = insertelement <8 x i1> poison, i1 %x, i32 0 358 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 359 %3 = insertelement <8 x i1> %2, i1 1, i32 2 360 %4 = insertelement <8 x i1> %3, i1 %y, i32 3 361 %5 = insertelement <8 x i1> %4, i1 %x, i32 4 362 %6 = insertelement <8 x i1> %5, i1 %w, i32 5 363 %7 = insertelement <8 x i1> %6, i1 0, i32 6 364 %8 = insertelement <8 x i1> %7, i1 %z, i32 7 365 ret <8 x i1> %8 366} 367 368define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize { 369; CHECK-LABEL: buildvec_mask_optsize_nonconst_v8i1: 370; CHECK: # %bb.0: 371; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 372; CHECK-NEXT: vmv.v.x v8, a0 373; CHECK-NEXT: vmv.v.i v0, 15 374; CHECK-NEXT: vslide1down.vx v9, v8, a0 375; CHECK-NEXT: vslide1down.vx v8, v8, a1 376; CHECK-NEXT: vslide1down.vx v9, v9, a1 377; CHECK-NEXT: vslide1down.vx v8, v8, a1 378; CHECK-NEXT: vslide1down.vx v9, v9, a1 379; CHECK-NEXT: vslide1down.vx v8, v8, a1 380; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t 381; CHECK-NEXT: vand.vi v8, v8, 1 382; CHECK-NEXT: vmsne.vi v0, v8, 0 383; CHECK-NEXT: ret 384; 385; ZVE32F-LABEL: buildvec_mask_optsize_nonconst_v8i1: 386; ZVE32F: # %bb.0: 387; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 388; ZVE32F-NEXT: vmv.v.x v8, a0 389; ZVE32F-NEXT: vmv.v.i v0, 15 390; ZVE32F-NEXT: vslide1down.vx v9, v8, a0 391; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 392; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 393; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 394; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 395; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 396; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t 397; ZVE32F-NEXT: vand.vi v8, v8, 1 398; ZVE32F-NEXT: vmsne.vi v0, v8, 0 399; ZVE32F-NEXT: ret 400 %1 = insertelement <8 x i1> poison, i1 %x, i32 0 401 %2 = insertelement <8 x i1> %1, i1 %x, i32 1 402 %3 = insertelement <8 x i1> %2, i1 %y, i32 2 403 %4 = insertelement <8 x i1> %3, i1 %y, i32 3 404 %5 = insertelement <8 x i1> %4, i1 %x, i32 4 405 %6 = insertelement <8 x i1> %5, i1 %y, i32 5 406 %7 = insertelement <8 x i1> %6, i1 %y, i32 6 407 %8 = insertelement <8 x i1> %7, i1 %y, i32 7 408 ret <8 x i1> %8 409} 410 411define <10 x i1> @buildvec_mask_v10i1() { 412; CHECK-LABEL: buildvec_mask_v10i1: 413; CHECK: # %bb.0: 414; CHECK-NEXT: li a0, 949 415; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma 416; CHECK-NEXT: vmv.s.x v0, a0 417; CHECK-NEXT: ret 418; 419; ZVE32F-LABEL: buildvec_mask_v10i1: 420; ZVE32F: # %bb.0: 421; ZVE32F-NEXT: li a0, 949 422; ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma 423; ZVE32F-NEXT: vmv.s.x v0, a0 424; ZVE32F-NEXT: ret 425 ret <10 x i1> <i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1> 426} 427 428define <16 x i1> @buildvec_mask_v16i1() { 429; CHECK-LABEL: buildvec_mask_v16i1: 430; CHECK: # %bb.0: 431; CHECK-NEXT: lui a0, 11 432; CHECK-NEXT: addi a0, a0, 1718 433; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma 434; CHECK-NEXT: vmv.s.x v0, a0 435; CHECK-NEXT: ret 436; 437; ZVE32F-LABEL: buildvec_mask_v16i1: 438; ZVE32F: # %bb.0: 439; ZVE32F-NEXT: lui a0, 11 440; ZVE32F-NEXT: addi a0, a0, 1718 441; ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma 442; ZVE32F-NEXT: vmv.s.x v0, a0 443; ZVE32F-NEXT: ret 444 ret <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> 445} 446 447define <16 x i1> @buildvec_mask_v16i1_undefs() { 448; CHECK-LABEL: buildvec_mask_v16i1_undefs: 449; CHECK: # %bb.0: 450; CHECK-NEXT: li a0, 1722 451; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma 452; CHECK-NEXT: vmv.s.x v0, a0 453; CHECK-NEXT: ret 454; 455; ZVE32F-LABEL: buildvec_mask_v16i1_undefs: 456; ZVE32F: # %bb.0: 457; ZVE32F-NEXT: li a0, 1722 458; ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma 459; ZVE32F-NEXT: vmv.s.x v0, a0 460; ZVE32F-NEXT: ret 461 ret <16 x i1> <i1 undef, i1 1, i1 undef, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef> 462} 463 464define <32 x i1> @buildvec_mask_v32i1() { 465; CHECK-LABEL: buildvec_mask_v32i1: 466; CHECK: # %bb.0: 467; CHECK-NEXT: lui a0, 748384 468; CHECK-NEXT: addi a0, a0, 1776 469; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma 470; CHECK-NEXT: vmv.s.x v0, a0 471; CHECK-NEXT: ret 472; 473; ZVE32F-LABEL: buildvec_mask_v32i1: 474; ZVE32F: # %bb.0: 475; ZVE32F-NEXT: lui a0, 748384 476; ZVE32F-NEXT: addi a0, a0, 1776 477; ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma 478; ZVE32F-NEXT: vmv.s.x v0, a0 479; ZVE32F-NEXT: ret 480 ret <32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> 481} 482 483define <64 x i1> @buildvec_mask_v64i1() { 484; RV32-LABEL: buildvec_mask_v64i1: 485; RV32: # %bb.0: 486; RV32-NEXT: lui a0, 748388 487; RV32-NEXT: addi a0, a0, -1793 488; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 489; RV32-NEXT: vmv.v.x v0, a0 490; RV32-NEXT: lui a0, 748384 491; RV32-NEXT: addi a0, a0, 1776 492; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma 493; RV32-NEXT: vmv.s.x v0, a0 494; RV32-NEXT: ret 495; 496; RV64-LABEL: buildvec_mask_v64i1: 497; RV64: # %bb.0: 498; RV64-NEXT: lui a0, %hi(.LCPI19_0) 499; RV64-NEXT: addi a0, a0, %lo(.LCPI19_0) 500; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma 501; RV64-NEXT: vle64.v v0, (a0) 502; RV64-NEXT: ret 503; 504; ZVE32F-LABEL: buildvec_mask_v64i1: 505; ZVE32F: # %bb.0: 506; ZVE32F-NEXT: lui a0, 748388 507; ZVE32F-NEXT: addi a0, a0, -1793 508; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma 509; ZVE32F-NEXT: vmv.v.x v0, a0 510; ZVE32F-NEXT: lui a0, 748384 511; ZVE32F-NEXT: addi a0, a0, 1776 512; ZVE32F-NEXT: vsetvli zero, zero, e32, m1, tu, ma 513; ZVE32F-NEXT: vmv.s.x v0, a0 514; ZVE32F-NEXT: ret 515 ret <64 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1> 516} 517 518define <128 x i1> @buildvec_mask_v128i1() { 519; RV32-LABEL: buildvec_mask_v128i1: 520; RV32: # %bb.0: 521; RV32-NEXT: lui a0, %hi(.LCPI20_0) 522; RV32-NEXT: addi a0, a0, %lo(.LCPI20_0) 523; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 524; RV32-NEXT: vle32.v v0, (a0) 525; RV32-NEXT: ret 526; 527; RV64-LABEL: buildvec_mask_v128i1: 528; RV64: # %bb.0: 529; RV64-NEXT: lui a0, %hi(.LCPI20_0) 530; RV64-NEXT: ld a0, %lo(.LCPI20_0)(a0) 531; RV64-NEXT: lui a1, %hi(.LCPI20_1) 532; RV64-NEXT: ld a1, %lo(.LCPI20_1)(a1) 533; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 534; RV64-NEXT: vmv.v.x v0, a0 535; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma 536; RV64-NEXT: vmv.s.x v0, a1 537; RV64-NEXT: ret 538; 539; ZVE32F-LABEL: buildvec_mask_v128i1: 540; ZVE32F: # %bb.0: 541; ZVE32F-NEXT: lui a0, %hi(.LCPI20_0) 542; ZVE32F-NEXT: addi a0, a0, %lo(.LCPI20_0) 543; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma 544; ZVE32F-NEXT: vle32.v v0, (a0) 545; ZVE32F-NEXT: ret 546 ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1> 547} 548 549define <128 x i1> @buildvec_mask_optsize_v128i1() optsize { 550; CHECK-LABEL: buildvec_mask_optsize_v128i1: 551; CHECK: # %bb.0: 552; CHECK-NEXT: li a0, 128 553; CHECK-NEXT: lui a1, %hi(.LCPI21_0) 554; CHECK-NEXT: addi a1, a1, %lo(.LCPI21_0) 555; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 556; CHECK-NEXT: vlm.v v0, (a1) 557; CHECK-NEXT: ret 558; 559; ZVE32F-LABEL: buildvec_mask_optsize_v128i1: 560; ZVE32F: # %bb.0: 561; ZVE32F-NEXT: li a0, 128 562; ZVE32F-NEXT: lui a1, %hi(.LCPI21_0) 563; ZVE32F-NEXT: addi a1, a1, %lo(.LCPI21_0) 564; ZVE32F-NEXT: vsetvli zero, a0, e8, m8, ta, ma 565; ZVE32F-NEXT: vlm.v v0, (a1) 566; ZVE32F-NEXT: ret 567 ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1> 568} 569 570define <4 x i1> @buildvec_mask_splat(i1 %e1) { 571; CHECK-LABEL: buildvec_mask_splat: 572; CHECK: # %bb.0: 573; CHECK-NEXT: andi a0, a0, 1 574; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 575; CHECK-NEXT: vmv.v.x v8, a0 576; CHECK-NEXT: vmsne.vi v0, v8, 0 577; CHECK-NEXT: ret 578; 579; ZVE32F-LABEL: buildvec_mask_splat: 580; ZVE32F: # %bb.0: 581; ZVE32F-NEXT: andi a0, a0, 1 582; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 583; ZVE32F-NEXT: vmv.v.x v8, a0 584; ZVE32F-NEXT: vmsne.vi v0, v8, 0 585; ZVE32F-NEXT: ret 586 %v1 = insertelement <4 x i1> poison, i1 %e1, i32 0 587 %v2 = insertelement <4 x i1> %v1, i1 %e1, i32 1 588 %v3 = insertelement <4 x i1> %v2, i1 %e1, i32 2 589 %v4 = insertelement <4 x i1> %v3, i1 %e1, i32 3 590 ret <4 x i1> %v4 591} 592