xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \
3; RUN:     -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV32
4; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
5; RUN:     -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i32
6; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
7; RUN:     -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i64
8
9define <1 x iXLen> @lrint_v1f32(<1 x float> %x) {
10; RV32-LABEL: lrint_v1f32:
11; RV32:       # %bb.0:
12; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
13; RV32-NEXT:    vfmv.f.s fa5, v8
14; RV32-NEXT:    fcvt.w.s a0, fa5
15; RV32-NEXT:    vmv.s.x v8, a0
16; RV32-NEXT:    ret
17;
18; RV64-i32-LABEL: lrint_v1f32:
19; RV64-i32:       # %bb.0:
20; RV64-i32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
21; RV64-i32-NEXT:    vfmv.f.s fa5, v8
22; RV64-i32-NEXT:    fcvt.l.s a0, fa5
23; RV64-i32-NEXT:    vmv.s.x v8, a0
24; RV64-i32-NEXT:    ret
25;
26; RV64-i64-LABEL: lrint_v1f32:
27; RV64-i64:       # %bb.0:
28; RV64-i64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
29; RV64-i64-NEXT:    vfmv.f.s fa5, v8
30; RV64-i64-NEXT:    fcvt.l.s a0, fa5
31; RV64-i64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
32; RV64-i64-NEXT:    vmv.s.x v8, a0
33; RV64-i64-NEXT:    ret
34  %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float> %x)
35  ret <1 x iXLen> %a
36}
37declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float>)
38
39define <2 x iXLen> @lrint_v2f32(<2 x float> %x) {
40; RV32-LABEL: lrint_v2f32:
41; RV32:       # %bb.0:
42; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
43; RV32-NEXT:    vslidedown.vi v9, v8, 1
44; RV32-NEXT:    vfmv.f.s fa5, v8
45; RV32-NEXT:    fcvt.w.s a0, fa5
46; RV32-NEXT:    vfmv.f.s fa5, v9
47; RV32-NEXT:    fcvt.w.s a1, fa5
48; RV32-NEXT:    vmv.v.x v8, a0
49; RV32-NEXT:    vslide1down.vx v8, v8, a1
50; RV32-NEXT:    ret
51;
52; RV64-i32-LABEL: lrint_v2f32:
53; RV64-i32:       # %bb.0:
54; RV64-i32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
55; RV64-i32-NEXT:    vslidedown.vi v9, v8, 1
56; RV64-i32-NEXT:    vfmv.f.s fa5, v8
57; RV64-i32-NEXT:    fcvt.l.s a0, fa5
58; RV64-i32-NEXT:    vfmv.f.s fa5, v9
59; RV64-i32-NEXT:    fcvt.l.s a1, fa5
60; RV64-i32-NEXT:    vmv.v.x v8, a0
61; RV64-i32-NEXT:    vslide1down.vx v8, v8, a1
62; RV64-i32-NEXT:    ret
63;
64; RV64-i64-LABEL: lrint_v2f32:
65; RV64-i64:       # %bb.0:
66; RV64-i64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
67; RV64-i64-NEXT:    vslidedown.vi v9, v8, 1
68; RV64-i64-NEXT:    vfmv.f.s fa5, v8
69; RV64-i64-NEXT:    fcvt.l.s a0, fa5
70; RV64-i64-NEXT:    vfmv.f.s fa5, v9
71; RV64-i64-NEXT:    fcvt.l.s a1, fa5
72; RV64-i64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
73; RV64-i64-NEXT:    vmv.v.x v8, a0
74; RV64-i64-NEXT:    vslide1down.vx v8, v8, a1
75; RV64-i64-NEXT:    ret
76  %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float> %x)
77  ret <2 x iXLen> %a
78}
79declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f32(<2 x float>)
80
81define <3 x iXLen> @lrint_v3f32(<3 x float> %x) {
82; RV32-LABEL: lrint_v3f32:
83; RV32:       # %bb.0:
84; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
85; RV32-NEXT:    vslidedown.vi v9, v8, 1
86; RV32-NEXT:    vfmv.f.s fa5, v8
87; RV32-NEXT:    vslidedown.vi v10, v8, 2
88; RV32-NEXT:    vslidedown.vi v8, v8, 3
89; RV32-NEXT:    fcvt.w.s a0, fa5
90; RV32-NEXT:    vfmv.f.s fa5, v9
91; RV32-NEXT:    fcvt.w.s a1, fa5
92; RV32-NEXT:    vfmv.f.s fa5, v10
93; RV32-NEXT:    vmv.v.x v9, a0
94; RV32-NEXT:    fcvt.w.s a0, fa5
95; RV32-NEXT:    vfmv.f.s fa5, v8
96; RV32-NEXT:    vslide1down.vx v8, v9, a1
97; RV32-NEXT:    vslide1down.vx v8, v8, a0
98; RV32-NEXT:    fcvt.w.s a0, fa5
99; RV32-NEXT:    vslide1down.vx v8, v8, a0
100; RV32-NEXT:    ret
101;
102; RV64-i32-LABEL: lrint_v3f32:
103; RV64-i32:       # %bb.0:
104; RV64-i32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
105; RV64-i32-NEXT:    vslidedown.vi v9, v8, 1
106; RV64-i32-NEXT:    vfmv.f.s fa5, v8
107; RV64-i32-NEXT:    vslidedown.vi v10, v8, 2
108; RV64-i32-NEXT:    vslidedown.vi v8, v8, 3
109; RV64-i32-NEXT:    fcvt.l.s a0, fa5
110; RV64-i32-NEXT:    vfmv.f.s fa5, v9
111; RV64-i32-NEXT:    fcvt.l.s a1, fa5
112; RV64-i32-NEXT:    vfmv.f.s fa5, v10
113; RV64-i32-NEXT:    vmv.v.x v9, a0
114; RV64-i32-NEXT:    fcvt.l.s a0, fa5
115; RV64-i32-NEXT:    vfmv.f.s fa5, v8
116; RV64-i32-NEXT:    vslide1down.vx v8, v9, a1
117; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
118; RV64-i32-NEXT:    fcvt.l.s a0, fa5
119; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
120; RV64-i32-NEXT:    ret
121;
122; RV64-i64-LABEL: lrint_v3f32:
123; RV64-i64:       # %bb.0:
124; RV64-i64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
125; RV64-i64-NEXT:    vslidedown.vi v9, v8, 1
126; RV64-i64-NEXT:    vfmv.f.s fa5, v8
127; RV64-i64-NEXT:    vslidedown.vi v10, v8, 2
128; RV64-i64-NEXT:    vslidedown.vi v8, v8, 3
129; RV64-i64-NEXT:    fcvt.l.s a0, fa5
130; RV64-i64-NEXT:    vfmv.f.s fa5, v9
131; RV64-i64-NEXT:    fcvt.l.s a1, fa5
132; RV64-i64-NEXT:    vfmv.f.s fa5, v10
133; RV64-i64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
134; RV64-i64-NEXT:    vmv.v.x v10, a0
135; RV64-i64-NEXT:    fcvt.l.s a0, fa5
136; RV64-i64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
137; RV64-i64-NEXT:    vfmv.f.s fa5, v8
138; RV64-i64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
139; RV64-i64-NEXT:    vslide1down.vx v8, v10, a1
140; RV64-i64-NEXT:    vslide1down.vx v8, v8, a0
141; RV64-i64-NEXT:    fcvt.l.s a0, fa5
142; RV64-i64-NEXT:    vslide1down.vx v8, v8, a0
143; RV64-i64-NEXT:    ret
144  %a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3f32(<3 x float> %x)
145  ret <3 x iXLen> %a
146}
147declare <3 x iXLen> @llvm.lrint.v3iXLen.v3f32(<3 x float>)
148
149define <4 x iXLen> @lrint_v4f32(<4 x float> %x) {
150; RV32-LABEL: lrint_v4f32:
151; RV32:       # %bb.0:
152; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
153; RV32-NEXT:    vslidedown.vi v9, v8, 1
154; RV32-NEXT:    vfmv.f.s fa5, v8
155; RV32-NEXT:    vslidedown.vi v10, v8, 2
156; RV32-NEXT:    vslidedown.vi v8, v8, 3
157; RV32-NEXT:    fcvt.w.s a0, fa5
158; RV32-NEXT:    vfmv.f.s fa5, v9
159; RV32-NEXT:    fcvt.w.s a1, fa5
160; RV32-NEXT:    vfmv.f.s fa5, v10
161; RV32-NEXT:    vmv.v.x v9, a0
162; RV32-NEXT:    fcvt.w.s a0, fa5
163; RV32-NEXT:    vfmv.f.s fa5, v8
164; RV32-NEXT:    vslide1down.vx v8, v9, a1
165; RV32-NEXT:    vslide1down.vx v8, v8, a0
166; RV32-NEXT:    fcvt.w.s a0, fa5
167; RV32-NEXT:    vslide1down.vx v8, v8, a0
168; RV32-NEXT:    ret
169;
170; RV64-i32-LABEL: lrint_v4f32:
171; RV64-i32:       # %bb.0:
172; RV64-i32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
173; RV64-i32-NEXT:    vslidedown.vi v9, v8, 1
174; RV64-i32-NEXT:    vfmv.f.s fa5, v8
175; RV64-i32-NEXT:    vslidedown.vi v10, v8, 2
176; RV64-i32-NEXT:    vslidedown.vi v8, v8, 3
177; RV64-i32-NEXT:    fcvt.l.s a0, fa5
178; RV64-i32-NEXT:    vfmv.f.s fa5, v9
179; RV64-i32-NEXT:    fcvt.l.s a1, fa5
180; RV64-i32-NEXT:    vfmv.f.s fa5, v10
181; RV64-i32-NEXT:    vmv.v.x v9, a0
182; RV64-i32-NEXT:    fcvt.l.s a0, fa5
183; RV64-i32-NEXT:    vfmv.f.s fa5, v8
184; RV64-i32-NEXT:    vslide1down.vx v8, v9, a1
185; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
186; RV64-i32-NEXT:    fcvt.l.s a0, fa5
187; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
188; RV64-i32-NEXT:    ret
189;
190; RV64-i64-LABEL: lrint_v4f32:
191; RV64-i64:       # %bb.0:
192; RV64-i64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
193; RV64-i64-NEXT:    vslidedown.vi v9, v8, 1
194; RV64-i64-NEXT:    vfmv.f.s fa5, v8
195; RV64-i64-NEXT:    vslidedown.vi v10, v8, 2
196; RV64-i64-NEXT:    vslidedown.vi v8, v8, 3
197; RV64-i64-NEXT:    fcvt.l.s a0, fa5
198; RV64-i64-NEXT:    vfmv.f.s fa5, v9
199; RV64-i64-NEXT:    fcvt.l.s a1, fa5
200; RV64-i64-NEXT:    vfmv.f.s fa5, v10
201; RV64-i64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
202; RV64-i64-NEXT:    vmv.v.x v10, a0
203; RV64-i64-NEXT:    fcvt.l.s a0, fa5
204; RV64-i64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
205; RV64-i64-NEXT:    vfmv.f.s fa5, v8
206; RV64-i64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
207; RV64-i64-NEXT:    vslide1down.vx v8, v10, a1
208; RV64-i64-NEXT:    vslide1down.vx v8, v8, a0
209; RV64-i64-NEXT:    fcvt.l.s a0, fa5
210; RV64-i64-NEXT:    vslide1down.vx v8, v8, a0
211; RV64-i64-NEXT:    ret
212  %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float> %x)
213  ret <4 x iXLen> %a
214}
215declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f32(<4 x float>)
216
217define <8 x iXLen> @lrint_v8f32(<8 x float> %x) {
218; RV32-LABEL: lrint_v8f32:
219; RV32:       # %bb.0:
220; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
221; RV32-NEXT:    vslidedown.vi v10, v8, 1
222; RV32-NEXT:    vfmv.f.s fa5, v8
223; RV32-NEXT:    vslidedown.vi v11, v8, 2
224; RV32-NEXT:    vslidedown.vi v12, v8, 3
225; RV32-NEXT:    fcvt.w.s a0, fa5
226; RV32-NEXT:    vfmv.f.s fa5, v10
227; RV32-NEXT:    fcvt.w.s a1, fa5
228; RV32-NEXT:    vfmv.f.s fa5, v11
229; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
230; RV32-NEXT:    vmv.v.x v10, a0
231; RV32-NEXT:    fcvt.w.s a0, fa5
232; RV32-NEXT:    vfmv.f.s fa5, v12
233; RV32-NEXT:    vslidedown.vi v12, v8, 4
234; RV32-NEXT:    vslide1down.vx v10, v10, a1
235; RV32-NEXT:    fcvt.w.s a1, fa5
236; RV32-NEXT:    vfmv.f.s fa5, v12
237; RV32-NEXT:    vslidedown.vi v12, v8, 5
238; RV32-NEXT:    vslide1down.vx v10, v10, a0
239; RV32-NEXT:    fcvt.w.s a0, fa5
240; RV32-NEXT:    vfmv.f.s fa5, v12
241; RV32-NEXT:    vslidedown.vi v12, v8, 6
242; RV32-NEXT:    vslidedown.vi v8, v8, 7
243; RV32-NEXT:    vslide1down.vx v10, v10, a1
244; RV32-NEXT:    fcvt.w.s a1, fa5
245; RV32-NEXT:    vfmv.f.s fa5, v12
246; RV32-NEXT:    vslide1down.vx v10, v10, a0
247; RV32-NEXT:    fcvt.w.s a0, fa5
248; RV32-NEXT:    vfmv.f.s fa5, v8
249; RV32-NEXT:    vslide1down.vx v8, v10, a1
250; RV32-NEXT:    vslide1down.vx v8, v8, a0
251; RV32-NEXT:    fcvt.w.s a0, fa5
252; RV32-NEXT:    vslide1down.vx v8, v8, a0
253; RV32-NEXT:    ret
254;
255; RV64-i32-LABEL: lrint_v8f32:
256; RV64-i32:       # %bb.0:
257; RV64-i32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
258; RV64-i32-NEXT:    vslidedown.vi v10, v8, 1
259; RV64-i32-NEXT:    vfmv.f.s fa5, v8
260; RV64-i32-NEXT:    vslidedown.vi v11, v8, 2
261; RV64-i32-NEXT:    vslidedown.vi v12, v8, 3
262; RV64-i32-NEXT:    fcvt.l.s a0, fa5
263; RV64-i32-NEXT:    vfmv.f.s fa5, v10
264; RV64-i32-NEXT:    fcvt.l.s a1, fa5
265; RV64-i32-NEXT:    vfmv.f.s fa5, v11
266; RV64-i32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
267; RV64-i32-NEXT:    vmv.v.x v10, a0
268; RV64-i32-NEXT:    fcvt.l.s a0, fa5
269; RV64-i32-NEXT:    vfmv.f.s fa5, v12
270; RV64-i32-NEXT:    vslidedown.vi v12, v8, 4
271; RV64-i32-NEXT:    vslide1down.vx v10, v10, a1
272; RV64-i32-NEXT:    fcvt.l.s a1, fa5
273; RV64-i32-NEXT:    vfmv.f.s fa5, v12
274; RV64-i32-NEXT:    vslidedown.vi v12, v8, 5
275; RV64-i32-NEXT:    vslide1down.vx v10, v10, a0
276; RV64-i32-NEXT:    fcvt.l.s a0, fa5
277; RV64-i32-NEXT:    vfmv.f.s fa5, v12
278; RV64-i32-NEXT:    vslidedown.vi v12, v8, 6
279; RV64-i32-NEXT:    vslidedown.vi v8, v8, 7
280; RV64-i32-NEXT:    vslide1down.vx v10, v10, a1
281; RV64-i32-NEXT:    fcvt.l.s a1, fa5
282; RV64-i32-NEXT:    vfmv.f.s fa5, v12
283; RV64-i32-NEXT:    vslide1down.vx v10, v10, a0
284; RV64-i32-NEXT:    fcvt.l.s a0, fa5
285; RV64-i32-NEXT:    vfmv.f.s fa5, v8
286; RV64-i32-NEXT:    vslide1down.vx v8, v10, a1
287; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
288; RV64-i32-NEXT:    fcvt.l.s a0, fa5
289; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
290; RV64-i32-NEXT:    ret
291;
292; RV64-i64-LABEL: lrint_v8f32:
293; RV64-i64:       # %bb.0:
294; RV64-i64-NEXT:    addi sp, sp, -128
295; RV64-i64-NEXT:    .cfi_def_cfa_offset 128
296; RV64-i64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
297; RV64-i64-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
298; RV64-i64-NEXT:    .cfi_offset ra, -8
299; RV64-i64-NEXT:    .cfi_offset s0, -16
300; RV64-i64-NEXT:    addi s0, sp, 128
301; RV64-i64-NEXT:    .cfi_def_cfa s0, 0
302; RV64-i64-NEXT:    andi sp, sp, -64
303; RV64-i64-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
304; RV64-i64-NEXT:    vfmv.f.s fa5, v8
305; RV64-i64-NEXT:    vslidedown.vi v10, v8, 7
306; RV64-i64-NEXT:    fcvt.l.s a0, fa5
307; RV64-i64-NEXT:    vfmv.f.s fa5, v10
308; RV64-i64-NEXT:    vslidedown.vi v10, v8, 6
309; RV64-i64-NEXT:    fcvt.l.s a1, fa5
310; RV64-i64-NEXT:    vfmv.f.s fa5, v10
311; RV64-i64-NEXT:    vslidedown.vi v10, v8, 5
312; RV64-i64-NEXT:    fcvt.l.s a2, fa5
313; RV64-i64-NEXT:    vfmv.f.s fa5, v10
314; RV64-i64-NEXT:    vslidedown.vi v10, v8, 4
315; RV64-i64-NEXT:    fcvt.l.s a3, fa5
316; RV64-i64-NEXT:    vfmv.f.s fa5, v10
317; RV64-i64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
318; RV64-i64-NEXT:    vslidedown.vi v9, v8, 3
319; RV64-i64-NEXT:    vslidedown.vi v10, v8, 2
320; RV64-i64-NEXT:    vslidedown.vi v8, v8, 1
321; RV64-i64-NEXT:    fcvt.l.s a4, fa5
322; RV64-i64-NEXT:    vfmv.f.s fa5, v9
323; RV64-i64-NEXT:    fcvt.l.s a5, fa5
324; RV64-i64-NEXT:    vfmv.f.s fa5, v10
325; RV64-i64-NEXT:    fcvt.l.s a6, fa5
326; RV64-i64-NEXT:    vfmv.f.s fa5, v8
327; RV64-i64-NEXT:    sd a4, 32(sp)
328; RV64-i64-NEXT:    sd a3, 40(sp)
329; RV64-i64-NEXT:    sd a2, 48(sp)
330; RV64-i64-NEXT:    sd a1, 56(sp)
331; RV64-i64-NEXT:    fcvt.l.s a1, fa5
332; RV64-i64-NEXT:    sd a0, 0(sp)
333; RV64-i64-NEXT:    sd a1, 8(sp)
334; RV64-i64-NEXT:    sd a6, 16(sp)
335; RV64-i64-NEXT:    sd a5, 24(sp)
336; RV64-i64-NEXT:    mv a0, sp
337; RV64-i64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
338; RV64-i64-NEXT:    vle64.v v8, (a0)
339; RV64-i64-NEXT:    addi sp, s0, -128
340; RV64-i64-NEXT:    .cfi_def_cfa sp, 128
341; RV64-i64-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
342; RV64-i64-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
343; RV64-i64-NEXT:    .cfi_restore ra
344; RV64-i64-NEXT:    .cfi_restore s0
345; RV64-i64-NEXT:    addi sp, sp, 128
346; RV64-i64-NEXT:    .cfi_def_cfa_offset 0
347; RV64-i64-NEXT:    ret
348  %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float> %x)
349  ret <8 x iXLen> %a
350}
351declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float>)
352
353define <16 x iXLen> @lrint_v16f32(<16 x float> %x) {
354; RV32-LABEL: lrint_v16f32:
355; RV32:       # %bb.0:
356; RV32-NEXT:    addi sp, sp, -192
357; RV32-NEXT:    .cfi_def_cfa_offset 192
358; RV32-NEXT:    sw ra, 188(sp) # 4-byte Folded Spill
359; RV32-NEXT:    sw s0, 184(sp) # 4-byte Folded Spill
360; RV32-NEXT:    .cfi_offset ra, -4
361; RV32-NEXT:    .cfi_offset s0, -8
362; RV32-NEXT:    addi s0, sp, 192
363; RV32-NEXT:    .cfi_def_cfa s0, 0
364; RV32-NEXT:    andi sp, sp, -64
365; RV32-NEXT:    mv a0, sp
366; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
367; RV32-NEXT:    vse32.v v8, (a0)
368; RV32-NEXT:    flw fa5, 60(sp)
369; RV32-NEXT:    vfmv.f.s fa4, v8
370; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
371; RV32-NEXT:    vslidedown.vi v10, v8, 3
372; RV32-NEXT:    vslidedown.vi v11, v8, 2
373; RV32-NEXT:    fcvt.w.s a0, fa5
374; RV32-NEXT:    sw a0, 124(sp)
375; RV32-NEXT:    flw fa5, 56(sp)
376; RV32-NEXT:    fcvt.w.s a0, fa4
377; RV32-NEXT:    vfmv.f.s fa4, v10
378; RV32-NEXT:    vslidedown.vi v10, v8, 1
379; RV32-NEXT:    fcvt.w.s a1, fa5
380; RV32-NEXT:    sw a1, 120(sp)
381; RV32-NEXT:    flw fa5, 52(sp)
382; RV32-NEXT:    fcvt.w.s a1, fa4
383; RV32-NEXT:    vfmv.f.s fa4, v11
384; RV32-NEXT:    fcvt.w.s a2, fa4
385; RV32-NEXT:    fcvt.w.s a3, fa5
386; RV32-NEXT:    sw a3, 116(sp)
387; RV32-NEXT:    flw fa5, 48(sp)
388; RV32-NEXT:    vfmv.f.s fa4, v10
389; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
390; RV32-NEXT:    vslidedown.vi v10, v8, 7
391; RV32-NEXT:    fcvt.w.s a3, fa4
392; RV32-NEXT:    fcvt.w.s a4, fa5
393; RV32-NEXT:    sw a4, 112(sp)
394; RV32-NEXT:    flw fa5, 44(sp)
395; RV32-NEXT:    vfmv.f.s fa4, v10
396; RV32-NEXT:    vslidedown.vi v10, v8, 6
397; RV32-NEXT:    fcvt.w.s a4, fa4
398; RV32-NEXT:    fcvt.w.s a5, fa5
399; RV32-NEXT:    sw a5, 108(sp)
400; RV32-NEXT:    flw fa5, 40(sp)
401; RV32-NEXT:    vfmv.f.s fa4, v10
402; RV32-NEXT:    vslidedown.vi v10, v8, 5
403; RV32-NEXT:    fcvt.w.s a5, fa4
404; RV32-NEXT:    fcvt.w.s a6, fa5
405; RV32-NEXT:    sw a6, 104(sp)
406; RV32-NEXT:    flw fa5, 36(sp)
407; RV32-NEXT:    vfmv.f.s fa4, v10
408; RV32-NEXT:    fcvt.w.s a6, fa4
409; RV32-NEXT:    vslidedown.vi v8, v8, 4
410; RV32-NEXT:    fcvt.w.s a7, fa5
411; RV32-NEXT:    vfmv.f.s fa5, v8
412; RV32-NEXT:    sw a7, 100(sp)
413; RV32-NEXT:    fcvt.w.s a7, fa5
414; RV32-NEXT:    flw fa5, 32(sp)
415; RV32-NEXT:    sw a0, 64(sp)
416; RV32-NEXT:    sw a3, 68(sp)
417; RV32-NEXT:    sw a2, 72(sp)
418; RV32-NEXT:    sw a1, 76(sp)
419; RV32-NEXT:    sw a7, 80(sp)
420; RV32-NEXT:    sw a6, 84(sp)
421; RV32-NEXT:    sw a5, 88(sp)
422; RV32-NEXT:    sw a4, 92(sp)
423; RV32-NEXT:    fcvt.w.s a0, fa5
424; RV32-NEXT:    sw a0, 96(sp)
425; RV32-NEXT:    addi a0, sp, 64
426; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
427; RV32-NEXT:    vle32.v v8, (a0)
428; RV32-NEXT:    addi sp, s0, -192
429; RV32-NEXT:    .cfi_def_cfa sp, 192
430; RV32-NEXT:    lw ra, 188(sp) # 4-byte Folded Reload
431; RV32-NEXT:    lw s0, 184(sp) # 4-byte Folded Reload
432; RV32-NEXT:    .cfi_restore ra
433; RV32-NEXT:    .cfi_restore s0
434; RV32-NEXT:    addi sp, sp, 192
435; RV32-NEXT:    .cfi_def_cfa_offset 0
436; RV32-NEXT:    ret
437;
438; RV64-i32-LABEL: lrint_v16f32:
439; RV64-i32:       # %bb.0:
440; RV64-i32-NEXT:    addi sp, sp, -192
441; RV64-i32-NEXT:    .cfi_def_cfa_offset 192
442; RV64-i32-NEXT:    sd ra, 184(sp) # 8-byte Folded Spill
443; RV64-i32-NEXT:    sd s0, 176(sp) # 8-byte Folded Spill
444; RV64-i32-NEXT:    .cfi_offset ra, -8
445; RV64-i32-NEXT:    .cfi_offset s0, -16
446; RV64-i32-NEXT:    addi s0, sp, 192
447; RV64-i32-NEXT:    .cfi_def_cfa s0, 0
448; RV64-i32-NEXT:    andi sp, sp, -64
449; RV64-i32-NEXT:    mv a0, sp
450; RV64-i32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
451; RV64-i32-NEXT:    vse32.v v8, (a0)
452; RV64-i32-NEXT:    flw fa5, 60(sp)
453; RV64-i32-NEXT:    vfmv.f.s fa4, v8
454; RV64-i32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
455; RV64-i32-NEXT:    vslidedown.vi v10, v8, 3
456; RV64-i32-NEXT:    vslidedown.vi v11, v8, 2
457; RV64-i32-NEXT:    fcvt.l.s a0, fa5
458; RV64-i32-NEXT:    sw a0, 124(sp)
459; RV64-i32-NEXT:    flw fa5, 56(sp)
460; RV64-i32-NEXT:    fcvt.l.s a0, fa4
461; RV64-i32-NEXT:    vfmv.f.s fa4, v10
462; RV64-i32-NEXT:    vslidedown.vi v10, v8, 1
463; RV64-i32-NEXT:    fcvt.l.s a1, fa5
464; RV64-i32-NEXT:    sw a1, 120(sp)
465; RV64-i32-NEXT:    flw fa5, 52(sp)
466; RV64-i32-NEXT:    fcvt.l.s a1, fa4
467; RV64-i32-NEXT:    vfmv.f.s fa4, v11
468; RV64-i32-NEXT:    fcvt.l.s a2, fa4
469; RV64-i32-NEXT:    fcvt.l.s a3, fa5
470; RV64-i32-NEXT:    sw a3, 116(sp)
471; RV64-i32-NEXT:    flw fa5, 48(sp)
472; RV64-i32-NEXT:    vfmv.f.s fa4, v10
473; RV64-i32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
474; RV64-i32-NEXT:    vslidedown.vi v10, v8, 7
475; RV64-i32-NEXT:    fcvt.l.s a3, fa4
476; RV64-i32-NEXT:    fcvt.l.s a4, fa5
477; RV64-i32-NEXT:    sw a4, 112(sp)
478; RV64-i32-NEXT:    flw fa5, 44(sp)
479; RV64-i32-NEXT:    vfmv.f.s fa4, v10
480; RV64-i32-NEXT:    vslidedown.vi v10, v8, 6
481; RV64-i32-NEXT:    fcvt.l.s a4, fa4
482; RV64-i32-NEXT:    fcvt.l.s a5, fa5
483; RV64-i32-NEXT:    sw a5, 108(sp)
484; RV64-i32-NEXT:    flw fa5, 40(sp)
485; RV64-i32-NEXT:    vfmv.f.s fa4, v10
486; RV64-i32-NEXT:    vslidedown.vi v10, v8, 5
487; RV64-i32-NEXT:    fcvt.l.s a5, fa4
488; RV64-i32-NEXT:    fcvt.l.s a6, fa5
489; RV64-i32-NEXT:    sw a6, 104(sp)
490; RV64-i32-NEXT:    flw fa5, 36(sp)
491; RV64-i32-NEXT:    vfmv.f.s fa4, v10
492; RV64-i32-NEXT:    fcvt.l.s a6, fa4
493; RV64-i32-NEXT:    vslidedown.vi v8, v8, 4
494; RV64-i32-NEXT:    fcvt.l.s a7, fa5
495; RV64-i32-NEXT:    vfmv.f.s fa5, v8
496; RV64-i32-NEXT:    sw a7, 100(sp)
497; RV64-i32-NEXT:    fcvt.l.s a7, fa5
498; RV64-i32-NEXT:    flw fa5, 32(sp)
499; RV64-i32-NEXT:    sw a0, 64(sp)
500; RV64-i32-NEXT:    sw a3, 68(sp)
501; RV64-i32-NEXT:    sw a2, 72(sp)
502; RV64-i32-NEXT:    sw a1, 76(sp)
503; RV64-i32-NEXT:    sw a7, 80(sp)
504; RV64-i32-NEXT:    sw a6, 84(sp)
505; RV64-i32-NEXT:    sw a5, 88(sp)
506; RV64-i32-NEXT:    sw a4, 92(sp)
507; RV64-i32-NEXT:    fcvt.l.s a0, fa5
508; RV64-i32-NEXT:    sw a0, 96(sp)
509; RV64-i32-NEXT:    addi a0, sp, 64
510; RV64-i32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
511; RV64-i32-NEXT:    vle32.v v8, (a0)
512; RV64-i32-NEXT:    addi sp, s0, -192
513; RV64-i32-NEXT:    .cfi_def_cfa sp, 192
514; RV64-i32-NEXT:    ld ra, 184(sp) # 8-byte Folded Reload
515; RV64-i32-NEXT:    ld s0, 176(sp) # 8-byte Folded Reload
516; RV64-i32-NEXT:    .cfi_restore ra
517; RV64-i32-NEXT:    .cfi_restore s0
518; RV64-i32-NEXT:    addi sp, sp, 192
519; RV64-i32-NEXT:    .cfi_def_cfa_offset 0
520; RV64-i32-NEXT:    ret
521;
522; RV64-i64-LABEL: lrint_v16f32:
523; RV64-i64:       # %bb.0:
524; RV64-i64-NEXT:    addi sp, sp, -384
525; RV64-i64-NEXT:    .cfi_def_cfa_offset 384
526; RV64-i64-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
527; RV64-i64-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
528; RV64-i64-NEXT:    .cfi_offset ra, -8
529; RV64-i64-NEXT:    .cfi_offset s0, -16
530; RV64-i64-NEXT:    addi s0, sp, 384
531; RV64-i64-NEXT:    .cfi_def_cfa s0, 0
532; RV64-i64-NEXT:    andi sp, sp, -128
533; RV64-i64-NEXT:    addi a0, sp, 64
534; RV64-i64-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
535; RV64-i64-NEXT:    vse32.v v8, (a0)
536; RV64-i64-NEXT:    flw fa5, 124(sp)
537; RV64-i64-NEXT:    vfmv.f.s fa4, v8
538; RV64-i64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
539; RV64-i64-NEXT:    vslidedown.vi v10, v8, 3
540; RV64-i64-NEXT:    vslidedown.vi v11, v8, 2
541; RV64-i64-NEXT:    fcvt.l.s a0, fa5
542; RV64-i64-NEXT:    sd a0, 248(sp)
543; RV64-i64-NEXT:    flw fa5, 120(sp)
544; RV64-i64-NEXT:    vslidedown.vi v12, v8, 1
545; RV64-i64-NEXT:    fcvt.l.s a0, fa4
546; RV64-i64-NEXT:    vfmv.f.s fa4, v10
547; RV64-i64-NEXT:    fcvt.l.s a1, fa5
548; RV64-i64-NEXT:    sd a1, 240(sp)
549; RV64-i64-NEXT:    flw fa5, 116(sp)
550; RV64-i64-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
551; RV64-i64-NEXT:    vslidedown.vi v14, v8, 7
552; RV64-i64-NEXT:    fcvt.l.s a1, fa4
553; RV64-i64-NEXT:    vfmv.f.s fa4, v11
554; RV64-i64-NEXT:    fcvt.l.s a2, fa5
555; RV64-i64-NEXT:    sd a2, 232(sp)
556; RV64-i64-NEXT:    flw fa5, 112(sp)
557; RV64-i64-NEXT:    fcvt.l.s a2, fa4
558; RV64-i64-NEXT:    vfmv.f.s fa4, v12
559; RV64-i64-NEXT:    vslidedown.vi v10, v8, 6
560; RV64-i64-NEXT:    fcvt.l.s a3, fa5
561; RV64-i64-NEXT:    sd a3, 224(sp)
562; RV64-i64-NEXT:    flw fa5, 108(sp)
563; RV64-i64-NEXT:    fcvt.l.s a3, fa4
564; RV64-i64-NEXT:    vfmv.f.s fa4, v14
565; RV64-i64-NEXT:    vslidedown.vi v12, v8, 5
566; RV64-i64-NEXT:    fcvt.l.s a4, fa5
567; RV64-i64-NEXT:    sd a4, 216(sp)
568; RV64-i64-NEXT:    flw fa5, 104(sp)
569; RV64-i64-NEXT:    fcvt.l.s a4, fa4
570; RV64-i64-NEXT:    vfmv.f.s fa4, v10
571; RV64-i64-NEXT:    fcvt.l.s a5, fa4
572; RV64-i64-NEXT:    fcvt.l.s a6, fa5
573; RV64-i64-NEXT:    sd a6, 208(sp)
574; RV64-i64-NEXT:    flw fa5, 100(sp)
575; RV64-i64-NEXT:    vfmv.f.s fa4, v12
576; RV64-i64-NEXT:    fcvt.l.s a6, fa4
577; RV64-i64-NEXT:    vslidedown.vi v8, v8, 4
578; RV64-i64-NEXT:    fcvt.l.s a7, fa5
579; RV64-i64-NEXT:    vfmv.f.s fa5, v8
580; RV64-i64-NEXT:    sd a7, 200(sp)
581; RV64-i64-NEXT:    fcvt.l.s a7, fa5
582; RV64-i64-NEXT:    flw fa5, 96(sp)
583; RV64-i64-NEXT:    sd a0, 128(sp)
584; RV64-i64-NEXT:    sd a3, 136(sp)
585; RV64-i64-NEXT:    sd a2, 144(sp)
586; RV64-i64-NEXT:    sd a1, 152(sp)
587; RV64-i64-NEXT:    sd a7, 160(sp)
588; RV64-i64-NEXT:    sd a6, 168(sp)
589; RV64-i64-NEXT:    sd a5, 176(sp)
590; RV64-i64-NEXT:    sd a4, 184(sp)
591; RV64-i64-NEXT:    fcvt.l.s a0, fa5
592; RV64-i64-NEXT:    sd a0, 192(sp)
593; RV64-i64-NEXT:    addi a0, sp, 128
594; RV64-i64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
595; RV64-i64-NEXT:    vle64.v v8, (a0)
596; RV64-i64-NEXT:    addi sp, s0, -384
597; RV64-i64-NEXT:    .cfi_def_cfa sp, 384
598; RV64-i64-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
599; RV64-i64-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
600; RV64-i64-NEXT:    .cfi_restore ra
601; RV64-i64-NEXT:    .cfi_restore s0
602; RV64-i64-NEXT:    addi sp, sp, 384
603; RV64-i64-NEXT:    .cfi_def_cfa_offset 0
604; RV64-i64-NEXT:    ret
605  %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x)
606  ret <16 x iXLen> %a
607}
608declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float>)
609
610define <1 x iXLen> @lrint_v1f64(<1 x double> %x) {
611; RV32-LABEL: lrint_v1f64:
612; RV32:       # %bb.0:
613; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
614; RV32-NEXT:    vfmv.f.s fa5, v8
615; RV32-NEXT:    fcvt.w.d a0, fa5
616; RV32-NEXT:    vmv.s.x v8, a0
617; RV32-NEXT:    ret
618;
619; RV64-i32-LABEL: lrint_v1f64:
620; RV64-i32:       # %bb.0:
621; RV64-i32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
622; RV64-i32-NEXT:    vfmv.f.s fa5, v8
623; RV64-i32-NEXT:    fcvt.l.d a0, fa5
624; RV64-i32-NEXT:    vmv.s.x v8, a0
625; RV64-i32-NEXT:    ret
626;
627; RV64-i64-LABEL: lrint_v1f64:
628; RV64-i64:       # %bb.0:
629; RV64-i64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
630; RV64-i64-NEXT:    vfmv.f.s fa5, v8
631; RV64-i64-NEXT:    fcvt.l.d a0, fa5
632; RV64-i64-NEXT:    vmv.s.x v8, a0
633; RV64-i64-NEXT:    ret
634  %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double> %x)
635  ret <1 x iXLen> %a
636}
637declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f64(<1 x double>)
638
639define <2 x iXLen> @lrint_v2f64(<2 x double> %x) {
640; RV32-LABEL: lrint_v2f64:
641; RV32:       # %bb.0:
642; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
643; RV32-NEXT:    vslidedown.vi v9, v8, 1
644; RV32-NEXT:    vfmv.f.s fa5, v8
645; RV32-NEXT:    fcvt.w.d a0, fa5
646; RV32-NEXT:    vfmv.f.s fa5, v9
647; RV32-NEXT:    fcvt.w.d a1, fa5
648; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
649; RV32-NEXT:    vmv.v.x v8, a0
650; RV32-NEXT:    vslide1down.vx v8, v8, a1
651; RV32-NEXT:    ret
652;
653; RV64-i32-LABEL: lrint_v2f64:
654; RV64-i32:       # %bb.0:
655; RV64-i32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
656; RV64-i32-NEXT:    vslidedown.vi v9, v8, 1
657; RV64-i32-NEXT:    vfmv.f.s fa5, v8
658; RV64-i32-NEXT:    fcvt.l.d a0, fa5
659; RV64-i32-NEXT:    vfmv.f.s fa5, v9
660; RV64-i32-NEXT:    fcvt.l.d a1, fa5
661; RV64-i32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
662; RV64-i32-NEXT:    vmv.v.x v8, a0
663; RV64-i32-NEXT:    vslide1down.vx v8, v8, a1
664; RV64-i32-NEXT:    ret
665;
666; RV64-i64-LABEL: lrint_v2f64:
667; RV64-i64:       # %bb.0:
668; RV64-i64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
669; RV64-i64-NEXT:    vslidedown.vi v9, v8, 1
670; RV64-i64-NEXT:    vfmv.f.s fa5, v8
671; RV64-i64-NEXT:    fcvt.l.d a0, fa5
672; RV64-i64-NEXT:    vfmv.f.s fa5, v9
673; RV64-i64-NEXT:    fcvt.l.d a1, fa5
674; RV64-i64-NEXT:    vmv.v.x v8, a0
675; RV64-i64-NEXT:    vslide1down.vx v8, v8, a1
676; RV64-i64-NEXT:    ret
677  %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double> %x)
678  ret <2 x iXLen> %a
679}
680declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f64(<2 x double>)
681
682define <4 x iXLen> @lrint_v4f64(<4 x double> %x) {
683; RV32-LABEL: lrint_v4f64:
684; RV32:       # %bb.0:
685; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
686; RV32-NEXT:    vslidedown.vi v10, v8, 1
687; RV32-NEXT:    vfmv.f.s fa5, v8
688; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
689; RV32-NEXT:    vslidedown.vi v12, v8, 2
690; RV32-NEXT:    vslidedown.vi v8, v8, 3
691; RV32-NEXT:    fcvt.w.d a0, fa5
692; RV32-NEXT:    vfmv.f.s fa5, v10
693; RV32-NEXT:    fcvt.w.d a1, fa5
694; RV32-NEXT:    vfmv.f.s fa5, v12
695; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
696; RV32-NEXT:    vmv.v.x v9, a0
697; RV32-NEXT:    fcvt.w.d a0, fa5
698; RV32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
699; RV32-NEXT:    vfmv.f.s fa5, v8
700; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
701; RV32-NEXT:    vslide1down.vx v8, v9, a1
702; RV32-NEXT:    vslide1down.vx v8, v8, a0
703; RV32-NEXT:    fcvt.w.d a0, fa5
704; RV32-NEXT:    vslide1down.vx v8, v8, a0
705; RV32-NEXT:    ret
706;
707; RV64-i32-LABEL: lrint_v4f64:
708; RV64-i32:       # %bb.0:
709; RV64-i32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
710; RV64-i32-NEXT:    vslidedown.vi v10, v8, 1
711; RV64-i32-NEXT:    vfmv.f.s fa5, v8
712; RV64-i32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
713; RV64-i32-NEXT:    vslidedown.vi v12, v8, 2
714; RV64-i32-NEXT:    vslidedown.vi v8, v8, 3
715; RV64-i32-NEXT:    fcvt.l.d a0, fa5
716; RV64-i32-NEXT:    vfmv.f.s fa5, v10
717; RV64-i32-NEXT:    fcvt.l.d a1, fa5
718; RV64-i32-NEXT:    vfmv.f.s fa5, v12
719; RV64-i32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
720; RV64-i32-NEXT:    vmv.v.x v9, a0
721; RV64-i32-NEXT:    fcvt.l.d a0, fa5
722; RV64-i32-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
723; RV64-i32-NEXT:    vfmv.f.s fa5, v8
724; RV64-i32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
725; RV64-i32-NEXT:    vslide1down.vx v8, v9, a1
726; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
727; RV64-i32-NEXT:    fcvt.l.d a0, fa5
728; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
729; RV64-i32-NEXT:    ret
730;
731; RV64-i64-LABEL: lrint_v4f64:
732; RV64-i64:       # %bb.0:
733; RV64-i64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
734; RV64-i64-NEXT:    vslidedown.vi v10, v8, 1
735; RV64-i64-NEXT:    vfmv.f.s fa5, v8
736; RV64-i64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
737; RV64-i64-NEXT:    vslidedown.vi v12, v8, 2
738; RV64-i64-NEXT:    vslidedown.vi v8, v8, 3
739; RV64-i64-NEXT:    fcvt.l.d a0, fa5
740; RV64-i64-NEXT:    vfmv.f.s fa5, v10
741; RV64-i64-NEXT:    fcvt.l.d a1, fa5
742; RV64-i64-NEXT:    vfmv.f.s fa5, v12
743; RV64-i64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
744; RV64-i64-NEXT:    vmv.v.x v10, a0
745; RV64-i64-NEXT:    fcvt.l.d a0, fa5
746; RV64-i64-NEXT:    vfmv.f.s fa5, v8
747; RV64-i64-NEXT:    vslide1down.vx v8, v10, a1
748; RV64-i64-NEXT:    vslide1down.vx v8, v8, a0
749; RV64-i64-NEXT:    fcvt.l.d a0, fa5
750; RV64-i64-NEXT:    vslide1down.vx v8, v8, a0
751; RV64-i64-NEXT:    ret
752  %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double> %x)
753  ret <4 x iXLen> %a
754}
755declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f64(<4 x double>)
756
757define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {
758; RV32-LABEL: lrint_v8f64:
759; RV32:       # %bb.0:
760; RV32-NEXT:    addi sp, sp, -128
761; RV32-NEXT:    .cfi_def_cfa_offset 128
762; RV32-NEXT:    sw ra, 124(sp) # 4-byte Folded Spill
763; RV32-NEXT:    sw s0, 120(sp) # 4-byte Folded Spill
764; RV32-NEXT:    .cfi_offset ra, -4
765; RV32-NEXT:    .cfi_offset s0, -8
766; RV32-NEXT:    addi s0, sp, 128
767; RV32-NEXT:    .cfi_def_cfa s0, 0
768; RV32-NEXT:    andi sp, sp, -64
769; RV32-NEXT:    mv a0, sp
770; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
771; RV32-NEXT:    vslidedown.vi v12, v8, 1
772; RV32-NEXT:    vfmv.f.s fa5, v8
773; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
774; RV32-NEXT:    vslidedown.vi v14, v8, 2
775; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
776; RV32-NEXT:    vse64.v v8, (a0)
777; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
778; RV32-NEXT:    vslidedown.vi v8, v8, 3
779; RV32-NEXT:    vfmv.f.s fa4, v12
780; RV32-NEXT:    fcvt.w.d a0, fa5
781; RV32-NEXT:    vfmv.f.s fa5, v14
782; RV32-NEXT:    vfmv.f.s fa3, v8
783; RV32-NEXT:    fcvt.w.d a1, fa4
784; RV32-NEXT:    fcvt.w.d a2, fa5
785; RV32-NEXT:    fcvt.w.d a3, fa3
786; RV32-NEXT:    fld fa5, 32(sp)
787; RV32-NEXT:    fld fa4, 40(sp)
788; RV32-NEXT:    fld fa3, 48(sp)
789; RV32-NEXT:    fld fa2, 56(sp)
790; RV32-NEXT:    fcvt.w.d a4, fa5
791; RV32-NEXT:    fcvt.w.d a5, fa4
792; RV32-NEXT:    fcvt.w.d a6, fa3
793; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
794; RV32-NEXT:    vmv.v.x v8, a0
795; RV32-NEXT:    vslide1down.vx v8, v8, a1
796; RV32-NEXT:    vslide1down.vx v8, v8, a2
797; RV32-NEXT:    vslide1down.vx v8, v8, a3
798; RV32-NEXT:    vslide1down.vx v8, v8, a4
799; RV32-NEXT:    vslide1down.vx v8, v8, a5
800; RV32-NEXT:    vslide1down.vx v8, v8, a6
801; RV32-NEXT:    fcvt.w.d a0, fa2
802; RV32-NEXT:    vslide1down.vx v8, v8, a0
803; RV32-NEXT:    addi sp, s0, -128
804; RV32-NEXT:    .cfi_def_cfa sp, 128
805; RV32-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload
806; RV32-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
807; RV32-NEXT:    .cfi_restore ra
808; RV32-NEXT:    .cfi_restore s0
809; RV32-NEXT:    addi sp, sp, 128
810; RV32-NEXT:    .cfi_def_cfa_offset 0
811; RV32-NEXT:    ret
812;
813; RV64-i32-LABEL: lrint_v8f64:
814; RV64-i32:       # %bb.0:
815; RV64-i32-NEXT:    addi sp, sp, -128
816; RV64-i32-NEXT:    .cfi_def_cfa_offset 128
817; RV64-i32-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
818; RV64-i32-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
819; RV64-i32-NEXT:    .cfi_offset ra, -8
820; RV64-i32-NEXT:    .cfi_offset s0, -16
821; RV64-i32-NEXT:    addi s0, sp, 128
822; RV64-i32-NEXT:    .cfi_def_cfa s0, 0
823; RV64-i32-NEXT:    andi sp, sp, -64
824; RV64-i32-NEXT:    mv a0, sp
825; RV64-i32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
826; RV64-i32-NEXT:    vslidedown.vi v12, v8, 1
827; RV64-i32-NEXT:    vfmv.f.s fa5, v8
828; RV64-i32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
829; RV64-i32-NEXT:    vslidedown.vi v14, v8, 2
830; RV64-i32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
831; RV64-i32-NEXT:    vse64.v v8, (a0)
832; RV64-i32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
833; RV64-i32-NEXT:    vslidedown.vi v8, v8, 3
834; RV64-i32-NEXT:    vfmv.f.s fa4, v12
835; RV64-i32-NEXT:    fcvt.l.d a0, fa5
836; RV64-i32-NEXT:    vfmv.f.s fa5, v14
837; RV64-i32-NEXT:    vfmv.f.s fa3, v8
838; RV64-i32-NEXT:    fcvt.l.d a1, fa4
839; RV64-i32-NEXT:    fcvt.l.d a2, fa5
840; RV64-i32-NEXT:    fcvt.l.d a3, fa3
841; RV64-i32-NEXT:    fld fa5, 32(sp)
842; RV64-i32-NEXT:    fld fa4, 40(sp)
843; RV64-i32-NEXT:    fld fa3, 48(sp)
844; RV64-i32-NEXT:    fld fa2, 56(sp)
845; RV64-i32-NEXT:    fcvt.l.d a4, fa5
846; RV64-i32-NEXT:    fcvt.l.d a5, fa4
847; RV64-i32-NEXT:    fcvt.l.d a6, fa3
848; RV64-i32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
849; RV64-i32-NEXT:    vmv.v.x v8, a0
850; RV64-i32-NEXT:    vslide1down.vx v8, v8, a1
851; RV64-i32-NEXT:    vslide1down.vx v8, v8, a2
852; RV64-i32-NEXT:    vslide1down.vx v8, v8, a3
853; RV64-i32-NEXT:    vslide1down.vx v8, v8, a4
854; RV64-i32-NEXT:    vslide1down.vx v8, v8, a5
855; RV64-i32-NEXT:    vslide1down.vx v8, v8, a6
856; RV64-i32-NEXT:    fcvt.l.d a0, fa2
857; RV64-i32-NEXT:    vslide1down.vx v8, v8, a0
858; RV64-i32-NEXT:    addi sp, s0, -128
859; RV64-i32-NEXT:    .cfi_def_cfa sp, 128
860; RV64-i32-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
861; RV64-i32-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
862; RV64-i32-NEXT:    .cfi_restore ra
863; RV64-i32-NEXT:    .cfi_restore s0
864; RV64-i32-NEXT:    addi sp, sp, 128
865; RV64-i32-NEXT:    .cfi_def_cfa_offset 0
866; RV64-i32-NEXT:    ret
867;
868; RV64-i64-LABEL: lrint_v8f64:
869; RV64-i64:       # %bb.0:
870; RV64-i64-NEXT:    addi sp, sp, -192
871; RV64-i64-NEXT:    .cfi_def_cfa_offset 192
872; RV64-i64-NEXT:    sd ra, 184(sp) # 8-byte Folded Spill
873; RV64-i64-NEXT:    sd s0, 176(sp) # 8-byte Folded Spill
874; RV64-i64-NEXT:    .cfi_offset ra, -8
875; RV64-i64-NEXT:    .cfi_offset s0, -16
876; RV64-i64-NEXT:    addi s0, sp, 192
877; RV64-i64-NEXT:    .cfi_def_cfa s0, 0
878; RV64-i64-NEXT:    andi sp, sp, -64
879; RV64-i64-NEXT:    mv a0, sp
880; RV64-i64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
881; RV64-i64-NEXT:    vse64.v v8, (a0)
882; RV64-i64-NEXT:    fld fa5, 56(sp)
883; RV64-i64-NEXT:    vfmv.f.s fa4, v8
884; RV64-i64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
885; RV64-i64-NEXT:    vslidedown.vi v10, v8, 1
886; RV64-i64-NEXT:    fcvt.l.d a0, fa4
887; RV64-i64-NEXT:    fcvt.l.d a1, fa5
888; RV64-i64-NEXT:    sd a1, 120(sp)
889; RV64-i64-NEXT:    fld fa5, 48(sp)
890; RV64-i64-NEXT:    vfmv.f.s fa4, v10
891; RV64-i64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
892; RV64-i64-NEXT:    vslidedown.vi v10, v8, 3
893; RV64-i64-NEXT:    fcvt.l.d a1, fa4
894; RV64-i64-NEXT:    fcvt.l.d a2, fa5
895; RV64-i64-NEXT:    sd a2, 112(sp)
896; RV64-i64-NEXT:    fld fa5, 40(sp)
897; RV64-i64-NEXT:    vfmv.f.s fa4, v10
898; RV64-i64-NEXT:    fcvt.l.d a2, fa4
899; RV64-i64-NEXT:    vslidedown.vi v8, v8, 2
900; RV64-i64-NEXT:    fcvt.l.d a3, fa5
901; RV64-i64-NEXT:    vfmv.f.s fa5, v8
902; RV64-i64-NEXT:    sd a3, 104(sp)
903; RV64-i64-NEXT:    fcvt.l.d a3, fa5
904; RV64-i64-NEXT:    fld fa5, 32(sp)
905; RV64-i64-NEXT:    sd a0, 64(sp)
906; RV64-i64-NEXT:    sd a1, 72(sp)
907; RV64-i64-NEXT:    sd a3, 80(sp)
908; RV64-i64-NEXT:    sd a2, 88(sp)
909; RV64-i64-NEXT:    fcvt.l.d a0, fa5
910; RV64-i64-NEXT:    sd a0, 96(sp)
911; RV64-i64-NEXT:    addi a0, sp, 64
912; RV64-i64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
913; RV64-i64-NEXT:    vle64.v v8, (a0)
914; RV64-i64-NEXT:    addi sp, s0, -192
915; RV64-i64-NEXT:    .cfi_def_cfa sp, 192
916; RV64-i64-NEXT:    ld ra, 184(sp) # 8-byte Folded Reload
917; RV64-i64-NEXT:    ld s0, 176(sp) # 8-byte Folded Reload
918; RV64-i64-NEXT:    .cfi_restore ra
919; RV64-i64-NEXT:    .cfi_restore s0
920; RV64-i64-NEXT:    addi sp, sp, 192
921; RV64-i64-NEXT:    .cfi_def_cfa_offset 0
922; RV64-i64-NEXT:    ret
923  %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double> %x)
924  ret <8 x iXLen> %a
925}
926declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
927