xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s
3; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s
4
5define <5 x i8> @load_v5i8(ptr %p) {
6; CHECK-LABEL: load_v5i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
9; CHECK-NEXT:    vle8.v v8, (a0)
10; CHECK-NEXT:    ret
11  %x = load <5 x i8>, ptr %p
12  ret <5 x i8> %x
13}
14
15define <5 x i8> @load_v5i8_align1(ptr %p) {
16; CHECK-LABEL: load_v5i8_align1:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetivli zero, 5, e8, mf2, ta, ma
19; CHECK-NEXT:    vle8.v v8, (a0)
20; CHECK-NEXT:    ret
21  %x = load <5 x i8>, ptr %p, align 1
22  ret <5 x i8> %x
23}
24
25define <6 x i8> @load_v6i8(ptr %p) {
26; CHECK-LABEL: load_v6i8:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetivli zero, 6, e8, mf2, ta, ma
29; CHECK-NEXT:    vle8.v v8, (a0)
30; CHECK-NEXT:    ret
31  %x = load <6 x i8>, ptr %p
32  ret <6 x i8> %x
33}
34
35define <12 x i8> @load_v12i8(ptr %p) {
36; CHECK-LABEL: load_v12i8:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetivli zero, 12, e8, m1, ta, ma
39; CHECK-NEXT:    vle8.v v8, (a0)
40; CHECK-NEXT:    ret
41  %x = load <12 x i8>, ptr %p
42  ret <12 x i8> %x
43}
44
45define <6 x i16> @load_v6i16(ptr %p) {
46; CHECK-LABEL: load_v6i16:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
49; CHECK-NEXT:    vle16.v v8, (a0)
50; CHECK-NEXT:    ret
51  %x = load <6 x i16>, ptr %p
52  ret <6 x i16> %x
53}
54
55define <6 x half> @load_v6f16(ptr %p) {
56; CHECK-LABEL: load_v6f16:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
59; CHECK-NEXT:    vle16.v v8, (a0)
60; CHECK-NEXT:    ret
61  %x = load <6 x half>, ptr %p
62  ret <6 x half> %x
63}
64
65define <6 x float> @load_v6f32(ptr %p) {
66; CHECK-LABEL: load_v6f32:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetivli zero, 6, e32, m2, ta, ma
69; CHECK-NEXT:    vle32.v v8, (a0)
70; CHECK-NEXT:    ret
71  %x = load <6 x float>, ptr %p
72  ret <6 x float> %x
73}
74
75define <6 x double> @load_v6f64(ptr %p) {
76; CHECK-LABEL: load_v6f64:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetivli zero, 6, e64, m4, ta, ma
79; CHECK-NEXT:    vle64.v v8, (a0)
80; CHECK-NEXT:    ret
81  %x = load <6 x double>, ptr %p
82  ret <6 x double> %x
83}
84
85define <6 x i1> @load_v6i1(ptr %p) {
86; RV32-LABEL: load_v6i1:
87; RV32:       # %bb.0:
88; RV32-NEXT:    lbu a0, 0(a0)
89; RV32-NEXT:    srli a1, a0, 5
90; RV32-NEXT:    slli a2, a0, 27
91; RV32-NEXT:    slli a3, a0, 28
92; RV32-NEXT:    slli a4, a0, 29
93; RV32-NEXT:    slli a5, a0, 30
94; RV32-NEXT:    andi a0, a0, 1
95; RV32-NEXT:    srli a2, a2, 31
96; RV32-NEXT:    srli a3, a3, 31
97; RV32-NEXT:    srli a4, a4, 31
98; RV32-NEXT:    srli a5, a5, 31
99; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
100; RV32-NEXT:    vmv.v.x v8, a0
101; RV32-NEXT:    vslide1down.vx v8, v8, a5
102; RV32-NEXT:    vslide1down.vx v8, v8, a4
103; RV32-NEXT:    vslide1down.vx v8, v8, a3
104; RV32-NEXT:    vslide1down.vx v8, v8, a2
105; RV32-NEXT:    vslide1down.vx v8, v8, a1
106; RV32-NEXT:    vslidedown.vi v8, v8, 2
107; RV32-NEXT:    vand.vi v8, v8, 1
108; RV32-NEXT:    vmsne.vi v0, v8, 0
109; RV32-NEXT:    ret
110;
111; RV64-LABEL: load_v6i1:
112; RV64:       # %bb.0:
113; RV64-NEXT:    lbu a0, 0(a0)
114; RV64-NEXT:    srli a1, a0, 5
115; RV64-NEXT:    slli a2, a0, 59
116; RV64-NEXT:    slli a3, a0, 60
117; RV64-NEXT:    slli a4, a0, 61
118; RV64-NEXT:    slli a5, a0, 62
119; RV64-NEXT:    andi a0, a0, 1
120; RV64-NEXT:    srli a2, a2, 63
121; RV64-NEXT:    srli a3, a3, 63
122; RV64-NEXT:    srli a4, a4, 63
123; RV64-NEXT:    srli a5, a5, 63
124; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
125; RV64-NEXT:    vmv.v.x v8, a0
126; RV64-NEXT:    vslide1down.vx v8, v8, a5
127; RV64-NEXT:    vslide1down.vx v8, v8, a4
128; RV64-NEXT:    vslide1down.vx v8, v8, a3
129; RV64-NEXT:    vslide1down.vx v8, v8, a2
130; RV64-NEXT:    vslide1down.vx v8, v8, a1
131; RV64-NEXT:    vslidedown.vi v8, v8, 2
132; RV64-NEXT:    vand.vi v8, v8, 1
133; RV64-NEXT:    vmsne.vi v0, v8, 0
134; RV64-NEXT:    ret
135  %x = load <6 x i1>, ptr %p
136  ret <6 x i1> %x
137}
138
139
140define <4 x i32> @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {
141; CHECK-LABEL: exact_vlen_i32_m1:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    vl1re32.v v8, (a0)
144; CHECK-NEXT:    ret
145  %v = load <4 x i32>, ptr %p
146  ret <4 x i32> %v
147}
148
149define <16 x i8> @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {
150; CHECK-LABEL: exact_vlen_i8_m1:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    vl1r.v v8, (a0)
153; CHECK-NEXT:    ret
154  %v = load <16 x i8>, ptr %p
155  ret <16 x i8> %v
156}
157
158define <32 x i8> @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {
159; CHECK-LABEL: exact_vlen_i8_m2:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vl2r.v v8, (a0)
162; CHECK-NEXT:    ret
163  %v = load <32 x i8>, ptr %p
164  ret <32 x i8> %v
165}
166
167define <128 x i8> @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {
168; CHECK-LABEL: exact_vlen_i8_m8:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vl8r.v v8, (a0)
171; CHECK-NEXT:    ret
172  %v = load <128 x i8>, ptr %p
173  ret <128 x i8> %v
174}
175
176define <16 x i64> @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
177; CHECK-LABEL: exact_vlen_i64_m8:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vl8re64.v v8, (a0)
180; CHECK-NEXT:    ret
181  %v = load <16 x i64>, ptr %p
182  ret <16 x i64> %v
183}
184
185define <6 x bfloat> @load_v6bf16(ptr %p) {
186; CHECK-LABEL: load_v6bf16:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetivli zero, 6, e16, m1, ta, ma
189; CHECK-NEXT:    vle16.v v8, (a0)
190; CHECK-NEXT:    ret
191  %x = load <6 x bfloat>, ptr %p
192  ret <6 x bfloat> %x
193}
194