xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
6
7define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
8; RV32-LABEL: llrint_v1i64_v1f32:
9; RV32:       # %bb.0:
10; RV32-NEXT:    addi sp, sp, -16
11; RV32-NEXT:    .cfi_def_cfa_offset 16
12; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
13; RV32-NEXT:    .cfi_offset ra, -4
14; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
15; RV32-NEXT:    vfmv.f.s fa0, v8
16; RV32-NEXT:    call llrintf
17; RV32-NEXT:    sw a0, 0(sp)
18; RV32-NEXT:    sw a1, 4(sp)
19; RV32-NEXT:    mv a0, sp
20; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
21; RV32-NEXT:    vlse64.v v8, (a0), zero
22; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
23; RV32-NEXT:    .cfi_restore ra
24; RV32-NEXT:    addi sp, sp, 16
25; RV32-NEXT:    .cfi_def_cfa_offset 0
26; RV32-NEXT:    ret
27;
28; RV64-LABEL: llrint_v1i64_v1f32:
29; RV64:       # %bb.0:
30; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
31; RV64-NEXT:    vfmv.f.s fa5, v8
32; RV64-NEXT:    fcvt.l.s a0, fa5
33; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
34; RV64-NEXT:    vmv.s.x v8, a0
35; RV64-NEXT:    ret
36  %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
37  ret <1 x i64> %a
38}
39declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)
40
41define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
42; RV32-LABEL: llrint_v2i64_v2f32:
43; RV32:       # %bb.0:
44; RV32-NEXT:    addi sp, sp, -32
45; RV32-NEXT:    .cfi_def_cfa_offset 32
46; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
47; RV32-NEXT:    .cfi_offset ra, -4
48; RV32-NEXT:    csrr a0, vlenb
49; RV32-NEXT:    slli a0, a0, 1
50; RV32-NEXT:    sub sp, sp, a0
51; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 2 * vlenb
52; RV32-NEXT:    addi a0, sp, 16
53; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
54; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
55; RV32-NEXT:    vfmv.f.s fa0, v8
56; RV32-NEXT:    call llrintf
57; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
58; RV32-NEXT:    vmv.v.x v8, a0
59; RV32-NEXT:    vslide1down.vx v8, v8, a1
60; RV32-NEXT:    csrr a0, vlenb
61; RV32-NEXT:    add a0, sp, a0
62; RV32-NEXT:    addi a0, a0, 16
63; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
64; RV32-NEXT:    addi a0, sp, 16
65; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
66; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
67; RV32-NEXT:    vslidedown.vi v8, v8, 1
68; RV32-NEXT:    vfmv.f.s fa0, v8
69; RV32-NEXT:    call llrintf
70; RV32-NEXT:    csrr a2, vlenb
71; RV32-NEXT:    add a2, sp, a2
72; RV32-NEXT:    addi a2, a2, 16
73; RV32-NEXT:    vl1r.v v8, (a2) # Unknown-size Folded Reload
74; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
75; RV32-NEXT:    vslide1down.vx v8, v8, a0
76; RV32-NEXT:    vslide1down.vx v8, v8, a1
77; RV32-NEXT:    csrr a0, vlenb
78; RV32-NEXT:    slli a0, a0, 1
79; RV32-NEXT:    add sp, sp, a0
80; RV32-NEXT:    .cfi_def_cfa sp, 32
81; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
82; RV32-NEXT:    .cfi_restore ra
83; RV32-NEXT:    addi sp, sp, 32
84; RV32-NEXT:    .cfi_def_cfa_offset 0
85; RV32-NEXT:    ret
86;
87; RV64-LABEL: llrint_v2i64_v2f32:
88; RV64:       # %bb.0:
89; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
90; RV64-NEXT:    vslidedown.vi v9, v8, 1
91; RV64-NEXT:    vfmv.f.s fa5, v8
92; RV64-NEXT:    fcvt.l.s a0, fa5
93; RV64-NEXT:    vfmv.f.s fa5, v9
94; RV64-NEXT:    fcvt.l.s a1, fa5
95; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
96; RV64-NEXT:    vmv.v.x v8, a0
97; RV64-NEXT:    vslide1down.vx v8, v8, a1
98; RV64-NEXT:    ret
99  %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)
100  ret <2 x i64> %a
101}
102declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)
103
104define <3 x i64> @llrint_v3i64_v3f32(<3 x float> %x) {
105; RV32-LABEL: llrint_v3i64_v3f32:
106; RV32:       # %bb.0:
107; RV32-NEXT:    addi sp, sp, -32
108; RV32-NEXT:    .cfi_def_cfa_offset 32
109; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
110; RV32-NEXT:    .cfi_offset ra, -4
111; RV32-NEXT:    csrr a0, vlenb
112; RV32-NEXT:    slli a1, a0, 1
113; RV32-NEXT:    add a0, a1, a0
114; RV32-NEXT:    sub sp, sp, a0
115; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x03, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 3 * vlenb
116; RV32-NEXT:    csrr a0, vlenb
117; RV32-NEXT:    slli a0, a0, 1
118; RV32-NEXT:    add a0, sp, a0
119; RV32-NEXT:    addi a0, a0, 16
120; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
121; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
122; RV32-NEXT:    vfmv.f.s fa0, v8
123; RV32-NEXT:    call llrintf
124; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
125; RV32-NEXT:    vmv.v.x v8, a0
126; RV32-NEXT:    vslide1down.vx v8, v8, a1
127; RV32-NEXT:    addi a0, sp, 16
128; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
129; RV32-NEXT:    csrr a0, vlenb
130; RV32-NEXT:    slli a0, a0, 1
131; RV32-NEXT:    add a0, sp, a0
132; RV32-NEXT:    addi a0, a0, 16
133; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
134; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
135; RV32-NEXT:    vslidedown.vi v8, v8, 1
136; RV32-NEXT:    vfmv.f.s fa0, v8
137; RV32-NEXT:    call llrintf
138; RV32-NEXT:    addi a2, sp, 16
139; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
140; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
141; RV32-NEXT:    vslide1down.vx v8, v8, a0
142; RV32-NEXT:    vslide1down.vx v8, v8, a1
143; RV32-NEXT:    addi a0, sp, 16
144; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
145; RV32-NEXT:    csrr a0, vlenb
146; RV32-NEXT:    slli a0, a0, 1
147; RV32-NEXT:    add a0, sp, a0
148; RV32-NEXT:    addi a0, a0, 16
149; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
150; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
151; RV32-NEXT:    vslidedown.vi v8, v8, 2
152; RV32-NEXT:    vfmv.f.s fa0, v8
153; RV32-NEXT:    call llrintf
154; RV32-NEXT:    addi a2, sp, 16
155; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
156; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
157; RV32-NEXT:    vslide1down.vx v8, v8, a0
158; RV32-NEXT:    vslide1down.vx v8, v8, a1
159; RV32-NEXT:    addi a0, sp, 16
160; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
161; RV32-NEXT:    csrr a0, vlenb
162; RV32-NEXT:    slli a0, a0, 1
163; RV32-NEXT:    add a0, sp, a0
164; RV32-NEXT:    addi a0, a0, 16
165; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
166; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
167; RV32-NEXT:    vslidedown.vi v8, v8, 3
168; RV32-NEXT:    vfmv.f.s fa0, v8
169; RV32-NEXT:    call llrintf
170; RV32-NEXT:    addi a2, sp, 16
171; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
172; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
173; RV32-NEXT:    vslide1down.vx v8, v8, a0
174; RV32-NEXT:    vslide1down.vx v8, v8, a1
175; RV32-NEXT:    csrr a0, vlenb
176; RV32-NEXT:    slli a1, a0, 1
177; RV32-NEXT:    add a0, a1, a0
178; RV32-NEXT:    add sp, sp, a0
179; RV32-NEXT:    .cfi_def_cfa sp, 32
180; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
181; RV32-NEXT:    .cfi_restore ra
182; RV32-NEXT:    addi sp, sp, 32
183; RV32-NEXT:    .cfi_def_cfa_offset 0
184; RV32-NEXT:    ret
185;
186; RV64-LABEL: llrint_v3i64_v3f32:
187; RV64:       # %bb.0:
188; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
189; RV64-NEXT:    vslidedown.vi v9, v8, 1
190; RV64-NEXT:    vfmv.f.s fa5, v8
191; RV64-NEXT:    vslidedown.vi v10, v8, 2
192; RV64-NEXT:    vslidedown.vi v8, v8, 3
193; RV64-NEXT:    fcvt.l.s a0, fa5
194; RV64-NEXT:    vfmv.f.s fa5, v9
195; RV64-NEXT:    fcvt.l.s a1, fa5
196; RV64-NEXT:    vfmv.f.s fa5, v10
197; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
198; RV64-NEXT:    vmv.v.x v10, a0
199; RV64-NEXT:    fcvt.l.s a0, fa5
200; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
201; RV64-NEXT:    vfmv.f.s fa5, v8
202; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
203; RV64-NEXT:    vslide1down.vx v8, v10, a1
204; RV64-NEXT:    vslide1down.vx v8, v8, a0
205; RV64-NEXT:    fcvt.l.s a0, fa5
206; RV64-NEXT:    vslide1down.vx v8, v8, a0
207; RV64-NEXT:    ret
208  %a = call <3 x i64> @llvm.llrint.v3i64.v3f32(<3 x float> %x)
209  ret <3 x i64> %a
210}
211declare <3 x i64> @llvm.llrint.v3i64.v3f32(<3 x float>)
212
213define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) {
214; RV32-LABEL: llrint_v4i64_v4f32:
215; RV32:       # %bb.0:
216; RV32-NEXT:    addi sp, sp, -32
217; RV32-NEXT:    .cfi_def_cfa_offset 32
218; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
219; RV32-NEXT:    .cfi_offset ra, -4
220; RV32-NEXT:    csrr a0, vlenb
221; RV32-NEXT:    slli a1, a0, 1
222; RV32-NEXT:    add a0, a1, a0
223; RV32-NEXT:    sub sp, sp, a0
224; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x03, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 3 * vlenb
225; RV32-NEXT:    csrr a0, vlenb
226; RV32-NEXT:    slli a0, a0, 1
227; RV32-NEXT:    add a0, sp, a0
228; RV32-NEXT:    addi a0, a0, 16
229; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
230; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
231; RV32-NEXT:    vfmv.f.s fa0, v8
232; RV32-NEXT:    call llrintf
233; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
234; RV32-NEXT:    vmv.v.x v8, a0
235; RV32-NEXT:    vslide1down.vx v8, v8, a1
236; RV32-NEXT:    addi a0, sp, 16
237; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
238; RV32-NEXT:    csrr a0, vlenb
239; RV32-NEXT:    slli a0, a0, 1
240; RV32-NEXT:    add a0, sp, a0
241; RV32-NEXT:    addi a0, a0, 16
242; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
243; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
244; RV32-NEXT:    vslidedown.vi v8, v8, 1
245; RV32-NEXT:    vfmv.f.s fa0, v8
246; RV32-NEXT:    call llrintf
247; RV32-NEXT:    addi a2, sp, 16
248; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
249; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
250; RV32-NEXT:    vslide1down.vx v8, v8, a0
251; RV32-NEXT:    vslide1down.vx v8, v8, a1
252; RV32-NEXT:    addi a0, sp, 16
253; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
254; RV32-NEXT:    csrr a0, vlenb
255; RV32-NEXT:    slli a0, a0, 1
256; RV32-NEXT:    add a0, sp, a0
257; RV32-NEXT:    addi a0, a0, 16
258; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
259; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
260; RV32-NEXT:    vslidedown.vi v8, v8, 2
261; RV32-NEXT:    vfmv.f.s fa0, v8
262; RV32-NEXT:    call llrintf
263; RV32-NEXT:    addi a2, sp, 16
264; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
265; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
266; RV32-NEXT:    vslide1down.vx v8, v8, a0
267; RV32-NEXT:    vslide1down.vx v8, v8, a1
268; RV32-NEXT:    addi a0, sp, 16
269; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
270; RV32-NEXT:    csrr a0, vlenb
271; RV32-NEXT:    slli a0, a0, 1
272; RV32-NEXT:    add a0, sp, a0
273; RV32-NEXT:    addi a0, a0, 16
274; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
275; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
276; RV32-NEXT:    vslidedown.vi v8, v8, 3
277; RV32-NEXT:    vfmv.f.s fa0, v8
278; RV32-NEXT:    call llrintf
279; RV32-NEXT:    addi a2, sp, 16
280; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
281; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
282; RV32-NEXT:    vslide1down.vx v8, v8, a0
283; RV32-NEXT:    vslide1down.vx v8, v8, a1
284; RV32-NEXT:    csrr a0, vlenb
285; RV32-NEXT:    slli a1, a0, 1
286; RV32-NEXT:    add a0, a1, a0
287; RV32-NEXT:    add sp, sp, a0
288; RV32-NEXT:    .cfi_def_cfa sp, 32
289; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
290; RV32-NEXT:    .cfi_restore ra
291; RV32-NEXT:    addi sp, sp, 32
292; RV32-NEXT:    .cfi_def_cfa_offset 0
293; RV32-NEXT:    ret
294;
295; RV64-LABEL: llrint_v4i64_v4f32:
296; RV64:       # %bb.0:
297; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
298; RV64-NEXT:    vslidedown.vi v9, v8, 1
299; RV64-NEXT:    vfmv.f.s fa5, v8
300; RV64-NEXT:    vslidedown.vi v10, v8, 2
301; RV64-NEXT:    vslidedown.vi v8, v8, 3
302; RV64-NEXT:    fcvt.l.s a0, fa5
303; RV64-NEXT:    vfmv.f.s fa5, v9
304; RV64-NEXT:    fcvt.l.s a1, fa5
305; RV64-NEXT:    vfmv.f.s fa5, v10
306; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
307; RV64-NEXT:    vmv.v.x v10, a0
308; RV64-NEXT:    fcvt.l.s a0, fa5
309; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
310; RV64-NEXT:    vfmv.f.s fa5, v8
311; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
312; RV64-NEXT:    vslide1down.vx v8, v10, a1
313; RV64-NEXT:    vslide1down.vx v8, v8, a0
314; RV64-NEXT:    fcvt.l.s a0, fa5
315; RV64-NEXT:    vslide1down.vx v8, v8, a0
316; RV64-NEXT:    ret
317  %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
318  ret <4 x i64> %a
319}
320declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)
321
322define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) {
323; RV32-LABEL: llrint_v8i64_v8f32:
324; RV32:       # %bb.0:
325; RV32-NEXT:    addi sp, sp, -208
326; RV32-NEXT:    .cfi_def_cfa_offset 208
327; RV32-NEXT:    sw ra, 204(sp) # 4-byte Folded Spill
328; RV32-NEXT:    sw s0, 200(sp) # 4-byte Folded Spill
329; RV32-NEXT:    .cfi_offset ra, -4
330; RV32-NEXT:    .cfi_offset s0, -8
331; RV32-NEXT:    addi s0, sp, 208
332; RV32-NEXT:    .cfi_def_cfa s0, 0
333; RV32-NEXT:    csrr a0, vlenb
334; RV32-NEXT:    slli a0, a0, 1
335; RV32-NEXT:    sub sp, sp, a0
336; RV32-NEXT:    andi sp, sp, -64
337; RV32-NEXT:    addi a0, sp, 192
338; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
339; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
340; RV32-NEXT:    vfmv.f.s fa0, v8
341; RV32-NEXT:    call llrintf
342; RV32-NEXT:    sw a0, 64(sp)
343; RV32-NEXT:    sw a1, 68(sp)
344; RV32-NEXT:    addi a0, sp, 192
345; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
346; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
347; RV32-NEXT:    vslidedown.vi v8, v8, 7
348; RV32-NEXT:    vfmv.f.s fa0, v8
349; RV32-NEXT:    call llrintf
350; RV32-NEXT:    sw a0, 120(sp)
351; RV32-NEXT:    sw a1, 124(sp)
352; RV32-NEXT:    addi a0, sp, 192
353; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
354; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
355; RV32-NEXT:    vslidedown.vi v8, v8, 6
356; RV32-NEXT:    vfmv.f.s fa0, v8
357; RV32-NEXT:    call llrintf
358; RV32-NEXT:    sw a0, 112(sp)
359; RV32-NEXT:    sw a1, 116(sp)
360; RV32-NEXT:    addi a0, sp, 192
361; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
362; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
363; RV32-NEXT:    vslidedown.vi v8, v8, 5
364; RV32-NEXT:    vfmv.f.s fa0, v8
365; RV32-NEXT:    call llrintf
366; RV32-NEXT:    sw a0, 104(sp)
367; RV32-NEXT:    sw a1, 108(sp)
368; RV32-NEXT:    addi a0, sp, 192
369; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
370; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
371; RV32-NEXT:    vslidedown.vi v8, v8, 4
372; RV32-NEXT:    vfmv.f.s fa0, v8
373; RV32-NEXT:    call llrintf
374; RV32-NEXT:    sw a0, 96(sp)
375; RV32-NEXT:    sw a1, 100(sp)
376; RV32-NEXT:    addi a0, sp, 192
377; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
378; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
379; RV32-NEXT:    vslidedown.vi v8, v8, 3
380; RV32-NEXT:    vfmv.f.s fa0, v8
381; RV32-NEXT:    call llrintf
382; RV32-NEXT:    sw a0, 88(sp)
383; RV32-NEXT:    sw a1, 92(sp)
384; RV32-NEXT:    addi a0, sp, 192
385; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
386; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
387; RV32-NEXT:    vslidedown.vi v8, v8, 2
388; RV32-NEXT:    vfmv.f.s fa0, v8
389; RV32-NEXT:    call llrintf
390; RV32-NEXT:    sw a0, 80(sp)
391; RV32-NEXT:    sw a1, 84(sp)
392; RV32-NEXT:    addi a0, sp, 192
393; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
394; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
395; RV32-NEXT:    vslidedown.vi v8, v8, 1
396; RV32-NEXT:    vfmv.f.s fa0, v8
397; RV32-NEXT:    call llrintf
398; RV32-NEXT:    sw a0, 72(sp)
399; RV32-NEXT:    sw a1, 76(sp)
400; RV32-NEXT:    addi a0, sp, 64
401; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
402; RV32-NEXT:    vle32.v v8, (a0)
403; RV32-NEXT:    addi sp, s0, -208
404; RV32-NEXT:    .cfi_def_cfa sp, 208
405; RV32-NEXT:    lw ra, 204(sp) # 4-byte Folded Reload
406; RV32-NEXT:    lw s0, 200(sp) # 4-byte Folded Reload
407; RV32-NEXT:    .cfi_restore ra
408; RV32-NEXT:    .cfi_restore s0
409; RV32-NEXT:    addi sp, sp, 208
410; RV32-NEXT:    .cfi_def_cfa_offset 0
411; RV32-NEXT:    ret
412;
413; RV64-LABEL: llrint_v8i64_v8f32:
414; RV64:       # %bb.0:
415; RV64-NEXT:    addi sp, sp, -128
416; RV64-NEXT:    .cfi_def_cfa_offset 128
417; RV64-NEXT:    sd ra, 120(sp) # 8-byte Folded Spill
418; RV64-NEXT:    sd s0, 112(sp) # 8-byte Folded Spill
419; RV64-NEXT:    .cfi_offset ra, -8
420; RV64-NEXT:    .cfi_offset s0, -16
421; RV64-NEXT:    addi s0, sp, 128
422; RV64-NEXT:    .cfi_def_cfa s0, 0
423; RV64-NEXT:    andi sp, sp, -64
424; RV64-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
425; RV64-NEXT:    vfmv.f.s fa5, v8
426; RV64-NEXT:    vslidedown.vi v10, v8, 7
427; RV64-NEXT:    fcvt.l.s a0, fa5
428; RV64-NEXT:    vfmv.f.s fa5, v10
429; RV64-NEXT:    vslidedown.vi v10, v8, 6
430; RV64-NEXT:    fcvt.l.s a1, fa5
431; RV64-NEXT:    vfmv.f.s fa5, v10
432; RV64-NEXT:    vslidedown.vi v10, v8, 5
433; RV64-NEXT:    fcvt.l.s a2, fa5
434; RV64-NEXT:    vfmv.f.s fa5, v10
435; RV64-NEXT:    vslidedown.vi v10, v8, 4
436; RV64-NEXT:    fcvt.l.s a3, fa5
437; RV64-NEXT:    vfmv.f.s fa5, v10
438; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
439; RV64-NEXT:    vslidedown.vi v9, v8, 3
440; RV64-NEXT:    vslidedown.vi v10, v8, 2
441; RV64-NEXT:    vslidedown.vi v8, v8, 1
442; RV64-NEXT:    fcvt.l.s a4, fa5
443; RV64-NEXT:    vfmv.f.s fa5, v9
444; RV64-NEXT:    fcvt.l.s a5, fa5
445; RV64-NEXT:    vfmv.f.s fa5, v10
446; RV64-NEXT:    fcvt.l.s a6, fa5
447; RV64-NEXT:    vfmv.f.s fa5, v8
448; RV64-NEXT:    sd a4, 32(sp)
449; RV64-NEXT:    sd a3, 40(sp)
450; RV64-NEXT:    sd a2, 48(sp)
451; RV64-NEXT:    sd a1, 56(sp)
452; RV64-NEXT:    fcvt.l.s a1, fa5
453; RV64-NEXT:    sd a0, 0(sp)
454; RV64-NEXT:    sd a1, 8(sp)
455; RV64-NEXT:    sd a6, 16(sp)
456; RV64-NEXT:    sd a5, 24(sp)
457; RV64-NEXT:    mv a0, sp
458; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
459; RV64-NEXT:    vle64.v v8, (a0)
460; RV64-NEXT:    addi sp, s0, -128
461; RV64-NEXT:    .cfi_def_cfa sp, 128
462; RV64-NEXT:    ld ra, 120(sp) # 8-byte Folded Reload
463; RV64-NEXT:    ld s0, 112(sp) # 8-byte Folded Reload
464; RV64-NEXT:    .cfi_restore ra
465; RV64-NEXT:    .cfi_restore s0
466; RV64-NEXT:    addi sp, sp, 128
467; RV64-NEXT:    .cfi_def_cfa_offset 0
468; RV64-NEXT:    ret
469  %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
470  ret <8 x i64> %a
471}
472declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)
473
474define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) {
475; RV32-LABEL: llrint_v16i64_v16f32:
476; RV32:       # %bb.0:
477; RV32-NEXT:    addi sp, sp, -400
478; RV32-NEXT:    .cfi_def_cfa_offset 400
479; RV32-NEXT:    sw ra, 396(sp) # 4-byte Folded Spill
480; RV32-NEXT:    sw s0, 392(sp) # 4-byte Folded Spill
481; RV32-NEXT:    .cfi_offset ra, -4
482; RV32-NEXT:    .cfi_offset s0, -8
483; RV32-NEXT:    addi s0, sp, 400
484; RV32-NEXT:    .cfi_def_cfa s0, 0
485; RV32-NEXT:    csrr a0, vlenb
486; RV32-NEXT:    slli a0, a0, 2
487; RV32-NEXT:    sub sp, sp, a0
488; RV32-NEXT:    andi sp, sp, -128
489; RV32-NEXT:    addi a0, sp, 384
490; RV32-NEXT:    vs4r.v v8, (a0) # Unknown-size Folded Spill
491; RV32-NEXT:    addi a0, sp, 64
492; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
493; RV32-NEXT:    vse32.v v8, (a0)
494; RV32-NEXT:    flw fa0, 124(sp)
495; RV32-NEXT:    call llrintf
496; RV32-NEXT:    sw a0, 248(sp)
497; RV32-NEXT:    sw a1, 252(sp)
498; RV32-NEXT:    flw fa0, 120(sp)
499; RV32-NEXT:    call llrintf
500; RV32-NEXT:    sw a0, 240(sp)
501; RV32-NEXT:    sw a1, 244(sp)
502; RV32-NEXT:    flw fa0, 116(sp)
503; RV32-NEXT:    call llrintf
504; RV32-NEXT:    sw a0, 232(sp)
505; RV32-NEXT:    sw a1, 236(sp)
506; RV32-NEXT:    flw fa0, 112(sp)
507; RV32-NEXT:    call llrintf
508; RV32-NEXT:    sw a0, 224(sp)
509; RV32-NEXT:    sw a1, 228(sp)
510; RV32-NEXT:    flw fa0, 108(sp)
511; RV32-NEXT:    call llrintf
512; RV32-NEXT:    sw a0, 216(sp)
513; RV32-NEXT:    sw a1, 220(sp)
514; RV32-NEXT:    flw fa0, 104(sp)
515; RV32-NEXT:    call llrintf
516; RV32-NEXT:    sw a0, 208(sp)
517; RV32-NEXT:    sw a1, 212(sp)
518; RV32-NEXT:    flw fa0, 100(sp)
519; RV32-NEXT:    call llrintf
520; RV32-NEXT:    sw a0, 200(sp)
521; RV32-NEXT:    sw a1, 204(sp)
522; RV32-NEXT:    flw fa0, 96(sp)
523; RV32-NEXT:    call llrintf
524; RV32-NEXT:    sw a0, 192(sp)
525; RV32-NEXT:    sw a1, 196(sp)
526; RV32-NEXT:    addi a0, sp, 384
527; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
528; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
529; RV32-NEXT:    vfmv.f.s fa0, v8
530; RV32-NEXT:    call llrintf
531; RV32-NEXT:    sw a0, 128(sp)
532; RV32-NEXT:    sw a1, 132(sp)
533; RV32-NEXT:    addi a0, sp, 384
534; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
535; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
536; RV32-NEXT:    vslidedown.vi v8, v8, 3
537; RV32-NEXT:    vfmv.f.s fa0, v8
538; RV32-NEXT:    call llrintf
539; RV32-NEXT:    sw a0, 152(sp)
540; RV32-NEXT:    sw a1, 156(sp)
541; RV32-NEXT:    addi a0, sp, 384
542; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
543; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
544; RV32-NEXT:    vslidedown.vi v8, v8, 2
545; RV32-NEXT:    vfmv.f.s fa0, v8
546; RV32-NEXT:    call llrintf
547; RV32-NEXT:    sw a0, 144(sp)
548; RV32-NEXT:    sw a1, 148(sp)
549; RV32-NEXT:    addi a0, sp, 384
550; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
551; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
552; RV32-NEXT:    vslidedown.vi v8, v8, 1
553; RV32-NEXT:    vfmv.f.s fa0, v8
554; RV32-NEXT:    call llrintf
555; RV32-NEXT:    sw a0, 136(sp)
556; RV32-NEXT:    sw a1, 140(sp)
557; RV32-NEXT:    addi a0, sp, 384
558; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
559; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
560; RV32-NEXT:    vslidedown.vi v8, v8, 7
561; RV32-NEXT:    vfmv.f.s fa0, v8
562; RV32-NEXT:    call llrintf
563; RV32-NEXT:    sw a0, 184(sp)
564; RV32-NEXT:    sw a1, 188(sp)
565; RV32-NEXT:    addi a0, sp, 384
566; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
567; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
568; RV32-NEXT:    vslidedown.vi v8, v8, 6
569; RV32-NEXT:    vfmv.f.s fa0, v8
570; RV32-NEXT:    call llrintf
571; RV32-NEXT:    sw a0, 176(sp)
572; RV32-NEXT:    sw a1, 180(sp)
573; RV32-NEXT:    addi a0, sp, 384
574; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
575; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
576; RV32-NEXT:    vslidedown.vi v8, v8, 5
577; RV32-NEXT:    vfmv.f.s fa0, v8
578; RV32-NEXT:    call llrintf
579; RV32-NEXT:    sw a0, 168(sp)
580; RV32-NEXT:    sw a1, 172(sp)
581; RV32-NEXT:    addi a0, sp, 384
582; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
583; RV32-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
584; RV32-NEXT:    vslidedown.vi v8, v8, 4
585; RV32-NEXT:    vfmv.f.s fa0, v8
586; RV32-NEXT:    call llrintf
587; RV32-NEXT:    sw a0, 160(sp)
588; RV32-NEXT:    sw a1, 164(sp)
589; RV32-NEXT:    li a0, 32
590; RV32-NEXT:    addi a1, sp, 128
591; RV32-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
592; RV32-NEXT:    vle32.v v8, (a1)
593; RV32-NEXT:    addi sp, s0, -400
594; RV32-NEXT:    .cfi_def_cfa sp, 400
595; RV32-NEXT:    lw ra, 396(sp) # 4-byte Folded Reload
596; RV32-NEXT:    lw s0, 392(sp) # 4-byte Folded Reload
597; RV32-NEXT:    .cfi_restore ra
598; RV32-NEXT:    .cfi_restore s0
599; RV32-NEXT:    addi sp, sp, 400
600; RV32-NEXT:    .cfi_def_cfa_offset 0
601; RV32-NEXT:    ret
602;
603; RV64-LABEL: llrint_v16i64_v16f32:
604; RV64:       # %bb.0:
605; RV64-NEXT:    addi sp, sp, -384
606; RV64-NEXT:    .cfi_def_cfa_offset 384
607; RV64-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
608; RV64-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
609; RV64-NEXT:    .cfi_offset ra, -8
610; RV64-NEXT:    .cfi_offset s0, -16
611; RV64-NEXT:    addi s0, sp, 384
612; RV64-NEXT:    .cfi_def_cfa s0, 0
613; RV64-NEXT:    andi sp, sp, -128
614; RV64-NEXT:    addi a0, sp, 64
615; RV64-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
616; RV64-NEXT:    vse32.v v8, (a0)
617; RV64-NEXT:    flw fa5, 124(sp)
618; RV64-NEXT:    vfmv.f.s fa4, v8
619; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
620; RV64-NEXT:    vslidedown.vi v10, v8, 3
621; RV64-NEXT:    vslidedown.vi v11, v8, 2
622; RV64-NEXT:    fcvt.l.s a0, fa5
623; RV64-NEXT:    sd a0, 248(sp)
624; RV64-NEXT:    flw fa5, 120(sp)
625; RV64-NEXT:    vslidedown.vi v12, v8, 1
626; RV64-NEXT:    fcvt.l.s a0, fa4
627; RV64-NEXT:    vfmv.f.s fa4, v10
628; RV64-NEXT:    fcvt.l.s a1, fa5
629; RV64-NEXT:    sd a1, 240(sp)
630; RV64-NEXT:    flw fa5, 116(sp)
631; RV64-NEXT:    vsetivli zero, 1, e32, m2, ta, ma
632; RV64-NEXT:    vslidedown.vi v14, v8, 7
633; RV64-NEXT:    fcvt.l.s a1, fa4
634; RV64-NEXT:    vfmv.f.s fa4, v11
635; RV64-NEXT:    fcvt.l.s a2, fa5
636; RV64-NEXT:    sd a2, 232(sp)
637; RV64-NEXT:    flw fa5, 112(sp)
638; RV64-NEXT:    fcvt.l.s a2, fa4
639; RV64-NEXT:    vfmv.f.s fa4, v12
640; RV64-NEXT:    vslidedown.vi v10, v8, 6
641; RV64-NEXT:    fcvt.l.s a3, fa5
642; RV64-NEXT:    sd a3, 224(sp)
643; RV64-NEXT:    flw fa5, 108(sp)
644; RV64-NEXT:    fcvt.l.s a3, fa4
645; RV64-NEXT:    vfmv.f.s fa4, v14
646; RV64-NEXT:    vslidedown.vi v12, v8, 5
647; RV64-NEXT:    fcvt.l.s a4, fa5
648; RV64-NEXT:    sd a4, 216(sp)
649; RV64-NEXT:    flw fa5, 104(sp)
650; RV64-NEXT:    fcvt.l.s a4, fa4
651; RV64-NEXT:    vfmv.f.s fa4, v10
652; RV64-NEXT:    fcvt.l.s a5, fa4
653; RV64-NEXT:    fcvt.l.s a6, fa5
654; RV64-NEXT:    sd a6, 208(sp)
655; RV64-NEXT:    flw fa5, 100(sp)
656; RV64-NEXT:    vfmv.f.s fa4, v12
657; RV64-NEXT:    fcvt.l.s a6, fa4
658; RV64-NEXT:    vslidedown.vi v8, v8, 4
659; RV64-NEXT:    fcvt.l.s a7, fa5
660; RV64-NEXT:    vfmv.f.s fa5, v8
661; RV64-NEXT:    sd a7, 200(sp)
662; RV64-NEXT:    fcvt.l.s a7, fa5
663; RV64-NEXT:    flw fa5, 96(sp)
664; RV64-NEXT:    sd a0, 128(sp)
665; RV64-NEXT:    sd a3, 136(sp)
666; RV64-NEXT:    sd a2, 144(sp)
667; RV64-NEXT:    sd a1, 152(sp)
668; RV64-NEXT:    sd a7, 160(sp)
669; RV64-NEXT:    sd a6, 168(sp)
670; RV64-NEXT:    sd a5, 176(sp)
671; RV64-NEXT:    sd a4, 184(sp)
672; RV64-NEXT:    fcvt.l.s a0, fa5
673; RV64-NEXT:    sd a0, 192(sp)
674; RV64-NEXT:    addi a0, sp, 128
675; RV64-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
676; RV64-NEXT:    vle64.v v8, (a0)
677; RV64-NEXT:    addi sp, s0, -384
678; RV64-NEXT:    .cfi_def_cfa sp, 384
679; RV64-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
680; RV64-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
681; RV64-NEXT:    .cfi_restore ra
682; RV64-NEXT:    .cfi_restore s0
683; RV64-NEXT:    addi sp, sp, 384
684; RV64-NEXT:    .cfi_def_cfa_offset 0
685; RV64-NEXT:    ret
686  %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
687  ret <16 x i64> %a
688}
689declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)
690
691define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) {
692; RV32-LABEL: llrint_v1i64_v1f64:
693; RV32:       # %bb.0:
694; RV32-NEXT:    addi sp, sp, -16
695; RV32-NEXT:    .cfi_def_cfa_offset 16
696; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
697; RV32-NEXT:    .cfi_offset ra, -4
698; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
699; RV32-NEXT:    vfmv.f.s fa0, v8
700; RV32-NEXT:    call llrint
701; RV32-NEXT:    sw a0, 0(sp)
702; RV32-NEXT:    sw a1, 4(sp)
703; RV32-NEXT:    mv a0, sp
704; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
705; RV32-NEXT:    vlse64.v v8, (a0), zero
706; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
707; RV32-NEXT:    .cfi_restore ra
708; RV32-NEXT:    addi sp, sp, 16
709; RV32-NEXT:    .cfi_def_cfa_offset 0
710; RV32-NEXT:    ret
711;
712; RV64-LABEL: llrint_v1i64_v1f64:
713; RV64:       # %bb.0:
714; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
715; RV64-NEXT:    vfmv.f.s fa5, v8
716; RV64-NEXT:    fcvt.l.d a0, fa5
717; RV64-NEXT:    vmv.s.x v8, a0
718; RV64-NEXT:    ret
719  %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)
720  ret <1 x i64> %a
721}
722declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)
723
724define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) {
725; RV32-LABEL: llrint_v2i64_v2f64:
726; RV32:       # %bb.0:
727; RV32-NEXT:    addi sp, sp, -32
728; RV32-NEXT:    .cfi_def_cfa_offset 32
729; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
730; RV32-NEXT:    .cfi_offset ra, -4
731; RV32-NEXT:    csrr a0, vlenb
732; RV32-NEXT:    slli a0, a0, 1
733; RV32-NEXT:    sub sp, sp, a0
734; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 2 * vlenb
735; RV32-NEXT:    addi a0, sp, 16
736; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
737; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
738; RV32-NEXT:    vfmv.f.s fa0, v8
739; RV32-NEXT:    call llrint
740; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
741; RV32-NEXT:    vmv.v.x v8, a0
742; RV32-NEXT:    vslide1down.vx v8, v8, a1
743; RV32-NEXT:    csrr a0, vlenb
744; RV32-NEXT:    add a0, sp, a0
745; RV32-NEXT:    addi a0, a0, 16
746; RV32-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
747; RV32-NEXT:    addi a0, sp, 16
748; RV32-NEXT:    vl1r.v v8, (a0) # Unknown-size Folded Reload
749; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
750; RV32-NEXT:    vslidedown.vi v8, v8, 1
751; RV32-NEXT:    vfmv.f.s fa0, v8
752; RV32-NEXT:    call llrint
753; RV32-NEXT:    csrr a2, vlenb
754; RV32-NEXT:    add a2, sp, a2
755; RV32-NEXT:    addi a2, a2, 16
756; RV32-NEXT:    vl1r.v v8, (a2) # Unknown-size Folded Reload
757; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
758; RV32-NEXT:    vslide1down.vx v8, v8, a0
759; RV32-NEXT:    vslide1down.vx v8, v8, a1
760; RV32-NEXT:    csrr a0, vlenb
761; RV32-NEXT:    slli a0, a0, 1
762; RV32-NEXT:    add sp, sp, a0
763; RV32-NEXT:    .cfi_def_cfa sp, 32
764; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
765; RV32-NEXT:    .cfi_restore ra
766; RV32-NEXT:    addi sp, sp, 32
767; RV32-NEXT:    .cfi_def_cfa_offset 0
768; RV32-NEXT:    ret
769;
770; RV64-LABEL: llrint_v2i64_v2f64:
771; RV64:       # %bb.0:
772; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
773; RV64-NEXT:    vslidedown.vi v9, v8, 1
774; RV64-NEXT:    vfmv.f.s fa5, v8
775; RV64-NEXT:    fcvt.l.d a0, fa5
776; RV64-NEXT:    vfmv.f.s fa5, v9
777; RV64-NEXT:    fcvt.l.d a1, fa5
778; RV64-NEXT:    vmv.v.x v8, a0
779; RV64-NEXT:    vslide1down.vx v8, v8, a1
780; RV64-NEXT:    ret
781  %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)
782  ret <2 x i64> %a
783}
784declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)
785
786define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) {
787; RV32-LABEL: llrint_v4i64_v4f64:
788; RV32:       # %bb.0:
789; RV32-NEXT:    addi sp, sp, -32
790; RV32-NEXT:    .cfi_def_cfa_offset 32
791; RV32-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
792; RV32-NEXT:    .cfi_offset ra, -4
793; RV32-NEXT:    csrr a0, vlenb
794; RV32-NEXT:    slli a0, a0, 2
795; RV32-NEXT:    sub sp, sp, a0
796; RV32-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 4 * vlenb
797; RV32-NEXT:    csrr a0, vlenb
798; RV32-NEXT:    slli a0, a0, 1
799; RV32-NEXT:    add a0, sp, a0
800; RV32-NEXT:    addi a0, a0, 16
801; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
802; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
803; RV32-NEXT:    vfmv.f.s fa0, v8
804; RV32-NEXT:    call llrint
805; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
806; RV32-NEXT:    vmv.v.x v8, a0
807; RV32-NEXT:    vslide1down.vx v8, v8, a1
808; RV32-NEXT:    addi a0, sp, 16
809; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
810; RV32-NEXT:    csrr a0, vlenb
811; RV32-NEXT:    slli a0, a0, 1
812; RV32-NEXT:    add a0, sp, a0
813; RV32-NEXT:    addi a0, a0, 16
814; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
815; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
816; RV32-NEXT:    vslidedown.vi v8, v8, 1
817; RV32-NEXT:    vfmv.f.s fa0, v8
818; RV32-NEXT:    call llrint
819; RV32-NEXT:    addi a2, sp, 16
820; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
821; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
822; RV32-NEXT:    vslide1down.vx v8, v8, a0
823; RV32-NEXT:    vslide1down.vx v8, v8, a1
824; RV32-NEXT:    addi a0, sp, 16
825; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
826; RV32-NEXT:    csrr a0, vlenb
827; RV32-NEXT:    slli a0, a0, 1
828; RV32-NEXT:    add a0, sp, a0
829; RV32-NEXT:    addi a0, a0, 16
830; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
831; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
832; RV32-NEXT:    vslidedown.vi v8, v8, 2
833; RV32-NEXT:    vfmv.f.s fa0, v8
834; RV32-NEXT:    call llrint
835; RV32-NEXT:    addi a2, sp, 16
836; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
837; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
838; RV32-NEXT:    vslide1down.vx v8, v8, a0
839; RV32-NEXT:    vslide1down.vx v8, v8, a1
840; RV32-NEXT:    addi a0, sp, 16
841; RV32-NEXT:    vs2r.v v8, (a0) # Unknown-size Folded Spill
842; RV32-NEXT:    csrr a0, vlenb
843; RV32-NEXT:    slli a0, a0, 1
844; RV32-NEXT:    add a0, sp, a0
845; RV32-NEXT:    addi a0, a0, 16
846; RV32-NEXT:    vl2r.v v8, (a0) # Unknown-size Folded Reload
847; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
848; RV32-NEXT:    vslidedown.vi v8, v8, 3
849; RV32-NEXT:    vfmv.f.s fa0, v8
850; RV32-NEXT:    call llrint
851; RV32-NEXT:    addi a2, sp, 16
852; RV32-NEXT:    vl2r.v v8, (a2) # Unknown-size Folded Reload
853; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
854; RV32-NEXT:    vslide1down.vx v8, v8, a0
855; RV32-NEXT:    vslide1down.vx v8, v8, a1
856; RV32-NEXT:    csrr a0, vlenb
857; RV32-NEXT:    slli a0, a0, 2
858; RV32-NEXT:    add sp, sp, a0
859; RV32-NEXT:    .cfi_def_cfa sp, 32
860; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
861; RV32-NEXT:    .cfi_restore ra
862; RV32-NEXT:    addi sp, sp, 32
863; RV32-NEXT:    .cfi_def_cfa_offset 0
864; RV32-NEXT:    ret
865;
866; RV64-LABEL: llrint_v4i64_v4f64:
867; RV64:       # %bb.0:
868; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
869; RV64-NEXT:    vslidedown.vi v10, v8, 1
870; RV64-NEXT:    vfmv.f.s fa5, v8
871; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
872; RV64-NEXT:    vslidedown.vi v12, v8, 2
873; RV64-NEXT:    vslidedown.vi v8, v8, 3
874; RV64-NEXT:    fcvt.l.d a0, fa5
875; RV64-NEXT:    vfmv.f.s fa5, v10
876; RV64-NEXT:    fcvt.l.d a1, fa5
877; RV64-NEXT:    vfmv.f.s fa5, v12
878; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
879; RV64-NEXT:    vmv.v.x v10, a0
880; RV64-NEXT:    fcvt.l.d a0, fa5
881; RV64-NEXT:    vfmv.f.s fa5, v8
882; RV64-NEXT:    vslide1down.vx v8, v10, a1
883; RV64-NEXT:    vslide1down.vx v8, v8, a0
884; RV64-NEXT:    fcvt.l.d a0, fa5
885; RV64-NEXT:    vslide1down.vx v8, v8, a0
886; RV64-NEXT:    ret
887  %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)
888  ret <4 x i64> %a
889}
890declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)
891
892define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) {
893; RV32-LABEL: llrint_v8i64_v8f64:
894; RV32:       # %bb.0:
895; RV32-NEXT:    addi sp, sp, -272
896; RV32-NEXT:    .cfi_def_cfa_offset 272
897; RV32-NEXT:    sw ra, 268(sp) # 4-byte Folded Spill
898; RV32-NEXT:    sw s0, 264(sp) # 4-byte Folded Spill
899; RV32-NEXT:    .cfi_offset ra, -4
900; RV32-NEXT:    .cfi_offset s0, -8
901; RV32-NEXT:    addi s0, sp, 272
902; RV32-NEXT:    .cfi_def_cfa s0, 0
903; RV32-NEXT:    csrr a0, vlenb
904; RV32-NEXT:    slli a0, a0, 2
905; RV32-NEXT:    sub sp, sp, a0
906; RV32-NEXT:    andi sp, sp, -64
907; RV32-NEXT:    addi a0, sp, 256
908; RV32-NEXT:    vs4r.v v8, (a0) # Unknown-size Folded Spill
909; RV32-NEXT:    addi a0, sp, 64
910; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
911; RV32-NEXT:    vse64.v v8, (a0)
912; RV32-NEXT:    fld fa0, 120(sp)
913; RV32-NEXT:    call llrint
914; RV32-NEXT:    sw a0, 184(sp)
915; RV32-NEXT:    sw a1, 188(sp)
916; RV32-NEXT:    fld fa0, 112(sp)
917; RV32-NEXT:    call llrint
918; RV32-NEXT:    sw a0, 176(sp)
919; RV32-NEXT:    sw a1, 180(sp)
920; RV32-NEXT:    fld fa0, 104(sp)
921; RV32-NEXT:    call llrint
922; RV32-NEXT:    sw a0, 168(sp)
923; RV32-NEXT:    sw a1, 172(sp)
924; RV32-NEXT:    fld fa0, 96(sp)
925; RV32-NEXT:    call llrint
926; RV32-NEXT:    sw a0, 160(sp)
927; RV32-NEXT:    sw a1, 164(sp)
928; RV32-NEXT:    addi a0, sp, 256
929; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
930; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
931; RV32-NEXT:    vfmv.f.s fa0, v8
932; RV32-NEXT:    call llrint
933; RV32-NEXT:    sw a0, 128(sp)
934; RV32-NEXT:    sw a1, 132(sp)
935; RV32-NEXT:    addi a0, sp, 256
936; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
937; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
938; RV32-NEXT:    vslidedown.vi v8, v8, 1
939; RV32-NEXT:    vfmv.f.s fa0, v8
940; RV32-NEXT:    call llrint
941; RV32-NEXT:    sw a0, 136(sp)
942; RV32-NEXT:    sw a1, 140(sp)
943; RV32-NEXT:    addi a0, sp, 256
944; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
945; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
946; RV32-NEXT:    vslidedown.vi v8, v8, 3
947; RV32-NEXT:    vfmv.f.s fa0, v8
948; RV32-NEXT:    call llrint
949; RV32-NEXT:    sw a0, 152(sp)
950; RV32-NEXT:    sw a1, 156(sp)
951; RV32-NEXT:    addi a0, sp, 256
952; RV32-NEXT:    vl4r.v v8, (a0) # Unknown-size Folded Reload
953; RV32-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
954; RV32-NEXT:    vslidedown.vi v8, v8, 2
955; RV32-NEXT:    vfmv.f.s fa0, v8
956; RV32-NEXT:    call llrint
957; RV32-NEXT:    sw a0, 144(sp)
958; RV32-NEXT:    sw a1, 148(sp)
959; RV32-NEXT:    addi a0, sp, 128
960; RV32-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
961; RV32-NEXT:    vle32.v v8, (a0)
962; RV32-NEXT:    addi sp, s0, -272
963; RV32-NEXT:    .cfi_def_cfa sp, 272
964; RV32-NEXT:    lw ra, 268(sp) # 4-byte Folded Reload
965; RV32-NEXT:    lw s0, 264(sp) # 4-byte Folded Reload
966; RV32-NEXT:    .cfi_restore ra
967; RV32-NEXT:    .cfi_restore s0
968; RV32-NEXT:    addi sp, sp, 272
969; RV32-NEXT:    .cfi_def_cfa_offset 0
970; RV32-NEXT:    ret
971;
972; RV64-LABEL: llrint_v8i64_v8f64:
973; RV64:       # %bb.0:
974; RV64-NEXT:    addi sp, sp, -192
975; RV64-NEXT:    .cfi_def_cfa_offset 192
976; RV64-NEXT:    sd ra, 184(sp) # 8-byte Folded Spill
977; RV64-NEXT:    sd s0, 176(sp) # 8-byte Folded Spill
978; RV64-NEXT:    .cfi_offset ra, -8
979; RV64-NEXT:    .cfi_offset s0, -16
980; RV64-NEXT:    addi s0, sp, 192
981; RV64-NEXT:    .cfi_def_cfa s0, 0
982; RV64-NEXT:    andi sp, sp, -64
983; RV64-NEXT:    mv a0, sp
984; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
985; RV64-NEXT:    vse64.v v8, (a0)
986; RV64-NEXT:    fld fa5, 56(sp)
987; RV64-NEXT:    vfmv.f.s fa4, v8
988; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
989; RV64-NEXT:    vslidedown.vi v10, v8, 1
990; RV64-NEXT:    fcvt.l.d a0, fa4
991; RV64-NEXT:    fcvt.l.d a1, fa5
992; RV64-NEXT:    sd a1, 120(sp)
993; RV64-NEXT:    fld fa5, 48(sp)
994; RV64-NEXT:    vfmv.f.s fa4, v10
995; RV64-NEXT:    vsetivli zero, 1, e64, m2, ta, ma
996; RV64-NEXT:    vslidedown.vi v10, v8, 3
997; RV64-NEXT:    fcvt.l.d a1, fa4
998; RV64-NEXT:    fcvt.l.d a2, fa5
999; RV64-NEXT:    sd a2, 112(sp)
1000; RV64-NEXT:    fld fa5, 40(sp)
1001; RV64-NEXT:    vfmv.f.s fa4, v10
1002; RV64-NEXT:    fcvt.l.d a2, fa4
1003; RV64-NEXT:    vslidedown.vi v8, v8, 2
1004; RV64-NEXT:    fcvt.l.d a3, fa5
1005; RV64-NEXT:    vfmv.f.s fa5, v8
1006; RV64-NEXT:    sd a3, 104(sp)
1007; RV64-NEXT:    fcvt.l.d a3, fa5
1008; RV64-NEXT:    fld fa5, 32(sp)
1009; RV64-NEXT:    sd a0, 64(sp)
1010; RV64-NEXT:    sd a1, 72(sp)
1011; RV64-NEXT:    sd a3, 80(sp)
1012; RV64-NEXT:    sd a2, 88(sp)
1013; RV64-NEXT:    fcvt.l.d a0, fa5
1014; RV64-NEXT:    sd a0, 96(sp)
1015; RV64-NEXT:    addi a0, sp, 64
1016; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1017; RV64-NEXT:    vle64.v v8, (a0)
1018; RV64-NEXT:    addi sp, s0, -192
1019; RV64-NEXT:    .cfi_def_cfa sp, 192
1020; RV64-NEXT:    ld ra, 184(sp) # 8-byte Folded Reload
1021; RV64-NEXT:    ld s0, 176(sp) # 8-byte Folded Reload
1022; RV64-NEXT:    .cfi_restore ra
1023; RV64-NEXT:    .cfi_restore s0
1024; RV64-NEXT:    addi sp, sp, 192
1025; RV64-NEXT:    .cfi_def_cfa_offset 0
1026; RV64-NEXT:    ret
1027  %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)
1028  ret <8 x i64> %a
1029}
1030declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)
1031