1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 4 5define void @add_v16i8(ptr %x, ptr %y) { 6; CHECK-LABEL: add_v16i8: 7; CHECK: # %bb.0: 8; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 9; CHECK-NEXT: vle8.v v8, (a0) 10; CHECK-NEXT: vle8.v v9, (a1) 11; CHECK-NEXT: vadd.vv v8, v8, v9 12; CHECK-NEXT: vse8.v v8, (a0) 13; CHECK-NEXT: ret 14 %a = load <16 x i8>, ptr %x 15 %b = load <16 x i8>, ptr %y 16 %c = add <16 x i8> %a, %b 17 store <16 x i8> %c, ptr %x 18 ret void 19} 20 21define void @add_v8i16(ptr %x, ptr %y) { 22; CHECK-LABEL: add_v8i16: 23; CHECK: # %bb.0: 24; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 25; CHECK-NEXT: vle16.v v8, (a0) 26; CHECK-NEXT: vle16.v v9, (a1) 27; CHECK-NEXT: vadd.vv v8, v8, v9 28; CHECK-NEXT: vse16.v v8, (a0) 29; CHECK-NEXT: ret 30 %a = load <8 x i16>, ptr %x 31 %b = load <8 x i16>, ptr %y 32 %c = add <8 x i16> %a, %b 33 store <8 x i16> %c, ptr %x 34 ret void 35} 36 37define void @add_v6i16(ptr %x, ptr %y) { 38; CHECK-LABEL: add_v6i16: 39; CHECK: # %bb.0: 40; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 41; CHECK-NEXT: vle16.v v8, (a0) 42; CHECK-NEXT: vle16.v v9, (a1) 43; CHECK-NEXT: vadd.vv v8, v8, v9 44; CHECK-NEXT: vse16.v v8, (a0) 45; CHECK-NEXT: ret 46 %a = load <6 x i16>, ptr %x 47 %b = load <6 x i16>, ptr %y 48 %c = add <6 x i16> %a, %b 49 store <6 x i16> %c, ptr %x 50 ret void 51} 52 53define void @add_v4i32(ptr %x, ptr %y) { 54; CHECK-LABEL: add_v4i32: 55; CHECK: # %bb.0: 56; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 57; CHECK-NEXT: vle32.v v8, (a0) 58; CHECK-NEXT: vle32.v v9, (a1) 59; CHECK-NEXT: vadd.vv v8, v8, v9 60; CHECK-NEXT: vse32.v v8, (a0) 61; CHECK-NEXT: ret 62 %a = load <4 x i32>, ptr %x 63 %b = load <4 x i32>, ptr %y 64 %c = add <4 x i32> %a, %b 65 store <4 x i32> %c, ptr %x 66 ret void 67} 68 69define void @add_v2i64(ptr %x, ptr %y) { 70; CHECK-LABEL: add_v2i64: 71; CHECK: # %bb.0: 72; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 73; CHECK-NEXT: vle64.v v8, (a0) 74; CHECK-NEXT: vle64.v v9, (a1) 75; CHECK-NEXT: vadd.vv v8, v8, v9 76; CHECK-NEXT: vse64.v v8, (a0) 77; CHECK-NEXT: ret 78 %a = load <2 x i64>, ptr %x 79 %b = load <2 x i64>, ptr %y 80 %c = add <2 x i64> %a, %b 81 store <2 x i64> %c, ptr %x 82 ret void 83} 84 85define void @sub_v16i8(ptr %x, ptr %y) { 86; CHECK-LABEL: sub_v16i8: 87; CHECK: # %bb.0: 88; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 89; CHECK-NEXT: vle8.v v8, (a0) 90; CHECK-NEXT: vle8.v v9, (a1) 91; CHECK-NEXT: vsub.vv v8, v8, v9 92; CHECK-NEXT: vse8.v v8, (a0) 93; CHECK-NEXT: ret 94 %a = load <16 x i8>, ptr %x 95 %b = load <16 x i8>, ptr %y 96 %c = sub <16 x i8> %a, %b 97 store <16 x i8> %c, ptr %x 98 ret void 99} 100 101define void @sub_v8i16(ptr %x, ptr %y) { 102; CHECK-LABEL: sub_v8i16: 103; CHECK: # %bb.0: 104; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 105; CHECK-NEXT: vle16.v v8, (a0) 106; CHECK-NEXT: vle16.v v9, (a1) 107; CHECK-NEXT: vsub.vv v8, v8, v9 108; CHECK-NEXT: vse16.v v8, (a0) 109; CHECK-NEXT: ret 110 %a = load <8 x i16>, ptr %x 111 %b = load <8 x i16>, ptr %y 112 %c = sub <8 x i16> %a, %b 113 store <8 x i16> %c, ptr %x 114 ret void 115} 116 117define void @sub_v6i16(ptr %x, ptr %y) { 118; CHECK-LABEL: sub_v6i16: 119; CHECK: # %bb.0: 120; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 121; CHECK-NEXT: vle16.v v8, (a0) 122; CHECK-NEXT: vle16.v v9, (a1) 123; CHECK-NEXT: vsub.vv v8, v8, v9 124; CHECK-NEXT: vse16.v v8, (a0) 125; CHECK-NEXT: ret 126 %a = load <6 x i16>, ptr %x 127 %b = load <6 x i16>, ptr %y 128 %c = sub <6 x i16> %a, %b 129 store <6 x i16> %c, ptr %x 130 ret void 131} 132 133define void @sub_v4i32(ptr %x, ptr %y) { 134; CHECK-LABEL: sub_v4i32: 135; CHECK: # %bb.0: 136; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 137; CHECK-NEXT: vle32.v v8, (a0) 138; CHECK-NEXT: vle32.v v9, (a1) 139; CHECK-NEXT: vsub.vv v8, v8, v9 140; CHECK-NEXT: vse32.v v8, (a0) 141; CHECK-NEXT: ret 142 %a = load <4 x i32>, ptr %x 143 %b = load <4 x i32>, ptr %y 144 %c = sub <4 x i32> %a, %b 145 store <4 x i32> %c, ptr %x 146 ret void 147} 148 149define void @sub_v2i64(ptr %x, ptr %y) { 150; CHECK-LABEL: sub_v2i64: 151; CHECK: # %bb.0: 152; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 153; CHECK-NEXT: vle64.v v8, (a0) 154; CHECK-NEXT: vle64.v v9, (a1) 155; CHECK-NEXT: vsub.vv v8, v8, v9 156; CHECK-NEXT: vse64.v v8, (a0) 157; CHECK-NEXT: ret 158 %a = load <2 x i64>, ptr %x 159 %b = load <2 x i64>, ptr %y 160 %c = sub <2 x i64> %a, %b 161 store <2 x i64> %c, ptr %x 162 ret void 163} 164 165define void @mul_v16i8(ptr %x, ptr %y) { 166; CHECK-LABEL: mul_v16i8: 167; CHECK: # %bb.0: 168; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 169; CHECK-NEXT: vle8.v v8, (a0) 170; CHECK-NEXT: vle8.v v9, (a1) 171; CHECK-NEXT: vmul.vv v8, v8, v9 172; CHECK-NEXT: vse8.v v8, (a0) 173; CHECK-NEXT: ret 174 %a = load <16 x i8>, ptr %x 175 %b = load <16 x i8>, ptr %y 176 %c = mul <16 x i8> %a, %b 177 store <16 x i8> %c, ptr %x 178 ret void 179} 180 181define void @mul_v8i16(ptr %x, ptr %y) { 182; CHECK-LABEL: mul_v8i16: 183; CHECK: # %bb.0: 184; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 185; CHECK-NEXT: vle16.v v8, (a0) 186; CHECK-NEXT: vle16.v v9, (a1) 187; CHECK-NEXT: vmul.vv v8, v8, v9 188; CHECK-NEXT: vse16.v v8, (a0) 189; CHECK-NEXT: ret 190 %a = load <8 x i16>, ptr %x 191 %b = load <8 x i16>, ptr %y 192 %c = mul <8 x i16> %a, %b 193 store <8 x i16> %c, ptr %x 194 ret void 195} 196 197define void @mul_v6i16(ptr %x, ptr %y) { 198; CHECK-LABEL: mul_v6i16: 199; CHECK: # %bb.0: 200; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 201; CHECK-NEXT: vle16.v v8, (a0) 202; CHECK-NEXT: vle16.v v9, (a1) 203; CHECK-NEXT: vmul.vv v8, v8, v9 204; CHECK-NEXT: vse16.v v8, (a0) 205; CHECK-NEXT: ret 206 %a = load <6 x i16>, ptr %x 207 %b = load <6 x i16>, ptr %y 208 %c = mul <6 x i16> %a, %b 209 store <6 x i16> %c, ptr %x 210 ret void 211} 212 213define void @mul_v4i32(ptr %x, ptr %y) { 214; CHECK-LABEL: mul_v4i32: 215; CHECK: # %bb.0: 216; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 217; CHECK-NEXT: vle32.v v8, (a0) 218; CHECK-NEXT: vle32.v v9, (a1) 219; CHECK-NEXT: vmul.vv v8, v8, v9 220; CHECK-NEXT: vse32.v v8, (a0) 221; CHECK-NEXT: ret 222 %a = load <4 x i32>, ptr %x 223 %b = load <4 x i32>, ptr %y 224 %c = mul <4 x i32> %a, %b 225 store <4 x i32> %c, ptr %x 226 ret void 227} 228 229define void @mul_v2i64(ptr %x, ptr %y) { 230; CHECK-LABEL: mul_v2i64: 231; CHECK: # %bb.0: 232; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 233; CHECK-NEXT: vle64.v v8, (a0) 234; CHECK-NEXT: vle64.v v9, (a1) 235; CHECK-NEXT: vmul.vv v8, v8, v9 236; CHECK-NEXT: vse64.v v8, (a0) 237; CHECK-NEXT: ret 238 %a = load <2 x i64>, ptr %x 239 %b = load <2 x i64>, ptr %y 240 %c = mul <2 x i64> %a, %b 241 store <2 x i64> %c, ptr %x 242 ret void 243} 244 245define void @and_v16i8(ptr %x, ptr %y) { 246; CHECK-LABEL: and_v16i8: 247; CHECK: # %bb.0: 248; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 249; CHECK-NEXT: vle8.v v8, (a0) 250; CHECK-NEXT: vle8.v v9, (a1) 251; CHECK-NEXT: vand.vv v8, v8, v9 252; CHECK-NEXT: vse8.v v8, (a0) 253; CHECK-NEXT: ret 254 %a = load <16 x i8>, ptr %x 255 %b = load <16 x i8>, ptr %y 256 %c = and <16 x i8> %a, %b 257 store <16 x i8> %c, ptr %x 258 ret void 259} 260 261define void @and_v8i16(ptr %x, ptr %y) { 262; CHECK-LABEL: and_v8i16: 263; CHECK: # %bb.0: 264; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 265; CHECK-NEXT: vle16.v v8, (a0) 266; CHECK-NEXT: vle16.v v9, (a1) 267; CHECK-NEXT: vand.vv v8, v8, v9 268; CHECK-NEXT: vse16.v v8, (a0) 269; CHECK-NEXT: ret 270 %a = load <8 x i16>, ptr %x 271 %b = load <8 x i16>, ptr %y 272 %c = and <8 x i16> %a, %b 273 store <8 x i16> %c, ptr %x 274 ret void 275} 276 277define void @and_v6i16(ptr %x, ptr %y) { 278; CHECK-LABEL: and_v6i16: 279; CHECK: # %bb.0: 280; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 281; CHECK-NEXT: vle16.v v8, (a0) 282; CHECK-NEXT: vle16.v v9, (a1) 283; CHECK-NEXT: vand.vv v8, v8, v9 284; CHECK-NEXT: vse16.v v8, (a0) 285; CHECK-NEXT: ret 286 %a = load <6 x i16>, ptr %x 287 %b = load <6 x i16>, ptr %y 288 %c = and <6 x i16> %a, %b 289 store <6 x i16> %c, ptr %x 290 ret void 291} 292 293define void @and_v4i32(ptr %x, ptr %y) { 294; CHECK-LABEL: and_v4i32: 295; CHECK: # %bb.0: 296; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 297; CHECK-NEXT: vle32.v v8, (a0) 298; CHECK-NEXT: vle32.v v9, (a1) 299; CHECK-NEXT: vand.vv v8, v8, v9 300; CHECK-NEXT: vse32.v v8, (a0) 301; CHECK-NEXT: ret 302 %a = load <4 x i32>, ptr %x 303 %b = load <4 x i32>, ptr %y 304 %c = and <4 x i32> %a, %b 305 store <4 x i32> %c, ptr %x 306 ret void 307} 308 309define void @and_v2i64(ptr %x, ptr %y) { 310; CHECK-LABEL: and_v2i64: 311; CHECK: # %bb.0: 312; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 313; CHECK-NEXT: vle64.v v8, (a0) 314; CHECK-NEXT: vle64.v v9, (a1) 315; CHECK-NEXT: vand.vv v8, v8, v9 316; CHECK-NEXT: vse64.v v8, (a0) 317; CHECK-NEXT: ret 318 %a = load <2 x i64>, ptr %x 319 %b = load <2 x i64>, ptr %y 320 %c = and <2 x i64> %a, %b 321 store <2 x i64> %c, ptr %x 322 ret void 323} 324 325define void @or_v16i8(ptr %x, ptr %y) { 326; CHECK-LABEL: or_v16i8: 327; CHECK: # %bb.0: 328; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 329; CHECK-NEXT: vle8.v v8, (a0) 330; CHECK-NEXT: vle8.v v9, (a1) 331; CHECK-NEXT: vor.vv v8, v8, v9 332; CHECK-NEXT: vse8.v v8, (a0) 333; CHECK-NEXT: ret 334 %a = load <16 x i8>, ptr %x 335 %b = load <16 x i8>, ptr %y 336 %c = or <16 x i8> %a, %b 337 store <16 x i8> %c, ptr %x 338 ret void 339} 340 341define void @or_v8i16(ptr %x, ptr %y) { 342; CHECK-LABEL: or_v8i16: 343; CHECK: # %bb.0: 344; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 345; CHECK-NEXT: vle16.v v8, (a0) 346; CHECK-NEXT: vle16.v v9, (a1) 347; CHECK-NEXT: vor.vv v8, v8, v9 348; CHECK-NEXT: vse16.v v8, (a0) 349; CHECK-NEXT: ret 350 %a = load <8 x i16>, ptr %x 351 %b = load <8 x i16>, ptr %y 352 %c = or <8 x i16> %a, %b 353 store <8 x i16> %c, ptr %x 354 ret void 355} 356 357define void @or_v6i16(ptr %x, ptr %y) { 358; CHECK-LABEL: or_v6i16: 359; CHECK: # %bb.0: 360; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 361; CHECK-NEXT: vle16.v v8, (a0) 362; CHECK-NEXT: vle16.v v9, (a1) 363; CHECK-NEXT: vor.vv v8, v8, v9 364; CHECK-NEXT: vse16.v v8, (a0) 365; CHECK-NEXT: ret 366 %a = load <6 x i16>, ptr %x 367 %b = load <6 x i16>, ptr %y 368 %c = or <6 x i16> %a, %b 369 store <6 x i16> %c, ptr %x 370 ret void 371} 372 373define void @or_v4i32(ptr %x, ptr %y) { 374; CHECK-LABEL: or_v4i32: 375; CHECK: # %bb.0: 376; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 377; CHECK-NEXT: vle32.v v8, (a0) 378; CHECK-NEXT: vle32.v v9, (a1) 379; CHECK-NEXT: vor.vv v8, v8, v9 380; CHECK-NEXT: vse32.v v8, (a0) 381; CHECK-NEXT: ret 382 %a = load <4 x i32>, ptr %x 383 %b = load <4 x i32>, ptr %y 384 %c = or <4 x i32> %a, %b 385 store <4 x i32> %c, ptr %x 386 ret void 387} 388 389define void @or_v2i64(ptr %x, ptr %y) { 390; CHECK-LABEL: or_v2i64: 391; CHECK: # %bb.0: 392; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 393; CHECK-NEXT: vle64.v v8, (a0) 394; CHECK-NEXT: vle64.v v9, (a1) 395; CHECK-NEXT: vor.vv v8, v8, v9 396; CHECK-NEXT: vse64.v v8, (a0) 397; CHECK-NEXT: ret 398 %a = load <2 x i64>, ptr %x 399 %b = load <2 x i64>, ptr %y 400 %c = or <2 x i64> %a, %b 401 store <2 x i64> %c, ptr %x 402 ret void 403} 404 405define void @xor_v16i8(ptr %x, ptr %y) { 406; CHECK-LABEL: xor_v16i8: 407; CHECK: # %bb.0: 408; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 409; CHECK-NEXT: vle8.v v8, (a0) 410; CHECK-NEXT: vle8.v v9, (a1) 411; CHECK-NEXT: vxor.vv v8, v8, v9 412; CHECK-NEXT: vse8.v v8, (a0) 413; CHECK-NEXT: ret 414 %a = load <16 x i8>, ptr %x 415 %b = load <16 x i8>, ptr %y 416 %c = xor <16 x i8> %a, %b 417 store <16 x i8> %c, ptr %x 418 ret void 419} 420 421define void @xor_v8i16(ptr %x, ptr %y) { 422; CHECK-LABEL: xor_v8i16: 423; CHECK: # %bb.0: 424; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 425; CHECK-NEXT: vle16.v v8, (a0) 426; CHECK-NEXT: vle16.v v9, (a1) 427; CHECK-NEXT: vxor.vv v8, v8, v9 428; CHECK-NEXT: vse16.v v8, (a0) 429; CHECK-NEXT: ret 430 %a = load <8 x i16>, ptr %x 431 %b = load <8 x i16>, ptr %y 432 %c = xor <8 x i16> %a, %b 433 store <8 x i16> %c, ptr %x 434 ret void 435} 436 437define void @xor_v6i16(ptr %x, ptr %y) { 438; CHECK-LABEL: xor_v6i16: 439; CHECK: # %bb.0: 440; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 441; CHECK-NEXT: vle16.v v8, (a0) 442; CHECK-NEXT: vle16.v v9, (a1) 443; CHECK-NEXT: vxor.vv v8, v8, v9 444; CHECK-NEXT: vse16.v v8, (a0) 445; CHECK-NEXT: ret 446 %a = load <6 x i16>, ptr %x 447 %b = load <6 x i16>, ptr %y 448 %c = xor <6 x i16> %a, %b 449 store <6 x i16> %c, ptr %x 450 ret void 451} 452 453define void @xor_v4i32(ptr %x, ptr %y) { 454; CHECK-LABEL: xor_v4i32: 455; CHECK: # %bb.0: 456; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 457; CHECK-NEXT: vle32.v v8, (a0) 458; CHECK-NEXT: vle32.v v9, (a1) 459; CHECK-NEXT: vxor.vv v8, v8, v9 460; CHECK-NEXT: vse32.v v8, (a0) 461; CHECK-NEXT: ret 462 %a = load <4 x i32>, ptr %x 463 %b = load <4 x i32>, ptr %y 464 %c = xor <4 x i32> %a, %b 465 store <4 x i32> %c, ptr %x 466 ret void 467} 468 469define void @xor_v2i64(ptr %x, ptr %y) { 470; CHECK-LABEL: xor_v2i64: 471; CHECK: # %bb.0: 472; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 473; CHECK-NEXT: vle64.v v8, (a0) 474; CHECK-NEXT: vle64.v v9, (a1) 475; CHECK-NEXT: vxor.vv v8, v8, v9 476; CHECK-NEXT: vse64.v v8, (a0) 477; CHECK-NEXT: ret 478 %a = load <2 x i64>, ptr %x 479 %b = load <2 x i64>, ptr %y 480 %c = xor <2 x i64> %a, %b 481 store <2 x i64> %c, ptr %x 482 ret void 483} 484 485define void @lshr_v16i8(ptr %x, ptr %y) { 486; CHECK-LABEL: lshr_v16i8: 487; CHECK: # %bb.0: 488; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 489; CHECK-NEXT: vle8.v v8, (a0) 490; CHECK-NEXT: vle8.v v9, (a1) 491; CHECK-NEXT: vsrl.vv v8, v8, v9 492; CHECK-NEXT: vse8.v v8, (a0) 493; CHECK-NEXT: ret 494 %a = load <16 x i8>, ptr %x 495 %b = load <16 x i8>, ptr %y 496 %c = lshr <16 x i8> %a, %b 497 store <16 x i8> %c, ptr %x 498 ret void 499} 500 501define void @lshr_v8i16(ptr %x, ptr %y) { 502; CHECK-LABEL: lshr_v8i16: 503; CHECK: # %bb.0: 504; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 505; CHECK-NEXT: vle16.v v8, (a0) 506; CHECK-NEXT: vle16.v v9, (a1) 507; CHECK-NEXT: vsrl.vv v8, v8, v9 508; CHECK-NEXT: vse16.v v8, (a0) 509; CHECK-NEXT: ret 510 %a = load <8 x i16>, ptr %x 511 %b = load <8 x i16>, ptr %y 512 %c = lshr <8 x i16> %a, %b 513 store <8 x i16> %c, ptr %x 514 ret void 515} 516 517define void @lshr_v6i16(ptr %x, ptr %y) { 518; CHECK-LABEL: lshr_v6i16: 519; CHECK: # %bb.0: 520; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 521; CHECK-NEXT: vle16.v v8, (a0) 522; CHECK-NEXT: vle16.v v9, (a1) 523; CHECK-NEXT: vsrl.vv v8, v8, v9 524; CHECK-NEXT: vse16.v v8, (a0) 525; CHECK-NEXT: ret 526 %a = load <6 x i16>, ptr %x 527 %b = load <6 x i16>, ptr %y 528 %c = lshr <6 x i16> %a, %b 529 store <6 x i16> %c, ptr %x 530 ret void 531} 532 533define void @lshr_v4i32(ptr %x, ptr %y) { 534; CHECK-LABEL: lshr_v4i32: 535; CHECK: # %bb.0: 536; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 537; CHECK-NEXT: vle32.v v8, (a0) 538; CHECK-NEXT: vle32.v v9, (a1) 539; CHECK-NEXT: vsrl.vv v8, v8, v9 540; CHECK-NEXT: vse32.v v8, (a0) 541; CHECK-NEXT: ret 542 %a = load <4 x i32>, ptr %x 543 %b = load <4 x i32>, ptr %y 544 %c = lshr <4 x i32> %a, %b 545 store <4 x i32> %c, ptr %x 546 ret void 547} 548 549define void @lshr_v2i64(ptr %x, ptr %y) { 550; CHECK-LABEL: lshr_v2i64: 551; CHECK: # %bb.0: 552; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 553; CHECK-NEXT: vle64.v v8, (a0) 554; CHECK-NEXT: vle64.v v9, (a1) 555; CHECK-NEXT: vsrl.vv v8, v8, v9 556; CHECK-NEXT: vse64.v v8, (a0) 557; CHECK-NEXT: ret 558 %a = load <2 x i64>, ptr %x 559 %b = load <2 x i64>, ptr %y 560 %c = lshr <2 x i64> %a, %b 561 store <2 x i64> %c, ptr %x 562 ret void 563} 564 565define void @ashr_v16i8(ptr %x, ptr %y) { 566; CHECK-LABEL: ashr_v16i8: 567; CHECK: # %bb.0: 568; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 569; CHECK-NEXT: vle8.v v8, (a0) 570; CHECK-NEXT: vle8.v v9, (a1) 571; CHECK-NEXT: vsra.vv v8, v8, v9 572; CHECK-NEXT: vse8.v v8, (a0) 573; CHECK-NEXT: ret 574 %a = load <16 x i8>, ptr %x 575 %b = load <16 x i8>, ptr %y 576 %c = ashr <16 x i8> %a, %b 577 store <16 x i8> %c, ptr %x 578 ret void 579} 580 581define void @ashr_v8i16(ptr %x, ptr %y) { 582; CHECK-LABEL: ashr_v8i16: 583; CHECK: # %bb.0: 584; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 585; CHECK-NEXT: vle16.v v8, (a0) 586; CHECK-NEXT: vle16.v v9, (a1) 587; CHECK-NEXT: vsra.vv v8, v8, v9 588; CHECK-NEXT: vse16.v v8, (a0) 589; CHECK-NEXT: ret 590 %a = load <8 x i16>, ptr %x 591 %b = load <8 x i16>, ptr %y 592 %c = ashr <8 x i16> %a, %b 593 store <8 x i16> %c, ptr %x 594 ret void 595} 596 597define void @ashr_v6i16(ptr %x, ptr %y) { 598; CHECK-LABEL: ashr_v6i16: 599; CHECK: # %bb.0: 600; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 601; CHECK-NEXT: vle16.v v8, (a0) 602; CHECK-NEXT: vle16.v v9, (a1) 603; CHECK-NEXT: vsra.vv v8, v8, v9 604; CHECK-NEXT: vse16.v v8, (a0) 605; CHECK-NEXT: ret 606 %a = load <6 x i16>, ptr %x 607 %b = load <6 x i16>, ptr %y 608 %c = ashr <6 x i16> %a, %b 609 store <6 x i16> %c, ptr %x 610 ret void 611} 612 613define void @ashr_v4i32(ptr %x, ptr %y) { 614; CHECK-LABEL: ashr_v4i32: 615; CHECK: # %bb.0: 616; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 617; CHECK-NEXT: vle32.v v8, (a0) 618; CHECK-NEXT: vle32.v v9, (a1) 619; CHECK-NEXT: vsra.vv v8, v8, v9 620; CHECK-NEXT: vse32.v v8, (a0) 621; CHECK-NEXT: ret 622 %a = load <4 x i32>, ptr %x 623 %b = load <4 x i32>, ptr %y 624 %c = ashr <4 x i32> %a, %b 625 store <4 x i32> %c, ptr %x 626 ret void 627} 628 629define void @ashr_v2i64(ptr %x, ptr %y) { 630; CHECK-LABEL: ashr_v2i64: 631; CHECK: # %bb.0: 632; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 633; CHECK-NEXT: vle64.v v8, (a0) 634; CHECK-NEXT: vle64.v v9, (a1) 635; CHECK-NEXT: vsra.vv v8, v8, v9 636; CHECK-NEXT: vse64.v v8, (a0) 637; CHECK-NEXT: ret 638 %a = load <2 x i64>, ptr %x 639 %b = load <2 x i64>, ptr %y 640 %c = ashr <2 x i64> %a, %b 641 store <2 x i64> %c, ptr %x 642 ret void 643} 644 645define void @shl_v16i8(ptr %x, ptr %y) { 646; CHECK-LABEL: shl_v16i8: 647; CHECK: # %bb.0: 648; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 649; CHECK-NEXT: vle8.v v8, (a0) 650; CHECK-NEXT: vle8.v v9, (a1) 651; CHECK-NEXT: vsll.vv v8, v8, v9 652; CHECK-NEXT: vse8.v v8, (a0) 653; CHECK-NEXT: ret 654 %a = load <16 x i8>, ptr %x 655 %b = load <16 x i8>, ptr %y 656 %c = shl <16 x i8> %a, %b 657 store <16 x i8> %c, ptr %x 658 ret void 659} 660 661define void @shl_v8i16(ptr %x, ptr %y) { 662; CHECK-LABEL: shl_v8i16: 663; CHECK: # %bb.0: 664; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 665; CHECK-NEXT: vle16.v v8, (a0) 666; CHECK-NEXT: vle16.v v9, (a1) 667; CHECK-NEXT: vsll.vv v8, v8, v9 668; CHECK-NEXT: vse16.v v8, (a0) 669; CHECK-NEXT: ret 670 %a = load <8 x i16>, ptr %x 671 %b = load <8 x i16>, ptr %y 672 %c = shl <8 x i16> %a, %b 673 store <8 x i16> %c, ptr %x 674 ret void 675} 676 677define void @shl_v6i16(ptr %x, ptr %y) { 678; CHECK-LABEL: shl_v6i16: 679; CHECK: # %bb.0: 680; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 681; CHECK-NEXT: vle16.v v8, (a0) 682; CHECK-NEXT: vle16.v v9, (a1) 683; CHECK-NEXT: vsll.vv v8, v8, v9 684; CHECK-NEXT: vse16.v v8, (a0) 685; CHECK-NEXT: ret 686 %a = load <6 x i16>, ptr %x 687 %b = load <6 x i16>, ptr %y 688 %c = shl <6 x i16> %a, %b 689 store <6 x i16> %c, ptr %x 690 ret void 691} 692 693define void @shl_v4i32(ptr %x, ptr %y) { 694; CHECK-LABEL: shl_v4i32: 695; CHECK: # %bb.0: 696; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 697; CHECK-NEXT: vle32.v v8, (a0) 698; CHECK-NEXT: vle32.v v9, (a1) 699; CHECK-NEXT: vsll.vv v8, v8, v9 700; CHECK-NEXT: vse32.v v8, (a0) 701; CHECK-NEXT: ret 702 %a = load <4 x i32>, ptr %x 703 %b = load <4 x i32>, ptr %y 704 %c = shl <4 x i32> %a, %b 705 store <4 x i32> %c, ptr %x 706 ret void 707} 708 709define void @shl_v2i64(ptr %x, ptr %y) { 710; CHECK-LABEL: shl_v2i64: 711; CHECK: # %bb.0: 712; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 713; CHECK-NEXT: vle64.v v8, (a0) 714; CHECK-NEXT: vle64.v v9, (a1) 715; CHECK-NEXT: vsll.vv v8, v8, v9 716; CHECK-NEXT: vse64.v v8, (a0) 717; CHECK-NEXT: ret 718 %a = load <2 x i64>, ptr %x 719 %b = load <2 x i64>, ptr %y 720 %c = shl <2 x i64> %a, %b 721 store <2 x i64> %c, ptr %x 722 ret void 723} 724 725define void @sdiv_v16i8(ptr %x, ptr %y) { 726; CHECK-LABEL: sdiv_v16i8: 727; CHECK: # %bb.0: 728; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 729; CHECK-NEXT: vle8.v v8, (a0) 730; CHECK-NEXT: vle8.v v9, (a1) 731; CHECK-NEXT: vdiv.vv v8, v8, v9 732; CHECK-NEXT: vse8.v v8, (a0) 733; CHECK-NEXT: ret 734 %a = load <16 x i8>, ptr %x 735 %b = load <16 x i8>, ptr %y 736 %c = sdiv <16 x i8> %a, %b 737 store <16 x i8> %c, ptr %x 738 ret void 739} 740 741define void @sdiv_v8i16(ptr %x, ptr %y) { 742; CHECK-LABEL: sdiv_v8i16: 743; CHECK: # %bb.0: 744; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 745; CHECK-NEXT: vle16.v v8, (a0) 746; CHECK-NEXT: vle16.v v9, (a1) 747; CHECK-NEXT: vdiv.vv v8, v8, v9 748; CHECK-NEXT: vse16.v v8, (a0) 749; CHECK-NEXT: ret 750 %a = load <8 x i16>, ptr %x 751 %b = load <8 x i16>, ptr %y 752 %c = sdiv <8 x i16> %a, %b 753 store <8 x i16> %c, ptr %x 754 ret void 755} 756 757define void @sdiv_v6i16(ptr %x, ptr %y) { 758; CHECK-LABEL: sdiv_v6i16: 759; CHECK: # %bb.0: 760; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 761; CHECK-NEXT: vle16.v v8, (a0) 762; CHECK-NEXT: vle16.v v9, (a1) 763; CHECK-NEXT: vdiv.vv v8, v8, v9 764; CHECK-NEXT: vse16.v v8, (a0) 765; CHECK-NEXT: ret 766 %a = load <6 x i16>, ptr %x 767 %b = load <6 x i16>, ptr %y 768 %c = sdiv <6 x i16> %a, %b 769 store <6 x i16> %c, ptr %x 770 ret void 771} 772 773define void @sdiv_v4i32(ptr %x, ptr %y) { 774; CHECK-LABEL: sdiv_v4i32: 775; CHECK: # %bb.0: 776; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 777; CHECK-NEXT: vle32.v v8, (a0) 778; CHECK-NEXT: vle32.v v9, (a1) 779; CHECK-NEXT: vdiv.vv v8, v8, v9 780; CHECK-NEXT: vse32.v v8, (a0) 781; CHECK-NEXT: ret 782 %a = load <4 x i32>, ptr %x 783 %b = load <4 x i32>, ptr %y 784 %c = sdiv <4 x i32> %a, %b 785 store <4 x i32> %c, ptr %x 786 ret void 787} 788 789define void @sdiv_v2i64(ptr %x, ptr %y) { 790; CHECK-LABEL: sdiv_v2i64: 791; CHECK: # %bb.0: 792; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 793; CHECK-NEXT: vle64.v v8, (a0) 794; CHECK-NEXT: vle64.v v9, (a1) 795; CHECK-NEXT: vdiv.vv v8, v8, v9 796; CHECK-NEXT: vse64.v v8, (a0) 797; CHECK-NEXT: ret 798 %a = load <2 x i64>, ptr %x 799 %b = load <2 x i64>, ptr %y 800 %c = sdiv <2 x i64> %a, %b 801 store <2 x i64> %c, ptr %x 802 ret void 803} 804 805define void @srem_v16i8(ptr %x, ptr %y) { 806; CHECK-LABEL: srem_v16i8: 807; CHECK: # %bb.0: 808; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 809; CHECK-NEXT: vle8.v v8, (a0) 810; CHECK-NEXT: vle8.v v9, (a1) 811; CHECK-NEXT: vrem.vv v8, v8, v9 812; CHECK-NEXT: vse8.v v8, (a0) 813; CHECK-NEXT: ret 814 %a = load <16 x i8>, ptr %x 815 %b = load <16 x i8>, ptr %y 816 %c = srem <16 x i8> %a, %b 817 store <16 x i8> %c, ptr %x 818 ret void 819} 820 821define void @srem_v8i16(ptr %x, ptr %y) { 822; CHECK-LABEL: srem_v8i16: 823; CHECK: # %bb.0: 824; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 825; CHECK-NEXT: vle16.v v8, (a0) 826; CHECK-NEXT: vle16.v v9, (a1) 827; CHECK-NEXT: vrem.vv v8, v8, v9 828; CHECK-NEXT: vse16.v v8, (a0) 829; CHECK-NEXT: ret 830 %a = load <8 x i16>, ptr %x 831 %b = load <8 x i16>, ptr %y 832 %c = srem <8 x i16> %a, %b 833 store <8 x i16> %c, ptr %x 834 ret void 835} 836 837define void @srem_v6i16(ptr %x, ptr %y) { 838; CHECK-LABEL: srem_v6i16: 839; CHECK: # %bb.0: 840; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 841; CHECK-NEXT: vle16.v v8, (a0) 842; CHECK-NEXT: vle16.v v9, (a1) 843; CHECK-NEXT: vrem.vv v8, v8, v9 844; CHECK-NEXT: vse16.v v8, (a0) 845; CHECK-NEXT: ret 846 %a = load <6 x i16>, ptr %x 847 %b = load <6 x i16>, ptr %y 848 %c = srem <6 x i16> %a, %b 849 store <6 x i16> %c, ptr %x 850 ret void 851} 852 853define void @srem_v4i32(ptr %x, ptr %y) { 854; CHECK-LABEL: srem_v4i32: 855; CHECK: # %bb.0: 856; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 857; CHECK-NEXT: vle32.v v8, (a0) 858; CHECK-NEXT: vle32.v v9, (a1) 859; CHECK-NEXT: vrem.vv v8, v8, v9 860; CHECK-NEXT: vse32.v v8, (a0) 861; CHECK-NEXT: ret 862 %a = load <4 x i32>, ptr %x 863 %b = load <4 x i32>, ptr %y 864 %c = srem <4 x i32> %a, %b 865 store <4 x i32> %c, ptr %x 866 ret void 867} 868 869define void @srem_v2i64(ptr %x, ptr %y) { 870; CHECK-LABEL: srem_v2i64: 871; CHECK: # %bb.0: 872; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 873; CHECK-NEXT: vle64.v v8, (a0) 874; CHECK-NEXT: vle64.v v9, (a1) 875; CHECK-NEXT: vrem.vv v8, v8, v9 876; CHECK-NEXT: vse64.v v8, (a0) 877; CHECK-NEXT: ret 878 %a = load <2 x i64>, ptr %x 879 %b = load <2 x i64>, ptr %y 880 %c = srem <2 x i64> %a, %b 881 store <2 x i64> %c, ptr %x 882 ret void 883} 884 885define void @udiv_v16i8(ptr %x, ptr %y) { 886; CHECK-LABEL: udiv_v16i8: 887; CHECK: # %bb.0: 888; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 889; CHECK-NEXT: vle8.v v8, (a0) 890; CHECK-NEXT: vle8.v v9, (a1) 891; CHECK-NEXT: vdivu.vv v8, v8, v9 892; CHECK-NEXT: vse8.v v8, (a0) 893; CHECK-NEXT: ret 894 %a = load <16 x i8>, ptr %x 895 %b = load <16 x i8>, ptr %y 896 %c = udiv <16 x i8> %a, %b 897 store <16 x i8> %c, ptr %x 898 ret void 899} 900 901define void @udiv_v8i16(ptr %x, ptr %y) { 902; CHECK-LABEL: udiv_v8i16: 903; CHECK: # %bb.0: 904; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 905; CHECK-NEXT: vle16.v v8, (a0) 906; CHECK-NEXT: vle16.v v9, (a1) 907; CHECK-NEXT: vdivu.vv v8, v8, v9 908; CHECK-NEXT: vse16.v v8, (a0) 909; CHECK-NEXT: ret 910 %a = load <8 x i16>, ptr %x 911 %b = load <8 x i16>, ptr %y 912 %c = udiv <8 x i16> %a, %b 913 store <8 x i16> %c, ptr %x 914 ret void 915} 916 917define void @udiv_v6i16(ptr %x, ptr %y) { 918; CHECK-LABEL: udiv_v6i16: 919; CHECK: # %bb.0: 920; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 921; CHECK-NEXT: vle16.v v8, (a0) 922; CHECK-NEXT: vle16.v v9, (a1) 923; CHECK-NEXT: vdivu.vv v8, v8, v9 924; CHECK-NEXT: vse16.v v8, (a0) 925; CHECK-NEXT: ret 926 %a = load <6 x i16>, ptr %x 927 %b = load <6 x i16>, ptr %y 928 %c = udiv <6 x i16> %a, %b 929 store <6 x i16> %c, ptr %x 930 ret void 931} 932 933define void @udiv_v4i32(ptr %x, ptr %y) { 934; CHECK-LABEL: udiv_v4i32: 935; CHECK: # %bb.0: 936; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 937; CHECK-NEXT: vle32.v v8, (a0) 938; CHECK-NEXT: vle32.v v9, (a1) 939; CHECK-NEXT: vdivu.vv v8, v8, v9 940; CHECK-NEXT: vse32.v v8, (a0) 941; CHECK-NEXT: ret 942 %a = load <4 x i32>, ptr %x 943 %b = load <4 x i32>, ptr %y 944 %c = udiv <4 x i32> %a, %b 945 store <4 x i32> %c, ptr %x 946 ret void 947} 948 949define void @udiv_v2i64(ptr %x, ptr %y) { 950; CHECK-LABEL: udiv_v2i64: 951; CHECK: # %bb.0: 952; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 953; CHECK-NEXT: vle64.v v8, (a0) 954; CHECK-NEXT: vle64.v v9, (a1) 955; CHECK-NEXT: vdivu.vv v8, v8, v9 956; CHECK-NEXT: vse64.v v8, (a0) 957; CHECK-NEXT: ret 958 %a = load <2 x i64>, ptr %x 959 %b = load <2 x i64>, ptr %y 960 %c = udiv <2 x i64> %a, %b 961 store <2 x i64> %c, ptr %x 962 ret void 963} 964 965define void @urem_v16i8(ptr %x, ptr %y) { 966; CHECK-LABEL: urem_v16i8: 967; CHECK: # %bb.0: 968; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 969; CHECK-NEXT: vle8.v v8, (a0) 970; CHECK-NEXT: vle8.v v9, (a1) 971; CHECK-NEXT: vremu.vv v8, v8, v9 972; CHECK-NEXT: vse8.v v8, (a0) 973; CHECK-NEXT: ret 974 %a = load <16 x i8>, ptr %x 975 %b = load <16 x i8>, ptr %y 976 %c = urem <16 x i8> %a, %b 977 store <16 x i8> %c, ptr %x 978 ret void 979} 980 981define void @urem_v8i16(ptr %x, ptr %y) { 982; CHECK-LABEL: urem_v8i16: 983; CHECK: # %bb.0: 984; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 985; CHECK-NEXT: vle16.v v8, (a0) 986; CHECK-NEXT: vle16.v v9, (a1) 987; CHECK-NEXT: vremu.vv v8, v8, v9 988; CHECK-NEXT: vse16.v v8, (a0) 989; CHECK-NEXT: ret 990 %a = load <8 x i16>, ptr %x 991 %b = load <8 x i16>, ptr %y 992 %c = urem <8 x i16> %a, %b 993 store <8 x i16> %c, ptr %x 994 ret void 995} 996 997define void @urem_v6i16(ptr %x, ptr %y) { 998; CHECK-LABEL: urem_v6i16: 999; CHECK: # %bb.0: 1000; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1001; CHECK-NEXT: vle16.v v8, (a0) 1002; CHECK-NEXT: vle16.v v9, (a1) 1003; CHECK-NEXT: vremu.vv v8, v8, v9 1004; CHECK-NEXT: vse16.v v8, (a0) 1005; CHECK-NEXT: ret 1006 %a = load <6 x i16>, ptr %x 1007 %b = load <6 x i16>, ptr %y 1008 %c = urem <6 x i16> %a, %b 1009 store <6 x i16> %c, ptr %x 1010 ret void 1011} 1012 1013define void @urem_v4i32(ptr %x, ptr %y) { 1014; CHECK-LABEL: urem_v4i32: 1015; CHECK: # %bb.0: 1016; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1017; CHECK-NEXT: vle32.v v8, (a0) 1018; CHECK-NEXT: vle32.v v9, (a1) 1019; CHECK-NEXT: vremu.vv v8, v8, v9 1020; CHECK-NEXT: vse32.v v8, (a0) 1021; CHECK-NEXT: ret 1022 %a = load <4 x i32>, ptr %x 1023 %b = load <4 x i32>, ptr %y 1024 %c = urem <4 x i32> %a, %b 1025 store <4 x i32> %c, ptr %x 1026 ret void 1027} 1028 1029define void @urem_v2i64(ptr %x, ptr %y) { 1030; CHECK-LABEL: urem_v2i64: 1031; CHECK: # %bb.0: 1032; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1033; CHECK-NEXT: vle64.v v8, (a0) 1034; CHECK-NEXT: vle64.v v9, (a1) 1035; CHECK-NEXT: vremu.vv v8, v8, v9 1036; CHECK-NEXT: vse64.v v8, (a0) 1037; CHECK-NEXT: ret 1038 %a = load <2 x i64>, ptr %x 1039 %b = load <2 x i64>, ptr %y 1040 %c = urem <2 x i64> %a, %b 1041 store <2 x i64> %c, ptr %x 1042 ret void 1043} 1044 1045define void @mulhu_v16i8(ptr %x) { 1046; CHECK-LABEL: mulhu_v16i8: 1047; CHECK: # %bb.0: 1048; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1049; CHECK-NEXT: vle8.v v9, (a0) 1050; CHECK-NEXT: lui a1, 3 1051; CHECK-NEXT: vmv.v.i v10, 0 1052; CHECK-NEXT: lui a2, %hi(.LCPI65_0) 1053; CHECK-NEXT: addi a2, a2, %lo(.LCPI65_0) 1054; CHECK-NEXT: vle8.v v11, (a2) 1055; CHECK-NEXT: lui a2, 1 1056; CHECK-NEXT: addi a1, a1, -2044 1057; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 1058; CHECK-NEXT: vmv.s.x v0, a1 1059; CHECK-NEXT: addi a1, a2, 32 1060; CHECK-NEXT: vmv.s.x v8, a1 1061; CHECK-NEXT: li a1, -128 1062; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1063; CHECK-NEXT: vmerge.vxm v12, v10, a1, v0 1064; CHECK-NEXT: li a1, 513 1065; CHECK-NEXT: vmv.v.i v13, 4 1066; CHECK-NEXT: vmv1r.v v0, v8 1067; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 1068; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 1069; CHECK-NEXT: vmv.s.x v0, a1 1070; CHECK-NEXT: addi a1, a2, 78 1071; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1072; CHECK-NEXT: vmerge.vim v10, v13, 1, v0 1073; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 1074; CHECK-NEXT: vmv.s.x v0, a1 1075; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1076; CHECK-NEXT: vsrl.vv v8, v9, v8 1077; CHECK-NEXT: vmulhu.vv v8, v8, v11 1078; CHECK-NEXT: vmerge.vim v10, v10, 3, v0 1079; CHECK-NEXT: lui a1, 8 1080; CHECK-NEXT: addi a1, a1, 304 1081; CHECK-NEXT: vsub.vv v9, v9, v8 1082; CHECK-NEXT: vmulhu.vv v9, v9, v12 1083; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 1084; CHECK-NEXT: vmv.s.x v0, a1 1085; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1086; CHECK-NEXT: vadd.vv v8, v9, v8 1087; CHECK-NEXT: vmerge.vim v9, v10, 2, v0 1088; CHECK-NEXT: vsrl.vv v8, v8, v9 1089; CHECK-NEXT: vse8.v v8, (a0) 1090; CHECK-NEXT: ret 1091 %a = load <16 x i8>, ptr %x 1092 %b = udiv <16 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25> 1093 store <16 x i8> %b, ptr %x 1094 ret void 1095} 1096 1097define void @mulhu_v8i16(ptr %x) { 1098; CHECK-LABEL: mulhu_v8i16: 1099; CHECK: # %bb.0: 1100; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1101; CHECK-NEXT: vle16.v v8, (a0) 1102; CHECK-NEXT: vmv.v.i v9, 0 1103; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma 1104; CHECK-NEXT: vmv.v.i v10, 1 1105; CHECK-NEXT: li a1, 33 1106; CHECK-NEXT: vmv.s.x v0, a1 1107; CHECK-NEXT: lui a1, %hi(.LCPI66_0) 1108; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0) 1109; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1110; CHECK-NEXT: vmv.v.i v11, 3 1111; CHECK-NEXT: vle16.v v12, (a1) 1112; CHECK-NEXT: vmerge.vim v11, v11, 2, v0 1113; CHECK-NEXT: vmv1r.v v13, v9 1114; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma 1115; CHECK-NEXT: vslideup.vi v9, v10, 6 1116; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1117; CHECK-NEXT: vsrl.vv v9, v8, v9 1118; CHECK-NEXT: vmulhu.vv v9, v9, v12 1119; CHECK-NEXT: lui a1, 1048568 1120; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma 1121; CHECK-NEXT: vmv.s.x v13, a1 1122; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma 1123; CHECK-NEXT: vsub.vv v8, v8, v9 1124; CHECK-NEXT: vmulhu.vv v8, v8, v13 1125; CHECK-NEXT: vadd.vv v8, v8, v9 1126; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma 1127; CHECK-NEXT: vslideup.vi v11, v10, 6 1128; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1129; CHECK-NEXT: vsrl.vv v8, v8, v11 1130; CHECK-NEXT: vse16.v v8, (a0) 1131; CHECK-NEXT: ret 1132 %a = load <8 x i16>, ptr %x 1133 %b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> 1134 store <8 x i16> %b, ptr %x 1135 ret void 1136} 1137 1138define void @mulhu_v6i16(ptr %x) { 1139; CHECK-LABEL: mulhu_v6i16: 1140; CHECK: # %bb.0: 1141; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1142; CHECK-NEXT: vle16.v v8, (a0) 1143; CHECK-NEXT: lui a1, %hi(.LCPI67_0) 1144; CHECK-NEXT: addi a1, a1, %lo(.LCPI67_0) 1145; CHECK-NEXT: vle16.v v9, (a1) 1146; CHECK-NEXT: vdivu.vv v8, v8, v9 1147; CHECK-NEXT: vse16.v v8, (a0) 1148; CHECK-NEXT: ret 1149 %a = load <6 x i16>, ptr %x 1150 %b = udiv <6 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13> 1151 store <6 x i16> %b, ptr %x 1152 ret void 1153} 1154 1155define void @mulhu_v4i32(ptr %x) { 1156; CHECK-LABEL: mulhu_v4i32: 1157; CHECK: # %bb.0: 1158; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1159; CHECK-NEXT: vle32.v v8, (a0) 1160; CHECK-NEXT: lui a1, 524288 1161; CHECK-NEXT: vmv.v.i v9, 0 1162; CHECK-NEXT: vmv.s.x v10, a1 1163; CHECK-NEXT: lui a1, %hi(.LCPI68_0) 1164; CHECK-NEXT: addi a1, a1, %lo(.LCPI68_0) 1165; CHECK-NEXT: vle32.v v11, (a1) 1166; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma 1167; CHECK-NEXT: vslideup.vi v9, v10, 2 1168; CHECK-NEXT: lui a1, 4128 1169; CHECK-NEXT: addi a1, a1, 514 1170; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1171; CHECK-NEXT: vmulhu.vv v10, v8, v11 1172; CHECK-NEXT: vsub.vv v8, v8, v10 1173; CHECK-NEXT: vmulhu.vv v8, v8, v9 1174; CHECK-NEXT: vmv.s.x v9, a1 1175; CHECK-NEXT: vadd.vv v8, v8, v10 1176; CHECK-NEXT: vsext.vf4 v10, v9 1177; CHECK-NEXT: vsrl.vv v8, v8, v10 1178; CHECK-NEXT: vse32.v v8, (a0) 1179; CHECK-NEXT: ret 1180 %a = load <4 x i32>, ptr %x 1181 %b = udiv <4 x i32> %a, <i32 5, i32 6, i32 7, i32 9> 1182 store <4 x i32> %b, ptr %x 1183 ret void 1184} 1185 1186define void @mulhu_v2i64(ptr %x) { 1187; RV32-LABEL: mulhu_v2i64: 1188; RV32: # %bb.0: 1189; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1190; RV32-NEXT: vle64.v v8, (a0) 1191; RV32-NEXT: lui a1, %hi(.LCPI69_0) 1192; RV32-NEXT: addi a1, a1, %lo(.LCPI69_0) 1193; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1194; RV32-NEXT: vle32.v v9, (a1) 1195; RV32-NEXT: lui a1, 32 1196; RV32-NEXT: addi a1, a1, 1 1197; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1198; RV32-NEXT: vmulhu.vv v8, v8, v9 1199; RV32-NEXT: vmv.s.x v9, a1 1200; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1201; RV32-NEXT: vsext.vf4 v10, v9 1202; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1203; RV32-NEXT: vsrl.vv v8, v8, v10 1204; RV32-NEXT: vse64.v v8, (a0) 1205; RV32-NEXT: ret 1206; 1207; RV64-LABEL: mulhu_v2i64: 1208; RV64: # %bb.0: 1209; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1210; RV64-NEXT: vle64.v v8, (a0) 1211; RV64-NEXT: lui a1, 838861 1212; RV64-NEXT: lui a2, 699051 1213; RV64-NEXT: addiw a1, a1, -819 1214; RV64-NEXT: addiw a2, a2, -1365 1215; RV64-NEXT: slli a3, a1, 32 1216; RV64-NEXT: add a1, a1, a3 1217; RV64-NEXT: slli a3, a2, 32 1218; RV64-NEXT: add a2, a2, a3 1219; RV64-NEXT: vmv.v.x v9, a1 1220; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma 1221; RV64-NEXT: vmv.s.x v9, a2 1222; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma 1223; RV64-NEXT: vmulhu.vv v8, v8, v9 1224; RV64-NEXT: vid.v v9 1225; RV64-NEXT: vadd.vi v9, v9, 1 1226; RV64-NEXT: vsrl.vv v8, v8, v9 1227; RV64-NEXT: vse64.v v8, (a0) 1228; RV64-NEXT: ret 1229 %a = load <2 x i64>, ptr %x 1230 %b = udiv <2 x i64> %a, <i64 3, i64 5> 1231 store <2 x i64> %b, ptr %x 1232 ret void 1233} 1234 1235define void @mulhs_v16i8(ptr %x) { 1236; CHECK-LABEL: mulhs_v16i8: 1237; CHECK: # %bb.0: 1238; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1239; CHECK-NEXT: vle8.v v8, (a0) 1240; CHECK-NEXT: li a1, -123 1241; CHECK-NEXT: vmv.v.x v9, a1 1242; CHECK-NEXT: lui a1, 5 1243; CHECK-NEXT: addi a1, a1, -1452 1244; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 1245; CHECK-NEXT: vmv.s.x v0, a1 1246; CHECK-NEXT: li a1, 57 1247; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1248; CHECK-NEXT: vmerge.vxm v9, v9, a1, v0 1249; CHECK-NEXT: vmv.v.i v10, 7 1250; CHECK-NEXT: vmulhu.vv v8, v8, v9 1251; CHECK-NEXT: vmerge.vim v9, v10, 1, v0 1252; CHECK-NEXT: vsrl.vv v8, v8, v9 1253; CHECK-NEXT: vse8.v v8, (a0) 1254; CHECK-NEXT: ret 1255 %a = load <16 x i8>, ptr %x 1256 %b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9> 1257 store <16 x i8> %b, ptr %x 1258 ret void 1259} 1260 1261define void @mulhs_v8i16(ptr %x) { 1262; CHECK-LABEL: mulhs_v8i16: 1263; CHECK: # %bb.0: 1264; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1265; CHECK-NEXT: vle16.v v8, (a0) 1266; CHECK-NEXT: li a1, 105 1267; CHECK-NEXT: vmv.s.x v0, a1 1268; CHECK-NEXT: lui a1, 5 1269; CHECK-NEXT: addi a1, a1, -1755 1270; CHECK-NEXT: vmv.v.x v9, a1 1271; CHECK-NEXT: lui a1, 1048571 1272; CHECK-NEXT: addi a1, a1, 1755 1273; CHECK-NEXT: vmerge.vxm v9, v9, a1, v0 1274; CHECK-NEXT: vmulh.vv v8, v8, v9 1275; CHECK-NEXT: vsra.vi v8, v8, 1 1276; CHECK-NEXT: vsrl.vi v9, v8, 15 1277; CHECK-NEXT: vadd.vv v8, v8, v9 1278; CHECK-NEXT: vse16.v v8, (a0) 1279; CHECK-NEXT: ret 1280 %a = load <8 x i16>, ptr %x 1281 %b = sdiv <8 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7> 1282 store <8 x i16> %b, ptr %x 1283 ret void 1284} 1285 1286define void @mulhs_v6i16(ptr %x) { 1287; CHECK-LABEL: mulhs_v6i16: 1288; CHECK: # %bb.0: 1289; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1290; CHECK-NEXT: vle16.v v8, (a0) 1291; CHECK-NEXT: li a1, 22 1292; CHECK-NEXT: vmv.s.x v0, a1 1293; CHECK-NEXT: vmv.v.i v9, -7 1294; CHECK-NEXT: vmerge.vim v9, v9, 7, v0 1295; CHECK-NEXT: vdiv.vv v8, v8, v9 1296; CHECK-NEXT: vse16.v v8, (a0) 1297; CHECK-NEXT: ret 1298 %a = load <6 x i16>, ptr %x 1299 %b = sdiv <6 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7> 1300 store <6 x i16> %b, ptr %x 1301 ret void 1302} 1303 1304define void @mulhs_v4i32(ptr %x) { 1305; RV32-LABEL: mulhs_v4i32: 1306; RV32: # %bb.0: 1307; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1308; RV32-NEXT: vle32.v v8, (a0) 1309; RV32-NEXT: lui a1, 419430 1310; RV32-NEXT: vmv.v.i v0, 5 1311; RV32-NEXT: addi a1, a1, 1639 1312; RV32-NEXT: vmv.v.x v9, a1 1313; RV32-NEXT: lui a1, 629146 1314; RV32-NEXT: addi a1, a1, -1639 1315; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 1316; RV32-NEXT: vmulh.vv v8, v8, v9 1317; RV32-NEXT: vsrl.vi v9, v8, 31 1318; RV32-NEXT: vsra.vi v8, v8, 1 1319; RV32-NEXT: vadd.vv v8, v8, v9 1320; RV32-NEXT: vse32.v v8, (a0) 1321; RV32-NEXT: ret 1322; 1323; RV64-LABEL: mulhs_v4i32: 1324; RV64: # %bb.0: 1325; RV64-NEXT: lui a1, %hi(.LCPI73_0) 1326; RV64-NEXT: ld a1, %lo(.LCPI73_0)(a1) 1327; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1328; RV64-NEXT: vle32.v v8, (a0) 1329; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1330; RV64-NEXT: vmv.v.x v9, a1 1331; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1332; RV64-NEXT: vmulh.vv v8, v8, v9 1333; RV64-NEXT: vsra.vi v8, v8, 1 1334; RV64-NEXT: vsrl.vi v9, v8, 31 1335; RV64-NEXT: vadd.vv v8, v8, v9 1336; RV64-NEXT: vse32.v v8, (a0) 1337; RV64-NEXT: ret 1338 %a = load <4 x i32>, ptr %x 1339 %b = sdiv <4 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5> 1340 store <4 x i32> %b, ptr %x 1341 ret void 1342} 1343 1344define void @mulhs_v2i64(ptr %x) { 1345; RV32-LABEL: mulhs_v2i64: 1346; RV32: # %bb.0: 1347; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1348; RV32-NEXT: vle64.v v8, (a0) 1349; RV32-NEXT: lui a1, 349525 1350; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1351; RV32-NEXT: vid.v v9 1352; RV32-NEXT: addi a2, a1, 1365 1353; RV32-NEXT: vmv.v.x v10, a2 1354; RV32-NEXT: li a2, 63 1355; RV32-NEXT: addi a1, a1, 1366 1356; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, ma 1357; RV32-NEXT: vmv.s.x v10, a1 1358; RV32-NEXT: lui a1, 16 1359; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma 1360; RV32-NEXT: vsrl.vi v9, v9, 1 1361; RV32-NEXT: vrsub.vi v9, v9, 0 1362; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1363; RV32-NEXT: vmulh.vv v10, v8, v10 1364; RV32-NEXT: vmadd.vv v9, v8, v10 1365; RV32-NEXT: vmv.s.x v8, a1 1366; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1367; RV32-NEXT: vsext.vf4 v10, v8 1368; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1369; RV32-NEXT: vsrl.vx v8, v9, a2 1370; RV32-NEXT: vsra.vv v9, v9, v10 1371; RV32-NEXT: vadd.vv v8, v9, v8 1372; RV32-NEXT: vse64.v v8, (a0) 1373; RV32-NEXT: ret 1374; 1375; RV64-LABEL: mulhs_v2i64: 1376; RV64: # %bb.0: 1377; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1378; RV64-NEXT: vle64.v v8, (a0) 1379; RV64-NEXT: lui a1, 349525 1380; RV64-NEXT: addiw a1, a1, 1365 1381; RV64-NEXT: slli a2, a1, 32 1382; RV64-NEXT: add a1, a1, a2 1383; RV64-NEXT: lui a2, %hi(.LCPI74_0) 1384; RV64-NEXT: vid.v v9 1385; RV64-NEXT: ld a2, %lo(.LCPI74_0)(a2) 1386; RV64-NEXT: vmv.v.x v10, a1 1387; RV64-NEXT: li a1, 63 1388; RV64-NEXT: vrsub.vi v11, v9, 0 1389; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma 1390; RV64-NEXT: vmv.s.x v10, a2 1391; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma 1392; RV64-NEXT: vmulh.vv v10, v8, v10 1393; RV64-NEXT: vmadd.vv v11, v8, v10 1394; RV64-NEXT: vsrl.vx v8, v11, a1 1395; RV64-NEXT: vsra.vv v9, v11, v9 1396; RV64-NEXT: vadd.vv v8, v9, v8 1397; RV64-NEXT: vse64.v v8, (a0) 1398; RV64-NEXT: ret 1399 %a = load <2 x i64>, ptr %x 1400 %b = sdiv <2 x i64> %a, <i64 3, i64 -3> 1401 store <2 x i64> %b, ptr %x 1402 ret void 1403} 1404 1405define void @smin_v16i8(ptr %x, ptr %y) { 1406; CHECK-LABEL: smin_v16i8: 1407; CHECK: # %bb.0: 1408; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1409; CHECK-NEXT: vle8.v v8, (a0) 1410; CHECK-NEXT: vle8.v v9, (a1) 1411; CHECK-NEXT: vmin.vv v8, v8, v9 1412; CHECK-NEXT: vse8.v v8, (a0) 1413; CHECK-NEXT: ret 1414 %a = load <16 x i8>, ptr %x 1415 %b = load <16 x i8>, ptr %y 1416 %cc = icmp slt <16 x i8> %a, %b 1417 %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b 1418 store <16 x i8> %c, ptr %x 1419 ret void 1420} 1421 1422define void @smin_v8i16(ptr %x, ptr %y) { 1423; CHECK-LABEL: smin_v8i16: 1424; CHECK: # %bb.0: 1425; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1426; CHECK-NEXT: vle16.v v8, (a0) 1427; CHECK-NEXT: vle16.v v9, (a1) 1428; CHECK-NEXT: vmin.vv v8, v8, v9 1429; CHECK-NEXT: vse16.v v8, (a0) 1430; CHECK-NEXT: ret 1431 %a = load <8 x i16>, ptr %x 1432 %b = load <8 x i16>, ptr %y 1433 %cc = icmp slt <8 x i16> %a, %b 1434 %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b 1435 store <8 x i16> %c, ptr %x 1436 ret void 1437} 1438 1439define void @smin_v6i16(ptr %x, ptr %y) { 1440; CHECK-LABEL: smin_v6i16: 1441; CHECK: # %bb.0: 1442; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1443; CHECK-NEXT: vle16.v v8, (a0) 1444; CHECK-NEXT: vle16.v v9, (a1) 1445; CHECK-NEXT: vmin.vv v8, v8, v9 1446; CHECK-NEXT: vse16.v v8, (a0) 1447; CHECK-NEXT: ret 1448 %a = load <6 x i16>, ptr %x 1449 %b = load <6 x i16>, ptr %y 1450 %cc = icmp slt <6 x i16> %a, %b 1451 %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b 1452 store <6 x i16> %c, ptr %x 1453 ret void 1454} 1455 1456define void @smin_v4i32(ptr %x, ptr %y) { 1457; CHECK-LABEL: smin_v4i32: 1458; CHECK: # %bb.0: 1459; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1460; CHECK-NEXT: vle32.v v8, (a0) 1461; CHECK-NEXT: vle32.v v9, (a1) 1462; CHECK-NEXT: vmin.vv v8, v8, v9 1463; CHECK-NEXT: vse32.v v8, (a0) 1464; CHECK-NEXT: ret 1465 %a = load <4 x i32>, ptr %x 1466 %b = load <4 x i32>, ptr %y 1467 %cc = icmp slt <4 x i32> %a, %b 1468 %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b 1469 store <4 x i32> %c, ptr %x 1470 ret void 1471} 1472 1473define void @smin_v2i64(ptr %x, ptr %y) { 1474; CHECK-LABEL: smin_v2i64: 1475; CHECK: # %bb.0: 1476; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1477; CHECK-NEXT: vle64.v v8, (a0) 1478; CHECK-NEXT: vle64.v v9, (a1) 1479; CHECK-NEXT: vmin.vv v8, v8, v9 1480; CHECK-NEXT: vse64.v v8, (a0) 1481; CHECK-NEXT: ret 1482 %a = load <2 x i64>, ptr %x 1483 %b = load <2 x i64>, ptr %y 1484 %cc = icmp slt <2 x i64> %a, %b 1485 %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b 1486 store <2 x i64> %c, ptr %x 1487 ret void 1488} 1489 1490define void @smin_vx_v16i8(ptr %x, i8 %y) { 1491; CHECK-LABEL: smin_vx_v16i8: 1492; CHECK: # %bb.0: 1493; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1494; CHECK-NEXT: vle8.v v8, (a0) 1495; CHECK-NEXT: vmin.vx v8, v8, a1 1496; CHECK-NEXT: vse8.v v8, (a0) 1497; CHECK-NEXT: ret 1498 %a = load <16 x i8>, ptr %x 1499 %b = insertelement <16 x i8> poison, i8 %y, i32 0 1500 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 1501 %d = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> %c) 1502 store <16 x i8> %d, ptr %x 1503 ret void 1504} 1505declare <16 x i8> @llvm.smin.v16i8(<16 x i8>, <16 x i8>) 1506 1507define void @smin_vx_v8i16(ptr %x, i16 %y) { 1508; CHECK-LABEL: smin_vx_v8i16: 1509; CHECK: # %bb.0: 1510; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1511; CHECK-NEXT: vle16.v v8, (a0) 1512; CHECK-NEXT: vmin.vx v8, v8, a1 1513; CHECK-NEXT: vse16.v v8, (a0) 1514; CHECK-NEXT: ret 1515 %a = load <8 x i16>, ptr %x 1516 %b = insertelement <8 x i16> poison, i16 %y, i32 0 1517 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 1518 %d = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %a, <8 x i16> %c) 1519 store <8 x i16> %d, ptr %x 1520 ret void 1521} 1522declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>) 1523 1524define void @smin_vx_v6i16(ptr %x, i16 %y) { 1525; CHECK-LABEL: smin_vx_v6i16: 1526; CHECK: # %bb.0: 1527; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1528; CHECK-NEXT: vle16.v v8, (a0) 1529; CHECK-NEXT: vmin.vx v8, v8, a1 1530; CHECK-NEXT: vse16.v v8, (a0) 1531; CHECK-NEXT: ret 1532 %a = load <6 x i16>, ptr %x 1533 %b = insertelement <6 x i16> poison, i16 %y, i32 0 1534 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 1535 %d = call <6 x i16> @llvm.smin.v6i16(<6 x i16> %a, <6 x i16> %c) 1536 store <6 x i16> %d, ptr %x 1537 ret void 1538} 1539declare <6 x i16> @llvm.smin.v6i16(<6 x i16>, <6 x i16>) 1540 1541define void @smin_vx_v4i32(ptr %x, i32 %y) { 1542; CHECK-LABEL: smin_vx_v4i32: 1543; CHECK: # %bb.0: 1544; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1545; CHECK-NEXT: vle32.v v8, (a0) 1546; CHECK-NEXT: vmin.vx v8, v8, a1 1547; CHECK-NEXT: vse32.v v8, (a0) 1548; CHECK-NEXT: ret 1549 %a = load <4 x i32>, ptr %x 1550 %b = insertelement <4 x i32> poison, i32 %y, i32 0 1551 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 1552 %d = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %c) 1553 store <4 x i32> %d, ptr %x 1554 ret void 1555} 1556declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) 1557 1558define void @smin_xv_v16i8(ptr %x, i8 %y) { 1559; CHECK-LABEL: smin_xv_v16i8: 1560; CHECK: # %bb.0: 1561; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1562; CHECK-NEXT: vle8.v v8, (a0) 1563; CHECK-NEXT: vmin.vx v8, v8, a1 1564; CHECK-NEXT: vse8.v v8, (a0) 1565; CHECK-NEXT: ret 1566 %a = load <16 x i8>, ptr %x 1567 %b = insertelement <16 x i8> poison, i8 %y, i32 0 1568 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 1569 %d = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %c, <16 x i8> %a) 1570 store <16 x i8> %d, ptr %x 1571 ret void 1572} 1573 1574define void @smin_xv_v8i16(ptr %x, i16 %y) { 1575; CHECK-LABEL: smin_xv_v8i16: 1576; CHECK: # %bb.0: 1577; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1578; CHECK-NEXT: vle16.v v8, (a0) 1579; CHECK-NEXT: vmin.vx v8, v8, a1 1580; CHECK-NEXT: vse16.v v8, (a0) 1581; CHECK-NEXT: ret 1582 %a = load <8 x i16>, ptr %x 1583 %b = insertelement <8 x i16> poison, i16 %y, i32 0 1584 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 1585 %d = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %c, <8 x i16> %a) 1586 store <8 x i16> %d, ptr %x 1587 ret void 1588} 1589 1590define void @smin_xv_v6i16(ptr %x, i16 %y) { 1591; CHECK-LABEL: smin_xv_v6i16: 1592; CHECK: # %bb.0: 1593; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1594; CHECK-NEXT: vle16.v v8, (a0) 1595; CHECK-NEXT: vmin.vx v8, v8, a1 1596; CHECK-NEXT: vse16.v v8, (a0) 1597; CHECK-NEXT: ret 1598 %a = load <6 x i16>, ptr %x 1599 %b = insertelement <6 x i16> poison, i16 %y, i32 0 1600 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 1601 %d = call <6 x i16> @llvm.smin.v6i16(<6 x i16> %c, <6 x i16> %a) 1602 store <6 x i16> %d, ptr %x 1603 ret void 1604} 1605 1606define void @smin_xv_v4i32(ptr %x, i32 %y) { 1607; CHECK-LABEL: smin_xv_v4i32: 1608; CHECK: # %bb.0: 1609; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1610; CHECK-NEXT: vle32.v v8, (a0) 1611; CHECK-NEXT: vmin.vx v8, v8, a1 1612; CHECK-NEXT: vse32.v v8, (a0) 1613; CHECK-NEXT: ret 1614 %a = load <4 x i32>, ptr %x 1615 %b = insertelement <4 x i32> poison, i32 %y, i32 0 1616 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 1617 %d = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %c, <4 x i32> %a) 1618 store <4 x i32> %d, ptr %x 1619 ret void 1620} 1621 1622define void @smax_v16i8(ptr %x, ptr %y) { 1623; CHECK-LABEL: smax_v16i8: 1624; CHECK: # %bb.0: 1625; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1626; CHECK-NEXT: vle8.v v8, (a0) 1627; CHECK-NEXT: vle8.v v9, (a1) 1628; CHECK-NEXT: vmax.vv v8, v8, v9 1629; CHECK-NEXT: vse8.v v8, (a0) 1630; CHECK-NEXT: ret 1631 %a = load <16 x i8>, ptr %x 1632 %b = load <16 x i8>, ptr %y 1633 %cc = icmp sgt <16 x i8> %a, %b 1634 %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b 1635 store <16 x i8> %c, ptr %x 1636 ret void 1637} 1638 1639define void @smax_v8i16(ptr %x, ptr %y) { 1640; CHECK-LABEL: smax_v8i16: 1641; CHECK: # %bb.0: 1642; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1643; CHECK-NEXT: vle16.v v8, (a0) 1644; CHECK-NEXT: vle16.v v9, (a1) 1645; CHECK-NEXT: vmax.vv v8, v8, v9 1646; CHECK-NEXT: vse16.v v8, (a0) 1647; CHECK-NEXT: ret 1648 %a = load <8 x i16>, ptr %x 1649 %b = load <8 x i16>, ptr %y 1650 %cc = icmp sgt <8 x i16> %a, %b 1651 %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b 1652 store <8 x i16> %c, ptr %x 1653 ret void 1654} 1655 1656define void @smax_v6i16(ptr %x, ptr %y) { 1657; CHECK-LABEL: smax_v6i16: 1658; CHECK: # %bb.0: 1659; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1660; CHECK-NEXT: vle16.v v8, (a0) 1661; CHECK-NEXT: vle16.v v9, (a1) 1662; CHECK-NEXT: vmax.vv v8, v8, v9 1663; CHECK-NEXT: vse16.v v8, (a0) 1664; CHECK-NEXT: ret 1665 %a = load <6 x i16>, ptr %x 1666 %b = load <6 x i16>, ptr %y 1667 %cc = icmp sgt <6 x i16> %a, %b 1668 %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b 1669 store <6 x i16> %c, ptr %x 1670 ret void 1671} 1672 1673define void @smax_v4i32(ptr %x, ptr %y) { 1674; CHECK-LABEL: smax_v4i32: 1675; CHECK: # %bb.0: 1676; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1677; CHECK-NEXT: vle32.v v8, (a0) 1678; CHECK-NEXT: vle32.v v9, (a1) 1679; CHECK-NEXT: vmax.vv v8, v8, v9 1680; CHECK-NEXT: vse32.v v8, (a0) 1681; CHECK-NEXT: ret 1682 %a = load <4 x i32>, ptr %x 1683 %b = load <4 x i32>, ptr %y 1684 %cc = icmp sgt <4 x i32> %a, %b 1685 %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b 1686 store <4 x i32> %c, ptr %x 1687 ret void 1688} 1689 1690define void @smax_v2i64(ptr %x, ptr %y) { 1691; CHECK-LABEL: smax_v2i64: 1692; CHECK: # %bb.0: 1693; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1694; CHECK-NEXT: vle64.v v8, (a0) 1695; CHECK-NEXT: vle64.v v9, (a1) 1696; CHECK-NEXT: vmax.vv v8, v8, v9 1697; CHECK-NEXT: vse64.v v8, (a0) 1698; CHECK-NEXT: ret 1699 %a = load <2 x i64>, ptr %x 1700 %b = load <2 x i64>, ptr %y 1701 %cc = icmp sgt <2 x i64> %a, %b 1702 %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b 1703 store <2 x i64> %c, ptr %x 1704 ret void 1705} 1706 1707define void @smax_vx_v16i8(ptr %x, i8 %y) { 1708; CHECK-LABEL: smax_vx_v16i8: 1709; CHECK: # %bb.0: 1710; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1711; CHECK-NEXT: vle8.v v8, (a0) 1712; CHECK-NEXT: vmax.vx v8, v8, a1 1713; CHECK-NEXT: vse8.v v8, (a0) 1714; CHECK-NEXT: ret 1715 %a = load <16 x i8>, ptr %x 1716 %b = insertelement <16 x i8> poison, i8 %y, i32 0 1717 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 1718 %d = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %a, <16 x i8> %c) 1719 store <16 x i8> %d, ptr %x 1720 ret void 1721} 1722declare <16 x i8> @llvm.smax.v16i8(<16 x i8>, <16 x i8>) 1723 1724define void @smax_vx_v8i16(ptr %x, i16 %y) { 1725; CHECK-LABEL: smax_vx_v8i16: 1726; CHECK: # %bb.0: 1727; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1728; CHECK-NEXT: vle16.v v8, (a0) 1729; CHECK-NEXT: vmax.vx v8, v8, a1 1730; CHECK-NEXT: vse16.v v8, (a0) 1731; CHECK-NEXT: ret 1732 %a = load <8 x i16>, ptr %x 1733 %b = insertelement <8 x i16> poison, i16 %y, i32 0 1734 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 1735 %d = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %c) 1736 store <8 x i16> %d, ptr %x 1737 ret void 1738} 1739declare <8 x i16> @llvm.smax.v8i16(<8 x i16>, <8 x i16>) 1740 1741define void @smax_vx_v6i16(ptr %x, i16 %y) { 1742; CHECK-LABEL: smax_vx_v6i16: 1743; CHECK: # %bb.0: 1744; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1745; CHECK-NEXT: vle16.v v8, (a0) 1746; CHECK-NEXT: vmax.vx v8, v8, a1 1747; CHECK-NEXT: vse16.v v8, (a0) 1748; CHECK-NEXT: ret 1749 %a = load <6 x i16>, ptr %x 1750 %b = insertelement <6 x i16> poison, i16 %y, i32 0 1751 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 1752 %d = call <6 x i16> @llvm.smax.v6i16(<6 x i16> %a, <6 x i16> %c) 1753 store <6 x i16> %d, ptr %x 1754 ret void 1755} 1756declare <6 x i16> @llvm.smax.v6i16(<6 x i16>, <6 x i16>) 1757 1758define void @smax_vx_v4i32(ptr %x, i32 %y) { 1759; CHECK-LABEL: smax_vx_v4i32: 1760; CHECK: # %bb.0: 1761; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1762; CHECK-NEXT: vle32.v v8, (a0) 1763; CHECK-NEXT: vmax.vx v8, v8, a1 1764; CHECK-NEXT: vse32.v v8, (a0) 1765; CHECK-NEXT: ret 1766 %a = load <4 x i32>, ptr %x 1767 %b = insertelement <4 x i32> poison, i32 %y, i32 0 1768 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 1769 %d = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %c) 1770 store <4 x i32> %d, ptr %x 1771 ret void 1772} 1773declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) 1774 1775define void @smax_xv_v16i8(ptr %x, i8 %y) { 1776; CHECK-LABEL: smax_xv_v16i8: 1777; CHECK: # %bb.0: 1778; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1779; CHECK-NEXT: vle8.v v8, (a0) 1780; CHECK-NEXT: vmax.vx v8, v8, a1 1781; CHECK-NEXT: vse8.v v8, (a0) 1782; CHECK-NEXT: ret 1783 %a = load <16 x i8>, ptr %x 1784 %b = insertelement <16 x i8> poison, i8 %y, i32 0 1785 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 1786 %d = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %c, <16 x i8> %a) 1787 store <16 x i8> %d, ptr %x 1788 ret void 1789} 1790 1791define void @smax_xv_v8i16(ptr %x, i16 %y) { 1792; CHECK-LABEL: smax_xv_v8i16: 1793; CHECK: # %bb.0: 1794; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1795; CHECK-NEXT: vle16.v v8, (a0) 1796; CHECK-NEXT: vmax.vx v8, v8, a1 1797; CHECK-NEXT: vse16.v v8, (a0) 1798; CHECK-NEXT: ret 1799 %a = load <8 x i16>, ptr %x 1800 %b = insertelement <8 x i16> poison, i16 %y, i32 0 1801 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 1802 %d = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %c, <8 x i16> %a) 1803 store <8 x i16> %d, ptr %x 1804 ret void 1805} 1806 1807define void @smax_xv_v6i16(ptr %x, i16 %y) { 1808; CHECK-LABEL: smax_xv_v6i16: 1809; CHECK: # %bb.0: 1810; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1811; CHECK-NEXT: vle16.v v8, (a0) 1812; CHECK-NEXT: vmax.vx v8, v8, a1 1813; CHECK-NEXT: vse16.v v8, (a0) 1814; CHECK-NEXT: ret 1815 %a = load <6 x i16>, ptr %x 1816 %b = insertelement <6 x i16> poison, i16 %y, i32 0 1817 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 1818 %d = call <6 x i16> @llvm.smax.v6i16(<6 x i16> %c, <6 x i16> %a) 1819 store <6 x i16> %d, ptr %x 1820 ret void 1821} 1822 1823define void @smax_xv_v4i32(ptr %x, i32 %y) { 1824; CHECK-LABEL: smax_xv_v4i32: 1825; CHECK: # %bb.0: 1826; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1827; CHECK-NEXT: vle32.v v8, (a0) 1828; CHECK-NEXT: vmax.vx v8, v8, a1 1829; CHECK-NEXT: vse32.v v8, (a0) 1830; CHECK-NEXT: ret 1831 %a = load <4 x i32>, ptr %x 1832 %b = insertelement <4 x i32> poison, i32 %y, i32 0 1833 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 1834 %d = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %c, <4 x i32> %a) 1835 store <4 x i32> %d, ptr %x 1836 ret void 1837} 1838 1839define void @umin_v16i8(ptr %x, ptr %y) { 1840; CHECK-LABEL: umin_v16i8: 1841; CHECK: # %bb.0: 1842; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1843; CHECK-NEXT: vle8.v v8, (a0) 1844; CHECK-NEXT: vle8.v v9, (a1) 1845; CHECK-NEXT: vminu.vv v8, v8, v9 1846; CHECK-NEXT: vse8.v v8, (a0) 1847; CHECK-NEXT: ret 1848 %a = load <16 x i8>, ptr %x 1849 %b = load <16 x i8>, ptr %y 1850 %cc = icmp ult <16 x i8> %a, %b 1851 %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b 1852 store <16 x i8> %c, ptr %x 1853 ret void 1854} 1855 1856define void @umin_v8i16(ptr %x, ptr %y) { 1857; CHECK-LABEL: umin_v8i16: 1858; CHECK: # %bb.0: 1859; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1860; CHECK-NEXT: vle16.v v8, (a0) 1861; CHECK-NEXT: vle16.v v9, (a1) 1862; CHECK-NEXT: vminu.vv v8, v8, v9 1863; CHECK-NEXT: vse16.v v8, (a0) 1864; CHECK-NEXT: ret 1865 %a = load <8 x i16>, ptr %x 1866 %b = load <8 x i16>, ptr %y 1867 %cc = icmp ult <8 x i16> %a, %b 1868 %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b 1869 store <8 x i16> %c, ptr %x 1870 ret void 1871} 1872 1873define void @umin_v6i16(ptr %x, ptr %y) { 1874; CHECK-LABEL: umin_v6i16: 1875; CHECK: # %bb.0: 1876; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1877; CHECK-NEXT: vle16.v v8, (a0) 1878; CHECK-NEXT: vle16.v v9, (a1) 1879; CHECK-NEXT: vminu.vv v8, v8, v9 1880; CHECK-NEXT: vse16.v v8, (a0) 1881; CHECK-NEXT: ret 1882 %a = load <6 x i16>, ptr %x 1883 %b = load <6 x i16>, ptr %y 1884 %cc = icmp ult <6 x i16> %a, %b 1885 %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b 1886 store <6 x i16> %c, ptr %x 1887 ret void 1888} 1889 1890define void @umin_v4i32(ptr %x, ptr %y) { 1891; CHECK-LABEL: umin_v4i32: 1892; CHECK: # %bb.0: 1893; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1894; CHECK-NEXT: vle32.v v8, (a0) 1895; CHECK-NEXT: vle32.v v9, (a1) 1896; CHECK-NEXT: vminu.vv v8, v8, v9 1897; CHECK-NEXT: vse32.v v8, (a0) 1898; CHECK-NEXT: ret 1899 %a = load <4 x i32>, ptr %x 1900 %b = load <4 x i32>, ptr %y 1901 %cc = icmp ult <4 x i32> %a, %b 1902 %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b 1903 store <4 x i32> %c, ptr %x 1904 ret void 1905} 1906 1907define void @umin_v2i64(ptr %x, ptr %y) { 1908; CHECK-LABEL: umin_v2i64: 1909; CHECK: # %bb.0: 1910; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1911; CHECK-NEXT: vle64.v v8, (a0) 1912; CHECK-NEXT: vle64.v v9, (a1) 1913; CHECK-NEXT: vminu.vv v8, v8, v9 1914; CHECK-NEXT: vse64.v v8, (a0) 1915; CHECK-NEXT: ret 1916 %a = load <2 x i64>, ptr %x 1917 %b = load <2 x i64>, ptr %y 1918 %cc = icmp ult <2 x i64> %a, %b 1919 %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b 1920 store <2 x i64> %c, ptr %x 1921 ret void 1922} 1923 1924define void @umin_vx_v16i8(ptr %x, i8 %y) { 1925; CHECK-LABEL: umin_vx_v16i8: 1926; CHECK: # %bb.0: 1927; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1928; CHECK-NEXT: vle8.v v8, (a0) 1929; CHECK-NEXT: vminu.vx v8, v8, a1 1930; CHECK-NEXT: vse8.v v8, (a0) 1931; CHECK-NEXT: ret 1932 %a = load <16 x i8>, ptr %x 1933 %b = insertelement <16 x i8> poison, i8 %y, i32 0 1934 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 1935 %d = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %c) 1936 store <16 x i8> %d, ptr %x 1937 ret void 1938} 1939declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>) 1940 1941define void @umin_vx_v8i16(ptr %x, i16 %y) { 1942; CHECK-LABEL: umin_vx_v8i16: 1943; CHECK: # %bb.0: 1944; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 1945; CHECK-NEXT: vle16.v v8, (a0) 1946; CHECK-NEXT: vminu.vx v8, v8, a1 1947; CHECK-NEXT: vse16.v v8, (a0) 1948; CHECK-NEXT: ret 1949 %a = load <8 x i16>, ptr %x 1950 %b = insertelement <8 x i16> poison, i16 %y, i32 0 1951 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 1952 %d = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %c) 1953 store <8 x i16> %d, ptr %x 1954 ret void 1955} 1956declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>) 1957 1958define void @umin_vx_v6i16(ptr %x, i16 %y) { 1959; CHECK-LABEL: umin_vx_v6i16: 1960; CHECK: # %bb.0: 1961; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 1962; CHECK-NEXT: vle16.v v8, (a0) 1963; CHECK-NEXT: vminu.vx v8, v8, a1 1964; CHECK-NEXT: vse16.v v8, (a0) 1965; CHECK-NEXT: ret 1966 %a = load <6 x i16>, ptr %x 1967 %b = insertelement <6 x i16> poison, i16 %y, i32 0 1968 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 1969 %d = call <6 x i16> @llvm.umin.v6i16(<6 x i16> %a, <6 x i16> %c) 1970 store <6 x i16> %d, ptr %x 1971 ret void 1972} 1973declare <6 x i16> @llvm.umin.v6i16(<6 x i16>, <6 x i16>) 1974 1975define void @umin_vx_v4i32(ptr %x, i32 %y) { 1976; CHECK-LABEL: umin_vx_v4i32: 1977; CHECK: # %bb.0: 1978; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1979; CHECK-NEXT: vle32.v v8, (a0) 1980; CHECK-NEXT: vminu.vx v8, v8, a1 1981; CHECK-NEXT: vse32.v v8, (a0) 1982; CHECK-NEXT: ret 1983 %a = load <4 x i32>, ptr %x 1984 %b = insertelement <4 x i32> poison, i32 %y, i32 0 1985 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 1986 %d = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %c) 1987 store <4 x i32> %d, ptr %x 1988 ret void 1989} 1990declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>) 1991 1992define void @umin_xv_v16i8(ptr %x, i8 %y) { 1993; CHECK-LABEL: umin_xv_v16i8: 1994; CHECK: # %bb.0: 1995; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 1996; CHECK-NEXT: vle8.v v8, (a0) 1997; CHECK-NEXT: vminu.vx v8, v8, a1 1998; CHECK-NEXT: vse8.v v8, (a0) 1999; CHECK-NEXT: ret 2000 %a = load <16 x i8>, ptr %x 2001 %b = insertelement <16 x i8> poison, i8 %y, i32 0 2002 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 2003 %d = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %c, <16 x i8> %a) 2004 store <16 x i8> %d, ptr %x 2005 ret void 2006} 2007 2008define void @umin_xv_v8i16(ptr %x, i16 %y) { 2009; CHECK-LABEL: umin_xv_v8i16: 2010; CHECK: # %bb.0: 2011; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 2012; CHECK-NEXT: vle16.v v8, (a0) 2013; CHECK-NEXT: vminu.vx v8, v8, a1 2014; CHECK-NEXT: vse16.v v8, (a0) 2015; CHECK-NEXT: ret 2016 %a = load <8 x i16>, ptr %x 2017 %b = insertelement <8 x i16> poison, i16 %y, i32 0 2018 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 2019 %d = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %c, <8 x i16> %a) 2020 store <8 x i16> %d, ptr %x 2021 ret void 2022} 2023 2024define void @umin_xv_v6i16(ptr %x, i16 %y) { 2025; CHECK-LABEL: umin_xv_v6i16: 2026; CHECK: # %bb.0: 2027; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 2028; CHECK-NEXT: vle16.v v8, (a0) 2029; CHECK-NEXT: vminu.vx v8, v8, a1 2030; CHECK-NEXT: vse16.v v8, (a0) 2031; CHECK-NEXT: ret 2032 %a = load <6 x i16>, ptr %x 2033 %b = insertelement <6 x i16> poison, i16 %y, i32 0 2034 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 2035 %d = call <6 x i16> @llvm.umin.v6i16(<6 x i16> %c, <6 x i16> %a) 2036 store <6 x i16> %d, ptr %x 2037 ret void 2038} 2039 2040define void @umin_xv_v4i32(ptr %x, i32 %y) { 2041; CHECK-LABEL: umin_xv_v4i32: 2042; CHECK: # %bb.0: 2043; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2044; CHECK-NEXT: vle32.v v8, (a0) 2045; CHECK-NEXT: vminu.vx v8, v8, a1 2046; CHECK-NEXT: vse32.v v8, (a0) 2047; CHECK-NEXT: ret 2048 %a = load <4 x i32>, ptr %x 2049 %b = insertelement <4 x i32> poison, i32 %y, i32 0 2050 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 2051 %d = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %c, <4 x i32> %a) 2052 store <4 x i32> %d, ptr %x 2053 ret void 2054} 2055 2056define void @umax_v16i8(ptr %x, ptr %y) { 2057; CHECK-LABEL: umax_v16i8: 2058; CHECK: # %bb.0: 2059; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2060; CHECK-NEXT: vle8.v v8, (a0) 2061; CHECK-NEXT: vle8.v v9, (a1) 2062; CHECK-NEXT: vmaxu.vv v8, v8, v9 2063; CHECK-NEXT: vse8.v v8, (a0) 2064; CHECK-NEXT: ret 2065 %a = load <16 x i8>, ptr %x 2066 %b = load <16 x i8>, ptr %y 2067 %cc = icmp ugt <16 x i8> %a, %b 2068 %c = select <16 x i1> %cc, <16 x i8> %a, <16 x i8> %b 2069 store <16 x i8> %c, ptr %x 2070 ret void 2071} 2072 2073define void @umax_v8i16(ptr %x, ptr %y) { 2074; CHECK-LABEL: umax_v8i16: 2075; CHECK: # %bb.0: 2076; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 2077; CHECK-NEXT: vle16.v v8, (a0) 2078; CHECK-NEXT: vle16.v v9, (a1) 2079; CHECK-NEXT: vmaxu.vv v8, v8, v9 2080; CHECK-NEXT: vse16.v v8, (a0) 2081; CHECK-NEXT: ret 2082 %a = load <8 x i16>, ptr %x 2083 %b = load <8 x i16>, ptr %y 2084 %cc = icmp ugt <8 x i16> %a, %b 2085 %c = select <8 x i1> %cc, <8 x i16> %a, <8 x i16> %b 2086 store <8 x i16> %c, ptr %x 2087 ret void 2088} 2089 2090define void @umax_v6i16(ptr %x, ptr %y) { 2091; CHECK-LABEL: umax_v6i16: 2092; CHECK: # %bb.0: 2093; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 2094; CHECK-NEXT: vle16.v v8, (a0) 2095; CHECK-NEXT: vle16.v v9, (a1) 2096; CHECK-NEXT: vmaxu.vv v8, v8, v9 2097; CHECK-NEXT: vse16.v v8, (a0) 2098; CHECK-NEXT: ret 2099 %a = load <6 x i16>, ptr %x 2100 %b = load <6 x i16>, ptr %y 2101 %cc = icmp ugt <6 x i16> %a, %b 2102 %c = select <6 x i1> %cc, <6 x i16> %a, <6 x i16> %b 2103 store <6 x i16> %c, ptr %x 2104 ret void 2105} 2106 2107define void @umax_v4i32(ptr %x, ptr %y) { 2108; CHECK-LABEL: umax_v4i32: 2109; CHECK: # %bb.0: 2110; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2111; CHECK-NEXT: vle32.v v8, (a0) 2112; CHECK-NEXT: vle32.v v9, (a1) 2113; CHECK-NEXT: vmaxu.vv v8, v8, v9 2114; CHECK-NEXT: vse32.v v8, (a0) 2115; CHECK-NEXT: ret 2116 %a = load <4 x i32>, ptr %x 2117 %b = load <4 x i32>, ptr %y 2118 %cc = icmp ugt <4 x i32> %a, %b 2119 %c = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b 2120 store <4 x i32> %c, ptr %x 2121 ret void 2122} 2123 2124define void @umax_v2i64(ptr %x, ptr %y) { 2125; CHECK-LABEL: umax_v2i64: 2126; CHECK: # %bb.0: 2127; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2128; CHECK-NEXT: vle64.v v8, (a0) 2129; CHECK-NEXT: vle64.v v9, (a1) 2130; CHECK-NEXT: vmaxu.vv v8, v8, v9 2131; CHECK-NEXT: vse64.v v8, (a0) 2132; CHECK-NEXT: ret 2133 %a = load <2 x i64>, ptr %x 2134 %b = load <2 x i64>, ptr %y 2135 %cc = icmp ugt <2 x i64> %a, %b 2136 %c = select <2 x i1> %cc, <2 x i64> %a, <2 x i64> %b 2137 store <2 x i64> %c, ptr %x 2138 ret void 2139} 2140 2141define void @umax_vx_v16i8(ptr %x, i8 %y) { 2142; CHECK-LABEL: umax_vx_v16i8: 2143; CHECK: # %bb.0: 2144; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2145; CHECK-NEXT: vle8.v v8, (a0) 2146; CHECK-NEXT: vmaxu.vx v8, v8, a1 2147; CHECK-NEXT: vse8.v v8, (a0) 2148; CHECK-NEXT: ret 2149 %a = load <16 x i8>, ptr %x 2150 %b = insertelement <16 x i8> poison, i8 %y, i32 0 2151 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 2152 %d = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> %c) 2153 store <16 x i8> %d, ptr %x 2154 ret void 2155} 2156declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>) 2157 2158define void @umax_vx_v8i16(ptr %x, i16 %y) { 2159; CHECK-LABEL: umax_vx_v8i16: 2160; CHECK: # %bb.0: 2161; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 2162; CHECK-NEXT: vle16.v v8, (a0) 2163; CHECK-NEXT: vmaxu.vx v8, v8, a1 2164; CHECK-NEXT: vse16.v v8, (a0) 2165; CHECK-NEXT: ret 2166 %a = load <8 x i16>, ptr %x 2167 %b = insertelement <8 x i16> poison, i16 %y, i32 0 2168 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 2169 %d = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %c) 2170 store <8 x i16> %d, ptr %x 2171 ret void 2172} 2173declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>) 2174 2175define void @umax_vx_v6i16(ptr %x, i16 %y) { 2176; CHECK-LABEL: umax_vx_v6i16: 2177; CHECK: # %bb.0: 2178; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 2179; CHECK-NEXT: vle16.v v8, (a0) 2180; CHECK-NEXT: vmaxu.vx v8, v8, a1 2181; CHECK-NEXT: vse16.v v8, (a0) 2182; CHECK-NEXT: ret 2183 %a = load <6 x i16>, ptr %x 2184 %b = insertelement <6 x i16> poison, i16 %y, i32 0 2185 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 2186 %d = call <6 x i16> @llvm.umax.v6i16(<6 x i16> %a, <6 x i16> %c) 2187 store <6 x i16> %d, ptr %x 2188 ret void 2189} 2190declare <6 x i16> @llvm.umax.v6i16(<6 x i16>, <6 x i16>) 2191 2192define void @umax_vx_v4i32(ptr %x, i32 %y) { 2193; CHECK-LABEL: umax_vx_v4i32: 2194; CHECK: # %bb.0: 2195; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2196; CHECK-NEXT: vle32.v v8, (a0) 2197; CHECK-NEXT: vmaxu.vx v8, v8, a1 2198; CHECK-NEXT: vse32.v v8, (a0) 2199; CHECK-NEXT: ret 2200 %a = load <4 x i32>, ptr %x 2201 %b = insertelement <4 x i32> poison, i32 %y, i32 0 2202 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 2203 %d = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %c) 2204 store <4 x i32> %d, ptr %x 2205 ret void 2206} 2207declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) 2208 2209define void @umax_xv_v16i8(ptr %x, i8 %y) { 2210; CHECK-LABEL: umax_xv_v16i8: 2211; CHECK: # %bb.0: 2212; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2213; CHECK-NEXT: vle8.v v8, (a0) 2214; CHECK-NEXT: vmaxu.vx v8, v8, a1 2215; CHECK-NEXT: vse8.v v8, (a0) 2216; CHECK-NEXT: ret 2217 %a = load <16 x i8>, ptr %x 2218 %b = insertelement <16 x i8> poison, i8 %y, i32 0 2219 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 2220 %d = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %c, <16 x i8> %a) 2221 store <16 x i8> %d, ptr %x 2222 ret void 2223} 2224 2225define void @umax_xv_v8i16(ptr %x, i16 %y) { 2226; CHECK-LABEL: umax_xv_v8i16: 2227; CHECK: # %bb.0: 2228; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 2229; CHECK-NEXT: vle16.v v8, (a0) 2230; CHECK-NEXT: vmaxu.vx v8, v8, a1 2231; CHECK-NEXT: vse16.v v8, (a0) 2232; CHECK-NEXT: ret 2233 %a = load <8 x i16>, ptr %x 2234 %b = insertelement <8 x i16> poison, i16 %y, i32 0 2235 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 2236 %d = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %c, <8 x i16> %a) 2237 store <8 x i16> %d, ptr %x 2238 ret void 2239} 2240 2241define void @umax_xv_v6i16(ptr %x, i16 %y) { 2242; CHECK-LABEL: umax_xv_v6i16: 2243; CHECK: # %bb.0: 2244; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma 2245; CHECK-NEXT: vle16.v v8, (a0) 2246; CHECK-NEXT: vmaxu.vx v8, v8, a1 2247; CHECK-NEXT: vse16.v v8, (a0) 2248; CHECK-NEXT: ret 2249 %a = load <6 x i16>, ptr %x 2250 %b = insertelement <6 x i16> poison, i16 %y, i32 0 2251 %c = shufflevector <6 x i16> %b, <6 x i16> poison, <6 x i32> zeroinitializer 2252 %d = call <6 x i16> @llvm.umax.v6i16(<6 x i16> %c, <6 x i16> %a) 2253 store <6 x i16> %d, ptr %x 2254 ret void 2255} 2256 2257define void @umax_xv_v4i32(ptr %x, i32 %y) { 2258; CHECK-LABEL: umax_xv_v4i32: 2259; CHECK: # %bb.0: 2260; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2261; CHECK-NEXT: vle32.v v8, (a0) 2262; CHECK-NEXT: vmaxu.vx v8, v8, a1 2263; CHECK-NEXT: vse32.v v8, (a0) 2264; CHECK-NEXT: ret 2265 %a = load <4 x i32>, ptr %x 2266 %b = insertelement <4 x i32> poison, i32 %y, i32 0 2267 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 2268 %d = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %c, <4 x i32> %a) 2269 store <4 x i32> %d, ptr %x 2270 ret void 2271} 2272 2273define void @add_v32i8(ptr %x, ptr %y) { 2274; CHECK-LABEL: add_v32i8: 2275; CHECK: # %bb.0: 2276; CHECK-NEXT: li a2, 32 2277; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2278; CHECK-NEXT: vle8.v v8, (a0) 2279; CHECK-NEXT: vle8.v v10, (a1) 2280; CHECK-NEXT: vadd.vv v8, v8, v10 2281; CHECK-NEXT: vse8.v v8, (a0) 2282; CHECK-NEXT: ret 2283 %a = load <32 x i8>, ptr %x 2284 %b = load <32 x i8>, ptr %y 2285 %c = add <32 x i8> %a, %b 2286 store <32 x i8> %c, ptr %x 2287 ret void 2288} 2289 2290define void @add_v16i16(ptr %x, ptr %y) { 2291; CHECK-LABEL: add_v16i16: 2292; CHECK: # %bb.0: 2293; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2294; CHECK-NEXT: vle16.v v8, (a0) 2295; CHECK-NEXT: vle16.v v10, (a1) 2296; CHECK-NEXT: vadd.vv v8, v8, v10 2297; CHECK-NEXT: vse16.v v8, (a0) 2298; CHECK-NEXT: ret 2299 %a = load <16 x i16>, ptr %x 2300 %b = load <16 x i16>, ptr %y 2301 %c = add <16 x i16> %a, %b 2302 store <16 x i16> %c, ptr %x 2303 ret void 2304} 2305 2306define void @add_v8i32(ptr %x, ptr %y) { 2307; CHECK-LABEL: add_v8i32: 2308; CHECK: # %bb.0: 2309; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2310; CHECK-NEXT: vle32.v v8, (a0) 2311; CHECK-NEXT: vle32.v v10, (a1) 2312; CHECK-NEXT: vadd.vv v8, v8, v10 2313; CHECK-NEXT: vse32.v v8, (a0) 2314; CHECK-NEXT: ret 2315 %a = load <8 x i32>, ptr %x 2316 %b = load <8 x i32>, ptr %y 2317 %c = add <8 x i32> %a, %b 2318 store <8 x i32> %c, ptr %x 2319 ret void 2320} 2321 2322define void @add_v6i32(ptr %x, ptr %y) { 2323; CHECK-LABEL: add_v6i32: 2324; CHECK: # %bb.0: 2325; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma 2326; CHECK-NEXT: vle32.v v8, (a0) 2327; CHECK-NEXT: vle32.v v10, (a1) 2328; CHECK-NEXT: vadd.vv v8, v8, v10 2329; CHECK-NEXT: vse32.v v8, (a0) 2330; CHECK-NEXT: ret 2331 %a = load <6 x i32>, ptr %x 2332 %b = load <6 x i32>, ptr %y 2333 %c = add <6 x i32> %a, %b 2334 store <6 x i32> %c, ptr %x 2335 ret void 2336} 2337 2338define void @add_v4i64(ptr %x, ptr %y) { 2339; CHECK-LABEL: add_v4i64: 2340; CHECK: # %bb.0: 2341; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2342; CHECK-NEXT: vle64.v v8, (a0) 2343; CHECK-NEXT: vle64.v v10, (a1) 2344; CHECK-NEXT: vadd.vv v8, v8, v10 2345; CHECK-NEXT: vse64.v v8, (a0) 2346; CHECK-NEXT: ret 2347 %a = load <4 x i64>, ptr %x 2348 %b = load <4 x i64>, ptr %y 2349 %c = add <4 x i64> %a, %b 2350 store <4 x i64> %c, ptr %x 2351 ret void 2352} 2353 2354define void @sub_v32i8(ptr %x, ptr %y) { 2355; CHECK-LABEL: sub_v32i8: 2356; CHECK: # %bb.0: 2357; CHECK-NEXT: li a2, 32 2358; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2359; CHECK-NEXT: vle8.v v8, (a0) 2360; CHECK-NEXT: vle8.v v10, (a1) 2361; CHECK-NEXT: vsub.vv v8, v8, v10 2362; CHECK-NEXT: vse8.v v8, (a0) 2363; CHECK-NEXT: ret 2364 %a = load <32 x i8>, ptr %x 2365 %b = load <32 x i8>, ptr %y 2366 %c = sub <32 x i8> %a, %b 2367 store <32 x i8> %c, ptr %x 2368 ret void 2369} 2370 2371define void @sub_v16i16(ptr %x, ptr %y) { 2372; CHECK-LABEL: sub_v16i16: 2373; CHECK: # %bb.0: 2374; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2375; CHECK-NEXT: vle16.v v8, (a0) 2376; CHECK-NEXT: vle16.v v10, (a1) 2377; CHECK-NEXT: vsub.vv v8, v8, v10 2378; CHECK-NEXT: vse16.v v8, (a0) 2379; CHECK-NEXT: ret 2380 %a = load <16 x i16>, ptr %x 2381 %b = load <16 x i16>, ptr %y 2382 %c = sub <16 x i16> %a, %b 2383 store <16 x i16> %c, ptr %x 2384 ret void 2385} 2386 2387define void @sub_v8i32(ptr %x, ptr %y) { 2388; CHECK-LABEL: sub_v8i32: 2389; CHECK: # %bb.0: 2390; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2391; CHECK-NEXT: vle32.v v8, (a0) 2392; CHECK-NEXT: vle32.v v10, (a1) 2393; CHECK-NEXT: vsub.vv v8, v8, v10 2394; CHECK-NEXT: vse32.v v8, (a0) 2395; CHECK-NEXT: ret 2396 %a = load <8 x i32>, ptr %x 2397 %b = load <8 x i32>, ptr %y 2398 %c = sub <8 x i32> %a, %b 2399 store <8 x i32> %c, ptr %x 2400 ret void 2401} 2402 2403define void @sub_v4i64(ptr %x, ptr %y) { 2404; CHECK-LABEL: sub_v4i64: 2405; CHECK: # %bb.0: 2406; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2407; CHECK-NEXT: vle64.v v8, (a0) 2408; CHECK-NEXT: vle64.v v10, (a1) 2409; CHECK-NEXT: vsub.vv v8, v8, v10 2410; CHECK-NEXT: vse64.v v8, (a0) 2411; CHECK-NEXT: ret 2412 %a = load <4 x i64>, ptr %x 2413 %b = load <4 x i64>, ptr %y 2414 %c = sub <4 x i64> %a, %b 2415 store <4 x i64> %c, ptr %x 2416 ret void 2417} 2418 2419define void @mul_v32i8(ptr %x, ptr %y) { 2420; CHECK-LABEL: mul_v32i8: 2421; CHECK: # %bb.0: 2422; CHECK-NEXT: li a2, 32 2423; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2424; CHECK-NEXT: vle8.v v8, (a0) 2425; CHECK-NEXT: vle8.v v10, (a1) 2426; CHECK-NEXT: vmul.vv v8, v8, v10 2427; CHECK-NEXT: vse8.v v8, (a0) 2428; CHECK-NEXT: ret 2429 %a = load <32 x i8>, ptr %x 2430 %b = load <32 x i8>, ptr %y 2431 %c = mul <32 x i8> %a, %b 2432 store <32 x i8> %c, ptr %x 2433 ret void 2434} 2435 2436define void @mul_v16i16(ptr %x, ptr %y) { 2437; CHECK-LABEL: mul_v16i16: 2438; CHECK: # %bb.0: 2439; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2440; CHECK-NEXT: vle16.v v8, (a0) 2441; CHECK-NEXT: vle16.v v10, (a1) 2442; CHECK-NEXT: vmul.vv v8, v8, v10 2443; CHECK-NEXT: vse16.v v8, (a0) 2444; CHECK-NEXT: ret 2445 %a = load <16 x i16>, ptr %x 2446 %b = load <16 x i16>, ptr %y 2447 %c = mul <16 x i16> %a, %b 2448 store <16 x i16> %c, ptr %x 2449 ret void 2450} 2451 2452define void @mul_v8i32(ptr %x, ptr %y) { 2453; CHECK-LABEL: mul_v8i32: 2454; CHECK: # %bb.0: 2455; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2456; CHECK-NEXT: vle32.v v8, (a0) 2457; CHECK-NEXT: vle32.v v10, (a1) 2458; CHECK-NEXT: vmul.vv v8, v8, v10 2459; CHECK-NEXT: vse32.v v8, (a0) 2460; CHECK-NEXT: ret 2461 %a = load <8 x i32>, ptr %x 2462 %b = load <8 x i32>, ptr %y 2463 %c = mul <8 x i32> %a, %b 2464 store <8 x i32> %c, ptr %x 2465 ret void 2466} 2467 2468define void @mul_v4i64(ptr %x, ptr %y) { 2469; CHECK-LABEL: mul_v4i64: 2470; CHECK: # %bb.0: 2471; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2472; CHECK-NEXT: vle64.v v8, (a0) 2473; CHECK-NEXT: vle64.v v10, (a1) 2474; CHECK-NEXT: vmul.vv v8, v8, v10 2475; CHECK-NEXT: vse64.v v8, (a0) 2476; CHECK-NEXT: ret 2477 %a = load <4 x i64>, ptr %x 2478 %b = load <4 x i64>, ptr %y 2479 %c = mul <4 x i64> %a, %b 2480 store <4 x i64> %c, ptr %x 2481 ret void 2482} 2483 2484define void @and_v32i8(ptr %x, ptr %y) { 2485; CHECK-LABEL: and_v32i8: 2486; CHECK: # %bb.0: 2487; CHECK-NEXT: li a2, 32 2488; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2489; CHECK-NEXT: vle8.v v8, (a0) 2490; CHECK-NEXT: vle8.v v10, (a1) 2491; CHECK-NEXT: vand.vv v8, v8, v10 2492; CHECK-NEXT: vse8.v v8, (a0) 2493; CHECK-NEXT: ret 2494 %a = load <32 x i8>, ptr %x 2495 %b = load <32 x i8>, ptr %y 2496 %c = and <32 x i8> %a, %b 2497 store <32 x i8> %c, ptr %x 2498 ret void 2499} 2500 2501define void @and_v16i16(ptr %x, ptr %y) { 2502; CHECK-LABEL: and_v16i16: 2503; CHECK: # %bb.0: 2504; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2505; CHECK-NEXT: vle16.v v8, (a0) 2506; CHECK-NEXT: vle16.v v10, (a1) 2507; CHECK-NEXT: vand.vv v8, v8, v10 2508; CHECK-NEXT: vse16.v v8, (a0) 2509; CHECK-NEXT: ret 2510 %a = load <16 x i16>, ptr %x 2511 %b = load <16 x i16>, ptr %y 2512 %c = and <16 x i16> %a, %b 2513 store <16 x i16> %c, ptr %x 2514 ret void 2515} 2516 2517define void @and_v8i32(ptr %x, ptr %y) { 2518; CHECK-LABEL: and_v8i32: 2519; CHECK: # %bb.0: 2520; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2521; CHECK-NEXT: vle32.v v8, (a0) 2522; CHECK-NEXT: vle32.v v10, (a1) 2523; CHECK-NEXT: vand.vv v8, v8, v10 2524; CHECK-NEXT: vse32.v v8, (a0) 2525; CHECK-NEXT: ret 2526 %a = load <8 x i32>, ptr %x 2527 %b = load <8 x i32>, ptr %y 2528 %c = and <8 x i32> %a, %b 2529 store <8 x i32> %c, ptr %x 2530 ret void 2531} 2532 2533define void @and_v4i64(ptr %x, ptr %y) { 2534; CHECK-LABEL: and_v4i64: 2535; CHECK: # %bb.0: 2536; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2537; CHECK-NEXT: vle64.v v8, (a0) 2538; CHECK-NEXT: vle64.v v10, (a1) 2539; CHECK-NEXT: vand.vv v8, v8, v10 2540; CHECK-NEXT: vse64.v v8, (a0) 2541; CHECK-NEXT: ret 2542 %a = load <4 x i64>, ptr %x 2543 %b = load <4 x i64>, ptr %y 2544 %c = and <4 x i64> %a, %b 2545 store <4 x i64> %c, ptr %x 2546 ret void 2547} 2548 2549define void @or_v32i8(ptr %x, ptr %y) { 2550; CHECK-LABEL: or_v32i8: 2551; CHECK: # %bb.0: 2552; CHECK-NEXT: li a2, 32 2553; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2554; CHECK-NEXT: vle8.v v8, (a0) 2555; CHECK-NEXT: vle8.v v10, (a1) 2556; CHECK-NEXT: vor.vv v8, v8, v10 2557; CHECK-NEXT: vse8.v v8, (a0) 2558; CHECK-NEXT: ret 2559 %a = load <32 x i8>, ptr %x 2560 %b = load <32 x i8>, ptr %y 2561 %c = or <32 x i8> %a, %b 2562 store <32 x i8> %c, ptr %x 2563 ret void 2564} 2565 2566define void @or_v16i16(ptr %x, ptr %y) { 2567; CHECK-LABEL: or_v16i16: 2568; CHECK: # %bb.0: 2569; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2570; CHECK-NEXT: vle16.v v8, (a0) 2571; CHECK-NEXT: vle16.v v10, (a1) 2572; CHECK-NEXT: vor.vv v8, v8, v10 2573; CHECK-NEXT: vse16.v v8, (a0) 2574; CHECK-NEXT: ret 2575 %a = load <16 x i16>, ptr %x 2576 %b = load <16 x i16>, ptr %y 2577 %c = or <16 x i16> %a, %b 2578 store <16 x i16> %c, ptr %x 2579 ret void 2580} 2581 2582define void @or_v8i32(ptr %x, ptr %y) { 2583; CHECK-LABEL: or_v8i32: 2584; CHECK: # %bb.0: 2585; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2586; CHECK-NEXT: vle32.v v8, (a0) 2587; CHECK-NEXT: vle32.v v10, (a1) 2588; CHECK-NEXT: vor.vv v8, v8, v10 2589; CHECK-NEXT: vse32.v v8, (a0) 2590; CHECK-NEXT: ret 2591 %a = load <8 x i32>, ptr %x 2592 %b = load <8 x i32>, ptr %y 2593 %c = or <8 x i32> %a, %b 2594 store <8 x i32> %c, ptr %x 2595 ret void 2596} 2597 2598define void @or_v4i64(ptr %x, ptr %y) { 2599; CHECK-LABEL: or_v4i64: 2600; CHECK: # %bb.0: 2601; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2602; CHECK-NEXT: vle64.v v8, (a0) 2603; CHECK-NEXT: vle64.v v10, (a1) 2604; CHECK-NEXT: vor.vv v8, v8, v10 2605; CHECK-NEXT: vse64.v v8, (a0) 2606; CHECK-NEXT: ret 2607 %a = load <4 x i64>, ptr %x 2608 %b = load <4 x i64>, ptr %y 2609 %c = or <4 x i64> %a, %b 2610 store <4 x i64> %c, ptr %x 2611 ret void 2612} 2613 2614define void @xor_v32i8(ptr %x, ptr %y) { 2615; CHECK-LABEL: xor_v32i8: 2616; CHECK: # %bb.0: 2617; CHECK-NEXT: li a2, 32 2618; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2619; CHECK-NEXT: vle8.v v8, (a0) 2620; CHECK-NEXT: vle8.v v10, (a1) 2621; CHECK-NEXT: vxor.vv v8, v8, v10 2622; CHECK-NEXT: vse8.v v8, (a0) 2623; CHECK-NEXT: ret 2624 %a = load <32 x i8>, ptr %x 2625 %b = load <32 x i8>, ptr %y 2626 %c = xor <32 x i8> %a, %b 2627 store <32 x i8> %c, ptr %x 2628 ret void 2629} 2630 2631define void @xor_v16i16(ptr %x, ptr %y) { 2632; CHECK-LABEL: xor_v16i16: 2633; CHECK: # %bb.0: 2634; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2635; CHECK-NEXT: vle16.v v8, (a0) 2636; CHECK-NEXT: vle16.v v10, (a1) 2637; CHECK-NEXT: vxor.vv v8, v8, v10 2638; CHECK-NEXT: vse16.v v8, (a0) 2639; CHECK-NEXT: ret 2640 %a = load <16 x i16>, ptr %x 2641 %b = load <16 x i16>, ptr %y 2642 %c = xor <16 x i16> %a, %b 2643 store <16 x i16> %c, ptr %x 2644 ret void 2645} 2646 2647define void @xor_v8i32(ptr %x, ptr %y) { 2648; CHECK-LABEL: xor_v8i32: 2649; CHECK: # %bb.0: 2650; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2651; CHECK-NEXT: vle32.v v8, (a0) 2652; CHECK-NEXT: vle32.v v10, (a1) 2653; CHECK-NEXT: vxor.vv v8, v8, v10 2654; CHECK-NEXT: vse32.v v8, (a0) 2655; CHECK-NEXT: ret 2656 %a = load <8 x i32>, ptr %x 2657 %b = load <8 x i32>, ptr %y 2658 %c = xor <8 x i32> %a, %b 2659 store <8 x i32> %c, ptr %x 2660 ret void 2661} 2662 2663define void @xor_v4i64(ptr %x, ptr %y) { 2664; CHECK-LABEL: xor_v4i64: 2665; CHECK: # %bb.0: 2666; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2667; CHECK-NEXT: vle64.v v8, (a0) 2668; CHECK-NEXT: vle64.v v10, (a1) 2669; CHECK-NEXT: vxor.vv v8, v8, v10 2670; CHECK-NEXT: vse64.v v8, (a0) 2671; CHECK-NEXT: ret 2672 %a = load <4 x i64>, ptr %x 2673 %b = load <4 x i64>, ptr %y 2674 %c = xor <4 x i64> %a, %b 2675 store <4 x i64> %c, ptr %x 2676 ret void 2677} 2678 2679define void @lshr_v32i8(ptr %x, ptr %y) { 2680; CHECK-LABEL: lshr_v32i8: 2681; CHECK: # %bb.0: 2682; CHECK-NEXT: li a2, 32 2683; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2684; CHECK-NEXT: vle8.v v8, (a0) 2685; CHECK-NEXT: vle8.v v10, (a1) 2686; CHECK-NEXT: vsrl.vv v8, v8, v10 2687; CHECK-NEXT: vse8.v v8, (a0) 2688; CHECK-NEXT: ret 2689 %a = load <32 x i8>, ptr %x 2690 %b = load <32 x i8>, ptr %y 2691 %c = lshr <32 x i8> %a, %b 2692 store <32 x i8> %c, ptr %x 2693 ret void 2694} 2695 2696define void @lshr_v16i16(ptr %x, ptr %y) { 2697; CHECK-LABEL: lshr_v16i16: 2698; CHECK: # %bb.0: 2699; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2700; CHECK-NEXT: vle16.v v8, (a0) 2701; CHECK-NEXT: vle16.v v10, (a1) 2702; CHECK-NEXT: vsrl.vv v8, v8, v10 2703; CHECK-NEXT: vse16.v v8, (a0) 2704; CHECK-NEXT: ret 2705 %a = load <16 x i16>, ptr %x 2706 %b = load <16 x i16>, ptr %y 2707 %c = lshr <16 x i16> %a, %b 2708 store <16 x i16> %c, ptr %x 2709 ret void 2710} 2711 2712define void @lshr_v8i32(ptr %x, ptr %y) { 2713; CHECK-LABEL: lshr_v8i32: 2714; CHECK: # %bb.0: 2715; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2716; CHECK-NEXT: vle32.v v8, (a0) 2717; CHECK-NEXT: vle32.v v10, (a1) 2718; CHECK-NEXT: vsrl.vv v8, v8, v10 2719; CHECK-NEXT: vse32.v v8, (a0) 2720; CHECK-NEXT: ret 2721 %a = load <8 x i32>, ptr %x 2722 %b = load <8 x i32>, ptr %y 2723 %c = lshr <8 x i32> %a, %b 2724 store <8 x i32> %c, ptr %x 2725 ret void 2726} 2727 2728define void @lshr_v4i64(ptr %x, ptr %y) { 2729; CHECK-LABEL: lshr_v4i64: 2730; CHECK: # %bb.0: 2731; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2732; CHECK-NEXT: vle64.v v8, (a0) 2733; CHECK-NEXT: vle64.v v10, (a1) 2734; CHECK-NEXT: vsrl.vv v8, v8, v10 2735; CHECK-NEXT: vse64.v v8, (a0) 2736; CHECK-NEXT: ret 2737 %a = load <4 x i64>, ptr %x 2738 %b = load <4 x i64>, ptr %y 2739 %c = lshr <4 x i64> %a, %b 2740 store <4 x i64> %c, ptr %x 2741 ret void 2742} 2743 2744define void @ashr_v32i8(ptr %x, ptr %y) { 2745; CHECK-LABEL: ashr_v32i8: 2746; CHECK: # %bb.0: 2747; CHECK-NEXT: li a2, 32 2748; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2749; CHECK-NEXT: vle8.v v8, (a0) 2750; CHECK-NEXT: vle8.v v10, (a1) 2751; CHECK-NEXT: vsra.vv v8, v8, v10 2752; CHECK-NEXT: vse8.v v8, (a0) 2753; CHECK-NEXT: ret 2754 %a = load <32 x i8>, ptr %x 2755 %b = load <32 x i8>, ptr %y 2756 %c = ashr <32 x i8> %a, %b 2757 store <32 x i8> %c, ptr %x 2758 ret void 2759} 2760 2761define void @ashr_v16i16(ptr %x, ptr %y) { 2762; CHECK-LABEL: ashr_v16i16: 2763; CHECK: # %bb.0: 2764; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2765; CHECK-NEXT: vle16.v v8, (a0) 2766; CHECK-NEXT: vle16.v v10, (a1) 2767; CHECK-NEXT: vsra.vv v8, v8, v10 2768; CHECK-NEXT: vse16.v v8, (a0) 2769; CHECK-NEXT: ret 2770 %a = load <16 x i16>, ptr %x 2771 %b = load <16 x i16>, ptr %y 2772 %c = ashr <16 x i16> %a, %b 2773 store <16 x i16> %c, ptr %x 2774 ret void 2775} 2776 2777define void @ashr_v8i32(ptr %x, ptr %y) { 2778; CHECK-LABEL: ashr_v8i32: 2779; CHECK: # %bb.0: 2780; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2781; CHECK-NEXT: vle32.v v8, (a0) 2782; CHECK-NEXT: vle32.v v10, (a1) 2783; CHECK-NEXT: vsra.vv v8, v8, v10 2784; CHECK-NEXT: vse32.v v8, (a0) 2785; CHECK-NEXT: ret 2786 %a = load <8 x i32>, ptr %x 2787 %b = load <8 x i32>, ptr %y 2788 %c = ashr <8 x i32> %a, %b 2789 store <8 x i32> %c, ptr %x 2790 ret void 2791} 2792 2793define void @ashr_v4i64(ptr %x, ptr %y) { 2794; CHECK-LABEL: ashr_v4i64: 2795; CHECK: # %bb.0: 2796; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2797; CHECK-NEXT: vle64.v v8, (a0) 2798; CHECK-NEXT: vle64.v v10, (a1) 2799; CHECK-NEXT: vsra.vv v8, v8, v10 2800; CHECK-NEXT: vse64.v v8, (a0) 2801; CHECK-NEXT: ret 2802 %a = load <4 x i64>, ptr %x 2803 %b = load <4 x i64>, ptr %y 2804 %c = ashr <4 x i64> %a, %b 2805 store <4 x i64> %c, ptr %x 2806 ret void 2807} 2808 2809define void @shl_v32i8(ptr %x, ptr %y) { 2810; CHECK-LABEL: shl_v32i8: 2811; CHECK: # %bb.0: 2812; CHECK-NEXT: li a2, 32 2813; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2814; CHECK-NEXT: vle8.v v8, (a0) 2815; CHECK-NEXT: vle8.v v10, (a1) 2816; CHECK-NEXT: vsll.vv v8, v8, v10 2817; CHECK-NEXT: vse8.v v8, (a0) 2818; CHECK-NEXT: ret 2819 %a = load <32 x i8>, ptr %x 2820 %b = load <32 x i8>, ptr %y 2821 %c = shl <32 x i8> %a, %b 2822 store <32 x i8> %c, ptr %x 2823 ret void 2824} 2825 2826define void @shl_v16i16(ptr %x, ptr %y) { 2827; CHECK-LABEL: shl_v16i16: 2828; CHECK: # %bb.0: 2829; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2830; CHECK-NEXT: vle16.v v8, (a0) 2831; CHECK-NEXT: vle16.v v10, (a1) 2832; CHECK-NEXT: vsll.vv v8, v8, v10 2833; CHECK-NEXT: vse16.v v8, (a0) 2834; CHECK-NEXT: ret 2835 %a = load <16 x i16>, ptr %x 2836 %b = load <16 x i16>, ptr %y 2837 %c = shl <16 x i16> %a, %b 2838 store <16 x i16> %c, ptr %x 2839 ret void 2840} 2841 2842define void @shl_v8i32(ptr %x, ptr %y) { 2843; CHECK-LABEL: shl_v8i32: 2844; CHECK: # %bb.0: 2845; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2846; CHECK-NEXT: vle32.v v8, (a0) 2847; CHECK-NEXT: vle32.v v10, (a1) 2848; CHECK-NEXT: vsll.vv v8, v8, v10 2849; CHECK-NEXT: vse32.v v8, (a0) 2850; CHECK-NEXT: ret 2851 %a = load <8 x i32>, ptr %x 2852 %b = load <8 x i32>, ptr %y 2853 %c = shl <8 x i32> %a, %b 2854 store <8 x i32> %c, ptr %x 2855 ret void 2856} 2857 2858define void @shl_v4i64(ptr %x, ptr %y) { 2859; CHECK-LABEL: shl_v4i64: 2860; CHECK: # %bb.0: 2861; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2862; CHECK-NEXT: vle64.v v8, (a0) 2863; CHECK-NEXT: vle64.v v10, (a1) 2864; CHECK-NEXT: vsll.vv v8, v8, v10 2865; CHECK-NEXT: vse64.v v8, (a0) 2866; CHECK-NEXT: ret 2867 %a = load <4 x i64>, ptr %x 2868 %b = load <4 x i64>, ptr %y 2869 %c = shl <4 x i64> %a, %b 2870 store <4 x i64> %c, ptr %x 2871 ret void 2872} 2873 2874define void @sdiv_v32i8(ptr %x, ptr %y) { 2875; CHECK-LABEL: sdiv_v32i8: 2876; CHECK: # %bb.0: 2877; CHECK-NEXT: li a2, 32 2878; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2879; CHECK-NEXT: vle8.v v8, (a0) 2880; CHECK-NEXT: vle8.v v10, (a1) 2881; CHECK-NEXT: vdiv.vv v8, v8, v10 2882; CHECK-NEXT: vse8.v v8, (a0) 2883; CHECK-NEXT: ret 2884 %a = load <32 x i8>, ptr %x 2885 %b = load <32 x i8>, ptr %y 2886 %c = sdiv <32 x i8> %a, %b 2887 store <32 x i8> %c, ptr %x 2888 ret void 2889} 2890 2891define void @sdiv_v16i16(ptr %x, ptr %y) { 2892; CHECK-LABEL: sdiv_v16i16: 2893; CHECK: # %bb.0: 2894; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2895; CHECK-NEXT: vle16.v v8, (a0) 2896; CHECK-NEXT: vle16.v v10, (a1) 2897; CHECK-NEXT: vdiv.vv v8, v8, v10 2898; CHECK-NEXT: vse16.v v8, (a0) 2899; CHECK-NEXT: ret 2900 %a = load <16 x i16>, ptr %x 2901 %b = load <16 x i16>, ptr %y 2902 %c = sdiv <16 x i16> %a, %b 2903 store <16 x i16> %c, ptr %x 2904 ret void 2905} 2906 2907define void @sdiv_v8i32(ptr %x, ptr %y) { 2908; CHECK-LABEL: sdiv_v8i32: 2909; CHECK: # %bb.0: 2910; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2911; CHECK-NEXT: vle32.v v8, (a0) 2912; CHECK-NEXT: vle32.v v10, (a1) 2913; CHECK-NEXT: vdiv.vv v8, v8, v10 2914; CHECK-NEXT: vse32.v v8, (a0) 2915; CHECK-NEXT: ret 2916 %a = load <8 x i32>, ptr %x 2917 %b = load <8 x i32>, ptr %y 2918 %c = sdiv <8 x i32> %a, %b 2919 store <8 x i32> %c, ptr %x 2920 ret void 2921} 2922 2923define void @sdiv_v4i64(ptr %x, ptr %y) { 2924; CHECK-LABEL: sdiv_v4i64: 2925; CHECK: # %bb.0: 2926; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2927; CHECK-NEXT: vle64.v v8, (a0) 2928; CHECK-NEXT: vle64.v v10, (a1) 2929; CHECK-NEXT: vdiv.vv v8, v8, v10 2930; CHECK-NEXT: vse64.v v8, (a0) 2931; CHECK-NEXT: ret 2932 %a = load <4 x i64>, ptr %x 2933 %b = load <4 x i64>, ptr %y 2934 %c = sdiv <4 x i64> %a, %b 2935 store <4 x i64> %c, ptr %x 2936 ret void 2937} 2938 2939define void @srem_v32i8(ptr %x, ptr %y) { 2940; CHECK-LABEL: srem_v32i8: 2941; CHECK: # %bb.0: 2942; CHECK-NEXT: li a2, 32 2943; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 2944; CHECK-NEXT: vle8.v v8, (a0) 2945; CHECK-NEXT: vle8.v v10, (a1) 2946; CHECK-NEXT: vrem.vv v8, v8, v10 2947; CHECK-NEXT: vse8.v v8, (a0) 2948; CHECK-NEXT: ret 2949 %a = load <32 x i8>, ptr %x 2950 %b = load <32 x i8>, ptr %y 2951 %c = srem <32 x i8> %a, %b 2952 store <32 x i8> %c, ptr %x 2953 ret void 2954} 2955 2956define void @srem_v16i16(ptr %x, ptr %y) { 2957; CHECK-LABEL: srem_v16i16: 2958; CHECK: # %bb.0: 2959; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 2960; CHECK-NEXT: vle16.v v8, (a0) 2961; CHECK-NEXT: vle16.v v10, (a1) 2962; CHECK-NEXT: vrem.vv v8, v8, v10 2963; CHECK-NEXT: vse16.v v8, (a0) 2964; CHECK-NEXT: ret 2965 %a = load <16 x i16>, ptr %x 2966 %b = load <16 x i16>, ptr %y 2967 %c = srem <16 x i16> %a, %b 2968 store <16 x i16> %c, ptr %x 2969 ret void 2970} 2971 2972define void @srem_v8i32(ptr %x, ptr %y) { 2973; CHECK-LABEL: srem_v8i32: 2974; CHECK: # %bb.0: 2975; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 2976; CHECK-NEXT: vle32.v v8, (a0) 2977; CHECK-NEXT: vle32.v v10, (a1) 2978; CHECK-NEXT: vrem.vv v8, v8, v10 2979; CHECK-NEXT: vse32.v v8, (a0) 2980; CHECK-NEXT: ret 2981 %a = load <8 x i32>, ptr %x 2982 %b = load <8 x i32>, ptr %y 2983 %c = srem <8 x i32> %a, %b 2984 store <8 x i32> %c, ptr %x 2985 ret void 2986} 2987 2988define void @srem_v4i64(ptr %x, ptr %y) { 2989; CHECK-LABEL: srem_v4i64: 2990; CHECK: # %bb.0: 2991; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 2992; CHECK-NEXT: vle64.v v8, (a0) 2993; CHECK-NEXT: vle64.v v10, (a1) 2994; CHECK-NEXT: vrem.vv v8, v8, v10 2995; CHECK-NEXT: vse64.v v8, (a0) 2996; CHECK-NEXT: ret 2997 %a = load <4 x i64>, ptr %x 2998 %b = load <4 x i64>, ptr %y 2999 %c = srem <4 x i64> %a, %b 3000 store <4 x i64> %c, ptr %x 3001 ret void 3002} 3003 3004define void @udiv_v32i8(ptr %x, ptr %y) { 3005; CHECK-LABEL: udiv_v32i8: 3006; CHECK: # %bb.0: 3007; CHECK-NEXT: li a2, 32 3008; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 3009; CHECK-NEXT: vle8.v v8, (a0) 3010; CHECK-NEXT: vle8.v v10, (a1) 3011; CHECK-NEXT: vdivu.vv v8, v8, v10 3012; CHECK-NEXT: vse8.v v8, (a0) 3013; CHECK-NEXT: ret 3014 %a = load <32 x i8>, ptr %x 3015 %b = load <32 x i8>, ptr %y 3016 %c = udiv <32 x i8> %a, %b 3017 store <32 x i8> %c, ptr %x 3018 ret void 3019} 3020 3021define void @udiv_v16i16(ptr %x, ptr %y) { 3022; CHECK-LABEL: udiv_v16i16: 3023; CHECK: # %bb.0: 3024; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3025; CHECK-NEXT: vle16.v v8, (a0) 3026; CHECK-NEXT: vle16.v v10, (a1) 3027; CHECK-NEXT: vdivu.vv v8, v8, v10 3028; CHECK-NEXT: vse16.v v8, (a0) 3029; CHECK-NEXT: ret 3030 %a = load <16 x i16>, ptr %x 3031 %b = load <16 x i16>, ptr %y 3032 %c = udiv <16 x i16> %a, %b 3033 store <16 x i16> %c, ptr %x 3034 ret void 3035} 3036 3037define void @udiv_v8i32(ptr %x, ptr %y) { 3038; CHECK-LABEL: udiv_v8i32: 3039; CHECK: # %bb.0: 3040; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3041; CHECK-NEXT: vle32.v v8, (a0) 3042; CHECK-NEXT: vle32.v v10, (a1) 3043; CHECK-NEXT: vdivu.vv v8, v8, v10 3044; CHECK-NEXT: vse32.v v8, (a0) 3045; CHECK-NEXT: ret 3046 %a = load <8 x i32>, ptr %x 3047 %b = load <8 x i32>, ptr %y 3048 %c = udiv <8 x i32> %a, %b 3049 store <8 x i32> %c, ptr %x 3050 ret void 3051} 3052 3053define void @udiv_v4i64(ptr %x, ptr %y) { 3054; CHECK-LABEL: udiv_v4i64: 3055; CHECK: # %bb.0: 3056; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3057; CHECK-NEXT: vle64.v v8, (a0) 3058; CHECK-NEXT: vle64.v v10, (a1) 3059; CHECK-NEXT: vdivu.vv v8, v8, v10 3060; CHECK-NEXT: vse64.v v8, (a0) 3061; CHECK-NEXT: ret 3062 %a = load <4 x i64>, ptr %x 3063 %b = load <4 x i64>, ptr %y 3064 %c = udiv <4 x i64> %a, %b 3065 store <4 x i64> %c, ptr %x 3066 ret void 3067} 3068 3069define void @urem_v32i8(ptr %x, ptr %y) { 3070; CHECK-LABEL: urem_v32i8: 3071; CHECK: # %bb.0: 3072; CHECK-NEXT: li a2, 32 3073; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 3074; CHECK-NEXT: vle8.v v8, (a0) 3075; CHECK-NEXT: vle8.v v10, (a1) 3076; CHECK-NEXT: vremu.vv v8, v8, v10 3077; CHECK-NEXT: vse8.v v8, (a0) 3078; CHECK-NEXT: ret 3079 %a = load <32 x i8>, ptr %x 3080 %b = load <32 x i8>, ptr %y 3081 %c = urem <32 x i8> %a, %b 3082 store <32 x i8> %c, ptr %x 3083 ret void 3084} 3085 3086define void @urem_v16i16(ptr %x, ptr %y) { 3087; CHECK-LABEL: urem_v16i16: 3088; CHECK: # %bb.0: 3089; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3090; CHECK-NEXT: vle16.v v8, (a0) 3091; CHECK-NEXT: vle16.v v10, (a1) 3092; CHECK-NEXT: vremu.vv v8, v8, v10 3093; CHECK-NEXT: vse16.v v8, (a0) 3094; CHECK-NEXT: ret 3095 %a = load <16 x i16>, ptr %x 3096 %b = load <16 x i16>, ptr %y 3097 %c = urem <16 x i16> %a, %b 3098 store <16 x i16> %c, ptr %x 3099 ret void 3100} 3101 3102define void @urem_v8i32(ptr %x, ptr %y) { 3103; CHECK-LABEL: urem_v8i32: 3104; CHECK: # %bb.0: 3105; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3106; CHECK-NEXT: vle32.v v8, (a0) 3107; CHECK-NEXT: vle32.v v10, (a1) 3108; CHECK-NEXT: vremu.vv v8, v8, v10 3109; CHECK-NEXT: vse32.v v8, (a0) 3110; CHECK-NEXT: ret 3111 %a = load <8 x i32>, ptr %x 3112 %b = load <8 x i32>, ptr %y 3113 %c = urem <8 x i32> %a, %b 3114 store <8 x i32> %c, ptr %x 3115 ret void 3116} 3117 3118define void @urem_v4i64(ptr %x, ptr %y) { 3119; CHECK-LABEL: urem_v4i64: 3120; CHECK: # %bb.0: 3121; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3122; CHECK-NEXT: vle64.v v8, (a0) 3123; CHECK-NEXT: vle64.v v10, (a1) 3124; CHECK-NEXT: vremu.vv v8, v8, v10 3125; CHECK-NEXT: vse64.v v8, (a0) 3126; CHECK-NEXT: ret 3127 %a = load <4 x i64>, ptr %x 3128 %b = load <4 x i64>, ptr %y 3129 %c = urem <4 x i64> %a, %b 3130 store <4 x i64> %c, ptr %x 3131 ret void 3132} 3133 3134define void @extract_v4i64(ptr %x, ptr %y) { 3135; CHECK-LABEL: extract_v4i64: 3136; CHECK: # %bb.0: 3137; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3138; CHECK-NEXT: vle64.v v8, (a0) 3139; CHECK-NEXT: vle64.v v10, (a1) 3140; CHECK-NEXT: vadd.vv v8, v8, v10 3141; CHECK-NEXT: vse64.v v8, (a0) 3142; CHECK-NEXT: ret 3143 %a = load <4 x i64>, ptr %x 3144 %b = load <4 x i64>, ptr %y 3145 br label %"compute" 3146"compute": 3147 %c = add <4 x i64> %a, %b 3148 store <4 x i64> %c, ptr %x 3149 ret void 3150} 3151 3152define void @mulhu_v32i8(ptr %x) { 3153; CHECK-LABEL: mulhu_v32i8: 3154; CHECK: # %bb.0: 3155; CHECK-NEXT: li a1, 32 3156; CHECK-NEXT: lui a2, 163907 3157; CHECK-NEXT: addi a2, a2, -2044 3158; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma 3159; CHECK-NEXT: vmv.s.x v0, a2 3160; CHECK-NEXT: lui a2, 66049 3161; CHECK-NEXT: addi a2, a2, 32 3162; CHECK-NEXT: vmv.s.x v8, a2 3163; CHECK-NEXT: li a2, -128 3164; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 3165; CHECK-NEXT: vmv.v.i v12, 0 3166; CHECK-NEXT: vmerge.vxm v10, v12, a2, v0 3167; CHECK-NEXT: lui a1, %hi(.LCPI181_0) 3168; CHECK-NEXT: addi a1, a1, %lo(.LCPI181_0) 3169; CHECK-NEXT: vle8.v v14, (a0) 3170; CHECK-NEXT: vmv1r.v v0, v8 3171; CHECK-NEXT: vmerge.vim v8, v12, 1, v0 3172; CHECK-NEXT: vle8.v v12, (a1) 3173; CHECK-NEXT: lui a1, 8208 3174; CHECK-NEXT: addi a1, a1, 513 3175; CHECK-NEXT: vsrl.vv v8, v14, v8 3176; CHECK-NEXT: vmulhu.vv v12, v8, v12 3177; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma 3178; CHECK-NEXT: vmv.s.x v0, a1 3179; CHECK-NEXT: lui a1, 66785 3180; CHECK-NEXT: addi a1, a1, 78 3181; CHECK-NEXT: vmv.s.x v8, a1 3182; CHECK-NEXT: lui a1, 529160 3183; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma 3184; CHECK-NEXT: vsub.vv v14, v14, v12 3185; CHECK-NEXT: vmulhu.vv v10, v14, v10 3186; CHECK-NEXT: vmv.v.i v14, 4 3187; CHECK-NEXT: addi a1, a1, 304 3188; CHECK-NEXT: vmerge.vim v14, v14, 1, v0 3189; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma 3190; CHECK-NEXT: vmv.s.x v9, a1 3191; CHECK-NEXT: vmv1r.v v0, v8 3192; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma 3193; CHECK-NEXT: vmerge.vim v14, v14, 3, v0 3194; CHECK-NEXT: vadd.vv v10, v10, v12 3195; CHECK-NEXT: vmv1r.v v0, v9 3196; CHECK-NEXT: vmerge.vim v8, v14, 2, v0 3197; CHECK-NEXT: vsrl.vv v8, v10, v8 3198; CHECK-NEXT: vse8.v v8, (a0) 3199; CHECK-NEXT: ret 3200 %a = load <32 x i8>, ptr %x 3201 %b = udiv <32 x i8> %a, <i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25> 3202 store <32 x i8> %b, ptr %x 3203 ret void 3204} 3205 3206define void @mulhu_v16i16(ptr %x) { 3207; RV32-LABEL: mulhu_v16i16: 3208; RV32: # %bb.0: 3209; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3210; RV32-NEXT: vle16.v v10, (a0) 3211; RV32-NEXT: li a1, 257 3212; RV32-NEXT: vmv.v.i v8, 0 3213; RV32-NEXT: vmv.s.x v0, a1 3214; RV32-NEXT: lui a1, 1048568 3215; RV32-NEXT: vmerge.vxm v12, v8, a1, v0 3216; RV32-NEXT: lui a1, 4 3217; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma 3218; RV32-NEXT: vmv.v.i v14, 0 3219; RV32-NEXT: addi a1, a1, 64 3220; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma 3221; RV32-NEXT: vmv.s.x v8, a1 3222; RV32-NEXT: lui a1, 2 3223; RV32-NEXT: addi a1, a1, 289 3224; RV32-NEXT: vmv.s.x v9, a1 3225; RV32-NEXT: lui a1, %hi(.LCPI182_0) 3226; RV32-NEXT: addi a1, a1, %lo(.LCPI182_0) 3227; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma 3228; RV32-NEXT: vmv.v.i v15, 3 3229; RV32-NEXT: vmv1r.v v0, v8 3230; RV32-NEXT: vmerge.vim v14, v14, 1, v0 3231; RV32-NEXT: vmv1r.v v0, v9 3232; RV32-NEXT: vmerge.vim v9, v15, 2, v0 3233; RV32-NEXT: vle16.v v16, (a1) 3234; RV32-NEXT: vmv1r.v v0, v8 3235; RV32-NEXT: vmerge.vim v8, v9, 1, v0 3236; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma 3237; RV32-NEXT: vsext.vf2 v18, v14 3238; RV32-NEXT: vsrl.vv v14, v10, v18 3239; RV32-NEXT: vmulhu.vv v14, v14, v16 3240; RV32-NEXT: vsub.vv v10, v10, v14 3241; RV32-NEXT: vmulhu.vv v10, v10, v12 3242; RV32-NEXT: vadd.vv v10, v10, v14 3243; RV32-NEXT: vsext.vf2 v12, v8 3244; RV32-NEXT: vsrl.vv v8, v10, v12 3245; RV32-NEXT: vse16.v v8, (a0) 3246; RV32-NEXT: ret 3247; 3248; RV64-LABEL: mulhu_v16i16: 3249; RV64: # %bb.0: 3250; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3251; RV64-NEXT: vle16.v v8, (a0) 3252; RV64-NEXT: li a1, 257 3253; RV64-NEXT: vmv.v.i v10, 0 3254; RV64-NEXT: vmv.s.x v0, a1 3255; RV64-NEXT: lui a1, %hi(.LCPI182_0) 3256; RV64-NEXT: addi a1, a1, %lo(.LCPI182_0) 3257; RV64-NEXT: vle16.v v12, (a1) 3258; RV64-NEXT: lui a1, 1048568 3259; RV64-NEXT: vmerge.vxm v10, v10, a1, v0 3260; RV64-NEXT: li a1, 1 3261; RV64-NEXT: slli a1, a1, 48 3262; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 3263; RV64-NEXT: vmv.v.x v14, a1 3264; RV64-NEXT: lui a1, %hi(.LCPI182_1) 3265; RV64-NEXT: ld a1, %lo(.LCPI182_1)(a1) 3266; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3267; RV64-NEXT: vsext.vf2 v16, v14 3268; RV64-NEXT: vsrl.vv v14, v8, v16 3269; RV64-NEXT: vmulhu.vv v12, v14, v12 3270; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 3271; RV64-NEXT: vmv.v.x v14, a1 3272; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3273; RV64-NEXT: vsub.vv v8, v8, v12 3274; RV64-NEXT: vmulhu.vv v8, v8, v10 3275; RV64-NEXT: vadd.vv v8, v8, v12 3276; RV64-NEXT: vsext.vf2 v10, v14 3277; RV64-NEXT: vsrl.vv v8, v8, v10 3278; RV64-NEXT: vse16.v v8, (a0) 3279; RV64-NEXT: ret 3280 %a = load <16 x i16>, ptr %x 3281 %b = udiv <16 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> 3282 store <16 x i16> %b, ptr %x 3283 ret void 3284} 3285 3286define void @mulhu_v8i32(ptr %x) { 3287; CHECK-LABEL: mulhu_v8i32: 3288; CHECK: # %bb.0: 3289; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3290; CHECK-NEXT: vle32.v v8, (a0) 3291; CHECK-NEXT: li a1, 68 3292; CHECK-NEXT: vmv.v.i v10, 0 3293; CHECK-NEXT: vmv.s.x v0, a1 3294; CHECK-NEXT: lui a1, %hi(.LCPI183_0) 3295; CHECK-NEXT: addi a1, a1, %lo(.LCPI183_0) 3296; CHECK-NEXT: vle32.v v12, (a1) 3297; CHECK-NEXT: lui a1, 524288 3298; CHECK-NEXT: vmerge.vxm v10, v10, a1, v0 3299; CHECK-NEXT: lui a1, 4128 3300; CHECK-NEXT: addi a1, a1, 514 3301; CHECK-NEXT: vmulhu.vv v12, v8, v12 3302; CHECK-NEXT: vsub.vv v8, v8, v12 3303; CHECK-NEXT: vmulhu.vv v8, v8, v10 3304; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3305; CHECK-NEXT: vmv.v.x v10, a1 3306; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3307; CHECK-NEXT: vadd.vv v8, v8, v12 3308; CHECK-NEXT: vsext.vf4 v12, v10 3309; CHECK-NEXT: vsrl.vv v8, v8, v12 3310; CHECK-NEXT: vse32.v v8, (a0) 3311; CHECK-NEXT: ret 3312 %a = load <8 x i32>, ptr %x 3313 %b = udiv <8 x i32> %a, <i32 5, i32 6, i32 7, i32 9, i32 5, i32 6, i32 7, i32 9> 3314 store <8 x i32> %b, ptr %x 3315 ret void 3316} 3317 3318define void @mulhu_v4i64(ptr %x) { 3319; RV32-LABEL: mulhu_v4i64: 3320; RV32: # %bb.0: 3321; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3322; RV32-NEXT: vle64.v v8, (a0) 3323; RV32-NEXT: lui a1, %hi(.LCPI184_0) 3324; RV32-NEXT: addi a1, a1, %lo(.LCPI184_0) 3325; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3326; RV32-NEXT: vle32.v v10, (a1) 3327; RV32-NEXT: lui a1, 524288 3328; RV32-NEXT: vmv.v.i v12, 0 3329; RV32-NEXT: vmv.s.x v14, a1 3330; RV32-NEXT: lui a1, %hi(.LCPI184_1) 3331; RV32-NEXT: addi a1, a1, %lo(.LCPI184_1) 3332; RV32-NEXT: vsetivli zero, 6, e32, m2, tu, ma 3333; RV32-NEXT: vslideup.vi v12, v14, 5 3334; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 3335; RV32-NEXT: vle8.v v14, (a1) 3336; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3337; RV32-NEXT: vmulhu.vv v10, v8, v10 3338; RV32-NEXT: vsub.vv v8, v8, v10 3339; RV32-NEXT: vmulhu.vv v8, v8, v12 3340; RV32-NEXT: vadd.vv v8, v8, v10 3341; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3342; RV32-NEXT: vsext.vf4 v10, v14 3343; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3344; RV32-NEXT: vsrl.vv v8, v8, v10 3345; RV32-NEXT: vse64.v v8, (a0) 3346; RV32-NEXT: ret 3347; 3348; RV64-LABEL: mulhu_v4i64: 3349; RV64: # %bb.0: 3350; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3351; RV64-NEXT: vle64.v v8, (a0) 3352; RV64-NEXT: lui a1, %hi(.LCPI184_0) 3353; RV64-NEXT: addi a1, a1, %lo(.LCPI184_0) 3354; RV64-NEXT: vle64.v v10, (a1) 3355; RV64-NEXT: li a1, -1 3356; RV64-NEXT: vmv.v.i v12, 0 3357; RV64-NEXT: slli a1, a1, 63 3358; RV64-NEXT: vmv.s.x v14, a1 3359; RV64-NEXT: lui a1, 12320 3360; RV64-NEXT: addi a1, a1, 513 3361; RV64-NEXT: vsetivli zero, 3, e64, m2, tu, ma 3362; RV64-NEXT: vslideup.vi v12, v14, 2 3363; RV64-NEXT: vmv.s.x v14, a1 3364; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3365; RV64-NEXT: vmulhu.vv v10, v8, v10 3366; RV64-NEXT: vsub.vv v8, v8, v10 3367; RV64-NEXT: vmulhu.vv v8, v8, v12 3368; RV64-NEXT: vadd.vv v8, v8, v10 3369; RV64-NEXT: vsext.vf8 v10, v14 3370; RV64-NEXT: vsrl.vv v8, v8, v10 3371; RV64-NEXT: vse64.v v8, (a0) 3372; RV64-NEXT: ret 3373 %a = load <4 x i64>, ptr %x 3374 %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9> 3375 store <4 x i64> %b, ptr %x 3376 ret void 3377} 3378 3379define void @mulhs_v32i8(ptr %x) { 3380; CHECK-LABEL: mulhs_v32i8: 3381; CHECK: # %bb.0: 3382; CHECK-NEXT: li a1, 32 3383; CHECK-NEXT: lui a2, 304453 3384; CHECK-NEXT: addi a2, a2, -1452 3385; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma 3386; CHECK-NEXT: vmv.s.x v0, a2 3387; CHECK-NEXT: li a2, -123 3388; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 3389; CHECK-NEXT: vle8.v v8, (a0) 3390; CHECK-NEXT: vmv.v.i v10, 7 3391; CHECK-NEXT: vmerge.vim v10, v10, 1, v0 3392; CHECK-NEXT: vmv.v.x v12, a2 3393; CHECK-NEXT: li a1, 57 3394; CHECK-NEXT: vmerge.vxm v12, v12, a1, v0 3395; CHECK-NEXT: vmulhu.vv v8, v8, v12 3396; CHECK-NEXT: vsrl.vv v8, v8, v10 3397; CHECK-NEXT: vse8.v v8, (a0) 3398; CHECK-NEXT: ret 3399 %a = load <32 x i8>, ptr %x 3400 %b = udiv <32 x i8> %a, <i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9, i8 9, i8 -9, i8 -9, i8 9, i8 -9> 3401 store <32 x i8> %b, ptr %x 3402 ret void 3403} 3404 3405define void @mulhs_v16i16(ptr %x) { 3406; CHECK-LABEL: mulhs_v16i16: 3407; CHECK: # %bb.0: 3408; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3409; CHECK-NEXT: vle16.v v8, (a0) 3410; CHECK-NEXT: lui a1, 5 3411; CHECK-NEXT: addi a1, a1, -1755 3412; CHECK-NEXT: vmv.v.x v10, a1 3413; CHECK-NEXT: lui a1, 7 3414; CHECK-NEXT: addi a1, a1, -1687 3415; CHECK-NEXT: vmv.s.x v0, a1 3416; CHECK-NEXT: lui a1, 1048571 3417; CHECK-NEXT: addi a1, a1, 1755 3418; CHECK-NEXT: vmerge.vxm v10, v10, a1, v0 3419; CHECK-NEXT: vmulh.vv v8, v8, v10 3420; CHECK-NEXT: vsra.vi v8, v8, 1 3421; CHECK-NEXT: vsrl.vi v10, v8, 15 3422; CHECK-NEXT: vadd.vv v8, v8, v10 3423; CHECK-NEXT: vse16.v v8, (a0) 3424; CHECK-NEXT: ret 3425 %a = load <16 x i16>, ptr %x 3426 %b = sdiv <16 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7, i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7, i16 -7, i16 7> 3427 store <16 x i16> %b, ptr %x 3428 ret void 3429} 3430 3431define void @mulhs_v8i32(ptr %x) { 3432; RV32-LABEL: mulhs_v8i32: 3433; RV32: # %bb.0: 3434; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3435; RV32-NEXT: vle32.v v8, (a0) 3436; RV32-NEXT: li a1, 85 3437; RV32-NEXT: vmv.s.x v0, a1 3438; RV32-NEXT: lui a1, 419430 3439; RV32-NEXT: addi a1, a1, 1639 3440; RV32-NEXT: vmv.v.x v10, a1 3441; RV32-NEXT: lui a1, 629146 3442; RV32-NEXT: addi a1, a1, -1639 3443; RV32-NEXT: vmerge.vxm v10, v10, a1, v0 3444; RV32-NEXT: vmulh.vv v8, v8, v10 3445; RV32-NEXT: vsrl.vi v10, v8, 31 3446; RV32-NEXT: vsra.vi v8, v8, 1 3447; RV32-NEXT: vadd.vv v8, v8, v10 3448; RV32-NEXT: vse32.v v8, (a0) 3449; RV32-NEXT: ret 3450; 3451; RV64-LABEL: mulhs_v8i32: 3452; RV64: # %bb.0: 3453; RV64-NEXT: lui a1, %hi(.LCPI187_0) 3454; RV64-NEXT: ld a1, %lo(.LCPI187_0)(a1) 3455; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3456; RV64-NEXT: vle32.v v8, (a0) 3457; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3458; RV64-NEXT: vmv.v.x v10, a1 3459; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3460; RV64-NEXT: vmulh.vv v8, v8, v10 3461; RV64-NEXT: vsra.vi v8, v8, 1 3462; RV64-NEXT: vsrl.vi v10, v8, 31 3463; RV64-NEXT: vadd.vv v8, v8, v10 3464; RV64-NEXT: vse32.v v8, (a0) 3465; RV64-NEXT: ret 3466 %a = load <8 x i32>, ptr %x 3467 %b = sdiv <8 x i32> %a, <i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5, i32 -5, i32 5> 3468 store <8 x i32> %b, ptr %x 3469 ret void 3470} 3471 3472define void @mulhs_v4i64(ptr %x) { 3473; RV32-LABEL: mulhs_v4i64: 3474; RV32: # %bb.0: 3475; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3476; RV32-NEXT: vle64.v v8, (a0) 3477; RV32-NEXT: lui a1, 349525 3478; RV32-NEXT: li a2, 17 3479; RV32-NEXT: vmv.s.x v0, a2 3480; RV32-NEXT: lui a2, 1048560 3481; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3482; RV32-NEXT: vmv.v.x v10, a2 3483; RV32-NEXT: addi a2, a1, 1365 3484; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3485; RV32-NEXT: vmv.v.x v12, a2 3486; RV32-NEXT: li a2, 63 3487; RV32-NEXT: addi a1, a1, 1366 3488; RV32-NEXT: vmerge.vxm v12, v12, a1, v0 3489; RV32-NEXT: lui a1, 16 3490; RV32-NEXT: vsext.vf4 v14, v10 3491; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3492; RV32-NEXT: vmulh.vv v10, v8, v12 3493; RV32-NEXT: vmadd.vv v14, v8, v10 3494; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3495; RV32-NEXT: vmv.v.x v8, a1 3496; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3497; RV32-NEXT: vsext.vf4 v10, v8 3498; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3499; RV32-NEXT: vsrl.vx v8, v14, a2 3500; RV32-NEXT: vsra.vv v10, v14, v10 3501; RV32-NEXT: vadd.vv v8, v10, v8 3502; RV32-NEXT: vse64.v v8, (a0) 3503; RV32-NEXT: ret 3504; 3505; RV64-LABEL: mulhs_v4i64: 3506; RV64: # %bb.0: 3507; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3508; RV64-NEXT: vle64.v v8, (a0) 3509; RV64-NEXT: lui a1, 349525 3510; RV64-NEXT: lui a2, 1044496 3511; RV64-NEXT: addiw a1, a1, 1365 3512; RV64-NEXT: addi a2, a2, -256 3513; RV64-NEXT: vmv.s.x v10, a2 3514; RV64-NEXT: slli a2, a1, 32 3515; RV64-NEXT: add a1, a1, a2 3516; RV64-NEXT: lui a2, %hi(.LCPI188_0) 3517; RV64-NEXT: ld a2, %lo(.LCPI188_0)(a2) 3518; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma 3519; RV64-NEXT: vmv.v.i v0, 5 3520; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3521; RV64-NEXT: vmv.v.x v12, a1 3522; RV64-NEXT: li a1, 63 3523; RV64-NEXT: vmerge.vxm v12, v12, a2, v0 3524; RV64-NEXT: lui a2, 4096 3525; RV64-NEXT: addi a2, a2, 256 3526; RV64-NEXT: vsext.vf8 v14, v10 3527; RV64-NEXT: vmulh.vv v10, v8, v12 3528; RV64-NEXT: vmadd.vv v14, v8, v10 3529; RV64-NEXT: vmv.s.x v8, a2 3530; RV64-NEXT: vsext.vf8 v10, v8 3531; RV64-NEXT: vsrl.vx v8, v14, a1 3532; RV64-NEXT: vsra.vv v10, v14, v10 3533; RV64-NEXT: vadd.vv v8, v10, v8 3534; RV64-NEXT: vse64.v v8, (a0) 3535; RV64-NEXT: ret 3536 %a = load <4 x i64>, ptr %x 3537 %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3> 3538 store <4 x i64> %b, ptr %x 3539 ret void 3540} 3541 3542define void @smin_v32i8(ptr %x, ptr %y) { 3543; CHECK-LABEL: smin_v32i8: 3544; CHECK: # %bb.0: 3545; CHECK-NEXT: li a2, 32 3546; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 3547; CHECK-NEXT: vle8.v v8, (a0) 3548; CHECK-NEXT: vle8.v v10, (a1) 3549; CHECK-NEXT: vmin.vv v8, v8, v10 3550; CHECK-NEXT: vse8.v v8, (a0) 3551; CHECK-NEXT: ret 3552 %a = load <32 x i8>, ptr %x 3553 %b = load <32 x i8>, ptr %y 3554 %cc = icmp slt <32 x i8> %a, %b 3555 %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b 3556 store <32 x i8> %c, ptr %x 3557 ret void 3558} 3559 3560define void @smin_v16i16(ptr %x, ptr %y) { 3561; CHECK-LABEL: smin_v16i16: 3562; CHECK: # %bb.0: 3563; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3564; CHECK-NEXT: vle16.v v8, (a0) 3565; CHECK-NEXT: vle16.v v10, (a1) 3566; CHECK-NEXT: vmin.vv v8, v8, v10 3567; CHECK-NEXT: vse16.v v8, (a0) 3568; CHECK-NEXT: ret 3569 %a = load <16 x i16>, ptr %x 3570 %b = load <16 x i16>, ptr %y 3571 %cc = icmp slt <16 x i16> %a, %b 3572 %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b 3573 store <16 x i16> %c, ptr %x 3574 ret void 3575} 3576 3577define void @smin_v8i32(ptr %x, ptr %y) { 3578; CHECK-LABEL: smin_v8i32: 3579; CHECK: # %bb.0: 3580; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3581; CHECK-NEXT: vle32.v v8, (a0) 3582; CHECK-NEXT: vle32.v v10, (a1) 3583; CHECK-NEXT: vmin.vv v8, v8, v10 3584; CHECK-NEXT: vse32.v v8, (a0) 3585; CHECK-NEXT: ret 3586 %a = load <8 x i32>, ptr %x 3587 %b = load <8 x i32>, ptr %y 3588 %cc = icmp slt <8 x i32> %a, %b 3589 %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b 3590 store <8 x i32> %c, ptr %x 3591 ret void 3592} 3593 3594define void @smin_v4i64(ptr %x, ptr %y) { 3595; CHECK-LABEL: smin_v4i64: 3596; CHECK: # %bb.0: 3597; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3598; CHECK-NEXT: vle64.v v8, (a0) 3599; CHECK-NEXT: vle64.v v10, (a1) 3600; CHECK-NEXT: vmin.vv v8, v8, v10 3601; CHECK-NEXT: vse64.v v8, (a0) 3602; CHECK-NEXT: ret 3603 %a = load <4 x i64>, ptr %x 3604 %b = load <4 x i64>, ptr %y 3605 %cc = icmp slt <4 x i64> %a, %b 3606 %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b 3607 store <4 x i64> %c, ptr %x 3608 ret void 3609} 3610 3611define void @smax_v32i8(ptr %x, ptr %y) { 3612; CHECK-LABEL: smax_v32i8: 3613; CHECK: # %bb.0: 3614; CHECK-NEXT: li a2, 32 3615; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 3616; CHECK-NEXT: vle8.v v8, (a0) 3617; CHECK-NEXT: vle8.v v10, (a1) 3618; CHECK-NEXT: vmax.vv v8, v8, v10 3619; CHECK-NEXT: vse8.v v8, (a0) 3620; CHECK-NEXT: ret 3621 %a = load <32 x i8>, ptr %x 3622 %b = load <32 x i8>, ptr %y 3623 %cc = icmp sgt <32 x i8> %a, %b 3624 %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b 3625 store <32 x i8> %c, ptr %x 3626 ret void 3627} 3628 3629define void @smax_v16i16(ptr %x, ptr %y) { 3630; CHECK-LABEL: smax_v16i16: 3631; CHECK: # %bb.0: 3632; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3633; CHECK-NEXT: vle16.v v8, (a0) 3634; CHECK-NEXT: vle16.v v10, (a1) 3635; CHECK-NEXT: vmax.vv v8, v8, v10 3636; CHECK-NEXT: vse16.v v8, (a0) 3637; CHECK-NEXT: ret 3638 %a = load <16 x i16>, ptr %x 3639 %b = load <16 x i16>, ptr %y 3640 %cc = icmp sgt <16 x i16> %a, %b 3641 %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b 3642 store <16 x i16> %c, ptr %x 3643 ret void 3644} 3645 3646define void @smax_v8i32(ptr %x, ptr %y) { 3647; CHECK-LABEL: smax_v8i32: 3648; CHECK: # %bb.0: 3649; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3650; CHECK-NEXT: vle32.v v8, (a0) 3651; CHECK-NEXT: vle32.v v10, (a1) 3652; CHECK-NEXT: vmax.vv v8, v8, v10 3653; CHECK-NEXT: vse32.v v8, (a0) 3654; CHECK-NEXT: ret 3655 %a = load <8 x i32>, ptr %x 3656 %b = load <8 x i32>, ptr %y 3657 %cc = icmp sgt <8 x i32> %a, %b 3658 %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b 3659 store <8 x i32> %c, ptr %x 3660 ret void 3661} 3662 3663define void @smax_v4i64(ptr %x, ptr %y) { 3664; CHECK-LABEL: smax_v4i64: 3665; CHECK: # %bb.0: 3666; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3667; CHECK-NEXT: vle64.v v8, (a0) 3668; CHECK-NEXT: vle64.v v10, (a1) 3669; CHECK-NEXT: vmax.vv v8, v8, v10 3670; CHECK-NEXT: vse64.v v8, (a0) 3671; CHECK-NEXT: ret 3672 %a = load <4 x i64>, ptr %x 3673 %b = load <4 x i64>, ptr %y 3674 %cc = icmp sgt <4 x i64> %a, %b 3675 %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b 3676 store <4 x i64> %c, ptr %x 3677 ret void 3678} 3679 3680define void @umin_v32i8(ptr %x, ptr %y) { 3681; CHECK-LABEL: umin_v32i8: 3682; CHECK: # %bb.0: 3683; CHECK-NEXT: li a2, 32 3684; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 3685; CHECK-NEXT: vle8.v v8, (a0) 3686; CHECK-NEXT: vle8.v v10, (a1) 3687; CHECK-NEXT: vminu.vv v8, v8, v10 3688; CHECK-NEXT: vse8.v v8, (a0) 3689; CHECK-NEXT: ret 3690 %a = load <32 x i8>, ptr %x 3691 %b = load <32 x i8>, ptr %y 3692 %cc = icmp ult <32 x i8> %a, %b 3693 %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b 3694 store <32 x i8> %c, ptr %x 3695 ret void 3696} 3697 3698define void @umin_v16i16(ptr %x, ptr %y) { 3699; CHECK-LABEL: umin_v16i16: 3700; CHECK: # %bb.0: 3701; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3702; CHECK-NEXT: vle16.v v8, (a0) 3703; CHECK-NEXT: vle16.v v10, (a1) 3704; CHECK-NEXT: vminu.vv v8, v8, v10 3705; CHECK-NEXT: vse16.v v8, (a0) 3706; CHECK-NEXT: ret 3707 %a = load <16 x i16>, ptr %x 3708 %b = load <16 x i16>, ptr %y 3709 %cc = icmp ult <16 x i16> %a, %b 3710 %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b 3711 store <16 x i16> %c, ptr %x 3712 ret void 3713} 3714 3715define void @umin_v8i32(ptr %x, ptr %y) { 3716; CHECK-LABEL: umin_v8i32: 3717; CHECK: # %bb.0: 3718; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3719; CHECK-NEXT: vle32.v v8, (a0) 3720; CHECK-NEXT: vle32.v v10, (a1) 3721; CHECK-NEXT: vminu.vv v8, v8, v10 3722; CHECK-NEXT: vse32.v v8, (a0) 3723; CHECK-NEXT: ret 3724 %a = load <8 x i32>, ptr %x 3725 %b = load <8 x i32>, ptr %y 3726 %cc = icmp ult <8 x i32> %a, %b 3727 %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b 3728 store <8 x i32> %c, ptr %x 3729 ret void 3730} 3731 3732define void @umin_v4i64(ptr %x, ptr %y) { 3733; CHECK-LABEL: umin_v4i64: 3734; CHECK: # %bb.0: 3735; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3736; CHECK-NEXT: vle64.v v8, (a0) 3737; CHECK-NEXT: vle64.v v10, (a1) 3738; CHECK-NEXT: vminu.vv v8, v8, v10 3739; CHECK-NEXT: vse64.v v8, (a0) 3740; CHECK-NEXT: ret 3741 %a = load <4 x i64>, ptr %x 3742 %b = load <4 x i64>, ptr %y 3743 %cc = icmp ult <4 x i64> %a, %b 3744 %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b 3745 store <4 x i64> %c, ptr %x 3746 ret void 3747} 3748 3749define void @umax_v32i8(ptr %x, ptr %y) { 3750; CHECK-LABEL: umax_v32i8: 3751; CHECK: # %bb.0: 3752; CHECK-NEXT: li a2, 32 3753; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma 3754; CHECK-NEXT: vle8.v v8, (a0) 3755; CHECK-NEXT: vle8.v v10, (a1) 3756; CHECK-NEXT: vmaxu.vv v8, v8, v10 3757; CHECK-NEXT: vse8.v v8, (a0) 3758; CHECK-NEXT: ret 3759 %a = load <32 x i8>, ptr %x 3760 %b = load <32 x i8>, ptr %y 3761 %cc = icmp ugt <32 x i8> %a, %b 3762 %c = select <32 x i1> %cc, <32 x i8> %a, <32 x i8> %b 3763 store <32 x i8> %c, ptr %x 3764 ret void 3765} 3766 3767define void @umax_v16i16(ptr %x, ptr %y) { 3768; CHECK-LABEL: umax_v16i16: 3769; CHECK: # %bb.0: 3770; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 3771; CHECK-NEXT: vle16.v v8, (a0) 3772; CHECK-NEXT: vle16.v v10, (a1) 3773; CHECK-NEXT: vmaxu.vv v8, v8, v10 3774; CHECK-NEXT: vse16.v v8, (a0) 3775; CHECK-NEXT: ret 3776 %a = load <16 x i16>, ptr %x 3777 %b = load <16 x i16>, ptr %y 3778 %cc = icmp ugt <16 x i16> %a, %b 3779 %c = select <16 x i1> %cc, <16 x i16> %a, <16 x i16> %b 3780 store <16 x i16> %c, ptr %x 3781 ret void 3782} 3783 3784define void @umax_v8i32(ptr %x, ptr %y) { 3785; CHECK-LABEL: umax_v8i32: 3786; CHECK: # %bb.0: 3787; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 3788; CHECK-NEXT: vle32.v v8, (a0) 3789; CHECK-NEXT: vle32.v v10, (a1) 3790; CHECK-NEXT: vmaxu.vv v8, v8, v10 3791; CHECK-NEXT: vse32.v v8, (a0) 3792; CHECK-NEXT: ret 3793 %a = load <8 x i32>, ptr %x 3794 %b = load <8 x i32>, ptr %y 3795 %cc = icmp ugt <8 x i32> %a, %b 3796 %c = select <8 x i1> %cc, <8 x i32> %a, <8 x i32> %b 3797 store <8 x i32> %c, ptr %x 3798 ret void 3799} 3800 3801define void @umax_v4i64(ptr %x, ptr %y) { 3802; CHECK-LABEL: umax_v4i64: 3803; CHECK: # %bb.0: 3804; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 3805; CHECK-NEXT: vle64.v v8, (a0) 3806; CHECK-NEXT: vle64.v v10, (a1) 3807; CHECK-NEXT: vmaxu.vv v8, v8, v10 3808; CHECK-NEXT: vse64.v v8, (a0) 3809; CHECK-NEXT: ret 3810 %a = load <4 x i64>, ptr %x 3811 %b = load <4 x i64>, ptr %y 3812 %cc = icmp ugt <4 x i64> %a, %b 3813 %c = select <4 x i1> %cc, <4 x i64> %a, <4 x i64> %b 3814 store <4 x i64> %c, ptr %x 3815 ret void 3816} 3817 3818define void @add_vi_v16i8(ptr %x) { 3819; CHECK-LABEL: add_vi_v16i8: 3820; CHECK: # %bb.0: 3821; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 3822; CHECK-NEXT: vle8.v v8, (a0) 3823; CHECK-NEXT: vadd.vi v8, v8, -1 3824; CHECK-NEXT: vse8.v v8, (a0) 3825; CHECK-NEXT: ret 3826 %a = load <16 x i8>, ptr %x 3827 %d = add <16 x i8> %a, splat (i8 -1) 3828 store <16 x i8> %d, ptr %x 3829 ret void 3830} 3831 3832define void @add_vi_v8i16(ptr %x) { 3833; CHECK-LABEL: add_vi_v8i16: 3834; CHECK: # %bb.0: 3835; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 3836; CHECK-NEXT: vle16.v v8, (a0) 3837; CHECK-NEXT: vadd.vi v8, v8, -1 3838; CHECK-NEXT: vse16.v v8, (a0) 3839; CHECK-NEXT: ret 3840 %a = load <8 x i16>, ptr %x 3841 %d = add <8 x i16> %a, splat (i16 -1) 3842 store <8 x i16> %d, ptr %x 3843 ret void 3844} 3845 3846define void @add_vi_v4i32(ptr %x) { 3847; CHECK-LABEL: add_vi_v4i32: 3848; CHECK: # %bb.0: 3849; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 3850; CHECK-NEXT: vle32.v v8, (a0) 3851; CHECK-NEXT: vadd.vi v8, v8, -1 3852; CHECK-NEXT: vse32.v v8, (a0) 3853; CHECK-NEXT: ret 3854 %a = load <4 x i32>, ptr %x 3855 %d = add <4 x i32> %a, splat (i32 -1) 3856 store <4 x i32> %d, ptr %x 3857 ret void 3858} 3859 3860define void @add_vi_v2i64(ptr %x) { 3861; CHECK-LABEL: add_vi_v2i64: 3862; CHECK: # %bb.0: 3863; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 3864; CHECK-NEXT: vle64.v v8, (a0) 3865; CHECK-NEXT: vadd.vi v8, v8, -1 3866; CHECK-NEXT: vse64.v v8, (a0) 3867; CHECK-NEXT: ret 3868 %a = load <2 x i64>, ptr %x 3869 %d = add <2 x i64> %a, splat (i64 -1) 3870 store <2 x i64> %d, ptr %x 3871 ret void 3872} 3873 3874define void @add_iv_v16i8(ptr %x) { 3875; CHECK-LABEL: add_iv_v16i8: 3876; CHECK: # %bb.0: 3877; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 3878; CHECK-NEXT: vle8.v v8, (a0) 3879; CHECK-NEXT: vadd.vi v8, v8, 1 3880; CHECK-NEXT: vse8.v v8, (a0) 3881; CHECK-NEXT: ret 3882 %a = load <16 x i8>, ptr %x 3883 %d = add <16 x i8> splat (i8 1), %a 3884 store <16 x i8> %d, ptr %x 3885 ret void 3886} 3887 3888define void @add_iv_v8i16(ptr %x) { 3889; CHECK-LABEL: add_iv_v8i16: 3890; CHECK: # %bb.0: 3891; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 3892; CHECK-NEXT: vle16.v v8, (a0) 3893; CHECK-NEXT: vadd.vi v8, v8, 1 3894; CHECK-NEXT: vse16.v v8, (a0) 3895; CHECK-NEXT: ret 3896 %a = load <8 x i16>, ptr %x 3897 %d = add <8 x i16> splat (i16 1), %a 3898 store <8 x i16> %d, ptr %x 3899 ret void 3900} 3901 3902define void @add_iv_v4i32(ptr %x) { 3903; CHECK-LABEL: add_iv_v4i32: 3904; CHECK: # %bb.0: 3905; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 3906; CHECK-NEXT: vle32.v v8, (a0) 3907; CHECK-NEXT: vadd.vi v8, v8, 1 3908; CHECK-NEXT: vse32.v v8, (a0) 3909; CHECK-NEXT: ret 3910 %a = load <4 x i32>, ptr %x 3911 %d = add <4 x i32> splat (i32 1), %a 3912 store <4 x i32> %d, ptr %x 3913 ret void 3914} 3915 3916define void @add_iv_v2i64(ptr %x) { 3917; CHECK-LABEL: add_iv_v2i64: 3918; CHECK: # %bb.0: 3919; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 3920; CHECK-NEXT: vle64.v v8, (a0) 3921; CHECK-NEXT: vadd.vi v8, v8, 1 3922; CHECK-NEXT: vse64.v v8, (a0) 3923; CHECK-NEXT: ret 3924 %a = load <2 x i64>, ptr %x 3925 %d = add <2 x i64> splat (i64 1), %a 3926 store <2 x i64> %d, ptr %x 3927 ret void 3928} 3929 3930define void @add_vx_v16i8(ptr %x, i8 %y) { 3931; CHECK-LABEL: add_vx_v16i8: 3932; CHECK: # %bb.0: 3933; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 3934; CHECK-NEXT: vle8.v v8, (a0) 3935; CHECK-NEXT: vadd.vx v8, v8, a1 3936; CHECK-NEXT: vse8.v v8, (a0) 3937; CHECK-NEXT: ret 3938 %a = load <16 x i8>, ptr %x 3939 %b = insertelement <16 x i8> poison, i8 %y, i32 0 3940 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 3941 %d = add <16 x i8> %a, %c 3942 store <16 x i8> %d, ptr %x 3943 ret void 3944} 3945 3946define void @add_vx_v8i16(ptr %x, i16 %y) { 3947; CHECK-LABEL: add_vx_v8i16: 3948; CHECK: # %bb.0: 3949; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 3950; CHECK-NEXT: vle16.v v8, (a0) 3951; CHECK-NEXT: vadd.vx v8, v8, a1 3952; CHECK-NEXT: vse16.v v8, (a0) 3953; CHECK-NEXT: ret 3954 %a = load <8 x i16>, ptr %x 3955 %b = insertelement <8 x i16> poison, i16 %y, i32 0 3956 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 3957 %d = add <8 x i16> %a, %c 3958 store <8 x i16> %d, ptr %x 3959 ret void 3960} 3961 3962define void @add_vx_v4i32(ptr %x, i32 %y) { 3963; CHECK-LABEL: add_vx_v4i32: 3964; CHECK: # %bb.0: 3965; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 3966; CHECK-NEXT: vle32.v v8, (a0) 3967; CHECK-NEXT: vadd.vx v8, v8, a1 3968; CHECK-NEXT: vse32.v v8, (a0) 3969; CHECK-NEXT: ret 3970 %a = load <4 x i32>, ptr %x 3971 %b = insertelement <4 x i32> poison, i32 %y, i32 0 3972 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 3973 %d = add <4 x i32> %a, %c 3974 store <4 x i32> %d, ptr %x 3975 ret void 3976} 3977 3978define void @add_xv_v16i8(ptr %x, i8 %y) { 3979; CHECK-LABEL: add_xv_v16i8: 3980; CHECK: # %bb.0: 3981; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 3982; CHECK-NEXT: vle8.v v8, (a0) 3983; CHECK-NEXT: vadd.vx v8, v8, a1 3984; CHECK-NEXT: vse8.v v8, (a0) 3985; CHECK-NEXT: ret 3986 %a = load <16 x i8>, ptr %x 3987 %b = insertelement <16 x i8> poison, i8 %y, i32 0 3988 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 3989 %d = add <16 x i8> %c, %a 3990 store <16 x i8> %d, ptr %x 3991 ret void 3992} 3993 3994define void @add_xv_v8i16(ptr %x, i16 %y) { 3995; CHECK-LABEL: add_xv_v8i16: 3996; CHECK: # %bb.0: 3997; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 3998; CHECK-NEXT: vle16.v v8, (a0) 3999; CHECK-NEXT: vadd.vx v8, v8, a1 4000; CHECK-NEXT: vse16.v v8, (a0) 4001; CHECK-NEXT: ret 4002 %a = load <8 x i16>, ptr %x 4003 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4004 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4005 %d = add <8 x i16> %c, %a 4006 store <8 x i16> %d, ptr %x 4007 ret void 4008} 4009 4010define void @add_xv_v4i32(ptr %x, i32 %y) { 4011; CHECK-LABEL: add_xv_v4i32: 4012; CHECK: # %bb.0: 4013; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4014; CHECK-NEXT: vle32.v v8, (a0) 4015; CHECK-NEXT: vadd.vx v8, v8, a1 4016; CHECK-NEXT: vse32.v v8, (a0) 4017; CHECK-NEXT: ret 4018 %a = load <4 x i32>, ptr %x 4019 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4020 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4021 %d = add <4 x i32> %c, %a 4022 store <4 x i32> %d, ptr %x 4023 ret void 4024} 4025 4026define void @sub_vi_v16i8(ptr %x) { 4027; CHECK-LABEL: sub_vi_v16i8: 4028; CHECK: # %bb.0: 4029; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4030; CHECK-NEXT: vle8.v v8, (a0) 4031; CHECK-NEXT: li a1, -1 4032; CHECK-NEXT: vsub.vx v8, v8, a1 4033; CHECK-NEXT: vse8.v v8, (a0) 4034; CHECK-NEXT: ret 4035 %a = load <16 x i8>, ptr %x 4036 %d = sub <16 x i8> %a, splat (i8 -1) 4037 store <16 x i8> %d, ptr %x 4038 ret void 4039} 4040 4041define void @sub_vi_v8i16(ptr %x) { 4042; CHECK-LABEL: sub_vi_v8i16: 4043; CHECK: # %bb.0: 4044; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4045; CHECK-NEXT: vle16.v v8, (a0) 4046; CHECK-NEXT: li a1, -1 4047; CHECK-NEXT: vsub.vx v8, v8, a1 4048; CHECK-NEXT: vse16.v v8, (a0) 4049; CHECK-NEXT: ret 4050 %a = load <8 x i16>, ptr %x 4051 %d = sub <8 x i16> %a, splat (i16 -1) 4052 store <8 x i16> %d, ptr %x 4053 ret void 4054} 4055 4056define void @sub_vi_v4i32(ptr %x) { 4057; CHECK-LABEL: sub_vi_v4i32: 4058; CHECK: # %bb.0: 4059; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4060; CHECK-NEXT: vle32.v v8, (a0) 4061; CHECK-NEXT: li a1, -1 4062; CHECK-NEXT: vsub.vx v8, v8, a1 4063; CHECK-NEXT: vse32.v v8, (a0) 4064; CHECK-NEXT: ret 4065 %a = load <4 x i32>, ptr %x 4066 %d = sub <4 x i32> %a, splat (i32 -1) 4067 store <4 x i32> %d, ptr %x 4068 ret void 4069} 4070 4071define void @sub_vi_v2i64(ptr %x) { 4072; CHECK-LABEL: sub_vi_v2i64: 4073; CHECK: # %bb.0: 4074; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4075; CHECK-NEXT: vle64.v v8, (a0) 4076; CHECK-NEXT: li a1, -1 4077; CHECK-NEXT: vsub.vx v8, v8, a1 4078; CHECK-NEXT: vse64.v v8, (a0) 4079; CHECK-NEXT: ret 4080 %a = load <2 x i64>, ptr %x 4081 %d = sub <2 x i64> %a, splat (i64 -1) 4082 store <2 x i64> %d, ptr %x 4083 ret void 4084} 4085 4086define void @sub_iv_v16i8(ptr %x) { 4087; CHECK-LABEL: sub_iv_v16i8: 4088; CHECK: # %bb.0: 4089; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4090; CHECK-NEXT: vle8.v v8, (a0) 4091; CHECK-NEXT: vrsub.vi v8, v8, 1 4092; CHECK-NEXT: vse8.v v8, (a0) 4093; CHECK-NEXT: ret 4094 %a = load <16 x i8>, ptr %x 4095 %d = sub <16 x i8> splat (i8 1), %a 4096 store <16 x i8> %d, ptr %x 4097 ret void 4098} 4099 4100define void @sub_iv_v8i16(ptr %x) { 4101; CHECK-LABEL: sub_iv_v8i16: 4102; CHECK: # %bb.0: 4103; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4104; CHECK-NEXT: vle16.v v8, (a0) 4105; CHECK-NEXT: vrsub.vi v8, v8, 1 4106; CHECK-NEXT: vse16.v v8, (a0) 4107; CHECK-NEXT: ret 4108 %a = load <8 x i16>, ptr %x 4109 %d = sub <8 x i16> splat (i16 1), %a 4110 store <8 x i16> %d, ptr %x 4111 ret void 4112} 4113 4114define void @sub_iv_v4i32(ptr %x) { 4115; CHECK-LABEL: sub_iv_v4i32: 4116; CHECK: # %bb.0: 4117; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4118; CHECK-NEXT: vle32.v v8, (a0) 4119; CHECK-NEXT: vrsub.vi v8, v8, 1 4120; CHECK-NEXT: vse32.v v8, (a0) 4121; CHECK-NEXT: ret 4122 %a = load <4 x i32>, ptr %x 4123 %d = sub <4 x i32> splat (i32 1), %a 4124 store <4 x i32> %d, ptr %x 4125 ret void 4126} 4127 4128define void @sub_iv_v2i64(ptr %x) { 4129; CHECK-LABEL: sub_iv_v2i64: 4130; CHECK: # %bb.0: 4131; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4132; CHECK-NEXT: vle64.v v8, (a0) 4133; CHECK-NEXT: vrsub.vi v8, v8, 1 4134; CHECK-NEXT: vse64.v v8, (a0) 4135; CHECK-NEXT: ret 4136 %a = load <2 x i64>, ptr %x 4137 %d = sub <2 x i64> splat (i64 1), %a 4138 store <2 x i64> %d, ptr %x 4139 ret void 4140} 4141 4142define void @sub_vx_v16i8(ptr %x, i8 %y) { 4143; CHECK-LABEL: sub_vx_v16i8: 4144; CHECK: # %bb.0: 4145; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4146; CHECK-NEXT: vle8.v v8, (a0) 4147; CHECK-NEXT: vsub.vx v8, v8, a1 4148; CHECK-NEXT: vse8.v v8, (a0) 4149; CHECK-NEXT: ret 4150 %a = load <16 x i8>, ptr %x 4151 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4152 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4153 %d = sub <16 x i8> %a, %c 4154 store <16 x i8> %d, ptr %x 4155 ret void 4156} 4157 4158define void @sub_vx_v8i16(ptr %x, i16 %y) { 4159; CHECK-LABEL: sub_vx_v8i16: 4160; CHECK: # %bb.0: 4161; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4162; CHECK-NEXT: vle16.v v8, (a0) 4163; CHECK-NEXT: vsub.vx v8, v8, a1 4164; CHECK-NEXT: vse16.v v8, (a0) 4165; CHECK-NEXT: ret 4166 %a = load <8 x i16>, ptr %x 4167 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4168 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4169 %d = sub <8 x i16> %a, %c 4170 store <8 x i16> %d, ptr %x 4171 ret void 4172} 4173 4174define void @sub_vx_v4i32(ptr %x, i32 %y) { 4175; CHECK-LABEL: sub_vx_v4i32: 4176; CHECK: # %bb.0: 4177; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4178; CHECK-NEXT: vle32.v v8, (a0) 4179; CHECK-NEXT: vsub.vx v8, v8, a1 4180; CHECK-NEXT: vse32.v v8, (a0) 4181; CHECK-NEXT: ret 4182 %a = load <4 x i32>, ptr %x 4183 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4184 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4185 %d = sub <4 x i32> %a, %c 4186 store <4 x i32> %d, ptr %x 4187 ret void 4188} 4189 4190define void @sub_xv_v16i8(ptr %x, i8 %y) { 4191; CHECK-LABEL: sub_xv_v16i8: 4192; CHECK: # %bb.0: 4193; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4194; CHECK-NEXT: vle8.v v8, (a0) 4195; CHECK-NEXT: vrsub.vx v8, v8, a1 4196; CHECK-NEXT: vse8.v v8, (a0) 4197; CHECK-NEXT: ret 4198 %a = load <16 x i8>, ptr %x 4199 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4200 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4201 %d = sub <16 x i8> %c, %a 4202 store <16 x i8> %d, ptr %x 4203 ret void 4204} 4205 4206define void @sub_xv_v8i16(ptr %x, i16 %y) { 4207; CHECK-LABEL: sub_xv_v8i16: 4208; CHECK: # %bb.0: 4209; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4210; CHECK-NEXT: vle16.v v8, (a0) 4211; CHECK-NEXT: vrsub.vx v8, v8, a1 4212; CHECK-NEXT: vse16.v v8, (a0) 4213; CHECK-NEXT: ret 4214 %a = load <8 x i16>, ptr %x 4215 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4216 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4217 %d = sub <8 x i16> %c, %a 4218 store <8 x i16> %d, ptr %x 4219 ret void 4220} 4221 4222define void @sub_xv_v4i32(ptr %x, i32 %y) { 4223; CHECK-LABEL: sub_xv_v4i32: 4224; CHECK: # %bb.0: 4225; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4226; CHECK-NEXT: vle32.v v8, (a0) 4227; CHECK-NEXT: vrsub.vx v8, v8, a1 4228; CHECK-NEXT: vse32.v v8, (a0) 4229; CHECK-NEXT: ret 4230 %a = load <4 x i32>, ptr %x 4231 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4232 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4233 %d = sub <4 x i32> %c, %a 4234 store <4 x i32> %d, ptr %x 4235 ret void 4236} 4237 4238define void @mul_vx_v16i8(ptr %x, i8 %y) { 4239; CHECK-LABEL: mul_vx_v16i8: 4240; CHECK: # %bb.0: 4241; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4242; CHECK-NEXT: vle8.v v8, (a0) 4243; CHECK-NEXT: vmul.vx v8, v8, a1 4244; CHECK-NEXT: vse8.v v8, (a0) 4245; CHECK-NEXT: ret 4246 %a = load <16 x i8>, ptr %x 4247 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4248 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4249 %d = mul <16 x i8> %a, %c 4250 store <16 x i8> %d, ptr %x 4251 ret void 4252} 4253 4254define void @mul_vx_v8i16(ptr %x, i16 %y) { 4255; CHECK-LABEL: mul_vx_v8i16: 4256; CHECK: # %bb.0: 4257; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4258; CHECK-NEXT: vle16.v v8, (a0) 4259; CHECK-NEXT: vmul.vx v8, v8, a1 4260; CHECK-NEXT: vse16.v v8, (a0) 4261; CHECK-NEXT: ret 4262 %a = load <8 x i16>, ptr %x 4263 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4264 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4265 %d = mul <8 x i16> %a, %c 4266 store <8 x i16> %d, ptr %x 4267 ret void 4268} 4269 4270define void @mul_vx_v4i32(ptr %x, i32 %y) { 4271; CHECK-LABEL: mul_vx_v4i32: 4272; CHECK: # %bb.0: 4273; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4274; CHECK-NEXT: vle32.v v8, (a0) 4275; CHECK-NEXT: vmul.vx v8, v8, a1 4276; CHECK-NEXT: vse32.v v8, (a0) 4277; CHECK-NEXT: ret 4278 %a = load <4 x i32>, ptr %x 4279 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4280 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4281 %d = mul <4 x i32> %a, %c 4282 store <4 x i32> %d, ptr %x 4283 ret void 4284} 4285 4286define void @mul_xv_v16i8(ptr %x, i8 %y) { 4287; CHECK-LABEL: mul_xv_v16i8: 4288; CHECK: # %bb.0: 4289; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4290; CHECK-NEXT: vle8.v v8, (a0) 4291; CHECK-NEXT: vmul.vx v8, v8, a1 4292; CHECK-NEXT: vse8.v v8, (a0) 4293; CHECK-NEXT: ret 4294 %a = load <16 x i8>, ptr %x 4295 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4296 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4297 %d = mul <16 x i8> %c, %a 4298 store <16 x i8> %d, ptr %x 4299 ret void 4300} 4301 4302define void @mul_xv_v8i16(ptr %x, i16 %y) { 4303; CHECK-LABEL: mul_xv_v8i16: 4304; CHECK: # %bb.0: 4305; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4306; CHECK-NEXT: vle16.v v8, (a0) 4307; CHECK-NEXT: vmul.vx v8, v8, a1 4308; CHECK-NEXT: vse16.v v8, (a0) 4309; CHECK-NEXT: ret 4310 %a = load <8 x i16>, ptr %x 4311 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4312 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4313 %d = mul <8 x i16> %c, %a 4314 store <8 x i16> %d, ptr %x 4315 ret void 4316} 4317 4318define void @mul_xv_v4i32(ptr %x, i32 %y) { 4319; CHECK-LABEL: mul_xv_v4i32: 4320; CHECK: # %bb.0: 4321; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4322; CHECK-NEXT: vle32.v v8, (a0) 4323; CHECK-NEXT: vmul.vx v8, v8, a1 4324; CHECK-NEXT: vse32.v v8, (a0) 4325; CHECK-NEXT: ret 4326 %a = load <4 x i32>, ptr %x 4327 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4328 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4329 %d = mul <4 x i32> %c, %a 4330 store <4 x i32> %d, ptr %x 4331 ret void 4332} 4333 4334define void @and_vi_v16i8(ptr %x) { 4335; CHECK-LABEL: and_vi_v16i8: 4336; CHECK: # %bb.0: 4337; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4338; CHECK-NEXT: vle8.v v8, (a0) 4339; CHECK-NEXT: vand.vi v8, v8, -2 4340; CHECK-NEXT: vse8.v v8, (a0) 4341; CHECK-NEXT: ret 4342 %a = load <16 x i8>, ptr %x 4343 %d = and <16 x i8> %a, splat (i8 -2) 4344 store <16 x i8> %d, ptr %x 4345 ret void 4346} 4347 4348define void @and_vi_v8i16(ptr %x) { 4349; CHECK-LABEL: and_vi_v8i16: 4350; CHECK: # %bb.0: 4351; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4352; CHECK-NEXT: vle16.v v8, (a0) 4353; CHECK-NEXT: vand.vi v8, v8, -2 4354; CHECK-NEXT: vse16.v v8, (a0) 4355; CHECK-NEXT: ret 4356 %a = load <8 x i16>, ptr %x 4357 %d = and <8 x i16> %a, splat (i16 -2) 4358 store <8 x i16> %d, ptr %x 4359 ret void 4360} 4361 4362define void @and_vi_v4i32(ptr %x) { 4363; CHECK-LABEL: and_vi_v4i32: 4364; CHECK: # %bb.0: 4365; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4366; CHECK-NEXT: vle32.v v8, (a0) 4367; CHECK-NEXT: vand.vi v8, v8, -2 4368; CHECK-NEXT: vse32.v v8, (a0) 4369; CHECK-NEXT: ret 4370 %a = load <4 x i32>, ptr %x 4371 %d = and <4 x i32> %a, splat (i32 -2) 4372 store <4 x i32> %d, ptr %x 4373 ret void 4374} 4375 4376define void @and_vi_v2i64(ptr %x) { 4377; CHECK-LABEL: and_vi_v2i64: 4378; CHECK: # %bb.0: 4379; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4380; CHECK-NEXT: vle64.v v8, (a0) 4381; CHECK-NEXT: vand.vi v8, v8, -2 4382; CHECK-NEXT: vse64.v v8, (a0) 4383; CHECK-NEXT: ret 4384 %a = load <2 x i64>, ptr %x 4385 %d = and <2 x i64> %a, splat (i64 -2) 4386 store <2 x i64> %d, ptr %x 4387 ret void 4388} 4389 4390define void @and_iv_v16i8(ptr %x) { 4391; CHECK-LABEL: and_iv_v16i8: 4392; CHECK: # %bb.0: 4393; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4394; CHECK-NEXT: vle8.v v8, (a0) 4395; CHECK-NEXT: vand.vi v8, v8, 1 4396; CHECK-NEXT: vse8.v v8, (a0) 4397; CHECK-NEXT: ret 4398 %a = load <16 x i8>, ptr %x 4399 %d = and <16 x i8> splat (i8 1), %a 4400 store <16 x i8> %d, ptr %x 4401 ret void 4402} 4403 4404define void @and_iv_v8i16(ptr %x) { 4405; CHECK-LABEL: and_iv_v8i16: 4406; CHECK: # %bb.0: 4407; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4408; CHECK-NEXT: vle16.v v8, (a0) 4409; CHECK-NEXT: vand.vi v8, v8, 1 4410; CHECK-NEXT: vse16.v v8, (a0) 4411; CHECK-NEXT: ret 4412 %a = load <8 x i16>, ptr %x 4413 %d = and <8 x i16> splat (i16 1), %a 4414 store <8 x i16> %d, ptr %x 4415 ret void 4416} 4417 4418define void @and_iv_v4i32(ptr %x) { 4419; CHECK-LABEL: and_iv_v4i32: 4420; CHECK: # %bb.0: 4421; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4422; CHECK-NEXT: vle32.v v8, (a0) 4423; CHECK-NEXT: vand.vi v8, v8, 1 4424; CHECK-NEXT: vse32.v v8, (a0) 4425; CHECK-NEXT: ret 4426 %a = load <4 x i32>, ptr %x 4427 %d = and <4 x i32> splat (i32 1), %a 4428 store <4 x i32> %d, ptr %x 4429 ret void 4430} 4431 4432define void @and_iv_v2i64(ptr %x) { 4433; CHECK-LABEL: and_iv_v2i64: 4434; CHECK: # %bb.0: 4435; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4436; CHECK-NEXT: vle64.v v8, (a0) 4437; CHECK-NEXT: vand.vi v8, v8, 1 4438; CHECK-NEXT: vse64.v v8, (a0) 4439; CHECK-NEXT: ret 4440 %a = load <2 x i64>, ptr %x 4441 %d = and <2 x i64> splat (i64 1), %a 4442 store <2 x i64> %d, ptr %x 4443 ret void 4444} 4445 4446define void @and_vx_v16i8(ptr %x, i8 %y) { 4447; CHECK-LABEL: and_vx_v16i8: 4448; CHECK: # %bb.0: 4449; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4450; CHECK-NEXT: vle8.v v8, (a0) 4451; CHECK-NEXT: vand.vx v8, v8, a1 4452; CHECK-NEXT: vse8.v v8, (a0) 4453; CHECK-NEXT: ret 4454 %a = load <16 x i8>, ptr %x 4455 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4456 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4457 %d = and <16 x i8> %a, %c 4458 store <16 x i8> %d, ptr %x 4459 ret void 4460} 4461 4462define void @and_vx_v8i16(ptr %x, i16 %y) { 4463; CHECK-LABEL: and_vx_v8i16: 4464; CHECK: # %bb.0: 4465; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4466; CHECK-NEXT: vle16.v v8, (a0) 4467; CHECK-NEXT: vand.vx v8, v8, a1 4468; CHECK-NEXT: vse16.v v8, (a0) 4469; CHECK-NEXT: ret 4470 %a = load <8 x i16>, ptr %x 4471 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4472 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4473 %d = and <8 x i16> %a, %c 4474 store <8 x i16> %d, ptr %x 4475 ret void 4476} 4477 4478define void @and_vx_v4i32(ptr %x, i32 %y) { 4479; CHECK-LABEL: and_vx_v4i32: 4480; CHECK: # %bb.0: 4481; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4482; CHECK-NEXT: vle32.v v8, (a0) 4483; CHECK-NEXT: vand.vx v8, v8, a1 4484; CHECK-NEXT: vse32.v v8, (a0) 4485; CHECK-NEXT: ret 4486 %a = load <4 x i32>, ptr %x 4487 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4488 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4489 %d = and <4 x i32> %a, %c 4490 store <4 x i32> %d, ptr %x 4491 ret void 4492} 4493 4494define void @and_xv_v16i8(ptr %x, i8 %y) { 4495; CHECK-LABEL: and_xv_v16i8: 4496; CHECK: # %bb.0: 4497; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4498; CHECK-NEXT: vle8.v v8, (a0) 4499; CHECK-NEXT: vand.vx v8, v8, a1 4500; CHECK-NEXT: vse8.v v8, (a0) 4501; CHECK-NEXT: ret 4502 %a = load <16 x i8>, ptr %x 4503 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4504 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4505 %d = and <16 x i8> %c, %a 4506 store <16 x i8> %d, ptr %x 4507 ret void 4508} 4509 4510define void @and_xv_v8i16(ptr %x, i16 %y) { 4511; CHECK-LABEL: and_xv_v8i16: 4512; CHECK: # %bb.0: 4513; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4514; CHECK-NEXT: vle16.v v8, (a0) 4515; CHECK-NEXT: vand.vx v8, v8, a1 4516; CHECK-NEXT: vse16.v v8, (a0) 4517; CHECK-NEXT: ret 4518 %a = load <8 x i16>, ptr %x 4519 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4520 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4521 %d = and <8 x i16> %c, %a 4522 store <8 x i16> %d, ptr %x 4523 ret void 4524} 4525 4526define void @and_xv_v4i32(ptr %x, i32 %y) { 4527; CHECK-LABEL: and_xv_v4i32: 4528; CHECK: # %bb.0: 4529; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4530; CHECK-NEXT: vle32.v v8, (a0) 4531; CHECK-NEXT: vand.vx v8, v8, a1 4532; CHECK-NEXT: vse32.v v8, (a0) 4533; CHECK-NEXT: ret 4534 %a = load <4 x i32>, ptr %x 4535 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4536 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4537 %d = and <4 x i32> %c, %a 4538 store <4 x i32> %d, ptr %x 4539 ret void 4540} 4541 4542define void @or_vi_v16i8(ptr %x) { 4543; CHECK-LABEL: or_vi_v16i8: 4544; CHECK: # %bb.0: 4545; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4546; CHECK-NEXT: vle8.v v8, (a0) 4547; CHECK-NEXT: vor.vi v8, v8, -2 4548; CHECK-NEXT: vse8.v v8, (a0) 4549; CHECK-NEXT: ret 4550 %a = load <16 x i8>, ptr %x 4551 %d = or <16 x i8> %a, splat (i8 -2) 4552 store <16 x i8> %d, ptr %x 4553 ret void 4554} 4555 4556define void @or_vi_v8i16(ptr %x) { 4557; CHECK-LABEL: or_vi_v8i16: 4558; CHECK: # %bb.0: 4559; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4560; CHECK-NEXT: vle16.v v8, (a0) 4561; CHECK-NEXT: vor.vi v8, v8, -2 4562; CHECK-NEXT: vse16.v v8, (a0) 4563; CHECK-NEXT: ret 4564 %a = load <8 x i16>, ptr %x 4565 %d = or <8 x i16> %a, splat (i16 -2) 4566 store <8 x i16> %d, ptr %x 4567 ret void 4568} 4569 4570define void @or_vi_v4i32(ptr %x) { 4571; CHECK-LABEL: or_vi_v4i32: 4572; CHECK: # %bb.0: 4573; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4574; CHECK-NEXT: vle32.v v8, (a0) 4575; CHECK-NEXT: vor.vi v8, v8, -2 4576; CHECK-NEXT: vse32.v v8, (a0) 4577; CHECK-NEXT: ret 4578 %a = load <4 x i32>, ptr %x 4579 %d = or <4 x i32> %a, splat (i32 -2) 4580 store <4 x i32> %d, ptr %x 4581 ret void 4582} 4583 4584define void @or_vi_v2i64(ptr %x) { 4585; CHECK-LABEL: or_vi_v2i64: 4586; CHECK: # %bb.0: 4587; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4588; CHECK-NEXT: vle64.v v8, (a0) 4589; CHECK-NEXT: vor.vi v8, v8, -2 4590; CHECK-NEXT: vse64.v v8, (a0) 4591; CHECK-NEXT: ret 4592 %a = load <2 x i64>, ptr %x 4593 %d = or <2 x i64> %a, splat (i64 -2) 4594 store <2 x i64> %d, ptr %x 4595 ret void 4596} 4597 4598define void @or_iv_v16i8(ptr %x) { 4599; CHECK-LABEL: or_iv_v16i8: 4600; CHECK: # %bb.0: 4601; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4602; CHECK-NEXT: vle8.v v8, (a0) 4603; CHECK-NEXT: vor.vi v8, v8, 1 4604; CHECK-NEXT: vse8.v v8, (a0) 4605; CHECK-NEXT: ret 4606 %a = load <16 x i8>, ptr %x 4607 %d = or <16 x i8> splat (i8 1), %a 4608 store <16 x i8> %d, ptr %x 4609 ret void 4610} 4611 4612define void @or_iv_v8i16(ptr %x) { 4613; CHECK-LABEL: or_iv_v8i16: 4614; CHECK: # %bb.0: 4615; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4616; CHECK-NEXT: vle16.v v8, (a0) 4617; CHECK-NEXT: vor.vi v8, v8, 1 4618; CHECK-NEXT: vse16.v v8, (a0) 4619; CHECK-NEXT: ret 4620 %a = load <8 x i16>, ptr %x 4621 %d = or <8 x i16> splat (i16 1), %a 4622 store <8 x i16> %d, ptr %x 4623 ret void 4624} 4625 4626define void @or_iv_v4i32(ptr %x) { 4627; CHECK-LABEL: or_iv_v4i32: 4628; CHECK: # %bb.0: 4629; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4630; CHECK-NEXT: vle32.v v8, (a0) 4631; CHECK-NEXT: vor.vi v8, v8, 1 4632; CHECK-NEXT: vse32.v v8, (a0) 4633; CHECK-NEXT: ret 4634 %a = load <4 x i32>, ptr %x 4635 %d = or <4 x i32> splat (i32 1), %a 4636 store <4 x i32> %d, ptr %x 4637 ret void 4638} 4639 4640define void @or_iv_v2i64(ptr %x) { 4641; CHECK-LABEL: or_iv_v2i64: 4642; CHECK: # %bb.0: 4643; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4644; CHECK-NEXT: vle64.v v8, (a0) 4645; CHECK-NEXT: vor.vi v8, v8, 1 4646; CHECK-NEXT: vse64.v v8, (a0) 4647; CHECK-NEXT: ret 4648 %a = load <2 x i64>, ptr %x 4649 %d = or <2 x i64> splat (i64 1), %a 4650 store <2 x i64> %d, ptr %x 4651 ret void 4652} 4653 4654define void @or_vx_v16i8(ptr %x, i8 %y) { 4655; CHECK-LABEL: or_vx_v16i8: 4656; CHECK: # %bb.0: 4657; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4658; CHECK-NEXT: vle8.v v8, (a0) 4659; CHECK-NEXT: vor.vx v8, v8, a1 4660; CHECK-NEXT: vse8.v v8, (a0) 4661; CHECK-NEXT: ret 4662 %a = load <16 x i8>, ptr %x 4663 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4664 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4665 %d = or <16 x i8> %a, %c 4666 store <16 x i8> %d, ptr %x 4667 ret void 4668} 4669 4670define void @or_vx_v8i16(ptr %x, i16 %y) { 4671; CHECK-LABEL: or_vx_v8i16: 4672; CHECK: # %bb.0: 4673; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4674; CHECK-NEXT: vle16.v v8, (a0) 4675; CHECK-NEXT: vor.vx v8, v8, a1 4676; CHECK-NEXT: vse16.v v8, (a0) 4677; CHECK-NEXT: ret 4678 %a = load <8 x i16>, ptr %x 4679 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4680 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4681 %d = or <8 x i16> %a, %c 4682 store <8 x i16> %d, ptr %x 4683 ret void 4684} 4685 4686define void @or_vx_v4i32(ptr %x, i32 %y) { 4687; CHECK-LABEL: or_vx_v4i32: 4688; CHECK: # %bb.0: 4689; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4690; CHECK-NEXT: vle32.v v8, (a0) 4691; CHECK-NEXT: vor.vx v8, v8, a1 4692; CHECK-NEXT: vse32.v v8, (a0) 4693; CHECK-NEXT: ret 4694 %a = load <4 x i32>, ptr %x 4695 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4696 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4697 %d = or <4 x i32> %a, %c 4698 store <4 x i32> %d, ptr %x 4699 ret void 4700} 4701 4702define void @or_xv_v16i8(ptr %x, i8 %y) { 4703; CHECK-LABEL: or_xv_v16i8: 4704; CHECK: # %bb.0: 4705; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4706; CHECK-NEXT: vle8.v v8, (a0) 4707; CHECK-NEXT: vor.vx v8, v8, a1 4708; CHECK-NEXT: vse8.v v8, (a0) 4709; CHECK-NEXT: ret 4710 %a = load <16 x i8>, ptr %x 4711 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4712 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4713 %d = or <16 x i8> %c, %a 4714 store <16 x i8> %d, ptr %x 4715 ret void 4716} 4717 4718define void @or_xv_v8i16(ptr %x, i16 %y) { 4719; CHECK-LABEL: or_xv_v8i16: 4720; CHECK: # %bb.0: 4721; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4722; CHECK-NEXT: vle16.v v8, (a0) 4723; CHECK-NEXT: vor.vx v8, v8, a1 4724; CHECK-NEXT: vse16.v v8, (a0) 4725; CHECK-NEXT: ret 4726 %a = load <8 x i16>, ptr %x 4727 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4728 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4729 %d = or <8 x i16> %c, %a 4730 store <8 x i16> %d, ptr %x 4731 ret void 4732} 4733 4734define void @or_xv_v4i32(ptr %x, i32 %y) { 4735; CHECK-LABEL: or_xv_v4i32: 4736; CHECK: # %bb.0: 4737; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4738; CHECK-NEXT: vle32.v v8, (a0) 4739; CHECK-NEXT: vor.vx v8, v8, a1 4740; CHECK-NEXT: vse32.v v8, (a0) 4741; CHECK-NEXT: ret 4742 %a = load <4 x i32>, ptr %x 4743 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4744 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4745 %d = or <4 x i32> %c, %a 4746 store <4 x i32> %d, ptr %x 4747 ret void 4748} 4749 4750define void @xor_vi_v16i8(ptr %x) { 4751; CHECK-LABEL: xor_vi_v16i8: 4752; CHECK: # %bb.0: 4753; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4754; CHECK-NEXT: vle8.v v8, (a0) 4755; CHECK-NEXT: vnot.v v8, v8 4756; CHECK-NEXT: vse8.v v8, (a0) 4757; CHECK-NEXT: ret 4758 %a = load <16 x i8>, ptr %x 4759 %d = xor <16 x i8> %a, splat (i8 -1) 4760 store <16 x i8> %d, ptr %x 4761 ret void 4762} 4763 4764define void @xor_vi_v8i16(ptr %x) { 4765; CHECK-LABEL: xor_vi_v8i16: 4766; CHECK: # %bb.0: 4767; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4768; CHECK-NEXT: vle16.v v8, (a0) 4769; CHECK-NEXT: vnot.v v8, v8 4770; CHECK-NEXT: vse16.v v8, (a0) 4771; CHECK-NEXT: ret 4772 %a = load <8 x i16>, ptr %x 4773 %d = xor <8 x i16> %a, splat (i16 -1) 4774 store <8 x i16> %d, ptr %x 4775 ret void 4776} 4777 4778define void @xor_vi_v4i32(ptr %x) { 4779; CHECK-LABEL: xor_vi_v4i32: 4780; CHECK: # %bb.0: 4781; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4782; CHECK-NEXT: vle32.v v8, (a0) 4783; CHECK-NEXT: vnot.v v8, v8 4784; CHECK-NEXT: vse32.v v8, (a0) 4785; CHECK-NEXT: ret 4786 %a = load <4 x i32>, ptr %x 4787 %d = xor <4 x i32> %a, splat (i32 -1) 4788 store <4 x i32> %d, ptr %x 4789 ret void 4790} 4791 4792define void @xor_vi_v2i64(ptr %x) { 4793; CHECK-LABEL: xor_vi_v2i64: 4794; CHECK: # %bb.0: 4795; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4796; CHECK-NEXT: vle64.v v8, (a0) 4797; CHECK-NEXT: vnot.v v8, v8 4798; CHECK-NEXT: vse64.v v8, (a0) 4799; CHECK-NEXT: ret 4800 %a = load <2 x i64>, ptr %x 4801 %d = xor <2 x i64> %a, splat (i64 -1) 4802 store <2 x i64> %d, ptr %x 4803 ret void 4804} 4805 4806define void @xor_iv_v16i8(ptr %x) { 4807; CHECK-LABEL: xor_iv_v16i8: 4808; CHECK: # %bb.0: 4809; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4810; CHECK-NEXT: vle8.v v8, (a0) 4811; CHECK-NEXT: vxor.vi v8, v8, 1 4812; CHECK-NEXT: vse8.v v8, (a0) 4813; CHECK-NEXT: ret 4814 %a = load <16 x i8>, ptr %x 4815 %d = xor <16 x i8> splat (i8 1), %a 4816 store <16 x i8> %d, ptr %x 4817 ret void 4818} 4819 4820define void @xor_iv_v8i16(ptr %x) { 4821; CHECK-LABEL: xor_iv_v8i16: 4822; CHECK: # %bb.0: 4823; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4824; CHECK-NEXT: vle16.v v8, (a0) 4825; CHECK-NEXT: vxor.vi v8, v8, 1 4826; CHECK-NEXT: vse16.v v8, (a0) 4827; CHECK-NEXT: ret 4828 %a = load <8 x i16>, ptr %x 4829 %d = xor <8 x i16> splat (i16 1), %a 4830 store <8 x i16> %d, ptr %x 4831 ret void 4832} 4833 4834define void @xor_iv_v4i32(ptr %x) { 4835; CHECK-LABEL: xor_iv_v4i32: 4836; CHECK: # %bb.0: 4837; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4838; CHECK-NEXT: vle32.v v8, (a0) 4839; CHECK-NEXT: vxor.vi v8, v8, 1 4840; CHECK-NEXT: vse32.v v8, (a0) 4841; CHECK-NEXT: ret 4842 %a = load <4 x i32>, ptr %x 4843 %d = xor <4 x i32> splat (i32 1), %a 4844 store <4 x i32> %d, ptr %x 4845 ret void 4846} 4847 4848define void @xor_iv_v2i64(ptr %x) { 4849; CHECK-LABEL: xor_iv_v2i64: 4850; CHECK: # %bb.0: 4851; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 4852; CHECK-NEXT: vle64.v v8, (a0) 4853; CHECK-NEXT: vxor.vi v8, v8, 1 4854; CHECK-NEXT: vse64.v v8, (a0) 4855; CHECK-NEXT: ret 4856 %a = load <2 x i64>, ptr %x 4857 %d = xor <2 x i64> splat (i64 1), %a 4858 store <2 x i64> %d, ptr %x 4859 ret void 4860} 4861 4862define void @xor_vx_v16i8(ptr %x, i8 %y) { 4863; CHECK-LABEL: xor_vx_v16i8: 4864; CHECK: # %bb.0: 4865; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4866; CHECK-NEXT: vle8.v v8, (a0) 4867; CHECK-NEXT: vxor.vx v8, v8, a1 4868; CHECK-NEXT: vse8.v v8, (a0) 4869; CHECK-NEXT: ret 4870 %a = load <16 x i8>, ptr %x 4871 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4872 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4873 %d = xor <16 x i8> %a, %c 4874 store <16 x i8> %d, ptr %x 4875 ret void 4876} 4877 4878define void @xor_vx_v8i16(ptr %x, i16 %y) { 4879; CHECK-LABEL: xor_vx_v8i16: 4880; CHECK: # %bb.0: 4881; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4882; CHECK-NEXT: vle16.v v8, (a0) 4883; CHECK-NEXT: vxor.vx v8, v8, a1 4884; CHECK-NEXT: vse16.v v8, (a0) 4885; CHECK-NEXT: ret 4886 %a = load <8 x i16>, ptr %x 4887 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4888 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4889 %d = xor <8 x i16> %a, %c 4890 store <8 x i16> %d, ptr %x 4891 ret void 4892} 4893 4894define void @xor_vx_v4i32(ptr %x, i32 %y) { 4895; CHECK-LABEL: xor_vx_v4i32: 4896; CHECK: # %bb.0: 4897; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4898; CHECK-NEXT: vle32.v v8, (a0) 4899; CHECK-NEXT: vxor.vx v8, v8, a1 4900; CHECK-NEXT: vse32.v v8, (a0) 4901; CHECK-NEXT: ret 4902 %a = load <4 x i32>, ptr %x 4903 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4904 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4905 %d = xor <4 x i32> %a, %c 4906 store <4 x i32> %d, ptr %x 4907 ret void 4908} 4909 4910define void @xor_xv_v16i8(ptr %x, i8 %y) { 4911; CHECK-LABEL: xor_xv_v16i8: 4912; CHECK: # %bb.0: 4913; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4914; CHECK-NEXT: vle8.v v8, (a0) 4915; CHECK-NEXT: vxor.vx v8, v8, a1 4916; CHECK-NEXT: vse8.v v8, (a0) 4917; CHECK-NEXT: ret 4918 %a = load <16 x i8>, ptr %x 4919 %b = insertelement <16 x i8> poison, i8 %y, i32 0 4920 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 4921 %d = xor <16 x i8> %c, %a 4922 store <16 x i8> %d, ptr %x 4923 ret void 4924} 4925 4926define void @xor_xv_v8i16(ptr %x, i16 %y) { 4927; CHECK-LABEL: xor_xv_v8i16: 4928; CHECK: # %bb.0: 4929; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4930; CHECK-NEXT: vle16.v v8, (a0) 4931; CHECK-NEXT: vxor.vx v8, v8, a1 4932; CHECK-NEXT: vse16.v v8, (a0) 4933; CHECK-NEXT: ret 4934 %a = load <8 x i16>, ptr %x 4935 %b = insertelement <8 x i16> poison, i16 %y, i32 0 4936 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 4937 %d = xor <8 x i16> %c, %a 4938 store <8 x i16> %d, ptr %x 4939 ret void 4940} 4941 4942define void @xor_xv_v4i32(ptr %x, i32 %y) { 4943; CHECK-LABEL: xor_xv_v4i32: 4944; CHECK: # %bb.0: 4945; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4946; CHECK-NEXT: vle32.v v8, (a0) 4947; CHECK-NEXT: vxor.vx v8, v8, a1 4948; CHECK-NEXT: vse32.v v8, (a0) 4949; CHECK-NEXT: ret 4950 %a = load <4 x i32>, ptr %x 4951 %b = insertelement <4 x i32> poison, i32 %y, i32 0 4952 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 4953 %d = xor <4 x i32> %c, %a 4954 store <4 x i32> %d, ptr %x 4955 ret void 4956} 4957 4958define void @lshr_vi_v16i8(ptr %x) { 4959; CHECK-LABEL: lshr_vi_v16i8: 4960; CHECK: # %bb.0: 4961; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 4962; CHECK-NEXT: vle8.v v8, (a0) 4963; CHECK-NEXT: vsrl.vi v8, v8, 7 4964; CHECK-NEXT: vse8.v v8, (a0) 4965; CHECK-NEXT: ret 4966 %a = load <16 x i8>, ptr %x 4967 %d = lshr <16 x i8> %a, splat (i8 7) 4968 store <16 x i8> %d, ptr %x 4969 ret void 4970} 4971 4972define void @lshr_vi_v8i16(ptr %x) { 4973; CHECK-LABEL: lshr_vi_v8i16: 4974; CHECK: # %bb.0: 4975; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 4976; CHECK-NEXT: vle16.v v8, (a0) 4977; CHECK-NEXT: vsrl.vi v8, v8, 15 4978; CHECK-NEXT: vse16.v v8, (a0) 4979; CHECK-NEXT: ret 4980 %a = load <8 x i16>, ptr %x 4981 %d = lshr <8 x i16> %a, splat (i16 15) 4982 store <8 x i16> %d, ptr %x 4983 ret void 4984} 4985 4986define void @lshr_vi_v4i32(ptr %x) { 4987; CHECK-LABEL: lshr_vi_v4i32: 4988; CHECK: # %bb.0: 4989; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 4990; CHECK-NEXT: vle32.v v8, (a0) 4991; CHECK-NEXT: vsrl.vi v8, v8, 31 4992; CHECK-NEXT: vse32.v v8, (a0) 4993; CHECK-NEXT: ret 4994 %a = load <4 x i32>, ptr %x 4995 %d = lshr <4 x i32> %a, splat (i32 31) 4996 store <4 x i32> %d, ptr %x 4997 ret void 4998} 4999 5000define void @lshr_vi_v2i64(ptr %x) { 5001; CHECK-LABEL: lshr_vi_v2i64: 5002; CHECK: # %bb.0: 5003; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5004; CHECK-NEXT: vle64.v v8, (a0) 5005; CHECK-NEXT: vsrl.vi v8, v8, 31 5006; CHECK-NEXT: vse64.v v8, (a0) 5007; CHECK-NEXT: ret 5008 %a = load <2 x i64>, ptr %x 5009 %d = lshr <2 x i64> %a, splat (i64 31) 5010 store <2 x i64> %d, ptr %x 5011 ret void 5012} 5013 5014define void @lshr_vx_v16i8(ptr %x, i8 %y) { 5015; CHECK-LABEL: lshr_vx_v16i8: 5016; CHECK: # %bb.0: 5017; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5018; CHECK-NEXT: vle8.v v8, (a0) 5019; CHECK-NEXT: vsrl.vx v8, v8, a1 5020; CHECK-NEXT: vse8.v v8, (a0) 5021; CHECK-NEXT: ret 5022 %a = load <16 x i8>, ptr %x 5023 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5024 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5025 %d = lshr <16 x i8> %a, %c 5026 store <16 x i8> %d, ptr %x 5027 ret void 5028} 5029 5030define void @lshr_vx_v8i16(ptr %x, i16 %y) { 5031; CHECK-LABEL: lshr_vx_v8i16: 5032; CHECK: # %bb.0: 5033; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5034; CHECK-NEXT: vle16.v v8, (a0) 5035; CHECK-NEXT: vsrl.vx v8, v8, a1 5036; CHECK-NEXT: vse16.v v8, (a0) 5037; CHECK-NEXT: ret 5038 %a = load <8 x i16>, ptr %x 5039 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5040 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5041 %d = lshr <8 x i16> %a, %c 5042 store <8 x i16> %d, ptr %x 5043 ret void 5044} 5045 5046define void @lshr_vx_v4i32(ptr %x, i32 %y) { 5047; CHECK-LABEL: lshr_vx_v4i32: 5048; CHECK: # %bb.0: 5049; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5050; CHECK-NEXT: vle32.v v8, (a0) 5051; CHECK-NEXT: vsrl.vx v8, v8, a1 5052; CHECK-NEXT: vse32.v v8, (a0) 5053; CHECK-NEXT: ret 5054 %a = load <4 x i32>, ptr %x 5055 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5056 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5057 %d = lshr <4 x i32> %a, %c 5058 store <4 x i32> %d, ptr %x 5059 ret void 5060} 5061 5062define void @ashr_vi_v16i8(ptr %x) { 5063; CHECK-LABEL: ashr_vi_v16i8: 5064; CHECK: # %bb.0: 5065; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5066; CHECK-NEXT: vle8.v v8, (a0) 5067; CHECK-NEXT: vsra.vi v8, v8, 7 5068; CHECK-NEXT: vse8.v v8, (a0) 5069; CHECK-NEXT: ret 5070 %a = load <16 x i8>, ptr %x 5071 %d = ashr <16 x i8> %a, splat (i8 7) 5072 store <16 x i8> %d, ptr %x 5073 ret void 5074} 5075 5076define void @ashr_vi_v8i16(ptr %x) { 5077; CHECK-LABEL: ashr_vi_v8i16: 5078; CHECK: # %bb.0: 5079; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5080; CHECK-NEXT: vle16.v v8, (a0) 5081; CHECK-NEXT: vsra.vi v8, v8, 15 5082; CHECK-NEXT: vse16.v v8, (a0) 5083; CHECK-NEXT: ret 5084 %a = load <8 x i16>, ptr %x 5085 %d = ashr <8 x i16> %a, splat (i16 15) 5086 store <8 x i16> %d, ptr %x 5087 ret void 5088} 5089 5090define void @ashr_vi_v4i32(ptr %x) { 5091; CHECK-LABEL: ashr_vi_v4i32: 5092; CHECK: # %bb.0: 5093; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5094; CHECK-NEXT: vle32.v v8, (a0) 5095; CHECK-NEXT: vsra.vi v8, v8, 31 5096; CHECK-NEXT: vse32.v v8, (a0) 5097; CHECK-NEXT: ret 5098 %a = load <4 x i32>, ptr %x 5099 %d = ashr <4 x i32> %a, splat (i32 31) 5100 store <4 x i32> %d, ptr %x 5101 ret void 5102} 5103 5104define void @ashr_vi_v2i64(ptr %x) { 5105; CHECK-LABEL: ashr_vi_v2i64: 5106; CHECK: # %bb.0: 5107; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5108; CHECK-NEXT: vle64.v v8, (a0) 5109; CHECK-NEXT: vsra.vi v8, v8, 31 5110; CHECK-NEXT: vse64.v v8, (a0) 5111; CHECK-NEXT: ret 5112 %a = load <2 x i64>, ptr %x 5113 %d = ashr <2 x i64> %a, splat (i64 31) 5114 store <2 x i64> %d, ptr %x 5115 ret void 5116} 5117 5118define void @ashr_vx_v16i8(ptr %x, i8 %y) { 5119; CHECK-LABEL: ashr_vx_v16i8: 5120; CHECK: # %bb.0: 5121; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5122; CHECK-NEXT: vle8.v v8, (a0) 5123; CHECK-NEXT: vsra.vx v8, v8, a1 5124; CHECK-NEXT: vse8.v v8, (a0) 5125; CHECK-NEXT: ret 5126 %a = load <16 x i8>, ptr %x 5127 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5128 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5129 %d = ashr <16 x i8> %a, %c 5130 store <16 x i8> %d, ptr %x 5131 ret void 5132} 5133 5134define void @ashr_vx_v8i16(ptr %x, i16 %y) { 5135; CHECK-LABEL: ashr_vx_v8i16: 5136; CHECK: # %bb.0: 5137; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5138; CHECK-NEXT: vle16.v v8, (a0) 5139; CHECK-NEXT: vsra.vx v8, v8, a1 5140; CHECK-NEXT: vse16.v v8, (a0) 5141; CHECK-NEXT: ret 5142 %a = load <8 x i16>, ptr %x 5143 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5144 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5145 %d = ashr <8 x i16> %a, %c 5146 store <8 x i16> %d, ptr %x 5147 ret void 5148} 5149 5150define void @ashr_vx_v4i32(ptr %x, i32 %y) { 5151; CHECK-LABEL: ashr_vx_v4i32: 5152; CHECK: # %bb.0: 5153; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5154; CHECK-NEXT: vle32.v v8, (a0) 5155; CHECK-NEXT: vsra.vx v8, v8, a1 5156; CHECK-NEXT: vse32.v v8, (a0) 5157; CHECK-NEXT: ret 5158 %a = load <4 x i32>, ptr %x 5159 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5160 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5161 %d = ashr <4 x i32> %a, %c 5162 store <4 x i32> %d, ptr %x 5163 ret void 5164} 5165 5166define void @shl_vi_v16i8(ptr %x) { 5167; CHECK-LABEL: shl_vi_v16i8: 5168; CHECK: # %bb.0: 5169; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5170; CHECK-NEXT: vle8.v v8, (a0) 5171; CHECK-NEXT: vsll.vi v8, v8, 7 5172; CHECK-NEXT: vse8.v v8, (a0) 5173; CHECK-NEXT: ret 5174 %a = load <16 x i8>, ptr %x 5175 %d = shl <16 x i8> %a, splat (i8 7) 5176 store <16 x i8> %d, ptr %x 5177 ret void 5178} 5179 5180define void @shl_vi_v8i16(ptr %x) { 5181; CHECK-LABEL: shl_vi_v8i16: 5182; CHECK: # %bb.0: 5183; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5184; CHECK-NEXT: vle16.v v8, (a0) 5185; CHECK-NEXT: vsll.vi v8, v8, 15 5186; CHECK-NEXT: vse16.v v8, (a0) 5187; CHECK-NEXT: ret 5188 %a = load <8 x i16>, ptr %x 5189 %d = shl <8 x i16> %a, splat (i16 15) 5190 store <8 x i16> %d, ptr %x 5191 ret void 5192} 5193 5194define void @shl_vi_v4i32(ptr %x) { 5195; CHECK-LABEL: shl_vi_v4i32: 5196; CHECK: # %bb.0: 5197; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5198; CHECK-NEXT: vle32.v v8, (a0) 5199; CHECK-NEXT: vsll.vi v8, v8, 31 5200; CHECK-NEXT: vse32.v v8, (a0) 5201; CHECK-NEXT: ret 5202 %a = load <4 x i32>, ptr %x 5203 %d = shl <4 x i32> %a, splat (i32 31) 5204 store <4 x i32> %d, ptr %x 5205 ret void 5206} 5207 5208define void @shl_vi_v2i64(ptr %x) { 5209; CHECK-LABEL: shl_vi_v2i64: 5210; CHECK: # %bb.0: 5211; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5212; CHECK-NEXT: vle64.v v8, (a0) 5213; CHECK-NEXT: vsll.vi v8, v8, 31 5214; CHECK-NEXT: vse64.v v8, (a0) 5215; CHECK-NEXT: ret 5216 %a = load <2 x i64>, ptr %x 5217 %d = shl <2 x i64> %a, splat (i64 31) 5218 store <2 x i64> %d, ptr %x 5219 ret void 5220} 5221 5222define void @shl_vx_v16i8(ptr %x, i8 %y) { 5223; CHECK-LABEL: shl_vx_v16i8: 5224; CHECK: # %bb.0: 5225; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5226; CHECK-NEXT: vle8.v v8, (a0) 5227; CHECK-NEXT: vsll.vx v8, v8, a1 5228; CHECK-NEXT: vse8.v v8, (a0) 5229; CHECK-NEXT: ret 5230 %a = load <16 x i8>, ptr %x 5231 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5232 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5233 %d = shl <16 x i8> %a, %c 5234 store <16 x i8> %d, ptr %x 5235 ret void 5236} 5237 5238define void @shl_vx_v8i16(ptr %x, i16 %y) { 5239; CHECK-LABEL: shl_vx_v8i16: 5240; CHECK: # %bb.0: 5241; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5242; CHECK-NEXT: vle16.v v8, (a0) 5243; CHECK-NEXT: vsll.vx v8, v8, a1 5244; CHECK-NEXT: vse16.v v8, (a0) 5245; CHECK-NEXT: ret 5246 %a = load <8 x i16>, ptr %x 5247 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5248 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5249 %d = shl <8 x i16> %a, %c 5250 store <8 x i16> %d, ptr %x 5251 ret void 5252} 5253 5254define void @shl_vx_v4i32(ptr %x, i32 %y) { 5255; CHECK-LABEL: shl_vx_v4i32: 5256; CHECK: # %bb.0: 5257; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5258; CHECK-NEXT: vle32.v v8, (a0) 5259; CHECK-NEXT: vsll.vx v8, v8, a1 5260; CHECK-NEXT: vse32.v v8, (a0) 5261; CHECK-NEXT: ret 5262 %a = load <4 x i32>, ptr %x 5263 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5264 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5265 %d = shl <4 x i32> %a, %c 5266 store <4 x i32> %d, ptr %x 5267 ret void 5268} 5269 5270define void @sdiv_vx_v16i8(ptr %x, i8 %y) { 5271; CHECK-LABEL: sdiv_vx_v16i8: 5272; CHECK: # %bb.0: 5273; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5274; CHECK-NEXT: vle8.v v8, (a0) 5275; CHECK-NEXT: vdiv.vx v8, v8, a1 5276; CHECK-NEXT: vse8.v v8, (a0) 5277; CHECK-NEXT: ret 5278 %a = load <16 x i8>, ptr %x 5279 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5280 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5281 %d = sdiv <16 x i8> %a, %c 5282 store <16 x i8> %d, ptr %x 5283 ret void 5284} 5285 5286define void @sdiv_vx_v8i16(ptr %x, i16 %y) { 5287; CHECK-LABEL: sdiv_vx_v8i16: 5288; CHECK: # %bb.0: 5289; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5290; CHECK-NEXT: vle16.v v8, (a0) 5291; CHECK-NEXT: vdiv.vx v8, v8, a1 5292; CHECK-NEXT: vse16.v v8, (a0) 5293; CHECK-NEXT: ret 5294 %a = load <8 x i16>, ptr %x 5295 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5296 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5297 %d = sdiv <8 x i16> %a, %c 5298 store <8 x i16> %d, ptr %x 5299 ret void 5300} 5301 5302define void @sdiv_vx_v4i32(ptr %x, i32 %y) { 5303; CHECK-LABEL: sdiv_vx_v4i32: 5304; CHECK: # %bb.0: 5305; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5306; CHECK-NEXT: vle32.v v8, (a0) 5307; CHECK-NEXT: vdiv.vx v8, v8, a1 5308; CHECK-NEXT: vse32.v v8, (a0) 5309; CHECK-NEXT: ret 5310 %a = load <4 x i32>, ptr %x 5311 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5312 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5313 %d = sdiv <4 x i32> %a, %c 5314 store <4 x i32> %d, ptr %x 5315 ret void 5316} 5317 5318define void @srem_vx_v16i8(ptr %x, i8 %y) { 5319; CHECK-LABEL: srem_vx_v16i8: 5320; CHECK: # %bb.0: 5321; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5322; CHECK-NEXT: vle8.v v8, (a0) 5323; CHECK-NEXT: vrem.vx v8, v8, a1 5324; CHECK-NEXT: vse8.v v8, (a0) 5325; CHECK-NEXT: ret 5326 %a = load <16 x i8>, ptr %x 5327 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5328 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5329 %d = srem <16 x i8> %a, %c 5330 store <16 x i8> %d, ptr %x 5331 ret void 5332} 5333 5334define void @srem_vx_v8i16(ptr %x, i16 %y) { 5335; CHECK-LABEL: srem_vx_v8i16: 5336; CHECK: # %bb.0: 5337; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5338; CHECK-NEXT: vle16.v v8, (a0) 5339; CHECK-NEXT: vrem.vx v8, v8, a1 5340; CHECK-NEXT: vse16.v v8, (a0) 5341; CHECK-NEXT: ret 5342 %a = load <8 x i16>, ptr %x 5343 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5344 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5345 %d = srem <8 x i16> %a, %c 5346 store <8 x i16> %d, ptr %x 5347 ret void 5348} 5349 5350define void @srem_vx_v4i32(ptr %x, i32 %y) { 5351; CHECK-LABEL: srem_vx_v4i32: 5352; CHECK: # %bb.0: 5353; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5354; CHECK-NEXT: vle32.v v8, (a0) 5355; CHECK-NEXT: vrem.vx v8, v8, a1 5356; CHECK-NEXT: vse32.v v8, (a0) 5357; CHECK-NEXT: ret 5358 %a = load <4 x i32>, ptr %x 5359 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5360 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5361 %d = srem <4 x i32> %a, %c 5362 store <4 x i32> %d, ptr %x 5363 ret void 5364} 5365 5366define void @udiv_vx_v16i8(ptr %x, i8 %y) { 5367; CHECK-LABEL: udiv_vx_v16i8: 5368; CHECK: # %bb.0: 5369; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5370; CHECK-NEXT: vle8.v v8, (a0) 5371; CHECK-NEXT: vdivu.vx v8, v8, a1 5372; CHECK-NEXT: vse8.v v8, (a0) 5373; CHECK-NEXT: ret 5374 %a = load <16 x i8>, ptr %x 5375 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5376 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5377 %d = udiv <16 x i8> %a, %c 5378 store <16 x i8> %d, ptr %x 5379 ret void 5380} 5381 5382define void @udiv_vx_v8i16(ptr %x, i16 %y) { 5383; CHECK-LABEL: udiv_vx_v8i16: 5384; CHECK: # %bb.0: 5385; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5386; CHECK-NEXT: vle16.v v8, (a0) 5387; CHECK-NEXT: vdivu.vx v8, v8, a1 5388; CHECK-NEXT: vse16.v v8, (a0) 5389; CHECK-NEXT: ret 5390 %a = load <8 x i16>, ptr %x 5391 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5392 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5393 %d = udiv <8 x i16> %a, %c 5394 store <8 x i16> %d, ptr %x 5395 ret void 5396} 5397 5398define void @udiv_vx_v4i32(ptr %x, i32 %y) { 5399; CHECK-LABEL: udiv_vx_v4i32: 5400; CHECK: # %bb.0: 5401; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5402; CHECK-NEXT: vle32.v v8, (a0) 5403; CHECK-NEXT: vdivu.vx v8, v8, a1 5404; CHECK-NEXT: vse32.v v8, (a0) 5405; CHECK-NEXT: ret 5406 %a = load <4 x i32>, ptr %x 5407 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5408 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5409 %d = udiv <4 x i32> %a, %c 5410 store <4 x i32> %d, ptr %x 5411 ret void 5412} 5413 5414define void @urem_vx_v16i8(ptr %x, i8 %y) { 5415; CHECK-LABEL: urem_vx_v16i8: 5416; CHECK: # %bb.0: 5417; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5418; CHECK-NEXT: vle8.v v8, (a0) 5419; CHECK-NEXT: vremu.vx v8, v8, a1 5420; CHECK-NEXT: vse8.v v8, (a0) 5421; CHECK-NEXT: ret 5422 %a = load <16 x i8>, ptr %x 5423 %b = insertelement <16 x i8> poison, i8 %y, i32 0 5424 %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer 5425 %d = urem <16 x i8> %a, %c 5426 store <16 x i8> %d, ptr %x 5427 ret void 5428} 5429 5430define void @urem_vx_v8i16(ptr %x, i16 %y) { 5431; CHECK-LABEL: urem_vx_v8i16: 5432; CHECK: # %bb.0: 5433; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5434; CHECK-NEXT: vle16.v v8, (a0) 5435; CHECK-NEXT: vremu.vx v8, v8, a1 5436; CHECK-NEXT: vse16.v v8, (a0) 5437; CHECK-NEXT: ret 5438 %a = load <8 x i16>, ptr %x 5439 %b = insertelement <8 x i16> poison, i16 %y, i32 0 5440 %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer 5441 %d = urem <8 x i16> %a, %c 5442 store <8 x i16> %d, ptr %x 5443 ret void 5444} 5445 5446define void @urem_vx_v4i32(ptr %x, i32 %y) { 5447; CHECK-LABEL: urem_vx_v4i32: 5448; CHECK: # %bb.0: 5449; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5450; CHECK-NEXT: vle32.v v8, (a0) 5451; CHECK-NEXT: vremu.vx v8, v8, a1 5452; CHECK-NEXT: vse32.v v8, (a0) 5453; CHECK-NEXT: ret 5454 %a = load <4 x i32>, ptr %x 5455 %b = insertelement <4 x i32> poison, i32 %y, i32 0 5456 %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer 5457 %d = urem <4 x i32> %a, %c 5458 store <4 x i32> %d, ptr %x 5459 ret void 5460} 5461 5462define void @mulhu_vx_v16i8(ptr %x) { 5463; CHECK-LABEL: mulhu_vx_v16i8: 5464; CHECK: # %bb.0: 5465; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5466; CHECK-NEXT: vle8.v v8, (a0) 5467; CHECK-NEXT: li a1, 57 5468; CHECK-NEXT: vmulhu.vx v8, v8, a1 5469; CHECK-NEXT: vsrl.vi v8, v8, 1 5470; CHECK-NEXT: vse8.v v8, (a0) 5471; CHECK-NEXT: ret 5472 %a = load <16 x i8>, ptr %x 5473 %b = udiv <16 x i8> %a, <i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9, i8 9> 5474 store <16 x i8> %b, ptr %x 5475 ret void 5476} 5477 5478define void @mulhu_vx_v8i16(ptr %x) { 5479; CHECK-LABEL: mulhu_vx_v8i16: 5480; CHECK: # %bb.0: 5481; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5482; CHECK-NEXT: vle16.v v8, (a0) 5483; CHECK-NEXT: lui a1, 2 5484; CHECK-NEXT: addi a1, a1, 1171 5485; CHECK-NEXT: vmulhu.vx v9, v8, a1 5486; CHECK-NEXT: vsub.vv v8, v8, v9 5487; CHECK-NEXT: vsrl.vi v8, v8, 1 5488; CHECK-NEXT: vadd.vv v8, v8, v9 5489; CHECK-NEXT: vsrl.vi v8, v8, 2 5490; CHECK-NEXT: vse16.v v8, (a0) 5491; CHECK-NEXT: ret 5492 %a = load <8 x i16>, ptr %x 5493 %b = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> 5494 store <8 x i16> %b, ptr %x 5495 ret void 5496} 5497 5498define void @mulhu_vx_v4i32(ptr %x) { 5499; CHECK-LABEL: mulhu_vx_v4i32: 5500; CHECK: # %bb.0: 5501; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5502; CHECK-NEXT: vle32.v v8, (a0) 5503; CHECK-NEXT: lui a1, 838861 5504; CHECK-NEXT: addi a1, a1, -819 5505; CHECK-NEXT: vmulhu.vx v8, v8, a1 5506; CHECK-NEXT: vsrl.vi v8, v8, 2 5507; CHECK-NEXT: vse32.v v8, (a0) 5508; CHECK-NEXT: ret 5509 %a = load <4 x i32>, ptr %x 5510 %b = udiv <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5> 5511 store <4 x i32> %b, ptr %x 5512 ret void 5513} 5514 5515define void @mulhu_vx_v2i64(ptr %x) { 5516; RV32-LABEL: mulhu_vx_v2i64: 5517; RV32: # %bb.0: 5518; RV32-NEXT: addi sp, sp, -16 5519; RV32-NEXT: .cfi_def_cfa_offset 16 5520; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5521; RV32-NEXT: vle64.v v8, (a0) 5522; RV32-NEXT: lui a1, 699051 5523; RV32-NEXT: addi a2, a1, -1366 5524; RV32-NEXT: addi a1, a1, -1365 5525; RV32-NEXT: sw a1, 8(sp) 5526; RV32-NEXT: sw a2, 12(sp) 5527; RV32-NEXT: addi a1, sp, 8 5528; RV32-NEXT: vlse64.v v9, (a1), zero 5529; RV32-NEXT: vmulhu.vv v8, v8, v9 5530; RV32-NEXT: vsrl.vi v8, v8, 1 5531; RV32-NEXT: vse64.v v8, (a0) 5532; RV32-NEXT: addi sp, sp, 16 5533; RV32-NEXT: .cfi_def_cfa_offset 0 5534; RV32-NEXT: ret 5535; 5536; RV64-LABEL: mulhu_vx_v2i64: 5537; RV64: # %bb.0: 5538; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5539; RV64-NEXT: vle64.v v8, (a0) 5540; RV64-NEXT: lui a1, 699051 5541; RV64-NEXT: addiw a1, a1, -1365 5542; RV64-NEXT: slli a2, a1, 32 5543; RV64-NEXT: add a1, a1, a2 5544; RV64-NEXT: vmulhu.vx v8, v8, a1 5545; RV64-NEXT: vsrl.vi v8, v8, 1 5546; RV64-NEXT: vse64.v v8, (a0) 5547; RV64-NEXT: ret 5548 %a = load <2 x i64>, ptr %x 5549 %b = udiv <2 x i64> %a, <i64 3, i64 3> 5550 store <2 x i64> %b, ptr %x 5551 ret void 5552} 5553 5554define void @mulhs_vx_v16i8(ptr %x) { 5555; CHECK-LABEL: mulhs_vx_v16i8: 5556; CHECK: # %bb.0: 5557; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 5558; CHECK-NEXT: vle8.v v8, (a0) 5559; CHECK-NEXT: li a1, -123 5560; CHECK-NEXT: vmulhu.vx v8, v8, a1 5561; CHECK-NEXT: vsrl.vi v8, v8, 7 5562; CHECK-NEXT: vse8.v v8, (a0) 5563; CHECK-NEXT: ret 5564 %a = load <16 x i8>, ptr %x 5565 %b = udiv <16 x i8> %a, <i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9, i8 -9> 5566 store <16 x i8> %b, ptr %x 5567 ret void 5568} 5569 5570define void @mulhs_vx_v8i16(ptr %x) { 5571; CHECK-LABEL: mulhs_vx_v8i16: 5572; CHECK: # %bb.0: 5573; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 5574; CHECK-NEXT: vle16.v v8, (a0) 5575; CHECK-NEXT: lui a1, 5 5576; CHECK-NEXT: addi a1, a1, -1755 5577; CHECK-NEXT: vmulh.vx v8, v8, a1 5578; CHECK-NEXT: vsra.vi v8, v8, 1 5579; CHECK-NEXT: vsrl.vi v9, v8, 15 5580; CHECK-NEXT: vadd.vv v8, v8, v9 5581; CHECK-NEXT: vse16.v v8, (a0) 5582; CHECK-NEXT: ret 5583 %a = load <8 x i16>, ptr %x 5584 %b = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> 5585 store <8 x i16> %b, ptr %x 5586 ret void 5587} 5588 5589define void @mulhs_vx_v4i32(ptr %x) { 5590; RV32-LABEL: mulhs_vx_v4i32: 5591; RV32: # %bb.0: 5592; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5593; RV32-NEXT: vle32.v v8, (a0) 5594; RV32-NEXT: lui a1, 629146 5595; RV32-NEXT: addi a1, a1, -1639 5596; RV32-NEXT: vmulh.vx v8, v8, a1 5597; RV32-NEXT: vsrl.vi v9, v8, 31 5598; RV32-NEXT: vsra.vi v8, v8, 1 5599; RV32-NEXT: vadd.vv v8, v8, v9 5600; RV32-NEXT: vse32.v v8, (a0) 5601; RV32-NEXT: ret 5602; 5603; RV64-LABEL: mulhs_vx_v4i32: 5604; RV64: # %bb.0: 5605; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma 5606; RV64-NEXT: vle32.v v8, (a0) 5607; RV64-NEXT: lui a1, 629146 5608; RV64-NEXT: addi a1, a1, -1639 5609; RV64-NEXT: vmulh.vx v8, v8, a1 5610; RV64-NEXT: vsra.vi v8, v8, 1 5611; RV64-NEXT: vsrl.vi v9, v8, 31 5612; RV64-NEXT: vadd.vv v8, v8, v9 5613; RV64-NEXT: vse32.v v8, (a0) 5614; RV64-NEXT: ret 5615 %a = load <4 x i32>, ptr %x 5616 %b = sdiv <4 x i32> %a, <i32 -5, i32 -5, i32 -5, i32 -5> 5617 store <4 x i32> %b, ptr %x 5618 ret void 5619} 5620 5621define void @mulhs_vx_v2i64(ptr %x) { 5622; RV32-LABEL: mulhs_vx_v2i64: 5623; RV32: # %bb.0: 5624; RV32-NEXT: addi sp, sp, -16 5625; RV32-NEXT: .cfi_def_cfa_offset 16 5626; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5627; RV32-NEXT: vle64.v v8, (a0) 5628; RV32-NEXT: lui a1, 349525 5629; RV32-NEXT: addi a2, sp, 8 5630; RV32-NEXT: addi a3, a1, 1365 5631; RV32-NEXT: addi a1, a1, 1366 5632; RV32-NEXT: sw a1, 8(sp) 5633; RV32-NEXT: sw a3, 12(sp) 5634; RV32-NEXT: vlse64.v v9, (a2), zero 5635; RV32-NEXT: vmulh.vv v8, v8, v9 5636; RV32-NEXT: li a1, 63 5637; RV32-NEXT: vsrl.vx v9, v8, a1 5638; RV32-NEXT: vadd.vv v8, v8, v9 5639; RV32-NEXT: vse64.v v8, (a0) 5640; RV32-NEXT: addi sp, sp, 16 5641; RV32-NEXT: .cfi_def_cfa_offset 0 5642; RV32-NEXT: ret 5643; 5644; RV64-LABEL: mulhs_vx_v2i64: 5645; RV64: # %bb.0: 5646; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5647; RV64-NEXT: vle64.v v8, (a0) 5648; RV64-NEXT: lui a1, %hi(.LCPI321_0) 5649; RV64-NEXT: ld a1, %lo(.LCPI321_0)(a1) 5650; RV64-NEXT: vmulh.vx v8, v8, a1 5651; RV64-NEXT: li a1, 63 5652; RV64-NEXT: vsrl.vx v9, v8, a1 5653; RV64-NEXT: vadd.vv v8, v8, v9 5654; RV64-NEXT: vse64.v v8, (a0) 5655; RV64-NEXT: ret 5656 %a = load <2 x i64>, ptr %x 5657 %b = sdiv <2 x i64> %a, <i64 3, i64 3> 5658 store <2 x i64> %b, ptr %x 5659 ret void 5660} 5661 5662define void @madd_vv_v2i64(ptr %x, <2 x i64> %y) { 5663; CHECK-LABEL: madd_vv_v2i64: 5664; CHECK: # %bb.0: 5665; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5666; CHECK-NEXT: vle64.v v9, (a0) 5667; CHECK-NEXT: vmadd.vv v9, v8, v8 5668; CHECK-NEXT: vse64.v v9, (a0) 5669; CHECK-NEXT: ret 5670 %a = load <2 x i64>, ptr %x 5671 %b = add <2 x i64> %a, <i64 1, i64 1> 5672 %c = mul <2 x i64> %b, %y 5673 store <2 x i64> %c, ptr %x 5674 ret void 5675} 5676 5677define void @madd_vv_v2i64_2(ptr %x, <2 x i64> %y) { 5678; CHECK-LABEL: madd_vv_v2i64_2: 5679; CHECK: # %bb.0: 5680; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5681; CHECK-NEXT: vle64.v v9, (a0) 5682; CHECK-NEXT: vmadd.vv v9, v8, v8 5683; CHECK-NEXT: vse64.v v9, (a0) 5684; CHECK-NEXT: ret 5685 %a = load <2 x i64>, ptr %x 5686 %b = add <2 x i64> %a, <i64 1, i64 1> 5687 %c = mul <2 x i64> %y, %b 5688 store <2 x i64> %c, ptr %x 5689 ret void 5690} 5691 5692define void @msub_vv_v2i64(ptr %x, <2 x i64> %y) { 5693; CHECK-LABEL: msub_vv_v2i64: 5694; CHECK: # %bb.0: 5695; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5696; CHECK-NEXT: vle64.v v9, (a0) 5697; CHECK-NEXT: vnmsub.vv v9, v8, v8 5698; CHECK-NEXT: vse64.v v9, (a0) 5699; CHECK-NEXT: ret 5700 %a = load <2 x i64>, ptr %x 5701 %b = sub <2 x i64> <i64 1, i64 1>, %a 5702 %c = mul <2 x i64> %b, %y 5703 store <2 x i64> %c, ptr %x 5704 ret void 5705} 5706 5707define void @msub_vv_v2i64_2(ptr %x, <2 x i64> %y) { 5708; CHECK-LABEL: msub_vv_v2i64_2: 5709; CHECK: # %bb.0: 5710; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 5711; CHECK-NEXT: vle64.v v9, (a0) 5712; CHECK-NEXT: vnmsub.vv v9, v8, v8 5713; CHECK-NEXT: vse64.v v9, (a0) 5714; CHECK-NEXT: ret 5715 %a = load <2 x i64>, ptr %x 5716 %b = sub <2 x i64> <i64 1, i64 1>, %a 5717 %c = mul <2 x i64> %y, %b 5718 store <2 x i64> %c, ptr %x 5719 ret void 5720} 5721