xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll (revision 0fee2115bb78a8168fd752ca01f6646cfbf74d07)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
4
5define void @sext_v4i8_v4i32(ptr %x, ptr %z) {
6; CHECK-LABEL: sext_v4i8_v4i32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
9; CHECK-NEXT:    vle8.v v8, (a0)
10; CHECK-NEXT:    vsext.vf4 v9, v8
11; CHECK-NEXT:    vse32.v v9, (a1)
12; CHECK-NEXT:    ret
13  %a = load <4 x i8>, ptr %x
14  %b = sext <4 x i8> %a to <4 x i32>
15  store <4 x i32> %b, ptr %z
16  ret void
17}
18
19define void @zext_v4i8_v4i32(ptr %x, ptr %z) {
20; CHECK-LABEL: zext_v4i8_v4i32:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
23; CHECK-NEXT:    vle8.v v8, (a0)
24; CHECK-NEXT:    vzext.vf4 v9, v8
25; CHECK-NEXT:    vse32.v v9, (a1)
26; CHECK-NEXT:    ret
27  %a = load <4 x i8>, ptr %x
28  %b = zext <4 x i8> %a to <4 x i32>
29  store <4 x i32> %b, ptr %z
30  ret void
31}
32
33define void @sext_v8i8_v8i32(ptr %x, ptr %z) {
34; CHECK-LABEL: sext_v8i8_v8i32:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
37; CHECK-NEXT:    vle8.v v8, (a0)
38; CHECK-NEXT:    vsext.vf4 v10, v8
39; CHECK-NEXT:    vse32.v v10, (a1)
40; CHECK-NEXT:    ret
41  %a = load <8 x i8>, ptr %x
42  %b = sext <8 x i8> %a to <8 x i32>
43  store <8 x i32> %b, ptr %z
44  ret void
45}
46
47define void @sext_v32i8_v32i32(ptr %x, ptr %z) {
48; CHECK-LABEL: sext_v32i8_v32i32:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    li a2, 32
51; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
52; CHECK-NEXT:    vle8.v v8, (a0)
53; CHECK-NEXT:    vsext.vf4 v16, v8
54; CHECK-NEXT:    vse32.v v16, (a1)
55; CHECK-NEXT:    ret
56  %a = load <32 x i8>, ptr %x
57  %b = sext <32 x i8> %a to <32 x i32>
58  store <32 x i32> %b, ptr %z
59  ret void
60}
61
62define void @trunc_v4i8_v4i32(ptr %x, ptr %z) {
63; CHECK-LABEL: trunc_v4i8_v4i32:
64; CHECK:       # %bb.0:
65; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
66; CHECK-NEXT:    vle32.v v8, (a0)
67; CHECK-NEXT:    vnsrl.wi v8, v8, 0
68; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
69; CHECK-NEXT:    vnsrl.wi v8, v8, 0
70; CHECK-NEXT:    vse8.v v8, (a1)
71; CHECK-NEXT:    ret
72  %a = load <4 x i32>, ptr %x
73  %b = trunc <4 x i32> %a to <4 x i8>
74  store <4 x i8> %b, ptr %z
75  ret void
76}
77
78define void @trunc_v8i8_v8i32(ptr %x, ptr %z) {
79; CHECK-LABEL: trunc_v8i8_v8i32:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
82; CHECK-NEXT:    vle32.v v8, (a0)
83; CHECK-NEXT:    vnsrl.wi v10, v8, 0
84; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
85; CHECK-NEXT:    vnsrl.wi v8, v10, 0
86; CHECK-NEXT:    vse8.v v8, (a1)
87; CHECK-NEXT:    ret
88  %a = load <8 x i32>, ptr %x
89  %b = trunc <8 x i32> %a to <8 x i8>
90  store <8 x i8> %b, ptr %z
91  ret void
92}
93