1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-ONLY 3; RUN: llc -mtriple=riscv32 -mattr=+v,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32VB 4; RUN: llc -mtriple=riscv32 -mattr=+v,+zba,+zbb,+zbkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32VB-PACK 5; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RV64V-ONLY 6; RUN: llc -mtriple=riscv64 -mattr=+v,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RVA22U64 7; RUN: llc -mtriple=riscv64 -mattr=+v,+rva22u64,+zbkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V,RVA22U64-PACK 8; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32 9 10define void @buildvec_vid_v16i8(ptr %x) { 11; CHECK-LABEL: buildvec_vid_v16i8: 12; CHECK: # %bb.0: 13; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 14; CHECK-NEXT: vid.v v8 15; CHECK-NEXT: vse8.v v8, (a0) 16; CHECK-NEXT: ret 17 store <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %x 18 ret void 19} 20 21define void @buildvec_vid_undefelts_v16i8(ptr %x) { 22; CHECK-LABEL: buildvec_vid_undefelts_v16i8: 23; CHECK: # %bb.0: 24; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 25; CHECK-NEXT: vid.v v8 26; CHECK-NEXT: vse8.v v8, (a0) 27; CHECK-NEXT: ret 28 store <16 x i8> <i8 0, i8 1, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %x 29 ret void 30} 31 32; TODO: Could do VID then insertelement on missing elements 33define void @buildvec_notquite_vid_v16i8(ptr %x) { 34; CHECK-LABEL: buildvec_notquite_vid_v16i8: 35; CHECK: # %bb.0: 36; CHECK-NEXT: lui a1, %hi(.LCPI2_0) 37; CHECK-NEXT: addi a1, a1, %lo(.LCPI2_0) 38; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 39; CHECK-NEXT: vle8.v v8, (a1) 40; CHECK-NEXT: vse8.v v8, (a0) 41; CHECK-NEXT: ret 42 store <16 x i8> <i8 0, i8 1, i8 3, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, ptr %x 43 ret void 44} 45 46define void @buildvec_vid_plus_imm_v16i8(ptr %x) { 47; CHECK-LABEL: buildvec_vid_plus_imm_v16i8: 48; CHECK: # %bb.0: 49; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 50; CHECK-NEXT: vid.v v8 51; CHECK-NEXT: vadd.vi v8, v8, 2 52; CHECK-NEXT: vse8.v v8, (a0) 53; CHECK-NEXT: ret 54 store <16 x i8> <i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17>, ptr %x 55 ret void 56} 57 58define void @buildvec_vid_plus_nonimm_v16i8(ptr %x) { 59; CHECK-LABEL: buildvec_vid_plus_nonimm_v16i8: 60; CHECK: # %bb.0: 61; CHECK-NEXT: lui a1, %hi(.LCPI4_0) 62; CHECK-NEXT: addi a1, a1, %lo(.LCPI4_0) 63; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 64; CHECK-NEXT: vle8.v v8, (a1) 65; CHECK-NEXT: vse8.v v8, (a0) 66; CHECK-NEXT: ret 67 store <16 x i8> <i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115>, ptr %x 68 ret void 69} 70 71define void @buildvec_vid_mpy_imm_v16i8(ptr %x) { 72; CHECK-LABEL: buildvec_vid_mpy_imm_v16i8: 73; CHECK: # %bb.0: 74; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 75; CHECK-NEXT: vid.v v8 76; CHECK-NEXT: li a1, 3 77; CHECK-NEXT: vmul.vx v8, v8, a1 78; CHECK-NEXT: vse8.v v8, (a0) 79; CHECK-NEXT: ret 80 store <16 x i8> <i8 0, i8 3, i8 6, i8 9, i8 12, i8 15, i8 18, i8 21, i8 24, i8 27, i8 30, i8 33, i8 36, i8 39, i8 42, i8 45>, ptr %x 81 ret void 82} 83 84define <4 x i8> @buildvec_vid_step2_add0_v4i8() { 85; CHECK-LABEL: buildvec_vid_step2_add0_v4i8: 86; CHECK: # %bb.0: 87; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 88; CHECK-NEXT: vid.v v8 89; CHECK-NEXT: vadd.vv v8, v8, v8 90; CHECK-NEXT: ret 91 ret <4 x i8> <i8 0, i8 2, i8 4, i8 6> 92} 93 94define <4 x i8> @buildvec_vid_step2_add0_v4i8_undef0() { 95; CHECK-LABEL: buildvec_vid_step2_add0_v4i8_undef0: 96; CHECK: # %bb.0: 97; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 98; CHECK-NEXT: vid.v v8 99; CHECK-NEXT: vadd.vv v8, v8, v8 100; CHECK-NEXT: ret 101 ret <4 x i8> <i8 undef, i8 2, i8 4, i8 6> 102} 103 104define <4 x i8> @buildvec_vid_step2_add0_v4i8_undef1() { 105; CHECK-LABEL: buildvec_vid_step2_add0_v4i8_undef1: 106; CHECK: # %bb.0: 107; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 108; CHECK-NEXT: vid.v v8 109; CHECK-NEXT: vadd.vv v8, v8, v8 110; CHECK-NEXT: ret 111 ret <4 x i8> <i8 undef, i8 undef, i8 4, i8 6> 112} 113 114define <4 x i8> @buildvec_vid_step2_add0_v4i8_undef2() { 115; CHECK-LABEL: buildvec_vid_step2_add0_v4i8_undef2: 116; CHECK: # %bb.0: 117; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 118; CHECK-NEXT: vid.v v8 119; CHECK-NEXT: vadd.vv v8, v8, v8 120; CHECK-NEXT: ret 121 ret <4 x i8> <i8 0, i8 undef, i8 undef, i8 6> 122} 123 124define <4 x i8> @buildvec_vid_step2_add1_v4i8() { 125; CHECK-LABEL: buildvec_vid_step2_add1_v4i8: 126; CHECK: # %bb.0: 127; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 128; CHECK-NEXT: vid.v v8 129; CHECK-NEXT: vadd.vv v8, v8, v8 130; CHECK-NEXT: vadd.vi v8, v8, 1 131; CHECK-NEXT: ret 132 ret <4 x i8> <i8 1, i8 3, i8 5, i8 7> 133} 134 135define <4 x i8> @buildvec_vid_step2_add1_v4i8_undef0() { 136; CHECK-LABEL: buildvec_vid_step2_add1_v4i8_undef0: 137; CHECK: # %bb.0: 138; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 139; CHECK-NEXT: vid.v v8 140; CHECK-NEXT: vadd.vv v8, v8, v8 141; CHECK-NEXT: vadd.vi v8, v8, 1 142; CHECK-NEXT: ret 143 ret <4 x i8> <i8 undef, i8 3, i8 5, i8 7> 144} 145 146define <4 x i8> @buildvec_vid_step2_add1_v4i8_undef1() { 147; CHECK-LABEL: buildvec_vid_step2_add1_v4i8_undef1: 148; CHECK: # %bb.0: 149; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 150; CHECK-NEXT: vid.v v8 151; CHECK-NEXT: vadd.vv v8, v8, v8 152; CHECK-NEXT: vadd.vi v8, v8, 1 153; CHECK-NEXT: ret 154 ret <4 x i8> <i8 undef, i8 undef, i8 5, i8 7> 155} 156 157define <4 x i8> @buildvec_vid_step2_add1_v4i8_undef2() { 158; CHECK-LABEL: buildvec_vid_step2_add1_v4i8_undef2: 159; CHECK: # %bb.0: 160; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 161; CHECK-NEXT: vid.v v8 162; CHECK-NEXT: vadd.vv v8, v8, v8 163; CHECK-NEXT: vadd.vi v8, v8, 1 164; CHECK-NEXT: ret 165 ret <4 x i8> <i8 1, i8 undef, i8 undef, i8 7> 166} 167 168define <4 x i8> @buildvec_vid_stepn1_add0_v4i8() { 169; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8: 170; CHECK: # %bb.0: 171; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 172; CHECK-NEXT: vid.v v8 173; CHECK-NEXT: vrsub.vi v8, v8, 0 174; CHECK-NEXT: ret 175 ret <4 x i8> <i8 0, i8 -1, i8 -2, i8 -3> 176} 177 178define <4 x i8> @buildvec_vid_stepn1_add0_v4i8_undef0() { 179; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8_undef0: 180; CHECK: # %bb.0: 181; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 182; CHECK-NEXT: vid.v v8 183; CHECK-NEXT: vrsub.vi v8, v8, 0 184; CHECK-NEXT: ret 185 ret <4 x i8> <i8 undef, i8 -1, i8 -2, i8 -3> 186} 187 188define <4 x i8> @buildvec_vid_stepn1_add0_v4i8_undef1() { 189; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8_undef1: 190; CHECK: # %bb.0: 191; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 192; CHECK-NEXT: vid.v v8 193; CHECK-NEXT: vrsub.vi v8, v8, 0 194; CHECK-NEXT: ret 195 ret <4 x i8> <i8 undef, i8 undef, i8 -2, i8 -3> 196} 197 198define <4 x i8> @buildvec_vid_stepn1_add0_v4i8_undef2() { 199; CHECK-LABEL: buildvec_vid_stepn1_add0_v4i8_undef2: 200; CHECK: # %bb.0: 201; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 202; CHECK-NEXT: vid.v v8 203; CHECK-NEXT: vrsub.vi v8, v8, 0 204; CHECK-NEXT: ret 205 ret <4 x i8> <i8 0, i8 undef, i8 undef, i8 -3> 206} 207 208define <4 x i8> @buildvec_vid_stepn2_add0_v4i8() { 209; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8: 210; CHECK: # %bb.0: 211; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 212; CHECK-NEXT: vid.v v8 213; CHECK-NEXT: vadd.vv v8, v8, v8 214; CHECK-NEXT: vrsub.vi v8, v8, 0 215; CHECK-NEXT: ret 216 ret <4 x i8> <i8 0, i8 -2, i8 -4, i8 -6> 217} 218 219define <4 x i8> @buildvec_vid_stepn2_add0_v4i8_undef0() { 220; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8_undef0: 221; CHECK: # %bb.0: 222; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 223; CHECK-NEXT: vid.v v8 224; CHECK-NEXT: vadd.vv v8, v8, v8 225; CHECK-NEXT: vrsub.vi v8, v8, 0 226; CHECK-NEXT: ret 227 ret <4 x i8> <i8 undef, i8 -2, i8 -4, i8 -6> 228} 229 230define <4 x i8> @buildvec_vid_stepn2_add0_v4i8_undef1() { 231; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8_undef1: 232; CHECK: # %bb.0: 233; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 234; CHECK-NEXT: vid.v v8 235; CHECK-NEXT: vadd.vv v8, v8, v8 236; CHECK-NEXT: vrsub.vi v8, v8, 0 237; CHECK-NEXT: ret 238 ret <4 x i8> <i8 undef, i8 undef, i8 -4, i8 -6> 239} 240 241define <4 x i8> @buildvec_vid_stepn2_add0_v4i8_undef2() { 242; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8_undef2: 243; CHECK: # %bb.0: 244; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 245; CHECK-NEXT: vmv.v.i v8, -6 246; CHECK-NEXT: ret 247 ret <4 x i8> <i8 undef, i8 undef, i8 undef, i8 -6> 248} 249 250define <4 x i8> @buildvec_vid_stepn2_add3_v4i8() { 251; CHECK-LABEL: buildvec_vid_stepn2_add3_v4i8: 252; CHECK: # %bb.0: 253; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 254; CHECK-NEXT: vid.v v8 255; CHECK-NEXT: vadd.vv v8, v8, v8 256; CHECK-NEXT: vrsub.vi v8, v8, 3 257; CHECK-NEXT: ret 258 ret <4 x i8> <i8 3, i8 1, i8 -1, i8 -3> 259} 260 261define <4 x i8> @buildvec_vid_stepn3_add3_v4i8() { 262; CHECK-LABEL: buildvec_vid_stepn3_add3_v4i8: 263; CHECK: # %bb.0: 264; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 265; CHECK-NEXT: vmv.v.i v9, 3 266; CHECK-NEXT: vid.v v8 267; CHECK-NEXT: li a0, -3 268; CHECK-NEXT: vmadd.vx v8, a0, v9 269; CHECK-NEXT: ret 270 ret <4 x i8> <i8 3, i8 0, i8 -3, i8 -6> 271} 272 273define void @buildvec_vid_stepn3_addn3_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3) { 274; CHECK-LABEL: buildvec_vid_stepn3_addn3_v4i32: 275; CHECK: # %bb.0: 276; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 277; CHECK-NEXT: vmv.v.i v8, -3 278; CHECK-NEXT: vid.v v9 279; CHECK-NEXT: li a4, -3 280; CHECK-NEXT: vmadd.vx v9, a4, v8 281; CHECK-NEXT: vse32.v v9, (a0) 282; CHECK-NEXT: vse32.v v9, (a1) 283; CHECK-NEXT: vse32.v v9, (a2) 284; CHECK-NEXT: vse32.v v9, (a3) 285; CHECK-NEXT: ret 286 store <4 x i32> <i32 -3, i32 -6, i32 -9, i32 -12>, ptr %z0 287 store <4 x i32> <i32 undef, i32 -6, i32 -9, i32 -12>, ptr %z1 288 store <4 x i32> <i32 undef, i32 undef, i32 -9, i32 -12>, ptr %z2 289 store <4 x i32> <i32 -3, i32 undef, i32 undef, i32 -12>, ptr %z3 290 ret void 291} 292 293; FIXME: RV32 doesn't catch this pattern due to BUILD_VECTOR legalization. 294define <4 x i64> @buildvec_vid_step1_add0_v4i64() { 295; RV32-LABEL: buildvec_vid_step1_add0_v4i64: 296; RV32: # %bb.0: 297; RV32-NEXT: lui a0, %hi(.LCPI25_0) 298; RV32-NEXT: addi a0, a0, %lo(.LCPI25_0) 299; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 300; RV32-NEXT: vle8.v v10, (a0) 301; RV32-NEXT: vsext.vf4 v8, v10 302; RV32-NEXT: ret 303; 304; RV64V-LABEL: buildvec_vid_step1_add0_v4i64: 305; RV64V: # %bb.0: 306; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma 307; RV64V-NEXT: vid.v v8 308; RV64V-NEXT: ret 309; 310; RV64ZVE32-LABEL: buildvec_vid_step1_add0_v4i64: 311; RV64ZVE32: # %bb.0: 312; RV64ZVE32-NEXT: li a1, 3 313; RV64ZVE32-NEXT: li a2, 2 314; RV64ZVE32-NEXT: li a3, 1 315; RV64ZVE32-NEXT: sd zero, 0(a0) 316; RV64ZVE32-NEXT: sd a3, 8(a0) 317; RV64ZVE32-NEXT: sd a2, 16(a0) 318; RV64ZVE32-NEXT: sd a1, 24(a0) 319; RV64ZVE32-NEXT: ret 320 ret <4 x i64> <i64 0, i64 1, i64 2, i64 3> 321} 322 323define <4 x i64> @buildvec_vid_step2_add0_v4i64() { 324; RV32-LABEL: buildvec_vid_step2_add0_v4i64: 325; RV32: # %bb.0: 326; RV32-NEXT: lui a0, %hi(.LCPI26_0) 327; RV32-NEXT: addi a0, a0, %lo(.LCPI26_0) 328; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma 329; RV32-NEXT: vle8.v v10, (a0) 330; RV32-NEXT: vsext.vf4 v8, v10 331; RV32-NEXT: ret 332; 333; RV64V-LABEL: buildvec_vid_step2_add0_v4i64: 334; RV64V: # %bb.0: 335; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma 336; RV64V-NEXT: vid.v v8 337; RV64V-NEXT: vadd.vv v8, v8, v8 338; RV64V-NEXT: ret 339; 340; RV64ZVE32-LABEL: buildvec_vid_step2_add0_v4i64: 341; RV64ZVE32: # %bb.0: 342; RV64ZVE32-NEXT: li a1, 6 343; RV64ZVE32-NEXT: li a2, 4 344; RV64ZVE32-NEXT: li a3, 2 345; RV64ZVE32-NEXT: sd zero, 0(a0) 346; RV64ZVE32-NEXT: sd a3, 8(a0) 347; RV64ZVE32-NEXT: sd a2, 16(a0) 348; RV64ZVE32-NEXT: sd a1, 24(a0) 349; RV64ZVE32-NEXT: ret 350 ret <4 x i64> <i64 0, i64 2, i64 4, i64 6> 351} 352 353define <4 x i8> @buildvec_no_vid_v4i8_0() { 354; CHECK-LABEL: buildvec_no_vid_v4i8_0: 355; CHECK: # %bb.0: 356; CHECK-NEXT: lui a0, 28768 357; CHECK-NEXT: addi a0, a0, 769 358; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 359; CHECK-NEXT: vmv.s.x v8, a0 360; CHECK-NEXT: ret 361 ret <4 x i8> <i8 1, i8 3, i8 6, i8 7> 362} 363 364define <4 x i8> @buildvec_no_vid_v4i8_1() { 365; CHECK-LABEL: buildvec_no_vid_v4i8_1: 366; CHECK: # %bb.0: 367; CHECK-NEXT: lui a0, 28752 368; CHECK-NEXT: addi a0, a0, 512 369; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 370; CHECK-NEXT: vmv.s.x v8, a0 371; CHECK-NEXT: ret 372 ret <4 x i8> <i8 undef, i8 2, i8 5, i8 7> 373} 374 375define <4 x i8> @buildvec_no_vid_v4i8_2() { 376; CHECK-LABEL: buildvec_no_vid_v4i8_2: 377; CHECK: # %bb.0: 378; CHECK-NEXT: lui a0, 32768 379; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 380; CHECK-NEXT: vmv.s.x v8, a0 381; CHECK-NEXT: ret 382 ret <4 x i8> <i8 0, i8 undef, i8 undef, i8 8> 383} 384 385define <4 x i8> @buildvec_no_vid_v4i8_3() { 386; CHECK-LABEL: buildvec_no_vid_v4i8_3: 387; CHECK: # %bb.0: 388; CHECK-NEXT: lui a0, 28672 389; CHECK-NEXT: addi a0, a0, 255 390; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 391; CHECK-NEXT: vmv.s.x v8, a0 392; CHECK-NEXT: ret 393 ret <4 x i8> <i8 -1, i8 undef, i8 undef, i8 7> 394} 395 396define <4 x i8> @buildvec_no_vid_v4i8_4() { 397; CHECK-LABEL: buildvec_no_vid_v4i8_4: 398; CHECK: # %bb.0: 399; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 400; CHECK-NEXT: vmv.v.i v8, -2 401; CHECK-NEXT: ret 402 ret <4 x i8> <i8 -2, i8 undef, i8 undef, i8 undef> 403} 404 405define <4 x i8> @buildvec_no_vid_v4i8_5() { 406; CHECK-LABEL: buildvec_no_vid_v4i8_5: 407; CHECK: # %bb.0: 408; CHECK-NEXT: lui a0, 1032144 409; CHECK-NEXT: addi a0, a0, -257 410; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 411; CHECK-NEXT: vmv.s.x v8, a0 412; CHECK-NEXT: ret 413 ret <4 x i8> <i8 -1, i8 -2, i8 -4, i8 -5> 414} 415 416define void @buildvec_dominant0_v8i16(ptr %x) { 417; CHECK-LABEL: buildvec_dominant0_v8i16: 418; CHECK: # %bb.0: 419; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 420; CHECK-NEXT: vmv.s.x v8, zero 421; CHECK-NEXT: vmv.v.i v9, 8 422; CHECK-NEXT: vsetivli zero, 4, e16, m1, tu, ma 423; CHECK-NEXT: vslideup.vi v9, v8, 3 424; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 425; CHECK-NEXT: vse16.v v9, (a0) 426; CHECK-NEXT: ret 427 store <8 x i16> <i16 8, i16 8, i16 undef, i16 0, i16 8, i16 undef, i16 8, i16 8>, ptr %x 428 ret void 429} 430 431define void @buildvec_dominant0_v8i16_with_end_element(ptr %x) { 432; CHECK-LABEL: buildvec_dominant0_v8i16_with_end_element: 433; CHECK: # %bb.0: 434; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 435; CHECK-NEXT: vmv.v.i v8, 8 436; CHECK-NEXT: li a1, 3 437; CHECK-NEXT: vslide1down.vx v8, v8, a1 438; CHECK-NEXT: vse16.v v8, (a0) 439; CHECK-NEXT: ret 440 store <8 x i16> <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 3>, ptr %x 441 ret void 442} 443 444define void @buildvec_dominant0_v8i16_with_tail(ptr %x) { 445; CHECK-LABEL: buildvec_dominant0_v8i16_with_tail: 446; CHECK: # %bb.0: 447; CHECK-NEXT: lui a1, %hi(.LCPI35_0) 448; CHECK-NEXT: addi a1, a1, %lo(.LCPI35_0) 449; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 450; CHECK-NEXT: vle16.v v8, (a1) 451; CHECK-NEXT: vse16.v v8, (a0) 452; CHECK-NEXT: ret 453 store <8 x i16> <i16 8, i16 8, i16 8, i16 8, i16 8, i16 undef, i16 2, i16 3>, ptr %x 454 ret void 455} 456 457 458define void @buildvec_dominant1_v8i16(ptr %x) { 459; CHECK-LABEL: buildvec_dominant1_v8i16: 460; CHECK: # %bb.0: 461; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 462; CHECK-NEXT: vmv.v.i v8, 8 463; CHECK-NEXT: vse16.v v8, (a0) 464; CHECK-NEXT: ret 465 store <8 x i16> <i16 undef, i16 8, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, ptr %x 466 ret void 467} 468 469define <2 x i8> @buildvec_dominant0_v2i8() { 470; CHECK-LABEL: buildvec_dominant0_v2i8: 471; CHECK: # %bb.0: 472; CHECK-NEXT: ret 473 ret <2 x i8> <i8 undef, i8 undef> 474} 475 476define <2 x i8> @buildvec_dominant1_v2i8() { 477; RV32-LABEL: buildvec_dominant1_v2i8: 478; RV32: # %bb.0: 479; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 480; RV32-NEXT: vmv.v.i v8, -1 481; RV32-NEXT: ret 482; 483; RV64V-LABEL: buildvec_dominant1_v2i8: 484; RV64V: # %bb.0: 485; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 486; RV64V-NEXT: vmv.v.i v8, -1 487; RV64V-NEXT: ret 488; 489; RV64ZVE32-LABEL: buildvec_dominant1_v2i8: 490; RV64ZVE32: # %bb.0: 491; RV64ZVE32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma 492; RV64ZVE32-NEXT: vmv.v.i v8, -1 493; RV64ZVE32-NEXT: ret 494 ret <2 x i8> <i8 undef, i8 -1> 495} 496 497define <2 x i8> @buildvec_dominant2_v2i8() { 498; RV32-LABEL: buildvec_dominant2_v2i8: 499; RV32: # %bb.0: 500; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 501; RV32-NEXT: vid.v v8 502; RV32-NEXT: vrsub.vi v8, v8, 0 503; RV32-NEXT: ret 504; 505; RV64V-LABEL: buildvec_dominant2_v2i8: 506; RV64V: # %bb.0: 507; RV64V-NEXT: vsetivli zero, 2, e8, mf8, ta, ma 508; RV64V-NEXT: vid.v v8 509; RV64V-NEXT: vrsub.vi v8, v8, 0 510; RV64V-NEXT: ret 511; 512; RV64ZVE32-LABEL: buildvec_dominant2_v2i8: 513; RV64ZVE32: # %bb.0: 514; RV64ZVE32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma 515; RV64ZVE32-NEXT: vid.v v8 516; RV64ZVE32-NEXT: vrsub.vi v8, v8, 0 517; RV64ZVE32-NEXT: ret 518 ret <2 x i8> <i8 0, i8 -1> 519} 520 521define void @buildvec_dominant0_v2i32(ptr %x) { 522; RV32-LABEL: buildvec_dominant0_v2i32: 523; RV32: # %bb.0: 524; RV32-NEXT: lui a1, %hi(.LCPI40_0) 525; RV32-NEXT: addi a1, a1, %lo(.LCPI40_0) 526; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 527; RV32-NEXT: vle32.v v8, (a1) 528; RV32-NEXT: vse32.v v8, (a0) 529; RV32-NEXT: ret 530; 531; RV64V-LABEL: buildvec_dominant0_v2i32: 532; RV64V: # %bb.0: 533; RV64V-NEXT: lui a1, %hi(.LCPI40_0) 534; RV64V-NEXT: ld a1, %lo(.LCPI40_0)(a1) 535; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 536; RV64V-NEXT: vmv.v.i v8, -1 537; RV64V-NEXT: vsetvli zero, zero, e64, m1, tu, ma 538; RV64V-NEXT: vmv.s.x v8, a1 539; RV64V-NEXT: vse64.v v8, (a0) 540; RV64V-NEXT: ret 541; 542; RV64ZVE32-LABEL: buildvec_dominant0_v2i32: 543; RV64ZVE32: # %bb.0: 544; RV64ZVE32-NEXT: lui a1, %hi(.LCPI40_0) 545; RV64ZVE32-NEXT: ld a1, %lo(.LCPI40_0)(a1) 546; RV64ZVE32-NEXT: li a2, -1 547; RV64ZVE32-NEXT: sd a1, 0(a0) 548; RV64ZVE32-NEXT: sd a2, 8(a0) 549; RV64ZVE32-NEXT: ret 550 store <2 x i64> <i64 2049638230412172402, i64 -1>, ptr %x 551 ret void 552} 553 554define void @buildvec_dominant1_optsize_v2i32(ptr %x) optsize { 555; RV32-LABEL: buildvec_dominant1_optsize_v2i32: 556; RV32: # %bb.0: 557; RV32-NEXT: lui a1, %hi(.LCPI41_0) 558; RV32-NEXT: addi a1, a1, %lo(.LCPI41_0) 559; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 560; RV32-NEXT: vle32.v v8, (a1) 561; RV32-NEXT: vse32.v v8, (a0) 562; RV32-NEXT: ret 563; 564; RV64V-LABEL: buildvec_dominant1_optsize_v2i32: 565; RV64V: # %bb.0: 566; RV64V-NEXT: lui a1, %hi(.LCPI41_0) 567; RV64V-NEXT: addi a1, a1, %lo(.LCPI41_0) 568; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 569; RV64V-NEXT: vle64.v v8, (a1) 570; RV64V-NEXT: vse64.v v8, (a0) 571; RV64V-NEXT: ret 572; 573; RV64ZVE32-LABEL: buildvec_dominant1_optsize_v2i32: 574; RV64ZVE32: # %bb.0: 575; RV64ZVE32-NEXT: lui a1, %hi(.LCPI41_0) 576; RV64ZVE32-NEXT: ld a1, %lo(.LCPI41_0)(a1) 577; RV64ZVE32-NEXT: li a2, -1 578; RV64ZVE32-NEXT: sd a1, 0(a0) 579; RV64ZVE32-NEXT: sd a2, 8(a0) 580; RV64ZVE32-NEXT: ret 581 store <2 x i64> <i64 2049638230412172402, i64 -1>, ptr %x 582 ret void 583} 584 585define void @buildvec_seq_v8i8_v4i16(ptr %x) { 586; CHECK-LABEL: buildvec_seq_v8i8_v4i16: 587; CHECK: # %bb.0: 588; CHECK-NEXT: li a1, 513 589; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 590; CHECK-NEXT: vmv.v.x v8, a1 591; CHECK-NEXT: vse8.v v8, (a0) 592; CHECK-NEXT: ret 593 store <8 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 undef, i8 2>, ptr %x 594 ret void 595} 596 597define void @buildvec_seq_v8i8_v2i32(ptr %x) { 598; RV32-LABEL: buildvec_seq_v8i8_v2i32: 599; RV32: # %bb.0: 600; RV32-NEXT: lui a1, 48 601; RV32-NEXT: addi a1, a1, 513 602; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 603; RV32-NEXT: vmv.v.x v8, a1 604; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 605; RV32-NEXT: vse8.v v8, (a0) 606; RV32-NEXT: ret 607; 608; RV64V-LABEL: buildvec_seq_v8i8_v2i32: 609; RV64V: # %bb.0: 610; RV64V-NEXT: lui a1, 48 611; RV64V-NEXT: addi a1, a1, 513 612; RV64V-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 613; RV64V-NEXT: vmv.v.x v8, a1 614; RV64V-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 615; RV64V-NEXT: vse8.v v8, (a0) 616; RV64V-NEXT: ret 617; 618; RV64ZVE32-LABEL: buildvec_seq_v8i8_v2i32: 619; RV64ZVE32: # %bb.0: 620; RV64ZVE32-NEXT: lui a1, 48 621; RV64ZVE32-NEXT: addi a1, a1, 513 622; RV64ZVE32-NEXT: vsetivli zero, 2, e32, m1, ta, ma 623; RV64ZVE32-NEXT: vmv.v.x v8, a1 624; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 625; RV64ZVE32-NEXT: vse8.v v8, (a0) 626; RV64ZVE32-NEXT: ret 627 store <8 x i8> <i8 1, i8 2, i8 3, i8 undef, i8 1, i8 2, i8 3, i8 undef>, ptr %x 628 ret void 629} 630 631define void @buildvec_seq_v16i8_v2i64(ptr %x) { 632; RV32-LABEL: buildvec_seq_v16i8_v2i64: 633; RV32: # %bb.0: 634; RV32-NEXT: lui a1, %hi(.LCPI44_0) 635; RV32-NEXT: addi a1, a1, %lo(.LCPI44_0) 636; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma 637; RV32-NEXT: vle8.v v8, (a1) 638; RV32-NEXT: vse8.v v8, (a0) 639; RV32-NEXT: ret 640; 641; RV64V-LABEL: buildvec_seq_v16i8_v2i64: 642; RV64V: # %bb.0: 643; RV64V-NEXT: lui a1, %hi(.LCPI44_0) 644; RV64V-NEXT: ld a1, %lo(.LCPI44_0)(a1) 645; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 646; RV64V-NEXT: vmv.v.x v8, a1 647; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma 648; RV64V-NEXT: vse8.v v8, (a0) 649; RV64V-NEXT: ret 650; 651; RV64ZVE32-LABEL: buildvec_seq_v16i8_v2i64: 652; RV64ZVE32: # %bb.0: 653; RV64ZVE32-NEXT: lui a1, %hi(.LCPI44_0) 654; RV64ZVE32-NEXT: addi a1, a1, %lo(.LCPI44_0) 655; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma 656; RV64ZVE32-NEXT: vle8.v v8, (a1) 657; RV64ZVE32-NEXT: vse8.v v8, (a0) 658; RV64ZVE32-NEXT: ret 659 store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr %x 660 ret void 661} 662 663define void @buildvec_seq2_v16i8_v2i64(ptr %x) { 664; RV32-LABEL: buildvec_seq2_v16i8_v2i64: 665; RV32: # %bb.0: 666; RV32-NEXT: lui a1, 528432 667; RV32-NEXT: addi a1, a1, 513 668; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 669; RV32-NEXT: vmv.v.x v8, a1 670; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma 671; RV32-NEXT: vse8.v v8, (a0) 672; RV32-NEXT: ret 673; 674; RV64V-LABEL: buildvec_seq2_v16i8_v2i64: 675; RV64V: # %bb.0: 676; RV64V-NEXT: lui a1, 528432 677; RV64V-NEXT: addiw a1, a1, 513 678; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 679; RV64V-NEXT: vmv.v.x v8, a1 680; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma 681; RV64V-NEXT: vse8.v v8, (a0) 682; RV64V-NEXT: ret 683; 684; RV64ZVE32-LABEL: buildvec_seq2_v16i8_v2i64: 685; RV64ZVE32: # %bb.0: 686; RV64ZVE32-NEXT: lui a1, %hi(.LCPI45_0) 687; RV64ZVE32-NEXT: addi a1, a1, %lo(.LCPI45_0) 688; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma 689; RV64ZVE32-NEXT: vle8.v v8, (a1) 690; RV64ZVE32-NEXT: vse8.v v8, (a0) 691; RV64ZVE32-NEXT: ret 692 store <16 x i8> <i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1, i8 1, i8 2, i8 3, i8 129, i8 -1, i8 -1, i8 -1, i8 -1>, ptr %x 693 ret void 694} 695 696define void @buildvec_seq_v9i8(ptr %x) { 697; CHECK-LABEL: buildvec_seq_v9i8: 698; CHECK: # %bb.0: 699; CHECK-NEXT: li a1, 73 700; CHECK-NEXT: vsetivli zero, 9, e8, m1, ta, ma 701; CHECK-NEXT: vmv.v.i v9, 3 702; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma 703; CHECK-NEXT: vmv.s.x v0, a1 704; CHECK-NEXT: li a1, 146 705; CHECK-NEXT: vmv.s.x v8, a1 706; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma 707; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 708; CHECK-NEXT: vmv1r.v v0, v8 709; CHECK-NEXT: vmerge.vim v8, v9, 2, v0 710; CHECK-NEXT: vse8.v v8, (a0) 711; CHECK-NEXT: ret 712 store <9 x i8> <i8 1, i8 2, i8 3, i8 1, i8 2, i8 3, i8 1, i8 2, i8 3>, ptr %x 713 ret void 714} 715 716define void @buildvec_seq_v4i16_v2i32(ptr %x) { 717; CHECK-LABEL: buildvec_seq_v4i16_v2i32: 718; CHECK: # %bb.0: 719; CHECK-NEXT: li a1, -127 720; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 721; CHECK-NEXT: vmv.v.x v8, a1 722; CHECK-NEXT: vse16.v v8, (a0) 723; CHECK-NEXT: ret 724 store <4 x i16> <i16 -127, i16 -1, i16 -127, i16 -1>, ptr %x 725 ret void 726} 727 728define void @buildvec_vid_step1o2_v4i32(ptr %z0, ptr %z1, ptr %z2, ptr %z3, ptr %z4, ptr %z5, ptr %z6) { 729; CHECK-LABEL: buildvec_vid_step1o2_v4i32: 730; CHECK: # %bb.0: 731; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 732; CHECK-NEXT: vmv.v.i v8, 1 733; CHECK-NEXT: vmv.s.x v9, zero 734; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma 735; CHECK-NEXT: vslideup.vi v8, v9, 1 736; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 737; CHECK-NEXT: vid.v v9 738; CHECK-NEXT: vsrl.vi v9, v9, 1 739; CHECK-NEXT: vse32.v v9, (a0) 740; CHECK-NEXT: vse32.v v9, (a1) 741; CHECK-NEXT: vse32.v v9, (a2) 742; CHECK-NEXT: vse32.v v9, (a3) 743; CHECK-NEXT: vse32.v v9, (a4) 744; CHECK-NEXT: vmv.v.i v9, 0 745; CHECK-NEXT: li a0, 1 746; CHECK-NEXT: vslide1down.vx v9, v9, a0 747; CHECK-NEXT: vse32.v v8, (a5) 748; CHECK-NEXT: vse32.v v9, (a6) 749; CHECK-NEXT: ret 750 store <4 x i32> <i32 0, i32 0, i32 1, i32 1>, ptr %z0 751 store <4 x i32> <i32 0, i32 0, i32 1, i32 undef>, ptr %z1 752 store <4 x i32> <i32 0, i32 undef, i32 1, i32 1>, ptr %z2 753 store <4 x i32> <i32 undef, i32 0, i32 undef, i32 1>, ptr %z3 754 store <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>, ptr %z4 755 ; We don't catch this one 756 store <4 x i32> <i32 undef, i32 0, i32 1, i32 1>, ptr %z5 757 ; We catch this one but as VID/3 rather than VID/2 758 store <4 x i32> <i32 0, i32 0, i32 undef, i32 1>, ptr %z6 759 ret void 760} 761 762define void @buildvec_vid_step1o2_add3_v4i16(ptr %z0, ptr %z1, ptr %z2, ptr %z3, ptr %z4, ptr %z5, ptr %z6) { 763; CHECK-LABEL: buildvec_vid_step1o2_add3_v4i16: 764; CHECK: # %bb.0: 765; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 766; CHECK-NEXT: vid.v v8 767; CHECK-NEXT: vmv.v.i v9, 3 768; CHECK-NEXT: vsrl.vi v8, v8, 1 769; CHECK-NEXT: vadd.vi v8, v8, 3 770; CHECK-NEXT: vse16.v v8, (a0) 771; CHECK-NEXT: vse16.v v8, (a1) 772; CHECK-NEXT: vse16.v v8, (a2) 773; CHECK-NEXT: vse16.v v8, (a3) 774; CHECK-NEXT: vse16.v v8, (a4) 775; CHECK-NEXT: vmv.v.i v8, 4 776; CHECK-NEXT: li a0, 4 777; CHECK-NEXT: vsetivli zero, 2, e16, mf2, tu, ma 778; CHECK-NEXT: vslideup.vi v8, v9, 1 779; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 780; CHECK-NEXT: vslide1down.vx v9, v9, a0 781; CHECK-NEXT: vse16.v v8, (a5) 782; CHECK-NEXT: vse16.v v9, (a6) 783; CHECK-NEXT: ret 784 store <4 x i16> <i16 3, i16 3, i16 4, i16 4>, ptr %z0 785 store <4 x i16> <i16 3, i16 3, i16 4, i16 undef>, ptr %z1 786 store <4 x i16> <i16 3, i16 undef, i16 4, i16 4>, ptr %z2 787 store <4 x i16> <i16 undef, i16 3, i16 undef, i16 4>, ptr %z3 788 store <4 x i16> <i16 3, i16 undef, i16 4, i16 undef>, ptr %z4 789 ; We don't catch this one 790 store <4 x i16> <i16 undef, i16 3, i16 4, i16 4>, ptr %z5 791 ; We catch this one but as VID/3 rather than VID/2 792 store <4 x i16> <i16 3, i16 3, i16 undef, i16 4>, ptr %z6 793 ret void 794} 795 796define void @buildvec_vid_stepn1o4_addn5_v8i8(ptr %z0) { 797; CHECK-LABEL: buildvec_vid_stepn1o4_addn5_v8i8: 798; CHECK: # %bb.0: 799; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 800; CHECK-NEXT: vid.v v8 801; CHECK-NEXT: vsrl.vi v8, v8, 2 802; CHECK-NEXT: vrsub.vi v8, v8, -5 803; CHECK-NEXT: vse8.v v8, (a0) 804; CHECK-NEXT: ret 805 store <8 x i8> <i8 -5, i8 -5, i8 -5, i8 -5, i8 -6, i8 -6, i8 -6, i8 -6>, ptr %z0 806 ret void 807} 808 809define void @buildvec_vid_mpy_imm_v8i16(ptr %x) { 810; CHECK-LABEL: buildvec_vid_mpy_imm_v8i16: 811; CHECK: # %bb.0: 812; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 813; CHECK-NEXT: vid.v v8 814; CHECK-NEXT: li a1, 17 815; CHECK-NEXT: vmul.vx v8, v8, a1 816; CHECK-NEXT: vse16.v v8, (a0) 817; CHECK-NEXT: ret 818 store <8 x i16> <i16 0, i16 17, i16 34, i16 51, i16 68, i16 85, i16 102, i16 119>, ptr %x 819 ret void 820} 821 822define void @buildvec_vid_shl_imm_v8i16(ptr %x) { 823; CHECK-LABEL: buildvec_vid_shl_imm_v8i16: 824; CHECK: # %bb.0: 825; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 826; CHECK-NEXT: vid.v v8 827; CHECK-NEXT: vsll.vi v8, v8, 9 828; CHECK-NEXT: vse16.v v8, (a0) 829; CHECK-NEXT: ret 830 store <8 x i16> <i16 0, i16 512, i16 1024, i16 1536, i16 2048, i16 2560, i16 3072, i16 3584>, ptr %x 831 ret void 832} 833 834define <4 x i32> @splat_c3_v4i32(<4 x i32> %v) { 835; CHECK-LABEL: splat_c3_v4i32: 836; CHECK: # %bb.0: 837; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 838; CHECK-NEXT: vrgather.vi v9, v8, 3 839; CHECK-NEXT: vmv.v.v v8, v9 840; CHECK-NEXT: ret 841 %x = extractelement <4 x i32> %v, i32 3 842 %ins = insertelement <4 x i32> poison, i32 %x, i32 0 843 %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer 844 ret <4 x i32> %splat 845} 846 847define <4 x i32> @splat_idx_v4i32(<4 x i32> %v, i64 %idx) { 848; CHECK-LABEL: splat_idx_v4i32: 849; CHECK: # %bb.0: 850; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 851; CHECK-NEXT: vrgather.vx v9, v8, a0 852; CHECK-NEXT: vmv.v.v v8, v9 853; CHECK-NEXT: ret 854 %x = extractelement <4 x i32> %v, i64 %idx 855 %ins = insertelement <4 x i32> poison, i32 %x, i32 0 856 %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer 857 ret <4 x i32> %splat 858} 859 860define <8 x i16> @splat_c4_v8i16(<8 x i16> %v) { 861; CHECK-LABEL: splat_c4_v8i16: 862; CHECK: # %bb.0: 863; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 864; CHECK-NEXT: vrgather.vi v9, v8, 4 865; CHECK-NEXT: vmv.v.v v8, v9 866; CHECK-NEXT: ret 867 %x = extractelement <8 x i16> %v, i32 4 868 %ins = insertelement <8 x i16> poison, i16 %x, i32 0 869 %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer 870 ret <8 x i16> %splat 871} 872 873define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) { 874; CHECK-LABEL: splat_idx_v8i16: 875; CHECK: # %bb.0: 876; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 877; CHECK-NEXT: vrgather.vx v9, v8, a0 878; CHECK-NEXT: vmv.v.v v8, v9 879; CHECK-NEXT: ret 880 %x = extractelement <8 x i16> %v, i64 %idx 881 %ins = insertelement <8 x i16> poison, i16 %x, i32 0 882 %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer 883 ret <8 x i16> %splat 884} 885 886define <4 x i8> @buildvec_not_vid_v4i8_1() { 887; CHECK-LABEL: buildvec_not_vid_v4i8_1: 888; CHECK: # %bb.0: 889; CHECK-NEXT: lui a0, 12320 890; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 891; CHECK-NEXT: vmv.s.x v8, a0 892; CHECK-NEXT: ret 893 ret <4 x i8> <i8 0, i8 0, i8 2, i8 3> 894} 895 896define <4 x i8> @buildvec_not_vid_v4i8_2() { 897; CHECK-LABEL: buildvec_not_vid_v4i8_2: 898; CHECK: # %bb.0: 899; CHECK-NEXT: lui a0, 16 900; CHECK-NEXT: addi a0, a0, 771 901; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 902; CHECK-NEXT: vmv.s.x v8, a0 903; CHECK-NEXT: ret 904 ret <4 x i8> <i8 3, i8 3, i8 1, i8 0> 905} 906 907; We match this as a VID sequence (-3 / 8) + 5 but choose not to introduce 908; division to compute it. 909define <16 x i8> @buildvec_not_vid_v16i8() { 910; CHECK-LABEL: buildvec_not_vid_v16i8: 911; CHECK: # %bb.0: 912; CHECK-NEXT: vsetivli zero, 7, e8, m1, ta, ma 913; CHECK-NEXT: vmv.v.i v9, 3 914; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 915; CHECK-NEXT: vmv.v.i v8, 0 916; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, ma 917; CHECK-NEXT: vslideup.vi v8, v9, 6 918; CHECK-NEXT: ret 919 ret <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 3, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0> 920} 921 922define <512 x i8> @buildvec_vid_v512i8_indices_overflow() vscale_range(16, 1024) { 923; CHECK-LABEL: buildvec_vid_v512i8_indices_overflow: 924; CHECK: # %bb.0: 925; CHECK-NEXT: li a0, 512 926; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 927; CHECK-NEXT: vid.v v8 928; CHECK-NEXT: ret 929 ret <512 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63, i8 64, i8 65, i8 66, i8 67, i8 68, i8 69, i8 70, i8 71, i8 72, i8 73, i8 74, i8 75, i8 76, i8 77, i8 78, i8 79, i8 80, i8 81, i8 82, i8 83, i8 84, i8 85, i8 86, i8 87, i8 88, i8 89, i8 90, i8 91, i8 92, i8 93, i8 94, i8 95, i8 96, i8 97, i8 98, i8 99, i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 128, i8 129, i8 130, i8 131, i8 132, i8 133, i8 134, i8 135, i8 136, i8 137, i8 138, i8 139, i8 140, i8 141, i8 142, i8 143, i8 144, i8 145, i8 146, i8 147, i8 148, i8 149, i8 150, i8 151, i8 152, i8 153, i8 154, i8 155, i8 156, i8 157, i8 158, i8 159, i8 160, i8 161, i8 162, i8 163, i8 164, i8 165, i8 166, i8 167, i8 168, i8 169, i8 170, i8 171, i8 172, i8 173, i8 174, i8 175, i8 176, i8 177, i8 178, i8 179, i8 180, i8 181, i8 182, i8 183, i8 184, i8 185, i8 186, i8 187, i8 188, i8 189, i8 190, i8 191, i8 192, i8 193, i8 194, i8 195, i8 196, i8 197, i8 198, i8 199, i8 200, i8 201, i8 202, i8 203, i8 204, i8 205, i8 206, i8 207, i8 208, i8 209, i8 210, i8 211, i8 212, i8 213, i8 214, i8 215, i8 216, i8 217, i8 218, i8 219, i8 220, i8 221, i8 222, i8 223, i8 224, i8 225, i8 226, i8 227, i8 228, i8 229, i8 230, i8 231, i8 232, i8 233, i8 234, i8 235, i8 236, i8 237, i8 238, i8 239, i8 240, i8 241, i8 242, i8 243, i8 244, i8 245, i8 246, i8 247, i8 248, i8 249, i8 250, i8 251, i8 252, i8 253, i8 254, i8 255, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63, i8 64, i8 65, i8 66, i8 67, i8 68, i8 69, i8 70, i8 71, i8 72, i8 73, i8 74, i8 75, i8 76, i8 77, i8 78, i8 79, i8 80, i8 81, i8 82, i8 83, i8 84, i8 85, i8 86, i8 87, i8 88, i8 89, i8 90, i8 91, i8 92, i8 93, i8 94, i8 95, i8 96, i8 97, i8 98, i8 99, i8 100, i8 101, i8 102, i8 103, i8 104, i8 105, i8 106, i8 107, i8 108, i8 109, i8 110, i8 111, i8 112, i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 128, i8 129, i8 130, i8 131, i8 132, i8 133, i8 134, i8 135, i8 136, i8 137, i8 138, i8 139, i8 140, i8 141, i8 142, i8 143, i8 144, i8 145, i8 146, i8 147, i8 148, i8 149, i8 150, i8 151, i8 152, i8 153, i8 154, i8 155, i8 156, i8 157, i8 158, i8 159, i8 160, i8 161, i8 162, i8 163, i8 164, i8 165, i8 166, i8 167, i8 168, i8 169, i8 170, i8 171, i8 172, i8 173, i8 174, i8 175, i8 176, i8 177, i8 178, i8 179, i8 180, i8 181, i8 182, i8 183, i8 184, i8 185, i8 186, i8 187, i8 188, i8 189, i8 190, i8 191, i8 192, i8 193, i8 194, i8 195, i8 196, i8 197, i8 198, i8 199, i8 200, i8 201, i8 202, i8 203, i8 204, i8 205, i8 206, i8 207, i8 208, i8 209, i8 210, i8 211, i8 212, i8 213, i8 214, i8 215, i8 216, i8 217, i8 218, i8 219, i8 220, i8 221, i8 222, i8 223, i8 224, i8 225, i8 226, i8 227, i8 228, i8 229, i8 230, i8 231, i8 232, i8 233, i8 234, i8 235, i8 236, i8 237, i8 238, i8 239, i8 240, i8 241, i8 242, i8 243, i8 244, i8 245, i8 246, i8 247, i8 248, i8 249, i8 250, i8 251, i8 252, i8 253, i8 254, i8 255> 930} 931 932define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_1() vscale_range(16, 1024) { 933; RV32-LABEL: buildvec_not_vid_v512i8_indices_overflow_1: 934; RV32: # %bb.0: 935; RV32-NEXT: li a0, 512 936; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma 937; RV32-NEXT: vid.v v8 938; RV32-NEXT: vsrl.vi v8, v8, 3 939; RV32-NEXT: vadd.vi v0, v8, -1 940; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 941; RV32-NEXT: vmv.v.i v8, 1 942; RV32-NEXT: vmerge.vim v8, v8, 0, v0 943; RV32-NEXT: ret 944; 945; RV64V-LABEL: buildvec_not_vid_v512i8_indices_overflow_1: 946; RV64V: # %bb.0: 947; RV64V-NEXT: li a0, 512 948; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma 949; RV64V-NEXT: vid.v v8 950; RV64V-NEXT: vsrl.vi v8, v8, 2 951; RV64V-NEXT: vadd.vi v0, v8, -1 952; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma 953; RV64V-NEXT: vmv.v.i v8, 1 954; RV64V-NEXT: vmerge.vim v8, v8, 0, v0 955; RV64V-NEXT: ret 956; 957; RV64ZVE32-LABEL: buildvec_not_vid_v512i8_indices_overflow_1: 958; RV64ZVE32: # %bb.0: 959; RV64ZVE32-NEXT: li a0, 512 960; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma 961; RV64ZVE32-NEXT: vid.v v8 962; RV64ZVE32-NEXT: vsrl.vi v8, v8, 3 963; RV64ZVE32-NEXT: vadd.vi v0, v8, -1 964; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 965; RV64ZVE32-NEXT: vmv.v.i v8, 1 966; RV64ZVE32-NEXT: vmerge.vim v8, v8, 0, v0 967; RV64ZVE32-NEXT: ret 968 ret <512 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 969} 970 971define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_2() vscale_range(16, 1024) { 972; RV32-LABEL: buildvec_not_vid_v512i8_indices_overflow_2: 973; RV32: # %bb.0: 974; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma 975; RV32-NEXT: vmv.v.i v0, 15 976; RV32-NEXT: vmv.v.i v9, 0 977; RV32-NEXT: li a0, 512 978; RV32-NEXT: li a1, 240 979; RV32-NEXT: vmv.s.x v8, a1 980; RV32-NEXT: li a1, 15 981; RV32-NEXT: vmerge.vim v10, v9, -1, v0 982; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 983; RV32-NEXT: vmv.v.i v12, 3 984; RV32-NEXT: slli a1, a1, 8 985; RV32-NEXT: vmv1r.v v0, v10 986; RV32-NEXT: vmerge.vim v12, v12, 0, v0 987; RV32-NEXT: vmv1r.v v0, v8 988; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma 989; RV32-NEXT: vmerge.vim v10, v9, -1, v0 990; RV32-NEXT: vmv.s.x v8, a1 991; RV32-NEXT: vmv1r.v v0, v10 992; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 993; RV32-NEXT: vmerge.vim v12, v12, 1, v0 994; RV32-NEXT: vmv1r.v v0, v8 995; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma 996; RV32-NEXT: vmerge.vim v8, v9, -1, v0 997; RV32-NEXT: vmv1r.v v0, v8 998; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 999; RV32-NEXT: vmerge.vim v8, v12, 2, v0 1000; RV32-NEXT: ret 1001; 1002; RV64V-LABEL: buildvec_not_vid_v512i8_indices_overflow_2: 1003; RV64V: # %bb.0: 1004; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma 1005; RV64V-NEXT: vmv.v.i v0, 3 1006; RV64V-NEXT: vmv.v.i v9, 0 1007; RV64V-NEXT: li a0, 512 1008; RV64V-NEXT: vmv.v.i v8, 12 1009; RV64V-NEXT: li a1, 48 1010; RV64V-NEXT: vmerge.vim v10, v9, -1, v0 1011; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1012; RV64V-NEXT: vmv.v.i v12, 3 1013; RV64V-NEXT: vmv1r.v v0, v10 1014; RV64V-NEXT: vmerge.vim v12, v12, 0, v0 1015; RV64V-NEXT: vmv1r.v v0, v8 1016; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma 1017; RV64V-NEXT: vmerge.vim v10, v9, -1, v0 1018; RV64V-NEXT: vmv.s.x v8, a1 1019; RV64V-NEXT: vmv.v.v v0, v10 1020; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1021; RV64V-NEXT: vmerge.vim v12, v12, 1, v0 1022; RV64V-NEXT: vmv1r.v v0, v8 1023; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma 1024; RV64V-NEXT: vmerge.vim v8, v9, -1, v0 1025; RV64V-NEXT: vmv.v.v v0, v8 1026; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1027; RV64V-NEXT: vmerge.vim v8, v12, 2, v0 1028; RV64V-NEXT: ret 1029; 1030; RV64ZVE32-LABEL: buildvec_not_vid_v512i8_indices_overflow_2: 1031; RV64ZVE32: # %bb.0: 1032; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma 1033; RV64ZVE32-NEXT: vmv.v.i v0, 15 1034; RV64ZVE32-NEXT: vmv.v.i v9, 0 1035; RV64ZVE32-NEXT: li a0, 512 1036; RV64ZVE32-NEXT: li a1, 240 1037; RV64ZVE32-NEXT: vmv.s.x v8, a1 1038; RV64ZVE32-NEXT: li a1, 15 1039; RV64ZVE32-NEXT: vmerge.vim v10, v9, -1, v0 1040; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1041; RV64ZVE32-NEXT: vmv.v.i v12, 3 1042; RV64ZVE32-NEXT: slli a1, a1, 8 1043; RV64ZVE32-NEXT: vmv1r.v v0, v10 1044; RV64ZVE32-NEXT: vmerge.vim v12, v12, 0, v0 1045; RV64ZVE32-NEXT: vmv1r.v v0, v8 1046; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma 1047; RV64ZVE32-NEXT: vmerge.vim v10, v9, -1, v0 1048; RV64ZVE32-NEXT: vmv.s.x v8, a1 1049; RV64ZVE32-NEXT: vmv.v.v v0, v10 1050; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1051; RV64ZVE32-NEXT: vmerge.vim v12, v12, 1, v0 1052; RV64ZVE32-NEXT: vmv1r.v v0, v8 1053; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma 1054; RV64ZVE32-NEXT: vmerge.vim v8, v9, -1, v0 1055; RV64ZVE32-NEXT: vmv.v.v v0, v8 1056; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1057; RV64ZVE32-NEXT: vmerge.vim v8, v12, 2, v0 1058; RV64ZVE32-NEXT: ret 1059 ret <512 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> 1060} 1061 1062define <8 x i32> @prefix_overwrite(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) { 1063; CHECK-LABEL: prefix_overwrite: 1064; CHECK: # %bb.0: 1065; CHECK-NEXT: vsetivli zero, 8, e32, m1, tu, ma 1066; CHECK-NEXT: vmv.s.x v10, a1 1067; CHECK-NEXT: vmv.s.x v8, a0 1068; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma 1069; CHECK-NEXT: vslideup.vi v8, v10, 1 1070; CHECK-NEXT: vmv.s.x v10, a2 1071; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma 1072; CHECK-NEXT: vslideup.vi v8, v10, 2 1073; CHECK-NEXT: vmv.s.x v10, a3 1074; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma 1075; CHECK-NEXT: vslideup.vi v8, v10, 3 1076; CHECK-NEXT: ret 1077 %v0 = insertelement <8 x i32> %vin, i32 %a, i32 0 1078 %v1 = insertelement <8 x i32> %v0, i32 %b, i32 1 1079 %v2 = insertelement <8 x i32> %v1, i32 %c, i32 2 1080 %v3 = insertelement <8 x i32> %v2, i32 %d, i32 3 1081 ret <8 x i32> %v3 1082} 1083 1084define <8 x i32> @suffix_overwrite(<8 x i32> %vin, i32 %a, i32 %b, i32 %c, i32 %d) { 1085; CHECK-LABEL: suffix_overwrite: 1086; CHECK: # %bb.0: 1087; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma 1088; CHECK-NEXT: vmv.s.x v10, a0 1089; CHECK-NEXT: vslideup.vi v8, v10, 4 1090; CHECK-NEXT: vmv.s.x v10, a1 1091; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma 1092; CHECK-NEXT: vslideup.vi v8, v10, 5 1093; CHECK-NEXT: vmv.s.x v10, a2 1094; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma 1095; CHECK-NEXT: vslideup.vi v8, v10, 6 1096; CHECK-NEXT: vmv.s.x v10, a3 1097; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 1098; CHECK-NEXT: vslideup.vi v8, v10, 7 1099; CHECK-NEXT: ret 1100 %v0 = insertelement <8 x i32> %vin, i32 %a, i32 4 1101 %v1 = insertelement <8 x i32> %v0, i32 %b, i32 5 1102 %v2 = insertelement <8 x i32> %v1, i32 %c, i32 6 1103 %v3 = insertelement <8 x i32> %v2, i32 %d, i32 7 1104 ret <8 x i32> %v3 1105} 1106 1107define <4 x i64> @v4xi64_exact(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) { 1108; RV32-LABEL: v4xi64_exact: 1109; RV32: # %bb.0: 1110; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1111; RV32-NEXT: vmv.v.x v8, a4 1112; RV32-NEXT: vmv.v.x v9, a0 1113; RV32-NEXT: vslide1down.vx v8, v8, a5 1114; RV32-NEXT: vslide1down.vx v10, v9, a1 1115; RV32-NEXT: vslide1down.vx v8, v8, a6 1116; RV32-NEXT: vslide1down.vx v9, v8, a7 1117; RV32-NEXT: vslide1down.vx v8, v10, a2 1118; RV32-NEXT: vslide1down.vx v8, v8, a3 1119; RV32-NEXT: ret 1120; 1121; RV64V-LABEL: v4xi64_exact: 1122; RV64V: # %bb.0: 1123; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1124; RV64V-NEXT: vmv.v.x v8, a2 1125; RV64V-NEXT: vslide1down.vx v9, v8, a3 1126; RV64V-NEXT: vmv.v.x v8, a0 1127; RV64V-NEXT: vslide1down.vx v8, v8, a1 1128; RV64V-NEXT: ret 1129; 1130; RV64ZVE32-LABEL: v4xi64_exact: 1131; RV64ZVE32: # %bb.0: 1132; RV64ZVE32-NEXT: sd a1, 0(a0) 1133; RV64ZVE32-NEXT: sd a2, 8(a0) 1134; RV64ZVE32-NEXT: sd a3, 16(a0) 1135; RV64ZVE32-NEXT: sd a4, 24(a0) 1136; RV64ZVE32-NEXT: ret 1137 %v1 = insertelement <4 x i64> poison, i64 %a, i32 0 1138 %v2 = insertelement <4 x i64> %v1, i64 %b, i32 1 1139 %v3 = insertelement <4 x i64> %v2, i64 %c, i32 2 1140 %v4 = insertelement <4 x i64> %v3, i64 %d, i32 3 1141 ret <4 x i64> %v4 1142} 1143 1144define <8 x i64> @v8xi64_exact(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) vscale_range(2,2) { 1145; RV32-LABEL: v8xi64_exact: 1146; RV32: # %bb.0: 1147; RV32-NEXT: addi sp, sp, -16 1148; RV32-NEXT: .cfi_def_cfa_offset 16 1149; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 1150; RV32-NEXT: .cfi_offset s0, -4 1151; RV32-NEXT: lw t0, 44(sp) 1152; RV32-NEXT: lw t1, 40(sp) 1153; RV32-NEXT: lw t2, 36(sp) 1154; RV32-NEXT: lw t3, 32(sp) 1155; RV32-NEXT: lw t4, 28(sp) 1156; RV32-NEXT: lw t5, 24(sp) 1157; RV32-NEXT: lw t6, 20(sp) 1158; RV32-NEXT: lw s0, 16(sp) 1159; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1160; RV32-NEXT: vmv.v.x v8, a4 1161; RV32-NEXT: vmv.v.x v9, a0 1162; RV32-NEXT: vslide1down.vx v8, v8, a5 1163; RV32-NEXT: vslide1down.vx v9, v9, a1 1164; RV32-NEXT: vslide1down.vx v8, v8, a6 1165; RV32-NEXT: vslide1down.vx v10, v9, a2 1166; RV32-NEXT: vslide1down.vx v9, v8, a7 1167; RV32-NEXT: vslide1down.vx v8, v10, a3 1168; RV32-NEXT: vmv.v.x v10, s0 1169; RV32-NEXT: vslide1down.vx v10, v10, t6 1170; RV32-NEXT: vslide1down.vx v10, v10, t5 1171; RV32-NEXT: vslide1down.vx v10, v10, t4 1172; RV32-NEXT: vmv.v.x v11, t3 1173; RV32-NEXT: vslide1down.vx v11, v11, t2 1174; RV32-NEXT: vslide1down.vx v11, v11, t1 1175; RV32-NEXT: vslide1down.vx v11, v11, t0 1176; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 1177; RV32-NEXT: .cfi_restore s0 1178; RV32-NEXT: addi sp, sp, 16 1179; RV32-NEXT: .cfi_def_cfa_offset 0 1180; RV32-NEXT: ret 1181; 1182; RV64V-LABEL: v8xi64_exact: 1183; RV64V: # %bb.0: 1184; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1185; RV64V-NEXT: vmv.v.x v8, a2 1186; RV64V-NEXT: vmv.v.x v10, a0 1187; RV64V-NEXT: vslide1down.vx v9, v8, a3 1188; RV64V-NEXT: vslide1down.vx v8, v10, a1 1189; RV64V-NEXT: vmv.v.x v10, a4 1190; RV64V-NEXT: vslide1down.vx v10, v10, a5 1191; RV64V-NEXT: vmv.v.x v11, a6 1192; RV64V-NEXT: vslide1down.vx v11, v11, a7 1193; RV64V-NEXT: ret 1194; 1195; RV64ZVE32-LABEL: v8xi64_exact: 1196; RV64ZVE32: # %bb.0: 1197; RV64ZVE32-NEXT: ld t0, 0(sp) 1198; RV64ZVE32-NEXT: sd a5, 32(a0) 1199; RV64ZVE32-NEXT: sd a6, 40(a0) 1200; RV64ZVE32-NEXT: sd a7, 48(a0) 1201; RV64ZVE32-NEXT: sd t0, 56(a0) 1202; RV64ZVE32-NEXT: sd a1, 0(a0) 1203; RV64ZVE32-NEXT: sd a2, 8(a0) 1204; RV64ZVE32-NEXT: sd a3, 16(a0) 1205; RV64ZVE32-NEXT: sd a4, 24(a0) 1206; RV64ZVE32-NEXT: ret 1207 %v1 = insertelement <8 x i64> poison, i64 %a, i32 0 1208 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 1 1209 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 2 1210 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 3 1211 %v5 = insertelement <8 x i64> %v4, i64 %e, i32 4 1212 %v6 = insertelement <8 x i64> %v5, i64 %f, i32 5 1213 %v7 = insertelement <8 x i64> %v6, i64 %g, i32 6 1214 %v8 = insertelement <8 x i64> %v7, i64 %h, i32 7 1215 ret <8 x i64> %v8 1216} 1217 1218define <8 x i64> @v8xi64_exact_equal_halves(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) { 1219; RV32-LABEL: v8xi64_exact_equal_halves: 1220; RV32: # %bb.0: 1221; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1222; RV32-NEXT: vmv.v.x v8, a4 1223; RV32-NEXT: vmv.v.x v9, a0 1224; RV32-NEXT: vslide1down.vx v8, v8, a5 1225; RV32-NEXT: vslide1down.vx v10, v9, a1 1226; RV32-NEXT: vslide1down.vx v8, v8, a6 1227; RV32-NEXT: vslide1down.vx v9, v8, a7 1228; RV32-NEXT: vslide1down.vx v8, v10, a2 1229; RV32-NEXT: vslide1down.vx v8, v8, a3 1230; RV32-NEXT: vmv.v.v v10, v8 1231; RV32-NEXT: vmv.v.v v11, v9 1232; RV32-NEXT: ret 1233; 1234; RV64V-LABEL: v8xi64_exact_equal_halves: 1235; RV64V: # %bb.0: 1236; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1237; RV64V-NEXT: vmv.v.x v8, a2 1238; RV64V-NEXT: vslide1down.vx v9, v8, a3 1239; RV64V-NEXT: vmv.v.x v8, a0 1240; RV64V-NEXT: vslide1down.vx v8, v8, a1 1241; RV64V-NEXT: vmv.v.v v10, v8 1242; RV64V-NEXT: vmv.v.v v11, v9 1243; RV64V-NEXT: ret 1244; 1245; RV64ZVE32-LABEL: v8xi64_exact_equal_halves: 1246; RV64ZVE32: # %bb.0: 1247; RV64ZVE32-NEXT: sd a1, 32(a0) 1248; RV64ZVE32-NEXT: sd a2, 40(a0) 1249; RV64ZVE32-NEXT: sd a3, 48(a0) 1250; RV64ZVE32-NEXT: sd a4, 56(a0) 1251; RV64ZVE32-NEXT: sd a1, 0(a0) 1252; RV64ZVE32-NEXT: sd a2, 8(a0) 1253; RV64ZVE32-NEXT: sd a3, 16(a0) 1254; RV64ZVE32-NEXT: sd a4, 24(a0) 1255; RV64ZVE32-NEXT: ret 1256 %v1 = insertelement <8 x i64> poison, i64 %a, i32 0 1257 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 1 1258 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 2 1259 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 3 1260 %v5 = insertelement <8 x i64> %v4, i64 %a, i32 4 1261 %v6 = insertelement <8 x i64> %v5, i64 %b, i32 5 1262 %v7 = insertelement <8 x i64> %v6, i64 %c, i32 6 1263 %v8 = insertelement <8 x i64> %v7, i64 %d, i32 7 1264 ret <8 x i64> %v8 1265} 1266 1267define <8 x i64> @v8xi64_exact_undef_suffix(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) { 1268; RV32-LABEL: v8xi64_exact_undef_suffix: 1269; RV32: # %bb.0: 1270; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1271; RV32-NEXT: vmv.v.x v8, a4 1272; RV32-NEXT: vmv.v.x v9, a0 1273; RV32-NEXT: vslide1down.vx v8, v8, a5 1274; RV32-NEXT: vslide1down.vx v10, v9, a1 1275; RV32-NEXT: vslide1down.vx v8, v8, a6 1276; RV32-NEXT: vslide1down.vx v9, v8, a7 1277; RV32-NEXT: vslide1down.vx v8, v10, a2 1278; RV32-NEXT: vslide1down.vx v8, v8, a3 1279; RV32-NEXT: ret 1280; 1281; RV64V-LABEL: v8xi64_exact_undef_suffix: 1282; RV64V: # %bb.0: 1283; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1284; RV64V-NEXT: vmv.v.x v8, a2 1285; RV64V-NEXT: vslide1down.vx v9, v8, a3 1286; RV64V-NEXT: vmv.v.x v8, a0 1287; RV64V-NEXT: vslide1down.vx v8, v8, a1 1288; RV64V-NEXT: ret 1289; 1290; RV64ZVE32-LABEL: v8xi64_exact_undef_suffix: 1291; RV64ZVE32: # %bb.0: 1292; RV64ZVE32-NEXT: sd a1, 0(a0) 1293; RV64ZVE32-NEXT: sd a2, 8(a0) 1294; RV64ZVE32-NEXT: sd a3, 16(a0) 1295; RV64ZVE32-NEXT: sd a4, 24(a0) 1296; RV64ZVE32-NEXT: ret 1297 %v1 = insertelement <8 x i64> poison, i64 %a, i32 0 1298 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 1 1299 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 2 1300 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 3 1301 ret <8 x i64> %v4 1302} 1303 1304define <8 x i64> @v8xi64_exact_undef_prefix(i64 %a, i64 %b, i64 %c, i64 %d) vscale_range(2,2) { 1305; RV32-LABEL: v8xi64_exact_undef_prefix: 1306; RV32: # %bb.0: 1307; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1308; RV32-NEXT: vmv.v.x v8, a4 1309; RV32-NEXT: vmv.v.x v9, a0 1310; RV32-NEXT: vslide1down.vx v8, v8, a5 1311; RV32-NEXT: vslide1down.vx v9, v9, a1 1312; RV32-NEXT: vslide1down.vx v8, v8, a6 1313; RV32-NEXT: vslide1down.vx v11, v8, a7 1314; RV32-NEXT: vslide1down.vx v8, v9, a2 1315; RV32-NEXT: vslide1down.vx v10, v8, a3 1316; RV32-NEXT: ret 1317; 1318; RV64V-LABEL: v8xi64_exact_undef_prefix: 1319; RV64V: # %bb.0: 1320; RV64V-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1321; RV64V-NEXT: vmv.v.x v8, a2 1322; RV64V-NEXT: vslide1down.vx v11, v8, a3 1323; RV64V-NEXT: vmv.v.x v8, a0 1324; RV64V-NEXT: vslide1down.vx v10, v8, a1 1325; RV64V-NEXT: ret 1326; 1327; RV64ZVE32-LABEL: v8xi64_exact_undef_prefix: 1328; RV64ZVE32: # %bb.0: 1329; RV64ZVE32-NEXT: sd a1, 32(a0) 1330; RV64ZVE32-NEXT: sd a2, 40(a0) 1331; RV64ZVE32-NEXT: sd a3, 48(a0) 1332; RV64ZVE32-NEXT: sd a4, 56(a0) 1333; RV64ZVE32-NEXT: ret 1334 %v1 = insertelement <8 x i64> poison, i64 %a, i32 4 1335 %v2 = insertelement <8 x i64> %v1, i64 %b, i32 5 1336 %v3 = insertelement <8 x i64> %v2, i64 %c, i32 6 1337 %v4 = insertelement <8 x i64> %v3, i64 %d, i32 7 1338 ret <8 x i64> %v4 1339} 1340 1341 1342define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) { 1343; RV32-ONLY-LABEL: buildvec_v16i8_loads_contigous: 1344; RV32-ONLY: # %bb.0: 1345; RV32-ONLY-NEXT: addi sp, sp, -16 1346; RV32-ONLY-NEXT: .cfi_def_cfa_offset 16 1347; RV32-ONLY-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 1348; RV32-ONLY-NEXT: .cfi_offset s0, -4 1349; RV32-ONLY-NEXT: lbu a1, 0(a0) 1350; RV32-ONLY-NEXT: lbu a2, 1(a0) 1351; RV32-ONLY-NEXT: lbu a3, 2(a0) 1352; RV32-ONLY-NEXT: lbu a4, 3(a0) 1353; RV32-ONLY-NEXT: lbu a5, 4(a0) 1354; RV32-ONLY-NEXT: lbu a6, 5(a0) 1355; RV32-ONLY-NEXT: lbu a7, 6(a0) 1356; RV32-ONLY-NEXT: lbu t0, 7(a0) 1357; RV32-ONLY-NEXT: lbu t1, 8(a0) 1358; RV32-ONLY-NEXT: lbu t2, 9(a0) 1359; RV32-ONLY-NEXT: lbu t3, 10(a0) 1360; RV32-ONLY-NEXT: lbu t4, 11(a0) 1361; RV32-ONLY-NEXT: li t5, 255 1362; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 1363; RV32-ONLY-NEXT: vmv.s.x v0, t5 1364; RV32-ONLY-NEXT: lbu t5, 12(a0) 1365; RV32-ONLY-NEXT: lbu t6, 13(a0) 1366; RV32-ONLY-NEXT: lbu s0, 14(a0) 1367; RV32-ONLY-NEXT: lbu a0, 15(a0) 1368; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 1369; RV32-ONLY-NEXT: vmv.v.x v8, a1 1370; RV32-ONLY-NEXT: vmv.v.x v9, t1 1371; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 1372; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t2 1373; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 1374; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t3 1375; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 1376; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t4 1377; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a5 1378; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t5 1379; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a6 1380; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t6 1381; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7 1382; RV32-ONLY-NEXT: vslide1down.vx v9, v9, s0 1383; RV32-ONLY-NEXT: vslide1down.vx v10, v8, t0 1384; RV32-ONLY-NEXT: vslide1down.vx v8, v9, a0 1385; RV32-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 1386; RV32-ONLY-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 1387; RV32-ONLY-NEXT: .cfi_restore s0 1388; RV32-ONLY-NEXT: addi sp, sp, 16 1389; RV32-ONLY-NEXT: .cfi_def_cfa_offset 0 1390; RV32-ONLY-NEXT: ret 1391; 1392; RV32VB-LABEL: buildvec_v16i8_loads_contigous: 1393; RV32VB: # %bb.0: 1394; RV32VB-NEXT: lbu a1, 0(a0) 1395; RV32VB-NEXT: lbu a2, 1(a0) 1396; RV32VB-NEXT: lbu a3, 2(a0) 1397; RV32VB-NEXT: lbu a4, 3(a0) 1398; RV32VB-NEXT: lbu a5, 4(a0) 1399; RV32VB-NEXT: lbu a6, 5(a0) 1400; RV32VB-NEXT: lbu a7, 6(a0) 1401; RV32VB-NEXT: lbu t0, 7(a0) 1402; RV32VB-NEXT: slli a2, a2, 8 1403; RV32VB-NEXT: slli a3, a3, 16 1404; RV32VB-NEXT: slli a4, a4, 24 1405; RV32VB-NEXT: slli a6, a6, 8 1406; RV32VB-NEXT: or a1, a1, a2 1407; RV32VB-NEXT: or a3, a4, a3 1408; RV32VB-NEXT: or a2, a5, a6 1409; RV32VB-NEXT: lbu a4, 8(a0) 1410; RV32VB-NEXT: lbu a5, 9(a0) 1411; RV32VB-NEXT: lbu a6, 10(a0) 1412; RV32VB-NEXT: lbu t1, 11(a0) 1413; RV32VB-NEXT: slli a7, a7, 16 1414; RV32VB-NEXT: slli t0, t0, 24 1415; RV32VB-NEXT: slli a5, a5, 8 1416; RV32VB-NEXT: slli a6, a6, 16 1417; RV32VB-NEXT: slli t1, t1, 24 1418; RV32VB-NEXT: or a7, t0, a7 1419; RV32VB-NEXT: or a4, a4, a5 1420; RV32VB-NEXT: lbu a5, 12(a0) 1421; RV32VB-NEXT: lbu t0, 13(a0) 1422; RV32VB-NEXT: or a6, t1, a6 1423; RV32VB-NEXT: lbu t1, 14(a0) 1424; RV32VB-NEXT: lbu a0, 15(a0) 1425; RV32VB-NEXT: slli t0, t0, 8 1426; RV32VB-NEXT: or a5, a5, t0 1427; RV32VB-NEXT: slli t1, t1, 16 1428; RV32VB-NEXT: slli a0, a0, 24 1429; RV32VB-NEXT: or a0, a0, t1 1430; RV32VB-NEXT: or a1, a1, a3 1431; RV32VB-NEXT: or a2, a2, a7 1432; RV32VB-NEXT: or a3, a4, a6 1433; RV32VB-NEXT: or a0, a5, a0 1434; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1435; RV32VB-NEXT: vmv.v.x v8, a1 1436; RV32VB-NEXT: vslide1down.vx v8, v8, a2 1437; RV32VB-NEXT: vslide1down.vx v8, v8, a3 1438; RV32VB-NEXT: vslide1down.vx v8, v8, a0 1439; RV32VB-NEXT: ret 1440; 1441; RV32VB-PACK-LABEL: buildvec_v16i8_loads_contigous: 1442; RV32VB-PACK: # %bb.0: 1443; RV32VB-PACK-NEXT: lbu a1, 0(a0) 1444; RV32VB-PACK-NEXT: lbu a2, 1(a0) 1445; RV32VB-PACK-NEXT: lbu a3, 2(a0) 1446; RV32VB-PACK-NEXT: lbu a4, 3(a0) 1447; RV32VB-PACK-NEXT: lbu a5, 4(a0) 1448; RV32VB-PACK-NEXT: lbu a6, 5(a0) 1449; RV32VB-PACK-NEXT: lbu a7, 6(a0) 1450; RV32VB-PACK-NEXT: lbu t0, 7(a0) 1451; RV32VB-PACK-NEXT: packh a1, a1, a2 1452; RV32VB-PACK-NEXT: lbu a2, 8(a0) 1453; RV32VB-PACK-NEXT: lbu t1, 9(a0) 1454; RV32VB-PACK-NEXT: lbu t2, 10(a0) 1455; RV32VB-PACK-NEXT: lbu t3, 11(a0) 1456; RV32VB-PACK-NEXT: packh a3, a3, a4 1457; RV32VB-PACK-NEXT: packh a4, a5, a6 1458; RV32VB-PACK-NEXT: packh a5, a7, t0 1459; RV32VB-PACK-NEXT: lbu a6, 12(a0) 1460; RV32VB-PACK-NEXT: lbu a7, 13(a0) 1461; RV32VB-PACK-NEXT: lbu t0, 14(a0) 1462; RV32VB-PACK-NEXT: lbu a0, 15(a0) 1463; RV32VB-PACK-NEXT: packh a2, a2, t1 1464; RV32VB-PACK-NEXT: packh t1, t2, t3 1465; RV32VB-PACK-NEXT: packh a6, a6, a7 1466; RV32VB-PACK-NEXT: packh a0, t0, a0 1467; RV32VB-PACK-NEXT: pack a1, a1, a3 1468; RV32VB-PACK-NEXT: pack a3, a4, a5 1469; RV32VB-PACK-NEXT: pack a2, a2, t1 1470; RV32VB-PACK-NEXT: pack a0, a6, a0 1471; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1472; RV32VB-PACK-NEXT: vmv.v.x v8, a1 1473; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a3 1474; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a2 1475; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 1476; RV32VB-PACK-NEXT: ret 1477; 1478; RV64V-ONLY-LABEL: buildvec_v16i8_loads_contigous: 1479; RV64V-ONLY: # %bb.0: 1480; RV64V-ONLY-NEXT: addi sp, sp, -16 1481; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 16 1482; RV64V-ONLY-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 1483; RV64V-ONLY-NEXT: .cfi_offset s0, -8 1484; RV64V-ONLY-NEXT: lbu a1, 0(a0) 1485; RV64V-ONLY-NEXT: lbu a2, 1(a0) 1486; RV64V-ONLY-NEXT: lbu a3, 2(a0) 1487; RV64V-ONLY-NEXT: lbu a4, 3(a0) 1488; RV64V-ONLY-NEXT: lbu a5, 4(a0) 1489; RV64V-ONLY-NEXT: lbu a6, 5(a0) 1490; RV64V-ONLY-NEXT: lbu a7, 6(a0) 1491; RV64V-ONLY-NEXT: lbu t0, 7(a0) 1492; RV64V-ONLY-NEXT: lbu t1, 8(a0) 1493; RV64V-ONLY-NEXT: lbu t2, 9(a0) 1494; RV64V-ONLY-NEXT: lbu t3, 10(a0) 1495; RV64V-ONLY-NEXT: lbu t4, 11(a0) 1496; RV64V-ONLY-NEXT: li t5, 255 1497; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 1498; RV64V-ONLY-NEXT: vmv.s.x v0, t5 1499; RV64V-ONLY-NEXT: lbu t5, 12(a0) 1500; RV64V-ONLY-NEXT: lbu t6, 13(a0) 1501; RV64V-ONLY-NEXT: lbu s0, 14(a0) 1502; RV64V-ONLY-NEXT: lbu a0, 15(a0) 1503; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 1504; RV64V-ONLY-NEXT: vmv.v.x v8, a1 1505; RV64V-ONLY-NEXT: vmv.v.x v9, t1 1506; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 1507; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t2 1508; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 1509; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t3 1510; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 1511; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t4 1512; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a5 1513; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t5 1514; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a6 1515; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t6 1516; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7 1517; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, s0 1518; RV64V-ONLY-NEXT: vslide1down.vx v10, v8, t0 1519; RV64V-ONLY-NEXT: vslide1down.vx v8, v9, a0 1520; RV64V-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 1521; RV64V-ONLY-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 1522; RV64V-ONLY-NEXT: .cfi_restore s0 1523; RV64V-ONLY-NEXT: addi sp, sp, 16 1524; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 0 1525; RV64V-ONLY-NEXT: ret 1526; 1527; RVA22U64-LABEL: buildvec_v16i8_loads_contigous: 1528; RVA22U64: # %bb.0: 1529; RVA22U64-NEXT: lbu a6, 0(a0) 1530; RVA22U64-NEXT: lbu a2, 1(a0) 1531; RVA22U64-NEXT: lbu a3, 2(a0) 1532; RVA22U64-NEXT: lbu a4, 3(a0) 1533; RVA22U64-NEXT: lbu a5, 4(a0) 1534; RVA22U64-NEXT: lbu a1, 5(a0) 1535; RVA22U64-NEXT: lbu a7, 6(a0) 1536; RVA22U64-NEXT: lbu t0, 7(a0) 1537; RVA22U64-NEXT: slli a2, a2, 8 1538; RVA22U64-NEXT: slli a3, a3, 16 1539; RVA22U64-NEXT: slli a4, a4, 24 1540; RVA22U64-NEXT: slli a5, a5, 32 1541; RVA22U64-NEXT: slli a1, a1, 40 1542; RVA22U64-NEXT: or a6, a6, a2 1543; RVA22U64-NEXT: or t2, a4, a3 1544; RVA22U64-NEXT: or t1, a1, a5 1545; RVA22U64-NEXT: lbu a4, 8(a0) 1546; RVA22U64-NEXT: lbu a5, 9(a0) 1547; RVA22U64-NEXT: lbu a2, 10(a0) 1548; RVA22U64-NEXT: lbu a1, 11(a0) 1549; RVA22U64-NEXT: slli a7, a7, 48 1550; RVA22U64-NEXT: slli t0, t0, 56 1551; RVA22U64-NEXT: slli a5, a5, 8 1552; RVA22U64-NEXT: slli a2, a2, 16 1553; RVA22U64-NEXT: slli a1, a1, 24 1554; RVA22U64-NEXT: or a7, t0, a7 1555; RVA22U64-NEXT: or a4, a4, a5 1556; RVA22U64-NEXT: or a1, a1, a2 1557; RVA22U64-NEXT: lbu a2, 12(a0) 1558; RVA22U64-NEXT: lbu a5, 13(a0) 1559; RVA22U64-NEXT: lbu a3, 14(a0) 1560; RVA22U64-NEXT: lbu a0, 15(a0) 1561; RVA22U64-NEXT: slli a2, a2, 32 1562; RVA22U64-NEXT: slli a5, a5, 40 1563; RVA22U64-NEXT: or a2, a2, a5 1564; RVA22U64-NEXT: slli a3, a3, 48 1565; RVA22U64-NEXT: slli a0, a0, 56 1566; RVA22U64-NEXT: or a0, a0, a3 1567; RVA22U64-NEXT: or a3, a6, t2 1568; RVA22U64-NEXT: or a5, a7, t1 1569; RVA22U64-NEXT: or a1, a1, a4 1570; RVA22U64-NEXT: or a0, a0, a2 1571; RVA22U64-NEXT: or a3, a3, a5 1572; RVA22U64-NEXT: or a0, a0, a1 1573; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1574; RVA22U64-NEXT: vmv.v.x v8, a3 1575; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 1576; RVA22U64-NEXT: ret 1577; 1578; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_contigous: 1579; RVA22U64-PACK: # %bb.0: 1580; RVA22U64-PACK-NEXT: lbu a1, 0(a0) 1581; RVA22U64-PACK-NEXT: lbu a2, 1(a0) 1582; RVA22U64-PACK-NEXT: lbu a6, 2(a0) 1583; RVA22U64-PACK-NEXT: lbu a7, 3(a0) 1584; RVA22U64-PACK-NEXT: lbu t0, 4(a0) 1585; RVA22U64-PACK-NEXT: lbu a3, 5(a0) 1586; RVA22U64-PACK-NEXT: lbu a4, 6(a0) 1587; RVA22U64-PACK-NEXT: lbu a5, 7(a0) 1588; RVA22U64-PACK-NEXT: packh t1, a1, a2 1589; RVA22U64-PACK-NEXT: lbu t2, 8(a0) 1590; RVA22U64-PACK-NEXT: lbu t3, 9(a0) 1591; RVA22U64-PACK-NEXT: lbu t4, 10(a0) 1592; RVA22U64-PACK-NEXT: lbu a1, 11(a0) 1593; RVA22U64-PACK-NEXT: packh a6, a6, a7 1594; RVA22U64-PACK-NEXT: packh a7, t0, a3 1595; RVA22U64-PACK-NEXT: packh t0, a4, a5 1596; RVA22U64-PACK-NEXT: lbu a5, 12(a0) 1597; RVA22U64-PACK-NEXT: lbu a3, 13(a0) 1598; RVA22U64-PACK-NEXT: lbu a2, 14(a0) 1599; RVA22U64-PACK-NEXT: lbu a0, 15(a0) 1600; RVA22U64-PACK-NEXT: packh a4, t2, t3 1601; RVA22U64-PACK-NEXT: packh a1, t4, a1 1602; RVA22U64-PACK-NEXT: packh a3, a5, a3 1603; RVA22U64-PACK-NEXT: packh a0, a2, a0 1604; RVA22U64-PACK-NEXT: packw a2, t1, a6 1605; RVA22U64-PACK-NEXT: packw a5, a7, t0 1606; RVA22U64-PACK-NEXT: packw a1, a4, a1 1607; RVA22U64-PACK-NEXT: packw a0, a3, a0 1608; RVA22U64-PACK-NEXT: pack a2, a2, a5 1609; RVA22U64-PACK-NEXT: pack a0, a1, a0 1610; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1611; RVA22U64-PACK-NEXT: vmv.v.x v8, a2 1612; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0 1613; RVA22U64-PACK-NEXT: ret 1614; 1615; RV64ZVE32-LABEL: buildvec_v16i8_loads_contigous: 1616; RV64ZVE32: # %bb.0: 1617; RV64ZVE32-NEXT: addi sp, sp, -16 1618; RV64ZVE32-NEXT: .cfi_def_cfa_offset 16 1619; RV64ZVE32-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 1620; RV64ZVE32-NEXT: .cfi_offset s0, -8 1621; RV64ZVE32-NEXT: lbu a1, 0(a0) 1622; RV64ZVE32-NEXT: lbu a2, 1(a0) 1623; RV64ZVE32-NEXT: lbu a3, 2(a0) 1624; RV64ZVE32-NEXT: lbu a4, 3(a0) 1625; RV64ZVE32-NEXT: lbu a5, 4(a0) 1626; RV64ZVE32-NEXT: lbu a6, 5(a0) 1627; RV64ZVE32-NEXT: lbu a7, 6(a0) 1628; RV64ZVE32-NEXT: lbu t0, 7(a0) 1629; RV64ZVE32-NEXT: lbu t1, 8(a0) 1630; RV64ZVE32-NEXT: lbu t2, 9(a0) 1631; RV64ZVE32-NEXT: lbu t3, 10(a0) 1632; RV64ZVE32-NEXT: lbu t4, 11(a0) 1633; RV64ZVE32-NEXT: li t5, 255 1634; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma 1635; RV64ZVE32-NEXT: vmv.s.x v0, t5 1636; RV64ZVE32-NEXT: lbu t5, 12(a0) 1637; RV64ZVE32-NEXT: lbu t6, 13(a0) 1638; RV64ZVE32-NEXT: lbu s0, 14(a0) 1639; RV64ZVE32-NEXT: lbu a0, 15(a0) 1640; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 1641; RV64ZVE32-NEXT: vmv.v.x v8, a1 1642; RV64ZVE32-NEXT: vmv.v.x v9, t1 1643; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 1644; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t2 1645; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 1646; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t3 1647; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 1648; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t4 1649; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a5 1650; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t5 1651; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a6 1652; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t6 1653; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7 1654; RV64ZVE32-NEXT: vslide1down.vx v9, v9, s0 1655; RV64ZVE32-NEXT: vslide1down.vx v10, v8, t0 1656; RV64ZVE32-NEXT: vslide1down.vx v8, v9, a0 1657; RV64ZVE32-NEXT: vslidedown.vi v8, v10, 8, v0.t 1658; RV64ZVE32-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 1659; RV64ZVE32-NEXT: .cfi_restore s0 1660; RV64ZVE32-NEXT: addi sp, sp, 16 1661; RV64ZVE32-NEXT: .cfi_def_cfa_offset 0 1662; RV64ZVE32-NEXT: ret 1663 %p2 = getelementptr i8, ptr %p, i32 1 1664 %p3 = getelementptr i8, ptr %p, i32 2 1665 %p4 = getelementptr i8, ptr %p, i32 3 1666 %p5 = getelementptr i8, ptr %p, i32 4 1667 %p6 = getelementptr i8, ptr %p, i32 5 1668 %p7 = getelementptr i8, ptr %p, i32 6 1669 %p8 = getelementptr i8, ptr %p, i32 7 1670 %p9 = getelementptr i8, ptr %p, i32 8 1671 %p10 = getelementptr i8, ptr %p, i32 9 1672 %p11 = getelementptr i8, ptr %p, i32 10 1673 %p12 = getelementptr i8, ptr %p, i32 11 1674 %p13 = getelementptr i8, ptr %p, i32 12 1675 %p14 = getelementptr i8, ptr %p, i32 13 1676 %p15 = getelementptr i8, ptr %p, i32 14 1677 %p16 = getelementptr i8, ptr %p, i32 15 1678 1679 %ld1 = load i8, ptr %p 1680 %ld2 = load i8, ptr %p2 1681 %ld3 = load i8, ptr %p3 1682 %ld4 = load i8, ptr %p4 1683 %ld5 = load i8, ptr %p5 1684 %ld6 = load i8, ptr %p6 1685 %ld7 = load i8, ptr %p7 1686 %ld8 = load i8, ptr %p8 1687 %ld9 = load i8, ptr %p9 1688 %ld10 = load i8, ptr %p10 1689 %ld11 = load i8, ptr %p11 1690 %ld12 = load i8, ptr %p12 1691 %ld13 = load i8, ptr %p13 1692 %ld14 = load i8, ptr %p14 1693 %ld15 = load i8, ptr %p15 1694 %ld16 = load i8, ptr %p16 1695 1696 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 0 1697 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 1 1698 %v3 = insertelement <16 x i8> %v2, i8 %ld3, i32 2 1699 %v4 = insertelement <16 x i8> %v3, i8 %ld4, i32 3 1700 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 4 1701 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 5 1702 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 6 1703 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 7 1704 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 8 1705 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 9 1706 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 10 1707 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 11 1708 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 12 1709 %v14 = insertelement <16 x i8> %v13, i8 %ld14, i32 13 1710 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 14 1711 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 15 1712 ret <16 x i8> %v16 1713} 1714 1715 1716define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) { 1717; RV32-ONLY-LABEL: buildvec_v16i8_loads_gather: 1718; RV32-ONLY: # %bb.0: 1719; RV32-ONLY-NEXT: addi sp, sp, -16 1720; RV32-ONLY-NEXT: .cfi_def_cfa_offset 16 1721; RV32-ONLY-NEXT: sw s0, 12(sp) # 4-byte Folded Spill 1722; RV32-ONLY-NEXT: .cfi_offset s0, -4 1723; RV32-ONLY-NEXT: lbu a1, 0(a0) 1724; RV32-ONLY-NEXT: lbu a2, 1(a0) 1725; RV32-ONLY-NEXT: lbu a3, 22(a0) 1726; RV32-ONLY-NEXT: lbu a4, 31(a0) 1727; RV32-ONLY-NEXT: lbu a5, 623(a0) 1728; RV32-ONLY-NEXT: lbu a6, 44(a0) 1729; RV32-ONLY-NEXT: lbu a7, 55(a0) 1730; RV32-ONLY-NEXT: lbu t0, 75(a0) 1731; RV32-ONLY-NEXT: lbu t1, 82(a0) 1732; RV32-ONLY-NEXT: lbu t2, 154(a0) 1733; RV32-ONLY-NEXT: lbu t3, 161(a0) 1734; RV32-ONLY-NEXT: lbu t4, 163(a0) 1735; RV32-ONLY-NEXT: li t5, 255 1736; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 1737; RV32-ONLY-NEXT: vmv.s.x v0, t5 1738; RV32-ONLY-NEXT: lbu t5, 93(a0) 1739; RV32-ONLY-NEXT: lbu t6, 105(a0) 1740; RV32-ONLY-NEXT: lbu s0, 124(a0) 1741; RV32-ONLY-NEXT: lbu a0, 144(a0) 1742; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 1743; RV32-ONLY-NEXT: vmv.v.x v8, a1 1744; RV32-ONLY-NEXT: vmv.v.x v9, t1 1745; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 1746; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t5 1747; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 1748; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t6 1749; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 1750; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t3 1751; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a6 1752; RV32-ONLY-NEXT: vslide1down.vx v9, v9, s0 1753; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7 1754; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t4 1755; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a5 1756; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a0 1757; RV32-ONLY-NEXT: vslide1down.vx v10, v8, t0 1758; RV32-ONLY-NEXT: vslide1down.vx v8, v9, t2 1759; RV32-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 1760; RV32-ONLY-NEXT: lw s0, 12(sp) # 4-byte Folded Reload 1761; RV32-ONLY-NEXT: .cfi_restore s0 1762; RV32-ONLY-NEXT: addi sp, sp, 16 1763; RV32-ONLY-NEXT: .cfi_def_cfa_offset 0 1764; RV32-ONLY-NEXT: ret 1765; 1766; RV32VB-LABEL: buildvec_v16i8_loads_gather: 1767; RV32VB: # %bb.0: 1768; RV32VB-NEXT: lbu a1, 0(a0) 1769; RV32VB-NEXT: lbu a2, 1(a0) 1770; RV32VB-NEXT: lbu a3, 22(a0) 1771; RV32VB-NEXT: lbu a4, 31(a0) 1772; RV32VB-NEXT: lbu a5, 623(a0) 1773; RV32VB-NEXT: lbu a6, 44(a0) 1774; RV32VB-NEXT: lbu a7, 55(a0) 1775; RV32VB-NEXT: lbu t0, 75(a0) 1776; RV32VB-NEXT: lbu t1, 82(a0) 1777; RV32VB-NEXT: slli a2, a2, 8 1778; RV32VB-NEXT: slli a3, a3, 16 1779; RV32VB-NEXT: slli a4, a4, 24 1780; RV32VB-NEXT: or a1, a1, a2 1781; RV32VB-NEXT: or a3, a4, a3 1782; RV32VB-NEXT: lbu a2, 93(a0) 1783; RV32VB-NEXT: lbu a4, 105(a0) 1784; RV32VB-NEXT: lbu t2, 124(a0) 1785; RV32VB-NEXT: lbu t3, 144(a0) 1786; RV32VB-NEXT: slli a7, a7, 8 1787; RV32VB-NEXT: slli a5, a5, 16 1788; RV32VB-NEXT: slli t0, t0, 24 1789; RV32VB-NEXT: slli a2, a2, 8 1790; RV32VB-NEXT: or a6, a6, a7 1791; RV32VB-NEXT: or a5, t0, a5 1792; RV32VB-NEXT: lbu a7, 154(a0) 1793; RV32VB-NEXT: lbu t0, 161(a0) 1794; RV32VB-NEXT: or a2, t1, a2 1795; RV32VB-NEXT: lbu a0, 163(a0) 1796; RV32VB-NEXT: slli a4, a4, 16 1797; RV32VB-NEXT: slli t0, t0, 24 1798; RV32VB-NEXT: or a4, t0, a4 1799; RV32VB-NEXT: slli a0, a0, 8 1800; RV32VB-NEXT: or a0, t2, a0 1801; RV32VB-NEXT: slli t3, t3, 16 1802; RV32VB-NEXT: slli a7, a7, 24 1803; RV32VB-NEXT: or a7, a7, t3 1804; RV32VB-NEXT: or a1, a1, a3 1805; RV32VB-NEXT: or a3, a6, a5 1806; RV32VB-NEXT: or a2, a2, a4 1807; RV32VB-NEXT: or a0, a0, a7 1808; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1809; RV32VB-NEXT: vmv.v.x v8, a1 1810; RV32VB-NEXT: vslide1down.vx v8, v8, a3 1811; RV32VB-NEXT: vslide1down.vx v8, v8, a2 1812; RV32VB-NEXT: vslide1down.vx v8, v8, a0 1813; RV32VB-NEXT: ret 1814; 1815; RV32VB-PACK-LABEL: buildvec_v16i8_loads_gather: 1816; RV32VB-PACK: # %bb.0: 1817; RV32VB-PACK-NEXT: lbu a1, 0(a0) 1818; RV32VB-PACK-NEXT: lbu a2, 1(a0) 1819; RV32VB-PACK-NEXT: lbu a3, 22(a0) 1820; RV32VB-PACK-NEXT: lbu a4, 31(a0) 1821; RV32VB-PACK-NEXT: lbu a5, 623(a0) 1822; RV32VB-PACK-NEXT: lbu a6, 44(a0) 1823; RV32VB-PACK-NEXT: lbu a7, 55(a0) 1824; RV32VB-PACK-NEXT: lbu t0, 75(a0) 1825; RV32VB-PACK-NEXT: lbu t1, 82(a0) 1826; RV32VB-PACK-NEXT: packh a1, a1, a2 1827; RV32VB-PACK-NEXT: lbu a2, 154(a0) 1828; RV32VB-PACK-NEXT: lbu t2, 161(a0) 1829; RV32VB-PACK-NEXT: lbu t3, 163(a0) 1830; RV32VB-PACK-NEXT: packh a3, a3, a4 1831; RV32VB-PACK-NEXT: packh a4, a6, a7 1832; RV32VB-PACK-NEXT: packh a5, a5, t0 1833; RV32VB-PACK-NEXT: lbu a6, 93(a0) 1834; RV32VB-PACK-NEXT: lbu a7, 105(a0) 1835; RV32VB-PACK-NEXT: lbu t0, 124(a0) 1836; RV32VB-PACK-NEXT: lbu a0, 144(a0) 1837; RV32VB-PACK-NEXT: packh a6, t1, a6 1838; RV32VB-PACK-NEXT: packh a7, a7, t2 1839; RV32VB-PACK-NEXT: packh t0, t0, t3 1840; RV32VB-PACK-NEXT: packh a0, a0, a2 1841; RV32VB-PACK-NEXT: pack a1, a1, a3 1842; RV32VB-PACK-NEXT: pack a2, a4, a5 1843; RV32VB-PACK-NEXT: pack a3, a6, a7 1844; RV32VB-PACK-NEXT: pack a0, t0, a0 1845; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 1846; RV32VB-PACK-NEXT: vmv.v.x v8, a1 1847; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a2 1848; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a3 1849; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 1850; RV32VB-PACK-NEXT: ret 1851; 1852; RV64V-ONLY-LABEL: buildvec_v16i8_loads_gather: 1853; RV64V-ONLY: # %bb.0: 1854; RV64V-ONLY-NEXT: addi sp, sp, -16 1855; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 16 1856; RV64V-ONLY-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 1857; RV64V-ONLY-NEXT: .cfi_offset s0, -8 1858; RV64V-ONLY-NEXT: lbu a1, 0(a0) 1859; RV64V-ONLY-NEXT: lbu a2, 1(a0) 1860; RV64V-ONLY-NEXT: lbu a3, 22(a0) 1861; RV64V-ONLY-NEXT: lbu a4, 31(a0) 1862; RV64V-ONLY-NEXT: lbu a5, 623(a0) 1863; RV64V-ONLY-NEXT: lbu a6, 44(a0) 1864; RV64V-ONLY-NEXT: lbu a7, 55(a0) 1865; RV64V-ONLY-NEXT: lbu t0, 75(a0) 1866; RV64V-ONLY-NEXT: lbu t1, 82(a0) 1867; RV64V-ONLY-NEXT: lbu t2, 154(a0) 1868; RV64V-ONLY-NEXT: lbu t3, 161(a0) 1869; RV64V-ONLY-NEXT: lbu t4, 163(a0) 1870; RV64V-ONLY-NEXT: li t5, 255 1871; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 1872; RV64V-ONLY-NEXT: vmv.s.x v0, t5 1873; RV64V-ONLY-NEXT: lbu t5, 93(a0) 1874; RV64V-ONLY-NEXT: lbu t6, 105(a0) 1875; RV64V-ONLY-NEXT: lbu s0, 124(a0) 1876; RV64V-ONLY-NEXT: lbu a0, 144(a0) 1877; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 1878; RV64V-ONLY-NEXT: vmv.v.x v8, a1 1879; RV64V-ONLY-NEXT: vmv.v.x v9, t1 1880; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 1881; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t5 1882; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 1883; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t6 1884; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 1885; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t3 1886; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a6 1887; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, s0 1888; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7 1889; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t4 1890; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a5 1891; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a0 1892; RV64V-ONLY-NEXT: vslide1down.vx v10, v8, t0 1893; RV64V-ONLY-NEXT: vslide1down.vx v8, v9, t2 1894; RV64V-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 1895; RV64V-ONLY-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 1896; RV64V-ONLY-NEXT: .cfi_restore s0 1897; RV64V-ONLY-NEXT: addi sp, sp, 16 1898; RV64V-ONLY-NEXT: .cfi_def_cfa_offset 0 1899; RV64V-ONLY-NEXT: ret 1900; 1901; RVA22U64-LABEL: buildvec_v16i8_loads_gather: 1902; RVA22U64: # %bb.0: 1903; RVA22U64-NEXT: lbu a1, 0(a0) 1904; RVA22U64-NEXT: lbu a2, 1(a0) 1905; RVA22U64-NEXT: lbu a3, 22(a0) 1906; RVA22U64-NEXT: lbu a4, 31(a0) 1907; RVA22U64-NEXT: lbu a6, 623(a0) 1908; RVA22U64-NEXT: lbu t0, 44(a0) 1909; RVA22U64-NEXT: lbu a7, 55(a0) 1910; RVA22U64-NEXT: lbu a5, 75(a0) 1911; RVA22U64-NEXT: lbu t1, 82(a0) 1912; RVA22U64-NEXT: slli a2, a2, 8 1913; RVA22U64-NEXT: slli a3, a3, 16 1914; RVA22U64-NEXT: slli a4, a4, 24 1915; RVA22U64-NEXT: or t2, a1, a2 1916; RVA22U64-NEXT: or t3, a4, a3 1917; RVA22U64-NEXT: lbu a2, 93(a0) 1918; RVA22U64-NEXT: lbu t4, 105(a0) 1919; RVA22U64-NEXT: lbu t6, 124(a0) 1920; RVA22U64-NEXT: lbu t5, 144(a0) 1921; RVA22U64-NEXT: slli t0, t0, 32 1922; RVA22U64-NEXT: slli a7, a7, 40 1923; RVA22U64-NEXT: slli a6, a6, 48 1924; RVA22U64-NEXT: slli a5, a5, 56 1925; RVA22U64-NEXT: slli a2, a2, 8 1926; RVA22U64-NEXT: or a7, a7, t0 1927; RVA22U64-NEXT: or a5, a5, a6 1928; RVA22U64-NEXT: lbu a3, 154(a0) 1929; RVA22U64-NEXT: lbu a1, 161(a0) 1930; RVA22U64-NEXT: or a2, t1, a2 1931; RVA22U64-NEXT: lbu a0, 163(a0) 1932; RVA22U64-NEXT: slli t4, t4, 16 1933; RVA22U64-NEXT: slli a1, a1, 24 1934; RVA22U64-NEXT: or a1, a1, t4 1935; RVA22U64-NEXT: slli t6, t6, 32 1936; RVA22U64-NEXT: slli a0, a0, 40 1937; RVA22U64-NEXT: or a0, a0, t6 1938; RVA22U64-NEXT: slli t5, t5, 48 1939; RVA22U64-NEXT: slli a3, a3, 56 1940; RVA22U64-NEXT: or a3, a3, t5 1941; RVA22U64-NEXT: or a4, t2, t3 1942; RVA22U64-NEXT: or a5, a5, a7 1943; RVA22U64-NEXT: or a1, a1, a2 1944; RVA22U64-NEXT: or a0, a0, a3 1945; RVA22U64-NEXT: or a4, a4, a5 1946; RVA22U64-NEXT: or a0, a0, a1 1947; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1948; RVA22U64-NEXT: vmv.v.x v8, a4 1949; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 1950; RVA22U64-NEXT: ret 1951; 1952; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_gather: 1953; RVA22U64-PACK: # %bb.0: 1954; RVA22U64-PACK-NEXT: addi sp, sp, -16 1955; RVA22U64-PACK-NEXT: .cfi_def_cfa_offset 16 1956; RVA22U64-PACK-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 1957; RVA22U64-PACK-NEXT: .cfi_offset s0, -8 1958; RVA22U64-PACK-NEXT: lbu a1, 0(a0) 1959; RVA22U64-PACK-NEXT: lbu a2, 1(a0) 1960; RVA22U64-PACK-NEXT: lbu a6, 22(a0) 1961; RVA22U64-PACK-NEXT: lbu a7, 31(a0) 1962; RVA22U64-PACK-NEXT: lbu t0, 623(a0) 1963; RVA22U64-PACK-NEXT: lbu t3, 44(a0) 1964; RVA22U64-PACK-NEXT: lbu t4, 55(a0) 1965; RVA22U64-PACK-NEXT: lbu t5, 75(a0) 1966; RVA22U64-PACK-NEXT: lbu t1, 82(a0) 1967; RVA22U64-PACK-NEXT: packh t2, a1, a2 1968; RVA22U64-PACK-NEXT: lbu t6, 154(a0) 1969; RVA22U64-PACK-NEXT: lbu s0, 161(a0) 1970; RVA22U64-PACK-NEXT: lbu a3, 163(a0) 1971; RVA22U64-PACK-NEXT: packh a6, a6, a7 1972; RVA22U64-PACK-NEXT: packh a7, t3, t4 1973; RVA22U64-PACK-NEXT: packh a2, t0, t5 1974; RVA22U64-PACK-NEXT: lbu a4, 93(a0) 1975; RVA22U64-PACK-NEXT: lbu a5, 105(a0) 1976; RVA22U64-PACK-NEXT: lbu a1, 124(a0) 1977; RVA22U64-PACK-NEXT: lbu a0, 144(a0) 1978; RVA22U64-PACK-NEXT: packh a4, t1, a4 1979; RVA22U64-PACK-NEXT: packh a5, a5, s0 1980; RVA22U64-PACK-NEXT: packh a1, a1, a3 1981; RVA22U64-PACK-NEXT: packh a0, a0, t6 1982; RVA22U64-PACK-NEXT: packw a3, t2, a6 1983; RVA22U64-PACK-NEXT: packw a2, a7, a2 1984; RVA22U64-PACK-NEXT: packw a4, a4, a5 1985; RVA22U64-PACK-NEXT: packw a0, a1, a0 1986; RVA22U64-PACK-NEXT: pack a1, a3, a2 1987; RVA22U64-PACK-NEXT: pack a0, a4, a0 1988; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1989; RVA22U64-PACK-NEXT: vmv.v.x v8, a1 1990; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0 1991; RVA22U64-PACK-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 1992; RVA22U64-PACK-NEXT: .cfi_restore s0 1993; RVA22U64-PACK-NEXT: addi sp, sp, 16 1994; RVA22U64-PACK-NEXT: .cfi_def_cfa_offset 0 1995; RVA22U64-PACK-NEXT: ret 1996; 1997; RV64ZVE32-LABEL: buildvec_v16i8_loads_gather: 1998; RV64ZVE32: # %bb.0: 1999; RV64ZVE32-NEXT: addi sp, sp, -16 2000; RV64ZVE32-NEXT: .cfi_def_cfa_offset 16 2001; RV64ZVE32-NEXT: sd s0, 8(sp) # 8-byte Folded Spill 2002; RV64ZVE32-NEXT: .cfi_offset s0, -8 2003; RV64ZVE32-NEXT: lbu a1, 0(a0) 2004; RV64ZVE32-NEXT: lbu a2, 1(a0) 2005; RV64ZVE32-NEXT: lbu a3, 22(a0) 2006; RV64ZVE32-NEXT: lbu a4, 31(a0) 2007; RV64ZVE32-NEXT: lbu a5, 623(a0) 2008; RV64ZVE32-NEXT: lbu a6, 44(a0) 2009; RV64ZVE32-NEXT: lbu a7, 55(a0) 2010; RV64ZVE32-NEXT: lbu t0, 75(a0) 2011; RV64ZVE32-NEXT: lbu t1, 82(a0) 2012; RV64ZVE32-NEXT: lbu t2, 154(a0) 2013; RV64ZVE32-NEXT: lbu t3, 161(a0) 2014; RV64ZVE32-NEXT: lbu t4, 163(a0) 2015; RV64ZVE32-NEXT: li t5, 255 2016; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2017; RV64ZVE32-NEXT: vmv.s.x v0, t5 2018; RV64ZVE32-NEXT: lbu t5, 93(a0) 2019; RV64ZVE32-NEXT: lbu t6, 105(a0) 2020; RV64ZVE32-NEXT: lbu s0, 124(a0) 2021; RV64ZVE32-NEXT: lbu a0, 144(a0) 2022; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2023; RV64ZVE32-NEXT: vmv.v.x v8, a1 2024; RV64ZVE32-NEXT: vmv.v.x v9, t1 2025; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 2026; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t5 2027; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 2028; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t6 2029; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 2030; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t3 2031; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a6 2032; RV64ZVE32-NEXT: vslide1down.vx v9, v9, s0 2033; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7 2034; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t4 2035; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a5 2036; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a0 2037; RV64ZVE32-NEXT: vslide1down.vx v10, v8, t0 2038; RV64ZVE32-NEXT: vslide1down.vx v8, v9, t2 2039; RV64ZVE32-NEXT: vslidedown.vi v8, v10, 8, v0.t 2040; RV64ZVE32-NEXT: ld s0, 8(sp) # 8-byte Folded Reload 2041; RV64ZVE32-NEXT: .cfi_restore s0 2042; RV64ZVE32-NEXT: addi sp, sp, 16 2043; RV64ZVE32-NEXT: .cfi_def_cfa_offset 0 2044; RV64ZVE32-NEXT: ret 2045 %p2 = getelementptr i8, ptr %p, i32 1 2046 %p3 = getelementptr i8, ptr %p, i32 22 2047 %p4 = getelementptr i8, ptr %p, i32 31 2048 %p5 = getelementptr i8, ptr %p, i32 44 2049 %p6 = getelementptr i8, ptr %p, i32 55 2050 %p7 = getelementptr i8, ptr %p, i32 623 2051 %p8 = getelementptr i8, ptr %p, i32 75 2052 %p9 = getelementptr i8, ptr %p, i32 82 2053 %p10 = getelementptr i8, ptr %p, i32 93 2054 %p11 = getelementptr i8, ptr %p, i32 105 2055 %p12 = getelementptr i8, ptr %p, i32 161 2056 %p13 = getelementptr i8, ptr %p, i32 124 2057 %p14 = getelementptr i8, ptr %p, i32 163 2058 %p15 = getelementptr i8, ptr %p, i32 144 2059 %p16 = getelementptr i8, ptr %p, i32 154 2060 2061 %ld1 = load i8, ptr %p 2062 %ld2 = load i8, ptr %p2 2063 %ld3 = load i8, ptr %p3 2064 %ld4 = load i8, ptr %p4 2065 %ld5 = load i8, ptr %p5 2066 %ld6 = load i8, ptr %p6 2067 %ld7 = load i8, ptr %p7 2068 %ld8 = load i8, ptr %p8 2069 %ld9 = load i8, ptr %p9 2070 %ld10 = load i8, ptr %p10 2071 %ld11 = load i8, ptr %p11 2072 %ld12 = load i8, ptr %p12 2073 %ld13 = load i8, ptr %p13 2074 %ld14 = load i8, ptr %p14 2075 %ld15 = load i8, ptr %p15 2076 %ld16 = load i8, ptr %p16 2077 2078 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 0 2079 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 1 2080 %v3 = insertelement <16 x i8> %v2, i8 %ld3, i32 2 2081 %v4 = insertelement <16 x i8> %v3, i8 %ld4, i32 3 2082 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 4 2083 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 5 2084 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 6 2085 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 7 2086 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 8 2087 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 9 2088 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 10 2089 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 11 2090 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 12 2091 %v14 = insertelement <16 x i8> %v13, i8 %ld14, i32 13 2092 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 14 2093 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 15 2094 ret <16 x i8> %v16 2095} 2096 2097define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) { 2098; RV32-ONLY-LABEL: buildvec_v16i8_undef_low_half: 2099; RV32-ONLY: # %bb.0: 2100; RV32-ONLY-NEXT: lbu a1, 82(a0) 2101; RV32-ONLY-NEXT: lbu a2, 93(a0) 2102; RV32-ONLY-NEXT: lbu a3, 105(a0) 2103; RV32-ONLY-NEXT: lbu a4, 124(a0) 2104; RV32-ONLY-NEXT: lbu a5, 144(a0) 2105; RV32-ONLY-NEXT: lbu a6, 154(a0) 2106; RV32-ONLY-NEXT: lbu a7, 161(a0) 2107; RV32-ONLY-NEXT: lbu a0, 163(a0) 2108; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2109; RV32-ONLY-NEXT: vmv.v.x v8, a1 2110; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 2111; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 2112; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7 2113; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 2114; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a0 2115; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a5 2116; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a6 2117; RV32-ONLY-NEXT: ret 2118; 2119; RV32VB-LABEL: buildvec_v16i8_undef_low_half: 2120; RV32VB: # %bb.0: 2121; RV32VB-NEXT: lbu a1, 93(a0) 2122; RV32VB-NEXT: lbu a2, 82(a0) 2123; RV32VB-NEXT: lbu a3, 105(a0) 2124; RV32VB-NEXT: lbu a4, 124(a0) 2125; RV32VB-NEXT: slli a1, a1, 8 2126; RV32VB-NEXT: lbu a5, 144(a0) 2127; RV32VB-NEXT: lbu a6, 154(a0) 2128; RV32VB-NEXT: lbu a7, 161(a0) 2129; RV32VB-NEXT: or a1, a2, a1 2130; RV32VB-NEXT: lbu a0, 163(a0) 2131; RV32VB-NEXT: slli a3, a3, 16 2132; RV32VB-NEXT: slli a7, a7, 24 2133; RV32VB-NEXT: or a2, a7, a3 2134; RV32VB-NEXT: slli a0, a0, 8 2135; RV32VB-NEXT: or a0, a4, a0 2136; RV32VB-NEXT: slli a5, a5, 16 2137; RV32VB-NEXT: slli a6, a6, 24 2138; RV32VB-NEXT: or a3, a6, a5 2139; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2140; RV32VB-NEXT: vmv.v.i v8, 0 2141; RV32VB-NEXT: or a1, a1, a2 2142; RV32VB-NEXT: or a0, a0, a3 2143; RV32VB-NEXT: vslide1down.vx v8, v8, zero 2144; RV32VB-NEXT: vslide1down.vx v8, v8, a1 2145; RV32VB-NEXT: vslide1down.vx v8, v8, a0 2146; RV32VB-NEXT: ret 2147; 2148; RV32VB-PACK-LABEL: buildvec_v16i8_undef_low_half: 2149; RV32VB-PACK: # %bb.0: 2150; RV32VB-PACK-NEXT: lbu a1, 82(a0) 2151; RV32VB-PACK-NEXT: lbu a2, 93(a0) 2152; RV32VB-PACK-NEXT: lbu a3, 105(a0) 2153; RV32VB-PACK-NEXT: lbu a4, 124(a0) 2154; RV32VB-PACK-NEXT: lbu a5, 161(a0) 2155; RV32VB-PACK-NEXT: lbu a6, 163(a0) 2156; RV32VB-PACK-NEXT: lbu a7, 144(a0) 2157; RV32VB-PACK-NEXT: lbu a0, 154(a0) 2158; RV32VB-PACK-NEXT: packh a1, a1, a2 2159; RV32VB-PACK-NEXT: packh a2, a3, a5 2160; RV32VB-PACK-NEXT: packh a3, a4, a6 2161; RV32VB-PACK-NEXT: packh a0, a7, a0 2162; RV32VB-PACK-NEXT: pack a1, a1, a2 2163; RV32VB-PACK-NEXT: packh a2, a0, a0 2164; RV32VB-PACK-NEXT: pack a2, a2, a2 2165; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2166; RV32VB-PACK-NEXT: vmv.v.x v8, a2 2167; RV32VB-PACK-NEXT: pack a0, a3, a0 2168; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a2 2169; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a1 2170; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2171; RV32VB-PACK-NEXT: ret 2172; 2173; RV64V-ONLY-LABEL: buildvec_v16i8_undef_low_half: 2174; RV64V-ONLY: # %bb.0: 2175; RV64V-ONLY-NEXT: lbu a1, 82(a0) 2176; RV64V-ONLY-NEXT: lbu a2, 93(a0) 2177; RV64V-ONLY-NEXT: lbu a3, 105(a0) 2178; RV64V-ONLY-NEXT: lbu a4, 124(a0) 2179; RV64V-ONLY-NEXT: lbu a5, 144(a0) 2180; RV64V-ONLY-NEXT: lbu a6, 154(a0) 2181; RV64V-ONLY-NEXT: lbu a7, 161(a0) 2182; RV64V-ONLY-NEXT: lbu a0, 163(a0) 2183; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2184; RV64V-ONLY-NEXT: vmv.v.x v8, a1 2185; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 2186; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 2187; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7 2188; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 2189; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a0 2190; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a5 2191; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a6 2192; RV64V-ONLY-NEXT: ret 2193; 2194; RVA22U64-LABEL: buildvec_v16i8_undef_low_half: 2195; RVA22U64: # %bb.0: 2196; RVA22U64-NEXT: lbu a1, 93(a0) 2197; RVA22U64-NEXT: lbu a6, 82(a0) 2198; RVA22U64-NEXT: lbu a7, 105(a0) 2199; RVA22U64-NEXT: lbu a4, 124(a0) 2200; RVA22U64-NEXT: slli a1, a1, 8 2201; RVA22U64-NEXT: lbu a5, 144(a0) 2202; RVA22U64-NEXT: lbu a2, 154(a0) 2203; RVA22U64-NEXT: lbu a3, 161(a0) 2204; RVA22U64-NEXT: or a1, a6, a1 2205; RVA22U64-NEXT: lbu a0, 163(a0) 2206; RVA22U64-NEXT: slli a7, a7, 16 2207; RVA22U64-NEXT: slli a3, a3, 24 2208; RVA22U64-NEXT: or a3, a3, a7 2209; RVA22U64-NEXT: slli a4, a4, 32 2210; RVA22U64-NEXT: slli a0, a0, 40 2211; RVA22U64-NEXT: or a0, a0, a4 2212; RVA22U64-NEXT: slli a5, a5, 48 2213; RVA22U64-NEXT: slli a2, a2, 56 2214; RVA22U64-NEXT: or a2, a2, a5 2215; RVA22U64-NEXT: or a1, a1, a3 2216; RVA22U64-NEXT: or a0, a0, a2 2217; RVA22U64-NEXT: or a0, a0, a1 2218; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2219; RVA22U64-NEXT: vmv.v.i v8, 0 2220; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 2221; RVA22U64-NEXT: ret 2222; 2223; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_low_half: 2224; RVA22U64-PACK: # %bb.0: 2225; RVA22U64-PACK-NEXT: lbu a6, 82(a0) 2226; RVA22U64-PACK-NEXT: lbu a7, 93(a0) 2227; RVA22U64-PACK-NEXT: lbu t0, 105(a0) 2228; RVA22U64-PACK-NEXT: lbu a4, 124(a0) 2229; RVA22U64-PACK-NEXT: lbu a5, 161(a0) 2230; RVA22U64-PACK-NEXT: lbu a1, 163(a0) 2231; RVA22U64-PACK-NEXT: lbu a2, 144(a0) 2232; RVA22U64-PACK-NEXT: lbu a0, 154(a0) 2233; RVA22U64-PACK-NEXT: packh a3, a6, a7 2234; RVA22U64-PACK-NEXT: packh a5, t0, a5 2235; RVA22U64-PACK-NEXT: packh a1, a4, a1 2236; RVA22U64-PACK-NEXT: packh a0, a2, a0 2237; RVA22U64-PACK-NEXT: packw a2, a3, a5 2238; RVA22U64-PACK-NEXT: packh a3, a0, a0 2239; RVA22U64-PACK-NEXT: packw a3, a3, a3 2240; RVA22U64-PACK-NEXT: pack a3, a3, a3 2241; RVA22U64-PACK-NEXT: packw a0, a1, a0 2242; RVA22U64-PACK-NEXT: pack a0, a2, a0 2243; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2244; RVA22U64-PACK-NEXT: vmv.v.x v8, a3 2245; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0 2246; RVA22U64-PACK-NEXT: ret 2247; 2248; RV64ZVE32-LABEL: buildvec_v16i8_undef_low_half: 2249; RV64ZVE32: # %bb.0: 2250; RV64ZVE32-NEXT: lbu a1, 82(a0) 2251; RV64ZVE32-NEXT: lbu a2, 93(a0) 2252; RV64ZVE32-NEXT: lbu a3, 105(a0) 2253; RV64ZVE32-NEXT: lbu a4, 124(a0) 2254; RV64ZVE32-NEXT: lbu a5, 144(a0) 2255; RV64ZVE32-NEXT: lbu a6, 154(a0) 2256; RV64ZVE32-NEXT: lbu a7, 161(a0) 2257; RV64ZVE32-NEXT: lbu a0, 163(a0) 2258; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2259; RV64ZVE32-NEXT: vmv.v.x v8, a1 2260; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 2261; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 2262; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7 2263; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 2264; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a0 2265; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a5 2266; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a6 2267; RV64ZVE32-NEXT: ret 2268 %p9 = getelementptr i8, ptr %p, i32 82 2269 %p10 = getelementptr i8, ptr %p, i32 93 2270 %p11 = getelementptr i8, ptr %p, i32 105 2271 %p12 = getelementptr i8, ptr %p, i32 161 2272 %p13 = getelementptr i8, ptr %p, i32 124 2273 %p14 = getelementptr i8, ptr %p, i32 163 2274 %p15 = getelementptr i8, ptr %p, i32 144 2275 %p16 = getelementptr i8, ptr %p, i32 154 2276 2277 %ld9 = load i8, ptr %p9 2278 %ld10 = load i8, ptr %p10 2279 %ld11 = load i8, ptr %p11 2280 %ld12 = load i8, ptr %p12 2281 %ld13 = load i8, ptr %p13 2282 %ld14 = load i8, ptr %p14 2283 %ld15 = load i8, ptr %p15 2284 %ld16 = load i8, ptr %p16 2285 2286 %v9 = insertelement <16 x i8> poison, i8 %ld9, i32 8 2287 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 9 2288 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 10 2289 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 11 2290 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 12 2291 %v14 = insertelement <16 x i8> %v13, i8 %ld14, i32 13 2292 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 14 2293 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 15 2294 ret <16 x i8> %v16 2295} 2296 2297define <16 x i8> @buildvec_v16i8_undef_high_half(ptr %p) { 2298; RV32-ONLY-LABEL: buildvec_v16i8_undef_high_half: 2299; RV32-ONLY: # %bb.0: 2300; RV32-ONLY-NEXT: lbu a1, 0(a0) 2301; RV32-ONLY-NEXT: lbu a2, 1(a0) 2302; RV32-ONLY-NEXT: lbu a3, 22(a0) 2303; RV32-ONLY-NEXT: lbu a4, 31(a0) 2304; RV32-ONLY-NEXT: lbu a5, 623(a0) 2305; RV32-ONLY-NEXT: lbu a6, 44(a0) 2306; RV32-ONLY-NEXT: lbu a7, 55(a0) 2307; RV32-ONLY-NEXT: lbu a0, 75(a0) 2308; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2309; RV32-ONLY-NEXT: vmv.v.x v8, a1 2310; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 2311; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 2312; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 2313; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a6 2314; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7 2315; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a5 2316; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a0 2317; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 8 2318; RV32-ONLY-NEXT: ret 2319; 2320; RV32VB-LABEL: buildvec_v16i8_undef_high_half: 2321; RV32VB: # %bb.0: 2322; RV32VB-NEXT: lbu a1, 1(a0) 2323; RV32VB-NEXT: lbu a2, 22(a0) 2324; RV32VB-NEXT: lbu a3, 31(a0) 2325; RV32VB-NEXT: lbu a4, 0(a0) 2326; RV32VB-NEXT: slli a1, a1, 8 2327; RV32VB-NEXT: slli a2, a2, 16 2328; RV32VB-NEXT: slli a3, a3, 24 2329; RV32VB-NEXT: or a1, a4, a1 2330; RV32VB-NEXT: lbu a4, 44(a0) 2331; RV32VB-NEXT: lbu a5, 55(a0) 2332; RV32VB-NEXT: or a2, a3, a2 2333; RV32VB-NEXT: lbu a3, 623(a0) 2334; RV32VB-NEXT: lbu a0, 75(a0) 2335; RV32VB-NEXT: slli a5, a5, 8 2336; RV32VB-NEXT: or a4, a4, a5 2337; RV32VB-NEXT: slli a3, a3, 16 2338; RV32VB-NEXT: slli a0, a0, 24 2339; RV32VB-NEXT: or a0, a0, a3 2340; RV32VB-NEXT: or a1, a1, a2 2341; RV32VB-NEXT: or a0, a4, a0 2342; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2343; RV32VB-NEXT: vmv.v.x v8, a1 2344; RV32VB-NEXT: vslide1down.vx v8, v8, a0 2345; RV32VB-NEXT: vslide1down.vx v8, v8, zero 2346; RV32VB-NEXT: vslide1down.vx v8, v8, zero 2347; RV32VB-NEXT: ret 2348; 2349; RV32VB-PACK-LABEL: buildvec_v16i8_undef_high_half: 2350; RV32VB-PACK: # %bb.0: 2351; RV32VB-PACK-NEXT: lbu a1, 0(a0) 2352; RV32VB-PACK-NEXT: lbu a2, 1(a0) 2353; RV32VB-PACK-NEXT: lbu a3, 22(a0) 2354; RV32VB-PACK-NEXT: lbu a4, 31(a0) 2355; RV32VB-PACK-NEXT: lbu a5, 623(a0) 2356; RV32VB-PACK-NEXT: lbu a6, 44(a0) 2357; RV32VB-PACK-NEXT: lbu a7, 55(a0) 2358; RV32VB-PACK-NEXT: lbu a0, 75(a0) 2359; RV32VB-PACK-NEXT: packh a1, a1, a2 2360; RV32VB-PACK-NEXT: packh a2, a3, a4 2361; RV32VB-PACK-NEXT: packh a3, a6, a7 2362; RV32VB-PACK-NEXT: packh a0, a5, a0 2363; RV32VB-PACK-NEXT: pack a1, a1, a2 2364; RV32VB-PACK-NEXT: packh a2, a0, a0 2365; RV32VB-PACK-NEXT: pack a0, a3, a0 2366; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2367; RV32VB-PACK-NEXT: vmv.v.x v8, a1 2368; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2369; RV32VB-PACK-NEXT: pack a0, a2, a2 2370; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2371; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2372; RV32VB-PACK-NEXT: ret 2373; 2374; RV64V-ONLY-LABEL: buildvec_v16i8_undef_high_half: 2375; RV64V-ONLY: # %bb.0: 2376; RV64V-ONLY-NEXT: lbu a1, 0(a0) 2377; RV64V-ONLY-NEXT: lbu a2, 1(a0) 2378; RV64V-ONLY-NEXT: lbu a3, 22(a0) 2379; RV64V-ONLY-NEXT: lbu a4, 31(a0) 2380; RV64V-ONLY-NEXT: lbu a5, 623(a0) 2381; RV64V-ONLY-NEXT: lbu a6, 44(a0) 2382; RV64V-ONLY-NEXT: lbu a7, 55(a0) 2383; RV64V-ONLY-NEXT: lbu a0, 75(a0) 2384; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2385; RV64V-ONLY-NEXT: vmv.v.x v8, a1 2386; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 2387; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 2388; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 2389; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a6 2390; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7 2391; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a5 2392; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a0 2393; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 8 2394; RV64V-ONLY-NEXT: ret 2395; 2396; RVA22U64-LABEL: buildvec_v16i8_undef_high_half: 2397; RVA22U64: # %bb.0: 2398; RVA22U64-NEXT: lbu a1, 1(a0) 2399; RVA22U64-NEXT: lbu a2, 22(a0) 2400; RVA22U64-NEXT: lbu a3, 31(a0) 2401; RVA22U64-NEXT: lbu a4, 0(a0) 2402; RVA22U64-NEXT: slli a1, a1, 8 2403; RVA22U64-NEXT: slli a2, a2, 16 2404; RVA22U64-NEXT: slli a3, a3, 24 2405; RVA22U64-NEXT: or a1, a1, a4 2406; RVA22U64-NEXT: or a2, a2, a3 2407; RVA22U64-NEXT: lbu a3, 44(a0) 2408; RVA22U64-NEXT: lbu a4, 55(a0) 2409; RVA22U64-NEXT: lbu a5, 623(a0) 2410; RVA22U64-NEXT: lbu a0, 75(a0) 2411; RVA22U64-NEXT: slli a3, a3, 32 2412; RVA22U64-NEXT: slli a4, a4, 40 2413; RVA22U64-NEXT: or a3, a3, a4 2414; RVA22U64-NEXT: slli a5, a5, 48 2415; RVA22U64-NEXT: slli a0, a0, 56 2416; RVA22U64-NEXT: or a0, a0, a5 2417; RVA22U64-NEXT: or a1, a1, a2 2418; RVA22U64-NEXT: or a0, a0, a3 2419; RVA22U64-NEXT: or a0, a0, a1 2420; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2421; RVA22U64-NEXT: vmv.v.x v8, a0 2422; RVA22U64-NEXT: vslide1down.vx v8, v8, zero 2423; RVA22U64-NEXT: ret 2424; 2425; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_high_half: 2426; RVA22U64-PACK: # %bb.0: 2427; RVA22U64-PACK-NEXT: lbu a6, 0(a0) 2428; RVA22U64-PACK-NEXT: lbu a7, 1(a0) 2429; RVA22U64-PACK-NEXT: lbu t0, 22(a0) 2430; RVA22U64-PACK-NEXT: lbu a4, 31(a0) 2431; RVA22U64-PACK-NEXT: lbu a5, 623(a0) 2432; RVA22U64-PACK-NEXT: lbu a1, 44(a0) 2433; RVA22U64-PACK-NEXT: lbu a2, 55(a0) 2434; RVA22U64-PACK-NEXT: lbu a0, 75(a0) 2435; RVA22U64-PACK-NEXT: packh a3, a6, a7 2436; RVA22U64-PACK-NEXT: packh a4, t0, a4 2437; RVA22U64-PACK-NEXT: packh a1, a1, a2 2438; RVA22U64-PACK-NEXT: packh a0, a5, a0 2439; RVA22U64-PACK-NEXT: packw a2, a3, a4 2440; RVA22U64-PACK-NEXT: packh a3, a0, a0 2441; RVA22U64-PACK-NEXT: packw a3, a3, a3 2442; RVA22U64-PACK-NEXT: packw a0, a1, a0 2443; RVA22U64-PACK-NEXT: pack a0, a2, a0 2444; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2445; RVA22U64-PACK-NEXT: vmv.v.x v8, a0 2446; RVA22U64-PACK-NEXT: pack a0, a3, a3 2447; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0 2448; RVA22U64-PACK-NEXT: ret 2449; 2450; RV64ZVE32-LABEL: buildvec_v16i8_undef_high_half: 2451; RV64ZVE32: # %bb.0: 2452; RV64ZVE32-NEXT: lbu a1, 0(a0) 2453; RV64ZVE32-NEXT: lbu a2, 1(a0) 2454; RV64ZVE32-NEXT: lbu a3, 22(a0) 2455; RV64ZVE32-NEXT: lbu a4, 31(a0) 2456; RV64ZVE32-NEXT: lbu a5, 623(a0) 2457; RV64ZVE32-NEXT: lbu a6, 44(a0) 2458; RV64ZVE32-NEXT: lbu a7, 55(a0) 2459; RV64ZVE32-NEXT: lbu a0, 75(a0) 2460; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2461; RV64ZVE32-NEXT: vmv.v.x v8, a1 2462; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 2463; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 2464; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 2465; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a6 2466; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7 2467; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a5 2468; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a0 2469; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 8 2470; RV64ZVE32-NEXT: ret 2471 %p2 = getelementptr i8, ptr %p, i32 1 2472 %p3 = getelementptr i8, ptr %p, i32 22 2473 %p4 = getelementptr i8, ptr %p, i32 31 2474 %p5 = getelementptr i8, ptr %p, i32 44 2475 %p6 = getelementptr i8, ptr %p, i32 55 2476 %p7 = getelementptr i8, ptr %p, i32 623 2477 %p8 = getelementptr i8, ptr %p, i32 75 2478 2479 %ld1 = load i8, ptr %p 2480 %ld2 = load i8, ptr %p2 2481 %ld3 = load i8, ptr %p3 2482 %ld4 = load i8, ptr %p4 2483 %ld5 = load i8, ptr %p5 2484 %ld6 = load i8, ptr %p6 2485 %ld7 = load i8, ptr %p7 2486 %ld8 = load i8, ptr %p8 2487 2488 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 0 2489 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 1 2490 %v3 = insertelement <16 x i8> %v2, i8 %ld3, i32 2 2491 %v4 = insertelement <16 x i8> %v3, i8 %ld4, i32 3 2492 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 4 2493 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 5 2494 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 6 2495 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 7 2496 ret <16 x i8> %v8 2497} 2498 2499define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) { 2500; RV32-ONLY-LABEL: buildvec_v16i8_undef_edges: 2501; RV32-ONLY: # %bb.0: 2502; RV32-ONLY-NEXT: lbu a1, 623(a0) 2503; RV32-ONLY-NEXT: lbu a2, 31(a0) 2504; RV32-ONLY-NEXT: lbu a3, 44(a0) 2505; RV32-ONLY-NEXT: lbu a4, 55(a0) 2506; RV32-ONLY-NEXT: lbu a5, 75(a0) 2507; RV32-ONLY-NEXT: li a6, 255 2508; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2509; RV32-ONLY-NEXT: vmv.s.x v0, a6 2510; RV32-ONLY-NEXT: lbu a6, 82(a0) 2511; RV32-ONLY-NEXT: lbu a7, 93(a0) 2512; RV32-ONLY-NEXT: lbu t0, 105(a0) 2513; RV32-ONLY-NEXT: lbu a0, 161(a0) 2514; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2515; RV32-ONLY-NEXT: vmv.v.x v8, a2 2516; RV32-ONLY-NEXT: vmv.v.x v9, a6 2517; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 2518; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a7 2519; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 2520; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t0 2521; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a1 2522; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a0 2523; RV32-ONLY-NEXT: vslide1down.vx v10, v8, a5 2524; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 4 2525; RV32-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 2526; RV32-ONLY-NEXT: ret 2527; 2528; RV32VB-LABEL: buildvec_v16i8_undef_edges: 2529; RV32VB: # %bb.0: 2530; RV32VB-NEXT: lbu a1, 623(a0) 2531; RV32VB-NEXT: lbu a2, 55(a0) 2532; RV32VB-NEXT: lbu a3, 75(a0) 2533; RV32VB-NEXT: lbu a4, 31(a0) 2534; RV32VB-NEXT: lbu a5, 44(a0) 2535; RV32VB-NEXT: slli a2, a2, 8 2536; RV32VB-NEXT: slli a1, a1, 16 2537; RV32VB-NEXT: slli a3, a3, 24 2538; RV32VB-NEXT: or a2, a5, a2 2539; RV32VB-NEXT: lbu a5, 82(a0) 2540; RV32VB-NEXT: lbu a6, 93(a0) 2541; RV32VB-NEXT: or a1, a3, a1 2542; RV32VB-NEXT: lbu a3, 105(a0) 2543; RV32VB-NEXT: lbu a0, 161(a0) 2544; RV32VB-NEXT: slli a6, a6, 8 2545; RV32VB-NEXT: or a5, a5, a6 2546; RV32VB-NEXT: slli a3, a3, 16 2547; RV32VB-NEXT: slli a0, a0, 24 2548; RV32VB-NEXT: or a0, a0, a3 2549; RV32VB-NEXT: slli a4, a4, 24 2550; RV32VB-NEXT: or a1, a2, a1 2551; RV32VB-NEXT: or a0, a5, a0 2552; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2553; RV32VB-NEXT: vmv.v.x v8, a4 2554; RV32VB-NEXT: vslide1down.vx v8, v8, a1 2555; RV32VB-NEXT: vslide1down.vx v8, v8, a0 2556; RV32VB-NEXT: vslide1down.vx v8, v8, zero 2557; RV32VB-NEXT: ret 2558; 2559; RV32VB-PACK-LABEL: buildvec_v16i8_undef_edges: 2560; RV32VB-PACK: # %bb.0: 2561; RV32VB-PACK-NEXT: lbu a1, 623(a0) 2562; RV32VB-PACK-NEXT: lbu a2, 31(a0) 2563; RV32VB-PACK-NEXT: lbu a3, 44(a0) 2564; RV32VB-PACK-NEXT: lbu a4, 55(a0) 2565; RV32VB-PACK-NEXT: lbu a5, 75(a0) 2566; RV32VB-PACK-NEXT: lbu a6, 82(a0) 2567; RV32VB-PACK-NEXT: lbu a7, 93(a0) 2568; RV32VB-PACK-NEXT: lbu t0, 105(a0) 2569; RV32VB-PACK-NEXT: lbu a0, 161(a0) 2570; RV32VB-PACK-NEXT: packh a3, a3, a4 2571; RV32VB-PACK-NEXT: packh a1, a1, a5 2572; RV32VB-PACK-NEXT: packh a4, a6, a7 2573; RV32VB-PACK-NEXT: packh a0, t0, a0 2574; RV32VB-PACK-NEXT: packh a5, a0, a0 2575; RV32VB-PACK-NEXT: packh a2, a0, a2 2576; RV32VB-PACK-NEXT: pack a2, a5, a2 2577; RV32VB-PACK-NEXT: pack a1, a3, a1 2578; RV32VB-PACK-NEXT: pack a0, a4, a0 2579; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2580; RV32VB-PACK-NEXT: vmv.v.x v8, a2 2581; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a1 2582; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2583; RV32VB-PACK-NEXT: pack a0, a5, a5 2584; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2585; RV32VB-PACK-NEXT: ret 2586; 2587; RV64V-ONLY-LABEL: buildvec_v16i8_undef_edges: 2588; RV64V-ONLY: # %bb.0: 2589; RV64V-ONLY-NEXT: lbu a1, 623(a0) 2590; RV64V-ONLY-NEXT: lbu a2, 31(a0) 2591; RV64V-ONLY-NEXT: lbu a3, 44(a0) 2592; RV64V-ONLY-NEXT: lbu a4, 55(a0) 2593; RV64V-ONLY-NEXT: lbu a5, 75(a0) 2594; RV64V-ONLY-NEXT: li a6, 255 2595; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2596; RV64V-ONLY-NEXT: vmv.s.x v0, a6 2597; RV64V-ONLY-NEXT: lbu a6, 82(a0) 2598; RV64V-ONLY-NEXT: lbu a7, 93(a0) 2599; RV64V-ONLY-NEXT: lbu t0, 105(a0) 2600; RV64V-ONLY-NEXT: lbu a0, 161(a0) 2601; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2602; RV64V-ONLY-NEXT: vmv.v.x v8, a2 2603; RV64V-ONLY-NEXT: vmv.v.x v9, a6 2604; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 2605; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a7 2606; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 2607; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t0 2608; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a1 2609; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a0 2610; RV64V-ONLY-NEXT: vslide1down.vx v10, v8, a5 2611; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 4 2612; RV64V-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 2613; RV64V-ONLY-NEXT: ret 2614; 2615; RVA22U64-LABEL: buildvec_v16i8_undef_edges: 2616; RVA22U64: # %bb.0: 2617; RVA22U64-NEXT: lbu a6, 31(a0) 2618; RVA22U64-NEXT: lbu a2, 44(a0) 2619; RVA22U64-NEXT: lbu a3, 55(a0) 2620; RVA22U64-NEXT: lbu a4, 623(a0) 2621; RVA22U64-NEXT: lbu a5, 75(a0) 2622; RVA22U64-NEXT: slli a2, a2, 32 2623; RVA22U64-NEXT: slli a3, a3, 40 2624; RVA22U64-NEXT: slli a4, a4, 48 2625; RVA22U64-NEXT: slli a5, a5, 56 2626; RVA22U64-NEXT: or a2, a2, a3 2627; RVA22U64-NEXT: lbu a3, 82(a0) 2628; RVA22U64-NEXT: lbu a1, 93(a0) 2629; RVA22U64-NEXT: or a4, a4, a5 2630; RVA22U64-NEXT: lbu a5, 105(a0) 2631; RVA22U64-NEXT: lbu a0, 161(a0) 2632; RVA22U64-NEXT: slli a1, a1, 8 2633; RVA22U64-NEXT: or a1, a1, a3 2634; RVA22U64-NEXT: slli a5, a5, 16 2635; RVA22U64-NEXT: slli a0, a0, 24 2636; RVA22U64-NEXT: or a0, a0, a5 2637; RVA22U64-NEXT: slli a6, a6, 24 2638; RVA22U64-NEXT: or a2, a2, a4 2639; RVA22U64-NEXT: add.uw a2, a6, a2 2640; RVA22U64-NEXT: or a0, a0, a1 2641; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2642; RVA22U64-NEXT: vmv.v.x v8, a2 2643; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 2644; RVA22U64-NEXT: ret 2645; 2646; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_edges: 2647; RVA22U64-PACK: # %bb.0: 2648; RVA22U64-PACK-NEXT: lbu a7, 623(a0) 2649; RVA22U64-PACK-NEXT: lbu a6, 31(a0) 2650; RVA22U64-PACK-NEXT: lbu t0, 44(a0) 2651; RVA22U64-PACK-NEXT: lbu a4, 55(a0) 2652; RVA22U64-PACK-NEXT: lbu a5, 75(a0) 2653; RVA22U64-PACK-NEXT: lbu a2, 82(a0) 2654; RVA22U64-PACK-NEXT: lbu a1, 93(a0) 2655; RVA22U64-PACK-NEXT: lbu a3, 105(a0) 2656; RVA22U64-PACK-NEXT: lbu a0, 161(a0) 2657; RVA22U64-PACK-NEXT: packh a4, t0, a4 2658; RVA22U64-PACK-NEXT: packh a5, a7, a5 2659; RVA22U64-PACK-NEXT: packh a1, a2, a1 2660; RVA22U64-PACK-NEXT: packh a0, a3, a0 2661; RVA22U64-PACK-NEXT: packh a2, a0, a0 2662; RVA22U64-PACK-NEXT: packh a3, a0, a6 2663; RVA22U64-PACK-NEXT: packw a3, a2, a3 2664; RVA22U64-PACK-NEXT: packw a2, a2, a2 2665; RVA22U64-PACK-NEXT: packw a4, a4, a5 2666; RVA22U64-PACK-NEXT: packw a0, a1, a0 2667; RVA22U64-PACK-NEXT: pack a1, a3, a4 2668; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2669; RVA22U64-PACK-NEXT: vmv.v.x v8, a1 2670; RVA22U64-PACK-NEXT: pack a0, a0, a2 2671; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0 2672; RVA22U64-PACK-NEXT: ret 2673; 2674; RV64ZVE32-LABEL: buildvec_v16i8_undef_edges: 2675; RV64ZVE32: # %bb.0: 2676; RV64ZVE32-NEXT: lbu a1, 623(a0) 2677; RV64ZVE32-NEXT: lbu a2, 31(a0) 2678; RV64ZVE32-NEXT: lbu a3, 44(a0) 2679; RV64ZVE32-NEXT: lbu a4, 55(a0) 2680; RV64ZVE32-NEXT: lbu a5, 75(a0) 2681; RV64ZVE32-NEXT: li a6, 255 2682; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2683; RV64ZVE32-NEXT: vmv.s.x v0, a6 2684; RV64ZVE32-NEXT: lbu a6, 82(a0) 2685; RV64ZVE32-NEXT: lbu a7, 93(a0) 2686; RV64ZVE32-NEXT: lbu t0, 105(a0) 2687; RV64ZVE32-NEXT: lbu a0, 161(a0) 2688; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2689; RV64ZVE32-NEXT: vmv.v.x v8, a2 2690; RV64ZVE32-NEXT: vmv.v.x v9, a6 2691; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 2692; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a7 2693; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 2694; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t0 2695; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a1 2696; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a0 2697; RV64ZVE32-NEXT: vslide1down.vx v10, v8, a5 2698; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 4 2699; RV64ZVE32-NEXT: vslidedown.vi v8, v10, 8, v0.t 2700; RV64ZVE32-NEXT: ret 2701 %p4 = getelementptr i8, ptr %p, i32 31 2702 %p5 = getelementptr i8, ptr %p, i32 44 2703 %p6 = getelementptr i8, ptr %p, i32 55 2704 %p7 = getelementptr i8, ptr %p, i32 623 2705 %p8 = getelementptr i8, ptr %p, i32 75 2706 %p9 = getelementptr i8, ptr %p, i32 82 2707 %p10 = getelementptr i8, ptr %p, i32 93 2708 %p11 = getelementptr i8, ptr %p, i32 105 2709 %p12 = getelementptr i8, ptr %p, i32 161 2710 2711 %ld4 = load i8, ptr %p4 2712 %ld5 = load i8, ptr %p5 2713 %ld6 = load i8, ptr %p6 2714 %ld7 = load i8, ptr %p7 2715 %ld8 = load i8, ptr %p8 2716 %ld9 = load i8, ptr %p9 2717 %ld10 = load i8, ptr %p10 2718 %ld11 = load i8, ptr %p11 2719 %ld12 = load i8, ptr %p12 2720 2721 %v4 = insertelement <16 x i8> poison, i8 %ld4, i32 3 2722 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 4 2723 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 5 2724 %v7 = insertelement <16 x i8> %v6, i8 %ld7, i32 6 2725 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 7 2726 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 8 2727 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 9 2728 %v11 = insertelement <16 x i8> %v10, i8 %ld11, i32 10 2729 %v12 = insertelement <16 x i8> %v11, i8 %ld12, i32 11 2730 ret <16 x i8> %v12 2731} 2732 2733define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) { 2734; RV32-ONLY-LABEL: buildvec_v16i8_loads_undef_scattered: 2735; RV32-ONLY: # %bb.0: 2736; RV32-ONLY-NEXT: lbu a1, 0(a0) 2737; RV32-ONLY-NEXT: lbu a2, 1(a0) 2738; RV32-ONLY-NEXT: lbu a3, 44(a0) 2739; RV32-ONLY-NEXT: lbu a4, 55(a0) 2740; RV32-ONLY-NEXT: lbu a5, 75(a0) 2741; RV32-ONLY-NEXT: lbu a6, 82(a0) 2742; RV32-ONLY-NEXT: lbu a7, 93(a0) 2743; RV32-ONLY-NEXT: lbu t0, 124(a0) 2744; RV32-ONLY-NEXT: li t1, 255 2745; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2746; RV32-ONLY-NEXT: vmv.s.x v0, t1 2747; RV32-ONLY-NEXT: lbu t1, 144(a0) 2748; RV32-ONLY-NEXT: lbu a0, 154(a0) 2749; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2750; RV32-ONLY-NEXT: vmv.v.x v8, a1 2751; RV32-ONLY-NEXT: vmv.v.x v9, a6 2752; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 2753; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a7 2754; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 2 2755; RV32-ONLY-NEXT: vslidedown.vi v9, v9, 2 2756; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 2757; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t0 2758; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 2759; RV32-ONLY-NEXT: vslidedown.vi v9, v9, 1 2760; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 1 2761; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t1 2762; RV32-ONLY-NEXT: vslide1down.vx v10, v8, a5 2763; RV32-ONLY-NEXT: vslide1down.vx v8, v9, a0 2764; RV32-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 2765; RV32-ONLY-NEXT: ret 2766; 2767; RV32VB-LABEL: buildvec_v16i8_loads_undef_scattered: 2768; RV32VB: # %bb.0: 2769; RV32VB-NEXT: lbu a1, 1(a0) 2770; RV32VB-NEXT: lbu a2, 0(a0) 2771; RV32VB-NEXT: lbu a3, 44(a0) 2772; RV32VB-NEXT: lbu a4, 55(a0) 2773; RV32VB-NEXT: slli a1, a1, 8 2774; RV32VB-NEXT: or a1, a2, a1 2775; RV32VB-NEXT: lbu a2, 75(a0) 2776; RV32VB-NEXT: lbu a5, 82(a0) 2777; RV32VB-NEXT: lbu a6, 93(a0) 2778; RV32VB-NEXT: lbu a7, 124(a0) 2779; RV32VB-NEXT: slli a4, a4, 8 2780; RV32VB-NEXT: or a3, a3, a4 2781; RV32VB-NEXT: lbu a4, 144(a0) 2782; RV32VB-NEXT: lbu a0, 154(a0) 2783; RV32VB-NEXT: slli a6, a6, 8 2784; RV32VB-NEXT: or a5, a5, a6 2785; RV32VB-NEXT: slli a4, a4, 16 2786; RV32VB-NEXT: slli a0, a0, 24 2787; RV32VB-NEXT: or a0, a0, a4 2788; RV32VB-NEXT: slli a2, a2, 24 2789; RV32VB-NEXT: or a2, a3, a2 2790; RV32VB-NEXT: or a0, a7, a0 2791; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2792; RV32VB-NEXT: vmv.v.x v8, a1 2793; RV32VB-NEXT: vslide1down.vx v8, v8, a2 2794; RV32VB-NEXT: vslide1down.vx v8, v8, a5 2795; RV32VB-NEXT: vslide1down.vx v8, v8, a0 2796; RV32VB-NEXT: ret 2797; 2798; RV32VB-PACK-LABEL: buildvec_v16i8_loads_undef_scattered: 2799; RV32VB-PACK: # %bb.0: 2800; RV32VB-PACK-NEXT: lbu a1, 0(a0) 2801; RV32VB-PACK-NEXT: lbu a2, 1(a0) 2802; RV32VB-PACK-NEXT: lbu a3, 44(a0) 2803; RV32VB-PACK-NEXT: lbu a4, 55(a0) 2804; RV32VB-PACK-NEXT: lbu a5, 75(a0) 2805; RV32VB-PACK-NEXT: lbu a6, 82(a0) 2806; RV32VB-PACK-NEXT: lbu a7, 93(a0) 2807; RV32VB-PACK-NEXT: packh a1, a1, a2 2808; RV32VB-PACK-NEXT: lbu a2, 144(a0) 2809; RV32VB-PACK-NEXT: lbu t0, 154(a0) 2810; RV32VB-PACK-NEXT: packh a3, a3, a4 2811; RV32VB-PACK-NEXT: lbu a0, 124(a0) 2812; RV32VB-PACK-NEXT: packh a4, a6, a7 2813; RV32VB-PACK-NEXT: packh a2, a2, t0 2814; RV32VB-PACK-NEXT: packh a5, a0, a5 2815; RV32VB-PACK-NEXT: pack a3, a3, a5 2816; RV32VB-PACK-NEXT: packh a5, a0, a0 2817; RV32VB-PACK-NEXT: packh a0, a0, a0 2818; RV32VB-PACK-NEXT: pack a0, a0, a2 2819; RV32VB-PACK-NEXT: pack a1, a1, a5 2820; RV32VB-PACK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 2821; RV32VB-PACK-NEXT: vmv.v.x v8, a1 2822; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a3 2823; RV32VB-PACK-NEXT: pack a1, a4, a5 2824; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a1 2825; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 2826; RV32VB-PACK-NEXT: ret 2827; 2828; RV64V-ONLY-LABEL: buildvec_v16i8_loads_undef_scattered: 2829; RV64V-ONLY: # %bb.0: 2830; RV64V-ONLY-NEXT: lbu a1, 0(a0) 2831; RV64V-ONLY-NEXT: lbu a2, 1(a0) 2832; RV64V-ONLY-NEXT: lbu a3, 44(a0) 2833; RV64V-ONLY-NEXT: lbu a4, 55(a0) 2834; RV64V-ONLY-NEXT: lbu a5, 75(a0) 2835; RV64V-ONLY-NEXT: lbu a6, 82(a0) 2836; RV64V-ONLY-NEXT: lbu a7, 93(a0) 2837; RV64V-ONLY-NEXT: lbu t0, 124(a0) 2838; RV64V-ONLY-NEXT: li t1, 255 2839; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2840; RV64V-ONLY-NEXT: vmv.s.x v0, t1 2841; RV64V-ONLY-NEXT: lbu t1, 144(a0) 2842; RV64V-ONLY-NEXT: lbu a0, 154(a0) 2843; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2844; RV64V-ONLY-NEXT: vmv.v.x v8, a1 2845; RV64V-ONLY-NEXT: vmv.v.x v9, a6 2846; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 2847; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a7 2848; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 2 2849; RV64V-ONLY-NEXT: vslidedown.vi v9, v9, 2 2850; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 2851; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t0 2852; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 2853; RV64V-ONLY-NEXT: vslidedown.vi v9, v9, 1 2854; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 1 2855; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t1 2856; RV64V-ONLY-NEXT: vslide1down.vx v10, v8, a5 2857; RV64V-ONLY-NEXT: vslide1down.vx v8, v9, a0 2858; RV64V-ONLY-NEXT: vslidedown.vi v8, v10, 8, v0.t 2859; RV64V-ONLY-NEXT: ret 2860; 2861; RVA22U64-LABEL: buildvec_v16i8_loads_undef_scattered: 2862; RVA22U64: # %bb.0: 2863; RVA22U64-NEXT: lbu a1, 1(a0) 2864; RVA22U64-NEXT: lbu a2, 0(a0) 2865; RVA22U64-NEXT: lbu a3, 44(a0) 2866; RVA22U64-NEXT: lbu a4, 55(a0) 2867; RVA22U64-NEXT: slli a1, a1, 8 2868; RVA22U64-NEXT: or a6, a2, a1 2869; RVA22U64-NEXT: lbu a7, 75(a0) 2870; RVA22U64-NEXT: lbu a5, 82(a0) 2871; RVA22U64-NEXT: lbu a1, 93(a0) 2872; RVA22U64-NEXT: lbu a2, 124(a0) 2873; RVA22U64-NEXT: slli a3, a3, 32 2874; RVA22U64-NEXT: slli a4, a4, 40 2875; RVA22U64-NEXT: or a3, a3, a4 2876; RVA22U64-NEXT: lbu a4, 144(a0) 2877; RVA22U64-NEXT: lbu a0, 154(a0) 2878; RVA22U64-NEXT: slli a1, a1, 8 2879; RVA22U64-NEXT: or a1, a1, a5 2880; RVA22U64-NEXT: slli a4, a4, 48 2881; RVA22U64-NEXT: slli a0, a0, 56 2882; RVA22U64-NEXT: or a0, a0, a4 2883; RVA22U64-NEXT: slli a7, a7, 56 2884; RVA22U64-NEXT: or a3, a7, a3 2885; RVA22U64-NEXT: slli a2, a2, 32 2886; RVA22U64-NEXT: or a0, a0, a2 2887; RVA22U64-NEXT: or a2, a6, a3 2888; RVA22U64-NEXT: or a0, a0, a1 2889; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2890; RVA22U64-NEXT: vmv.v.x v8, a2 2891; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 2892; RVA22U64-NEXT: ret 2893; 2894; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_undef_scattered: 2895; RVA22U64-PACK: # %bb.0: 2896; RVA22U64-PACK-NEXT: lbu a1, 0(a0) 2897; RVA22U64-PACK-NEXT: lbu a2, 1(a0) 2898; RVA22U64-PACK-NEXT: lbu a7, 44(a0) 2899; RVA22U64-PACK-NEXT: lbu t0, 55(a0) 2900; RVA22U64-PACK-NEXT: lbu a6, 75(a0) 2901; RVA22U64-PACK-NEXT: lbu a5, 82(a0) 2902; RVA22U64-PACK-NEXT: lbu a3, 93(a0) 2903; RVA22U64-PACK-NEXT: packh t1, a1, a2 2904; RVA22U64-PACK-NEXT: lbu a2, 144(a0) 2905; RVA22U64-PACK-NEXT: lbu a4, 154(a0) 2906; RVA22U64-PACK-NEXT: packh a1, a7, t0 2907; RVA22U64-PACK-NEXT: lbu a0, 124(a0) 2908; RVA22U64-PACK-NEXT: packh a3, a5, a3 2909; RVA22U64-PACK-NEXT: packh a2, a2, a4 2910; RVA22U64-PACK-NEXT: packh a4, a0, a6 2911; RVA22U64-PACK-NEXT: packw a1, a1, a4 2912; RVA22U64-PACK-NEXT: packh a4, a0, a0 2913; RVA22U64-PACK-NEXT: packh a0, a0, a0 2914; RVA22U64-PACK-NEXT: packw a5, t1, a4 2915; RVA22U64-PACK-NEXT: packw a0, a0, a2 2916; RVA22U64-PACK-NEXT: packw a2, a3, a4 2917; RVA22U64-PACK-NEXT: pack a1, a5, a1 2918; RVA22U64-PACK-NEXT: pack a0, a2, a0 2919; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 2920; RVA22U64-PACK-NEXT: vmv.v.x v8, a1 2921; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0 2922; RVA22U64-PACK-NEXT: ret 2923; 2924; RV64ZVE32-LABEL: buildvec_v16i8_loads_undef_scattered: 2925; RV64ZVE32: # %bb.0: 2926; RV64ZVE32-NEXT: lbu a1, 0(a0) 2927; RV64ZVE32-NEXT: lbu a2, 1(a0) 2928; RV64ZVE32-NEXT: lbu a3, 44(a0) 2929; RV64ZVE32-NEXT: lbu a4, 55(a0) 2930; RV64ZVE32-NEXT: lbu a5, 75(a0) 2931; RV64ZVE32-NEXT: lbu a6, 82(a0) 2932; RV64ZVE32-NEXT: lbu a7, 93(a0) 2933; RV64ZVE32-NEXT: lbu t0, 124(a0) 2934; RV64ZVE32-NEXT: li t1, 255 2935; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma 2936; RV64ZVE32-NEXT: vmv.s.x v0, t1 2937; RV64ZVE32-NEXT: lbu t1, 144(a0) 2938; RV64ZVE32-NEXT: lbu a0, 154(a0) 2939; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu 2940; RV64ZVE32-NEXT: vmv.v.x v8, a1 2941; RV64ZVE32-NEXT: vmv.v.x v9, a6 2942; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 2943; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a7 2944; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 2 2945; RV64ZVE32-NEXT: vslidedown.vi v9, v9, 2 2946; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 2947; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t0 2948; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 2949; RV64ZVE32-NEXT: vslidedown.vi v9, v9, 1 2950; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 1 2951; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t1 2952; RV64ZVE32-NEXT: vslide1down.vx v10, v8, a5 2953; RV64ZVE32-NEXT: vslide1down.vx v8, v9, a0 2954; RV64ZVE32-NEXT: vslidedown.vi v8, v10, 8, v0.t 2955; RV64ZVE32-NEXT: ret 2956 %p2 = getelementptr i8, ptr %p, i32 1 2957 %p3 = getelementptr i8, ptr %p, i32 22 2958 %p4 = getelementptr i8, ptr %p, i32 31 2959 %p5 = getelementptr i8, ptr %p, i32 44 2960 %p6 = getelementptr i8, ptr %p, i32 55 2961 %p7 = getelementptr i8, ptr %p, i32 623 2962 %p8 = getelementptr i8, ptr %p, i32 75 2963 %p9 = getelementptr i8, ptr %p, i32 82 2964 %p10 = getelementptr i8, ptr %p, i32 93 2965 %p11 = getelementptr i8, ptr %p, i32 105 2966 %p12 = getelementptr i8, ptr %p, i32 161 2967 %p13 = getelementptr i8, ptr %p, i32 124 2968 %p14 = getelementptr i8, ptr %p, i32 163 2969 %p15 = getelementptr i8, ptr %p, i32 144 2970 %p16 = getelementptr i8, ptr %p, i32 154 2971 2972 %ld1 = load i8, ptr %p 2973 %ld2 = load i8, ptr %p2 2974 %ld3 = load i8, ptr %p3 2975 %ld4 = load i8, ptr %p4 2976 %ld5 = load i8, ptr %p5 2977 %ld6 = load i8, ptr %p6 2978 %ld7 = load i8, ptr %p7 2979 %ld8 = load i8, ptr %p8 2980 %ld9 = load i8, ptr %p9 2981 %ld10 = load i8, ptr %p10 2982 %ld11 = load i8, ptr %p11 2983 %ld12 = load i8, ptr %p12 2984 %ld13 = load i8, ptr %p13 2985 %ld14 = load i8, ptr %p14 2986 %ld15 = load i8, ptr %p15 2987 %ld16 = load i8, ptr %p16 2988 2989 %v1 = insertelement <16 x i8> poison, i8 %ld1, i32 0 2990 %v2 = insertelement <16 x i8> %v1, i8 %ld2, i32 1 2991 %v3 = insertelement <16 x i8> %v2, i8 undef, i32 2 2992 %v4 = insertelement <16 x i8> %v3, i8 undef, i32 3 2993 %v5 = insertelement <16 x i8> %v4, i8 %ld5, i32 4 2994 %v6 = insertelement <16 x i8> %v5, i8 %ld6, i32 5 2995 %v7 = insertelement <16 x i8> %v6, i8 undef, i32 6 2996 %v8 = insertelement <16 x i8> %v7, i8 %ld8, i32 7 2997 %v9 = insertelement <16 x i8> %v8, i8 %ld9, i32 8 2998 %v10 = insertelement <16 x i8> %v9, i8 %ld10, i32 9 2999 %v11 = insertelement <16 x i8> %v10, i8 undef, i32 10 3000 %v12 = insertelement <16 x i8> %v11, i8 undef, i32 11 3001 %v13 = insertelement <16 x i8> %v12, i8 %ld13, i32 12 3002 %v14 = insertelement <16 x i8> %v13, i8 undef, i32 13 3003 %v15 = insertelement <16 x i8> %v14, i8 %ld15, i32 14 3004 %v16 = insertelement <16 x i8> %v15, i8 %ld16, i32 15 3005 ret <16 x i8> %v16 3006} 3007 3008define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %e6, i8 %e7, i8 %e8) { 3009; RV32-ONLY-LABEL: buildvec_v8i8_pack: 3010; RV32-ONLY: # %bb.0: 3011; RV32-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 3012; RV32-ONLY-NEXT: vmv.v.x v8, a0 3013; RV32-ONLY-NEXT: vmv.v.x v9, a4 3014; RV32-ONLY-NEXT: vmv.v.i v0, 15 3015; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a1 3016; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a5 3017; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 3018; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a6 3019; RV32-ONLY-NEXT: vslide1down.vx v10, v8, a3 3020; RV32-ONLY-NEXT: vslide1down.vx v8, v9, a7 3021; RV32-ONLY-NEXT: vslidedown.vi v8, v10, 4, v0.t 3022; RV32-ONLY-NEXT: ret 3023; 3024; RV32VB-LABEL: buildvec_v8i8_pack: 3025; RV32VB: # %bb.0: 3026; RV32VB-NEXT: slli a7, a7, 24 3027; RV32VB-NEXT: andi a6, a6, 255 3028; RV32VB-NEXT: andi a4, a4, 255 3029; RV32VB-NEXT: andi a5, a5, 255 3030; RV32VB-NEXT: slli a3, a3, 24 3031; RV32VB-NEXT: andi a2, a2, 255 3032; RV32VB-NEXT: andi a0, a0, 255 3033; RV32VB-NEXT: andi a1, a1, 255 3034; RV32VB-NEXT: slli a6, a6, 16 3035; RV32VB-NEXT: slli a5, a5, 8 3036; RV32VB-NEXT: slli a2, a2, 16 3037; RV32VB-NEXT: slli a1, a1, 8 3038; RV32VB-NEXT: or a6, a7, a6 3039; RV32VB-NEXT: or a4, a4, a5 3040; RV32VB-NEXT: or a2, a3, a2 3041; RV32VB-NEXT: or a0, a0, a1 3042; RV32VB-NEXT: or a1, a4, a6 3043; RV32VB-NEXT: or a0, a0, a2 3044; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3045; RV32VB-NEXT: vmv.v.x v8, a0 3046; RV32VB-NEXT: vslide1down.vx v8, v8, a1 3047; RV32VB-NEXT: ret 3048; 3049; RV32VB-PACK-LABEL: buildvec_v8i8_pack: 3050; RV32VB-PACK: # %bb.0: 3051; RV32VB-PACK-NEXT: packh a6, a6, a7 3052; RV32VB-PACK-NEXT: packh a4, a4, a5 3053; RV32VB-PACK-NEXT: packh a2, a2, a3 3054; RV32VB-PACK-NEXT: packh a0, a0, a1 3055; RV32VB-PACK-NEXT: pack a1, a4, a6 3056; RV32VB-PACK-NEXT: pack a0, a0, a2 3057; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3058; RV32VB-PACK-NEXT: vmv.v.x v8, a0 3059; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a1 3060; RV32VB-PACK-NEXT: ret 3061; 3062; RV64V-ONLY-LABEL: buildvec_v8i8_pack: 3063; RV64V-ONLY: # %bb.0: 3064; RV64V-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 3065; RV64V-ONLY-NEXT: vmv.v.x v8, a0 3066; RV64V-ONLY-NEXT: vmv.v.x v9, a4 3067; RV64V-ONLY-NEXT: vmv.v.i v0, 15 3068; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a1 3069; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a5 3070; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 3071; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a6 3072; RV64V-ONLY-NEXT: vslide1down.vx v10, v8, a3 3073; RV64V-ONLY-NEXT: vslide1down.vx v8, v9, a7 3074; RV64V-ONLY-NEXT: vslidedown.vi v8, v10, 4, v0.t 3075; RV64V-ONLY-NEXT: ret 3076; 3077; RVA22U64-LABEL: buildvec_v8i8_pack: 3078; RVA22U64: # %bb.0: 3079; RVA22U64-NEXT: andi t0, a4, 255 3080; RVA22U64-NEXT: andi a5, a5, 255 3081; RVA22U64-NEXT: slli a7, a7, 56 3082; RVA22U64-NEXT: andi a4, a6, 255 3083; RVA22U64-NEXT: andi a2, a2, 255 3084; RVA22U64-NEXT: andi a3, a3, 255 3085; RVA22U64-NEXT: andi a0, a0, 255 3086; RVA22U64-NEXT: andi a1, a1, 255 3087; RVA22U64-NEXT: slli t0, t0, 32 3088; RVA22U64-NEXT: slli a5, a5, 40 3089; RVA22U64-NEXT: slli a4, a4, 48 3090; RVA22U64-NEXT: slli a2, a2, 16 3091; RVA22U64-NEXT: slli a3, a3, 24 3092; RVA22U64-NEXT: slli a1, a1, 8 3093; RVA22U64-NEXT: or a5, a5, t0 3094; RVA22U64-NEXT: or a4, a7, a4 3095; RVA22U64-NEXT: or a2, a2, a3 3096; RVA22U64-NEXT: or a0, a0, a1 3097; RVA22U64-NEXT: or a4, a4, a5 3098; RVA22U64-NEXT: or a0, a0, a2 3099; RVA22U64-NEXT: or a0, a0, a4 3100; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3101; RVA22U64-NEXT: vmv.s.x v8, a0 3102; RVA22U64-NEXT: ret 3103; 3104; RVA22U64-PACK-LABEL: buildvec_v8i8_pack: 3105; RVA22U64-PACK: # %bb.0: 3106; RVA22U64-PACK-NEXT: packh a6, a6, a7 3107; RVA22U64-PACK-NEXT: packh a4, a4, a5 3108; RVA22U64-PACK-NEXT: packh a2, a2, a3 3109; RVA22U64-PACK-NEXT: packh a0, a0, a1 3110; RVA22U64-PACK-NEXT: packw a1, a4, a6 3111; RVA22U64-PACK-NEXT: packw a0, a0, a2 3112; RVA22U64-PACK-NEXT: pack a0, a0, a1 3113; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3114; RVA22U64-PACK-NEXT: vmv.s.x v8, a0 3115; RVA22U64-PACK-NEXT: ret 3116; 3117; RV64ZVE32-LABEL: buildvec_v8i8_pack: 3118; RV64ZVE32: # %bb.0: 3119; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu 3120; RV64ZVE32-NEXT: vmv.v.x v8, a0 3121; RV64ZVE32-NEXT: vmv.v.x v9, a4 3122; RV64ZVE32-NEXT: vmv.v.i v0, 15 3123; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a1 3124; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a5 3125; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 3126; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a6 3127; RV64ZVE32-NEXT: vslide1down.vx v10, v8, a3 3128; RV64ZVE32-NEXT: vslide1down.vx v8, v9, a7 3129; RV64ZVE32-NEXT: vslidedown.vi v8, v10, 4, v0.t 3130; RV64ZVE32-NEXT: ret 3131 %v1 = insertelement <8 x i8> poison, i8 %e1, i32 0 3132 %v2 = insertelement <8 x i8> %v1, i8 %e2, i32 1 3133 %v3 = insertelement <8 x i8> %v2, i8 %e3, i32 2 3134 %v4 = insertelement <8 x i8> %v3, i8 %e4, i32 3 3135 %v5 = insertelement <8 x i8> %v4, i8 %e5, i32 4 3136 %v6 = insertelement <8 x i8> %v5, i8 %e6, i32 5 3137 %v7 = insertelement <8 x i8> %v6, i8 %e7, i32 6 3138 %v8 = insertelement <8 x i8> %v7, i8 %e8, i32 7 3139 ret <8 x i8> %v8 3140} 3141 3142define <6 x i8> @buildvec_v6i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %e6) { 3143; RV32-ONLY-LABEL: buildvec_v6i8_pack: 3144; RV32-ONLY: # %bb.0: 3145; RV32-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 3146; RV32-ONLY-NEXT: vmv.v.x v8, a0 3147; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a1 3148; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 3149; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 3150; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a4 3151; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a5 3152; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 2 3153; RV32-ONLY-NEXT: ret 3154; 3155; RV32VB-LABEL: buildvec_v6i8_pack: 3156; RV32VB: # %bb.0: 3157; RV32VB-NEXT: slli a3, a3, 24 3158; RV32VB-NEXT: andi a2, a2, 255 3159; RV32VB-NEXT: andi a0, a0, 255 3160; RV32VB-NEXT: andi a1, a1, 255 3161; RV32VB-NEXT: andi a4, a4, 255 3162; RV32VB-NEXT: andi a5, a5, 255 3163; RV32VB-NEXT: slli a2, a2, 16 3164; RV32VB-NEXT: slli a1, a1, 8 3165; RV32VB-NEXT: slli a5, a5, 8 3166; RV32VB-NEXT: or a2, a3, a2 3167; RV32VB-NEXT: or a0, a0, a1 3168; RV32VB-NEXT: or a0, a0, a2 3169; RV32VB-NEXT: or a4, a4, a5 3170; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3171; RV32VB-NEXT: vmv.v.x v8, a0 3172; RV32VB-NEXT: vslide1down.vx v8, v8, a4 3173; RV32VB-NEXT: ret 3174; 3175; RV32VB-PACK-LABEL: buildvec_v6i8_pack: 3176; RV32VB-PACK: # %bb.0: 3177; RV32VB-PACK-NEXT: packh a2, a2, a3 3178; RV32VB-PACK-NEXT: packh a0, a0, a1 3179; RV32VB-PACK-NEXT: packh a1, a4, a5 3180; RV32VB-PACK-NEXT: packh a3, a0, a0 3181; RV32VB-PACK-NEXT: pack a0, a0, a2 3182; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3183; RV32VB-PACK-NEXT: vmv.v.x v8, a0 3184; RV32VB-PACK-NEXT: pack a0, a1, a3 3185; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a0 3186; RV32VB-PACK-NEXT: ret 3187; 3188; RV64V-ONLY-LABEL: buildvec_v6i8_pack: 3189; RV64V-ONLY: # %bb.0: 3190; RV64V-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 3191; RV64V-ONLY-NEXT: vmv.v.x v8, a0 3192; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a1 3193; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 3194; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 3195; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a4 3196; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a5 3197; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 2 3198; RV64V-ONLY-NEXT: ret 3199; 3200; RVA22U64-LABEL: buildvec_v6i8_pack: 3201; RVA22U64: # %bb.0: 3202; RVA22U64-NEXT: andi a2, a2, 255 3203; RVA22U64-NEXT: andi a3, a3, 255 3204; RVA22U64-NEXT: andi a0, a0, 255 3205; RVA22U64-NEXT: andi a1, a1, 255 3206; RVA22U64-NEXT: andi a4, a4, 255 3207; RVA22U64-NEXT: andi a5, a5, 255 3208; RVA22U64-NEXT: slli a2, a2, 16 3209; RVA22U64-NEXT: slli a3, a3, 24 3210; RVA22U64-NEXT: slli a1, a1, 8 3211; RVA22U64-NEXT: slli a4, a4, 32 3212; RVA22U64-NEXT: slli a5, a5, 40 3213; RVA22U64-NEXT: or a2, a2, a3 3214; RVA22U64-NEXT: or a0, a0, a1 3215; RVA22U64-NEXT: or a0, a0, a2 3216; RVA22U64-NEXT: or a4, a4, a5 3217; RVA22U64-NEXT: or a0, a0, a4 3218; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3219; RVA22U64-NEXT: vmv.s.x v8, a0 3220; RVA22U64-NEXT: ret 3221; 3222; RVA22U64-PACK-LABEL: buildvec_v6i8_pack: 3223; RVA22U64-PACK: # %bb.0: 3224; RVA22U64-PACK-NEXT: packh a2, a2, a3 3225; RVA22U64-PACK-NEXT: packh a0, a0, a1 3226; RVA22U64-PACK-NEXT: packh a1, a4, a5 3227; RVA22U64-PACK-NEXT: packh a3, a0, a0 3228; RVA22U64-PACK-NEXT: packw a0, a0, a2 3229; RVA22U64-PACK-NEXT: packw a1, a1, a3 3230; RVA22U64-PACK-NEXT: pack a0, a0, a1 3231; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3232; RVA22U64-PACK-NEXT: vmv.s.x v8, a0 3233; RVA22U64-PACK-NEXT: ret 3234; 3235; RV64ZVE32-LABEL: buildvec_v6i8_pack: 3236; RV64ZVE32: # %bb.0: 3237; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma 3238; RV64ZVE32-NEXT: vmv.v.x v8, a0 3239; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a1 3240; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 3241; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 3242; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a4 3243; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a5 3244; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 2 3245; RV64ZVE32-NEXT: ret 3246 %v1 = insertelement <6 x i8> poison, i8 %e1, i32 0 3247 %v2 = insertelement <6 x i8> %v1, i8 %e2, i32 1 3248 %v3 = insertelement <6 x i8> %v2, i8 %e3, i32 2 3249 %v4 = insertelement <6 x i8> %v3, i8 %e4, i32 3 3250 %v5 = insertelement <6 x i8> %v4, i8 %e5, i32 4 3251 %v6 = insertelement <6 x i8> %v5, i8 %e6, i32 5 3252 ret <6 x i8> %v6 3253} 3254 3255define <4 x i16> @buildvec_v4i16_pack(i16 %e1, i16 %e2, i16 %e3, i16 %e4) { 3256; RV32-ONLY-LABEL: buildvec_v4i16_pack: 3257; RV32-ONLY: # %bb.0: 3258; RV32-ONLY-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 3259; RV32-ONLY-NEXT: vmv.v.x v8, a0 3260; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a1 3261; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a2 3262; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a3 3263; RV32-ONLY-NEXT: ret 3264; 3265; RV32VB-LABEL: buildvec_v4i16_pack: 3266; RV32VB: # %bb.0: 3267; RV32VB-NEXT: slli a3, a3, 16 3268; RV32VB-NEXT: zext.h a2, a2 3269; RV32VB-NEXT: slli a1, a1, 16 3270; RV32VB-NEXT: zext.h a0, a0 3271; RV32VB-NEXT: or a2, a2, a3 3272; RV32VB-NEXT: or a0, a0, a1 3273; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3274; RV32VB-NEXT: vmv.v.x v8, a0 3275; RV32VB-NEXT: vslide1down.vx v8, v8, a2 3276; RV32VB-NEXT: ret 3277; 3278; RV32VB-PACK-LABEL: buildvec_v4i16_pack: 3279; RV32VB-PACK: # %bb.0: 3280; RV32VB-PACK-NEXT: pack a2, a2, a3 3281; RV32VB-PACK-NEXT: pack a0, a0, a1 3282; RV32VB-PACK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3283; RV32VB-PACK-NEXT: vmv.v.x v8, a0 3284; RV32VB-PACK-NEXT: vslide1down.vx v8, v8, a2 3285; RV32VB-PACK-NEXT: ret 3286; 3287; RV64V-ONLY-LABEL: buildvec_v4i16_pack: 3288; RV64V-ONLY: # %bb.0: 3289; RV64V-ONLY-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 3290; RV64V-ONLY-NEXT: vmv.v.x v8, a0 3291; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a1 3292; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a2 3293; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a3 3294; RV64V-ONLY-NEXT: ret 3295; 3296; RVA22U64-LABEL: buildvec_v4i16_pack: 3297; RVA22U64: # %bb.0: 3298; RVA22U64-NEXT: slli a3, a3, 48 3299; RVA22U64-NEXT: slli a2, a2, 48 3300; RVA22U64-NEXT: zext.h a0, a0 3301; RVA22U64-NEXT: slli a1, a1, 48 3302; RVA22U64-NEXT: srli a2, a2, 16 3303; RVA22U64-NEXT: srli a1, a1, 32 3304; RVA22U64-NEXT: or a2, a2, a3 3305; RVA22U64-NEXT: or a0, a0, a1 3306; RVA22U64-NEXT: or a0, a0, a2 3307; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3308; RVA22U64-NEXT: vmv.s.x v8, a0 3309; RVA22U64-NEXT: ret 3310; 3311; RVA22U64-PACK-LABEL: buildvec_v4i16_pack: 3312; RVA22U64-PACK: # %bb.0: 3313; RVA22U64-PACK-NEXT: packw a2, a2, a3 3314; RVA22U64-PACK-NEXT: packw a0, a0, a1 3315; RVA22U64-PACK-NEXT: pack a0, a0, a2 3316; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3317; RVA22U64-PACK-NEXT: vmv.s.x v8, a0 3318; RVA22U64-PACK-NEXT: ret 3319; 3320; RV64ZVE32-LABEL: buildvec_v4i16_pack: 3321; RV64ZVE32: # %bb.0: 3322; RV64ZVE32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 3323; RV64ZVE32-NEXT: vmv.v.x v8, a0 3324; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a1 3325; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a2 3326; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a3 3327; RV64ZVE32-NEXT: ret 3328 %v1 = insertelement <4 x i16> poison, i16 %e1, i32 0 3329 %v2 = insertelement <4 x i16> %v1, i16 %e2, i32 1 3330 %v3 = insertelement <4 x i16> %v2, i16 %e3, i32 2 3331 %v4 = insertelement <4 x i16> %v3, i16 %e4, i32 3 3332 ret <4 x i16> %v4 3333} 3334 3335define <2 x i32> @buildvec_v2i32_pack(i32 %e1, i32 %e2) { 3336; RV32-LABEL: buildvec_v2i32_pack: 3337; RV32: # %bb.0: 3338; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3339; RV32-NEXT: vmv.v.x v8, a0 3340; RV32-NEXT: vslide1down.vx v8, v8, a1 3341; RV32-NEXT: ret 3342; 3343; RV64V-ONLY-LABEL: buildvec_v2i32_pack: 3344; RV64V-ONLY: # %bb.0: 3345; RV64V-ONLY-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 3346; RV64V-ONLY-NEXT: vmv.v.x v8, a0 3347; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a1 3348; RV64V-ONLY-NEXT: ret 3349; 3350; RVA22U64-LABEL: buildvec_v2i32_pack: 3351; RVA22U64: # %bb.0: 3352; RVA22U64-NEXT: slli a1, a1, 32 3353; RVA22U64-NEXT: add.uw a0, a0, a1 3354; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3355; RVA22U64-NEXT: vmv.s.x v8, a0 3356; RVA22U64-NEXT: ret 3357; 3358; RVA22U64-PACK-LABEL: buildvec_v2i32_pack: 3359; RVA22U64-PACK: # %bb.0: 3360; RVA22U64-PACK-NEXT: pack a0, a0, a1 3361; RVA22U64-PACK-NEXT: vsetivli zero, 1, e64, m1, ta, ma 3362; RVA22U64-PACK-NEXT: vmv.s.x v8, a0 3363; RVA22U64-PACK-NEXT: ret 3364; 3365; RV64ZVE32-LABEL: buildvec_v2i32_pack: 3366; RV64ZVE32: # %bb.0: 3367; RV64ZVE32-NEXT: vsetivli zero, 2, e32, m1, ta, ma 3368; RV64ZVE32-NEXT: vmv.v.x v8, a0 3369; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a1 3370; RV64ZVE32-NEXT: ret 3371 %v1 = insertelement <2 x i32> poison, i32 %e1, i32 0 3372 %v2 = insertelement <2 x i32> %v1, i32 %e2, i32 1 3373 ret <2 x i32> %v2 3374} 3375 3376define <1 x i16> @buildvec_v1i16_pack(i16 %e1) { 3377; CHECK-LABEL: buildvec_v1i16_pack: 3378; CHECK: # %bb.0: 3379; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma 3380; CHECK-NEXT: vmv.s.x v8, a0 3381; CHECK-NEXT: ret 3382 %v1 = insertelement <1 x i16> poison, i16 %e1, i32 0 3383 ret <1 x i16> %v1 3384} 3385 3386define <1 x i32> @buildvec_v1i32_pack(i32 %e1) { 3387; CHECK-LABEL: buildvec_v1i32_pack: 3388; CHECK: # %bb.0: 3389; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma 3390; CHECK-NEXT: vmv.s.x v8, a0 3391; CHECK-NEXT: ret 3392 %v1 = insertelement <1 x i32> poison, i32 %e1, i32 0 3393 ret <1 x i32> %v1 3394} 3395 3396define <4 x i32> @buildvec_vslide1up(i32 %e1, i32 %e2) { 3397; CHECK-LABEL: buildvec_vslide1up: 3398; CHECK: # %bb.0: 3399; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 3400; CHECK-NEXT: vmv.v.x v8, a0 3401; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma 3402; CHECK-NEXT: vmv.s.x v8, a1 3403; CHECK-NEXT: ret 3404 %v1 = insertelement <4 x i32> poison, i32 %e2, i32 0 3405 %v2 = insertelement <4 x i32> %v1, i32 %e1, i32 1 3406 %v3 = insertelement <4 x i32> %v2, i32 %e1, i32 2 3407 %v4 = insertelement <4 x i32> %v3, i32 %e1, i32 3 3408 ret <4 x i32> %v4 3409} 3410 3411define <4 x i1> @buildvec_i1_splat(i1 %e1) { 3412; CHECK-LABEL: buildvec_i1_splat: 3413; CHECK: # %bb.0: 3414; CHECK-NEXT: andi a0, a0, 1 3415; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 3416; CHECK-NEXT: vmv.v.x v8, a0 3417; CHECK-NEXT: vmsne.vi v0, v8, 0 3418; CHECK-NEXT: ret 3419 %v1 = insertelement <4 x i1> poison, i1 %e1, i32 0 3420 %v2 = insertelement <4 x i1> %v1, i1 %e1, i32 1 3421 %v3 = insertelement <4 x i1> %v2, i1 %e1, i32 2 3422 %v4 = insertelement <4 x i1> %v3, i1 %e1, i32 3 3423 ret <4 x i1> %v4 3424} 3425 3426;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 3427; RV64: {{.*}} 3428