xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll (revision fb33268d2f7888f8e083dfa01e81d145748e9ad0) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mattr=+v -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mattr=+v -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
4
5define <4 x i32> @insert_subvector_load_v4i32_v4i32(<4 x i32> %v1, ptr %p) {
6; CHECK-LABEL: insert_subvector_load_v4i32_v4i32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
9; CHECK-NEXT:    vle32.v v8, (a0)
10; CHECK-NEXT:    ret
11  %v2 = load <4 x i32>, ptr %p
12  %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
13  ret <4 x i32> %v3
14}
15
16declare <4 x i32> @llvm.vp.load.v4i32(ptr, <4 x i1>, i32)
17define <4 x i32> @insert_subvector_vp_load_v4i32_v4i32(<4 x i32> %v1, ptr %p, <4 x i1> %mask) {
18; CHECK-LABEL: insert_subvector_vp_load_v4i32_v4i32:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, mu
21; CHECK-NEXT:    vle32.v v8, (a0), v0.t
22; CHECK-NEXT:    ret
23  %v2 = call <4 x i32> @llvm.vp.load.v4i32(ptr %p, <4 x i1> %mask, i32 4)
24  %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
25  ret <4 x i32> %v3
26}
27
28; Can't fold this in because the load has a non-undef passthru that isn't equal to the vmv.v.v passtrhu
29declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32, <4 x i1>, <4 x i32>)
30define <4 x i32> @insert_subvector_load_unfoldable_passthru_v4i32_v4i32(<4 x i32> %v1, ptr %p, <4 x i1> %mask, <4 x i32> %passthru) {
31; CHECK-LABEL: insert_subvector_load_unfoldable_passthru_v4i32_v4i32:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
34; CHECK-NEXT:    vle32.v v9, (a0), v0.t
35; CHECK-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
36; CHECK-NEXT:    vmv.v.v v8, v9
37; CHECK-NEXT:    ret
38  %v2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x i32> %passthru)
39  %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
40  ret <4 x i32> %v3
41}
42
43; Can fold this in because the load has a non-undef passthru, but it's equal to the vmv.v.v passtrhu
44define <4 x i32> @insert_subvector_load_foldable_passthru_v4i32_v4i32(<4 x i32> %v1, ptr %p, <4 x i1> %mask) {
45; CHECK-LABEL: insert_subvector_load_foldable_passthru_v4i32_v4i32:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, mu
48; CHECK-NEXT:    vle32.v v8, (a0), v0.t
49; CHECK-NEXT:    ret
50  %v2 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x i32> %v1)
51  %v3 = shufflevector <4 x i32> %v2, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
52  ret <4 x i32> %v3
53}
54
55define <4 x i32> @insert_subvector_add_v4i32_v4i32(<4 x i32> %v1, <4 x i32> %v2) {
56; CHECK-LABEL: insert_subvector_add_v4i32_v4i32:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
59; CHECK-NEXT:    vid.v v10
60; CHECK-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
61; CHECK-NEXT:    vadd.vv v8, v9, v10
62; CHECK-NEXT:    ret
63  %v3 = add <4 x i32> %v2, <i32 0, i32 1, i32 2, i32 3>
64  %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
65  ret <4 x i32> %v4
66}
67
68declare <4 x i32> @llvm.vp.add.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
69define <4 x i32> @insert_subvector_vp_add_v4i32_v4i32(<4 x i32> %v1, <4 x i32> %v2, <4 x i1> %mask) {
70; CHECK-LABEL: insert_subvector_vp_add_v4i32_v4i32:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, mu
73; CHECK-NEXT:    vadd.vi v8, v9, 1, v0.t
74; CHECK-NEXT:    ret
75  %v3 = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %v2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i1> %mask, i32 4)
76  %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
77  ret <4 x i32> %v4
78}
79
80define <4 x i32> @insert_subvector_load_v4i32_v2i32(<4 x i32> %v1, ptr %p) {
81; CHECK-LABEL: insert_subvector_load_v4i32_v2i32:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
84; CHECK-NEXT:    vle32.v v9, (a0)
85; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
86; CHECK-NEXT:    vmv.v.v v8, v9
87; CHECK-NEXT:    ret
88  %v2 = load <2 x i32>, ptr %p
89  %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
90  %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
91  ret <4 x i32> %v4
92}
93
94declare <2 x i32> @llvm.vp.load.v2i32(ptr, <2 x i1>, i32)
95define <4 x i32> @insert_subvector_vp_load_v4i32_v2i32(<4 x i32> %v1, ptr %p, <2 x i1> %mask) {
96; CHECK-LABEL: insert_subvector_vp_load_v4i32_v2i32:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
99; CHECK-NEXT:    vle32.v v9, (a0), v0.t
100; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
101; CHECK-NEXT:    vmv.v.v v8, v9
102; CHECK-NEXT:    ret
103  %v2 = call <2 x i32> @llvm.vp.load.v2i32(ptr %p, <2 x i1> %mask, i32 2)
104  %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
105  %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
106  ret <4 x i32> %v4
107}
108
109define <4 x i32> @insert_subvector_add_v4i32_v2i32(<4 x i32> %v1, <2 x i32> %v2) {
110; CHECK-LABEL: insert_subvector_add_v4i32_v2i32:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
113; CHECK-NEXT:    vid.v v10
114; CHECK-NEXT:    vadd.vv v9, v9, v10
115; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
116; CHECK-NEXT:    vmv.v.v v8, v9
117; CHECK-NEXT:    ret
118  %v3 = add <2 x i32> %v2, <i32 0, i32 1>
119  %v4 = shufflevector <2 x i32> %v3, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
120  %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
121  ret <4 x i32> %v5
122}
123
124declare <2 x i32> @llvm.vp.add.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
125define <4 x i32> @insert_subvector_vp_add_v4i32_v2i32(<4 x i32> %v1, <2 x i32> %v2, <2 x i1> %mask) {
126; CHECK-LABEL: insert_subvector_vp_add_v4i32_v2i32:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
129; CHECK-NEXT:    vadd.vi v9, v9, 1, v0.t
130; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
131; CHECK-NEXT:    vmv.v.v v8, v9
132; CHECK-NEXT:    ret
133  %v3 = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %v2, <2 x i32> <i32 1, i32 1>, <2 x i1> %mask, i32 2)
134  %v4 = shufflevector <2 x i32> %v3, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
135  %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
136  ret <4 x i32> %v5
137}
138
139define <4 x i32> @insert_subvector_load_v4i32_v8i32(<4 x i32> %v1, ptr %p) {
140; CHECK-LABEL: insert_subvector_load_v4i32_v8i32:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
143; CHECK-NEXT:    vle32.v v8, (a0)
144; CHECK-NEXT:    ret
145  %v2 = load <8 x i32>, ptr %p
146  %v3 = shufflevector <8 x i32> %v2, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
147  %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
148  ret <4 x i32> %v4
149}
150
151declare <8 x i32> @llvm.vp.load.v8i32(ptr, <8 x i1>, i32)
152define <4 x i32> @insert_subvector_vp_load_v4i32_v8i32(<4 x i32> %v1, ptr %p, <8 x i1> %mask) {
153; CHECK-LABEL: insert_subvector_vp_load_v4i32_v8i32:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
156; CHECK-NEXT:    vle32.v v10, (a0), v0.t
157; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
158; CHECK-NEXT:    vmv.v.v v8, v10
159; CHECK-NEXT:    ret
160  %v2 = call <8 x i32> @llvm.vp.load.v8i32(ptr %p, <8 x i1> %mask, i32 8)
161  %v3 = shufflevector <8 x i32> %v2, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
162  %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
163  ret <4 x i32> %v4
164}
165
166define <4 x i32> @insert_subvector_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %v2) {
167; CHECK-LABEL: insert_subvector_add_v4i32_v8i32:
168; CHECK:       # %bb.0:
169; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
170; CHECK-NEXT:    vid.v v9
171; CHECK-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
172; CHECK-NEXT:    vadd.vv v8, v10, v9
173; CHECK-NEXT:    ret
174  %v3 = add <8 x i32> %v2, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
175  %v4 = shufflevector <8 x i32> %v3, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
176  %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
177  ret <4 x i32> %v5
178}
179
180declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
181define <4 x i32> @insert_subvector_vp_add_v4i32_v8i32(<4 x i32> %v1, <8 x i32> %v2, <8 x i1> %mask) {
182; CHECK-LABEL: insert_subvector_vp_add_v4i32_v8i32:
183; CHECK:       # %bb.0:
184; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
185; CHECK-NEXT:    vadd.vi v10, v10, 1, v0.t
186; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
187; CHECK-NEXT:    vmv.v.v v8, v10
188; CHECK-NEXT:    ret
189  %v3 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %v2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <8 x i1> %mask, i32 8)
190  %v4 = shufflevector <8 x i32> %v3, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
191  %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
192  ret <4 x i32> %v5
193}
194
195; %v2 depends on the chain of %v1, so make sure the peephole optimisation
196; doesn't introduce a loop in the DAG
197define <4 x i32> @insert_subvector_dag_loop(ptr %p, ptr %q) {
198; CHECK-LABEL: insert_subvector_dag_loop:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
201; CHECK-NEXT:    vle32.v v9, (a0)
202; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
203; CHECK-NEXT:    vle32.v v8, (a1)
204; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
205; CHECK-NEXT:    vmv.v.v v8, v9
206; CHECK-NEXT:    ret
207  %v1 = load volatile <4 x i32>, ptr %p
208  %v2 = load volatile <4 x i32>, ptr %q
209  %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
210  ret <4 x i32> %v3
211}
212