xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
3; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
5; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
6; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \
7; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
8; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \
9; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
10
11; This file tests the code generation for `llvm.roundeven.*` on fixed vector type.
12
13define <1 x half> @roundeven_v1f16(<1 x half> %x) {
14; ZVFH-LABEL: roundeven_v1f16:
15; ZVFH:       # %bb.0:
16; ZVFH-NEXT:    lui a0, %hi(.LCPI0_0)
17; ZVFH-NEXT:    flh fa5, %lo(.LCPI0_0)(a0)
18; ZVFH-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
19; ZVFH-NEXT:    vfabs.v v9, v8
20; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
21; ZVFH-NEXT:    fsrmi a0, 0
22; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
23; ZVFH-NEXT:    fsrm a0
24; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
25; ZVFH-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
26; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
27; ZVFH-NEXT:    ret
28;
29; ZVFHMIN-LABEL: roundeven_v1f16:
30; ZVFHMIN:       # %bb.0:
31; ZVFHMIN-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
32; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
33; ZVFHMIN-NEXT:    lui a0, 307200
34; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
35; ZVFHMIN-NEXT:    vfabs.v v8, v9
36; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
37; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
38; ZVFHMIN-NEXT:    fsrmi a0, 0
39; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v9, v0.t
40; ZVFHMIN-NEXT:    fsrm a0
41; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
42; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
43; ZVFHMIN-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
44; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
45; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
46; ZVFHMIN-NEXT:    ret
47  %a = call <1 x half> @llvm.roundeven.v1f16(<1 x half> %x)
48  ret <1 x half> %a
49}
50declare <1 x half> @llvm.roundeven.v1f16(<1 x half>)
51
52define <2 x half> @roundeven_v2f16(<2 x half> %x) {
53; ZVFH-LABEL: roundeven_v2f16:
54; ZVFH:       # %bb.0:
55; ZVFH-NEXT:    lui a0, %hi(.LCPI1_0)
56; ZVFH-NEXT:    flh fa5, %lo(.LCPI1_0)(a0)
57; ZVFH-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
58; ZVFH-NEXT:    vfabs.v v9, v8
59; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
60; ZVFH-NEXT:    fsrmi a0, 0
61; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
62; ZVFH-NEXT:    fsrm a0
63; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
64; ZVFH-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
65; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
66; ZVFH-NEXT:    ret
67;
68; ZVFHMIN-LABEL: roundeven_v2f16:
69; ZVFHMIN:       # %bb.0:
70; ZVFHMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
71; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
72; ZVFHMIN-NEXT:    lui a0, 307200
73; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
74; ZVFHMIN-NEXT:    vfabs.v v8, v9
75; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
76; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
77; ZVFHMIN-NEXT:    fsrmi a0, 0
78; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v9, v0.t
79; ZVFHMIN-NEXT:    fsrm a0
80; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
81; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
82; ZVFHMIN-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
83; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
84; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
85; ZVFHMIN-NEXT:    ret
86  %a = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %x)
87  ret <2 x half> %a
88}
89declare <2 x half> @llvm.roundeven.v2f16(<2 x half>)
90
91define <4 x half> @roundeven_v4f16(<4 x half> %x) {
92; ZVFH-LABEL: roundeven_v4f16:
93; ZVFH:       # %bb.0:
94; ZVFH-NEXT:    lui a0, %hi(.LCPI2_0)
95; ZVFH-NEXT:    flh fa5, %lo(.LCPI2_0)(a0)
96; ZVFH-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
97; ZVFH-NEXT:    vfabs.v v9, v8
98; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
99; ZVFH-NEXT:    fsrmi a0, 0
100; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
101; ZVFH-NEXT:    fsrm a0
102; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
103; ZVFH-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
104; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
105; ZVFH-NEXT:    ret
106;
107; ZVFHMIN-LABEL: roundeven_v4f16:
108; ZVFHMIN:       # %bb.0:
109; ZVFHMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
110; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
111; ZVFHMIN-NEXT:    lui a0, 307200
112; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
113; ZVFHMIN-NEXT:    vfabs.v v8, v9
114; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
115; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
116; ZVFHMIN-NEXT:    fsrmi a0, 0
117; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v9, v0.t
118; ZVFHMIN-NEXT:    fsrm a0
119; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
120; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
121; ZVFHMIN-NEXT:    vfsgnj.vv v9, v8, v9, v0.t
122; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
123; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
124; ZVFHMIN-NEXT:    ret
125  %a = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %x)
126  ret <4 x half> %a
127}
128declare <4 x half> @llvm.roundeven.v4f16(<4 x half>)
129
130define <8 x half> @roundeven_v8f16(<8 x half> %x) {
131; ZVFH-LABEL: roundeven_v8f16:
132; ZVFH:       # %bb.0:
133; ZVFH-NEXT:    lui a0, %hi(.LCPI3_0)
134; ZVFH-NEXT:    flh fa5, %lo(.LCPI3_0)(a0)
135; ZVFH-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
136; ZVFH-NEXT:    vfabs.v v9, v8
137; ZVFH-NEXT:    vmflt.vf v0, v9, fa5
138; ZVFH-NEXT:    fsrmi a0, 0
139; ZVFH-NEXT:    vfcvt.x.f.v v9, v8, v0.t
140; ZVFH-NEXT:    fsrm a0
141; ZVFH-NEXT:    vfcvt.f.x.v v9, v9, v0.t
142; ZVFH-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
143; ZVFH-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
144; ZVFH-NEXT:    ret
145;
146; ZVFHMIN-LABEL: roundeven_v8f16:
147; ZVFHMIN:       # %bb.0:
148; ZVFHMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
149; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
150; ZVFHMIN-NEXT:    lui a0, 307200
151; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
152; ZVFHMIN-NEXT:    vfabs.v v8, v10
153; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
154; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
155; ZVFHMIN-NEXT:    fsrmi a0, 0
156; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v10, v0.t
157; ZVFHMIN-NEXT:    fsrm a0
158; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
159; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
160; ZVFHMIN-NEXT:    vfsgnj.vv v10, v8, v10, v0.t
161; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
162; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
163; ZVFHMIN-NEXT:    ret
164  %a = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %x)
165  ret <8 x half> %a
166}
167declare <8 x half> @llvm.roundeven.v8f16(<8 x half>)
168
169define <16 x half> @roundeven_v16f16(<16 x half> %x) {
170; ZVFH-LABEL: roundeven_v16f16:
171; ZVFH:       # %bb.0:
172; ZVFH-NEXT:    lui a0, %hi(.LCPI4_0)
173; ZVFH-NEXT:    flh fa5, %lo(.LCPI4_0)(a0)
174; ZVFH-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
175; ZVFH-NEXT:    vfabs.v v10, v8
176; ZVFH-NEXT:    vmflt.vf v0, v10, fa5
177; ZVFH-NEXT:    fsrmi a0, 0
178; ZVFH-NEXT:    vfcvt.x.f.v v10, v8, v0.t
179; ZVFH-NEXT:    fsrm a0
180; ZVFH-NEXT:    vfcvt.f.x.v v10, v10, v0.t
181; ZVFH-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
182; ZVFH-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
183; ZVFH-NEXT:    ret
184;
185; ZVFHMIN-LABEL: roundeven_v16f16:
186; ZVFHMIN:       # %bb.0:
187; ZVFHMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
188; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8
189; ZVFHMIN-NEXT:    lui a0, 307200
190; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
191; ZVFHMIN-NEXT:    vfabs.v v8, v12
192; ZVFHMIN-NEXT:    fmv.w.x fa5, a0
193; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
194; ZVFHMIN-NEXT:    fsrmi a0, 0
195; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v12, v0.t
196; ZVFHMIN-NEXT:    fsrm a0
197; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
198; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
199; ZVFHMIN-NEXT:    vfsgnj.vv v12, v8, v12, v0.t
200; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
201; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12
202; ZVFHMIN-NEXT:    ret
203  %a = call <16 x half> @llvm.roundeven.v16f16(<16 x half> %x)
204  ret <16 x half> %a
205}
206declare <16 x half> @llvm.roundeven.v16f16(<16 x half>)
207
208define <32 x half> @roundeven_v32f16(<32 x half> %x) {
209; ZVFH-LABEL: roundeven_v32f16:
210; ZVFH:       # %bb.0:
211; ZVFH-NEXT:    lui a0, %hi(.LCPI5_0)
212; ZVFH-NEXT:    flh fa5, %lo(.LCPI5_0)(a0)
213; ZVFH-NEXT:    li a0, 32
214; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
215; ZVFH-NEXT:    vfabs.v v12, v8
216; ZVFH-NEXT:    vmflt.vf v0, v12, fa5
217; ZVFH-NEXT:    fsrmi a0, 0
218; ZVFH-NEXT:    vfcvt.x.f.v v12, v8, v0.t
219; ZVFH-NEXT:    fsrm a0
220; ZVFH-NEXT:    vfcvt.f.x.v v12, v12, v0.t
221; ZVFH-NEXT:    vsetvli zero, zero, e16, m4, ta, mu
222; ZVFH-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
223; ZVFH-NEXT:    ret
224;
225; ZVFHMIN-LABEL: roundeven_v32f16:
226; ZVFHMIN:       # %bb.0:
227; ZVFHMIN-NEXT:    li a0, 32
228; ZVFHMIN-NEXT:    lui a1, 307200
229; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
230; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
231; ZVFHMIN-NEXT:    fmv.w.x fa5, a1
232; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
233; ZVFHMIN-NEXT:    vfabs.v v8, v16
234; ZVFHMIN-NEXT:    vmflt.vf v0, v8, fa5
235; ZVFHMIN-NEXT:    fsrmi a0, 0
236; ZVFHMIN-NEXT:    vfcvt.x.f.v v8, v16, v0.t
237; ZVFHMIN-NEXT:    fsrm a0
238; ZVFHMIN-NEXT:    vfcvt.f.x.v v8, v8, v0.t
239; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, mu
240; ZVFHMIN-NEXT:    vfsgnj.vv v16, v8, v16, v0.t
241; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
242; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
243; ZVFHMIN-NEXT:    ret
244  %a = call <32 x half> @llvm.roundeven.v32f16(<32 x half> %x)
245  ret <32 x half> %a
246}
247declare <32 x half> @llvm.roundeven.v32f16(<32 x half>)
248
249define <1 x float> @roundeven_v1f32(<1 x float> %x) {
250; CHECK-LABEL: roundeven_v1f32:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
253; CHECK-NEXT:    vfabs.v v9, v8
254; CHECK-NEXT:    lui a0, 307200
255; CHECK-NEXT:    fmv.w.x fa5, a0
256; CHECK-NEXT:    vmflt.vf v0, v9, fa5
257; CHECK-NEXT:    fsrmi a0, 0
258; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
259; CHECK-NEXT:    fsrm a0
260; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
261; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
262; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
263; CHECK-NEXT:    ret
264  %a = call <1 x float> @llvm.roundeven.v1f32(<1 x float> %x)
265  ret <1 x float> %a
266}
267declare <1 x float> @llvm.roundeven.v1f32(<1 x float>)
268
269define <2 x float> @roundeven_v2f32(<2 x float> %x) {
270; CHECK-LABEL: roundeven_v2f32:
271; CHECK:       # %bb.0:
272; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
273; CHECK-NEXT:    vfabs.v v9, v8
274; CHECK-NEXT:    lui a0, 307200
275; CHECK-NEXT:    fmv.w.x fa5, a0
276; CHECK-NEXT:    vmflt.vf v0, v9, fa5
277; CHECK-NEXT:    fsrmi a0, 0
278; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
279; CHECK-NEXT:    fsrm a0
280; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
281; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
282; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
283; CHECK-NEXT:    ret
284  %a = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %x)
285  ret <2 x float> %a
286}
287declare <2 x float> @llvm.roundeven.v2f32(<2 x float>)
288
289define <4 x float> @roundeven_v4f32(<4 x float> %x) {
290; CHECK-LABEL: roundeven_v4f32:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
293; CHECK-NEXT:    vfabs.v v9, v8
294; CHECK-NEXT:    lui a0, 307200
295; CHECK-NEXT:    fmv.w.x fa5, a0
296; CHECK-NEXT:    vmflt.vf v0, v9, fa5
297; CHECK-NEXT:    fsrmi a0, 0
298; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
299; CHECK-NEXT:    fsrm a0
300; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
301; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
302; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
303; CHECK-NEXT:    ret
304  %a = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %x)
305  ret <4 x float> %a
306}
307declare <4 x float> @llvm.roundeven.v4f32(<4 x float>)
308
309define <8 x float> @roundeven_v8f32(<8 x float> %x) {
310; CHECK-LABEL: roundeven_v8f32:
311; CHECK:       # %bb.0:
312; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
313; CHECK-NEXT:    vfabs.v v10, v8
314; CHECK-NEXT:    lui a0, 307200
315; CHECK-NEXT:    fmv.w.x fa5, a0
316; CHECK-NEXT:    vmflt.vf v0, v10, fa5
317; CHECK-NEXT:    fsrmi a0, 0
318; CHECK-NEXT:    vfcvt.x.f.v v10, v8, v0.t
319; CHECK-NEXT:    fsrm a0
320; CHECK-NEXT:    vfcvt.f.x.v v10, v10, v0.t
321; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, mu
322; CHECK-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
323; CHECK-NEXT:    ret
324  %a = call <8 x float> @llvm.roundeven.v8f32(<8 x float> %x)
325  ret <8 x float> %a
326}
327declare <8 x float> @llvm.roundeven.v8f32(<8 x float>)
328
329define <16 x float> @roundeven_v16f32(<16 x float> %x) {
330; CHECK-LABEL: roundeven_v16f32:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
333; CHECK-NEXT:    vfabs.v v12, v8
334; CHECK-NEXT:    lui a0, 307200
335; CHECK-NEXT:    fmv.w.x fa5, a0
336; CHECK-NEXT:    vmflt.vf v0, v12, fa5
337; CHECK-NEXT:    fsrmi a0, 0
338; CHECK-NEXT:    vfcvt.x.f.v v12, v8, v0.t
339; CHECK-NEXT:    fsrm a0
340; CHECK-NEXT:    vfcvt.f.x.v v12, v12, v0.t
341; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, mu
342; CHECK-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
343; CHECK-NEXT:    ret
344  %a = call <16 x float> @llvm.roundeven.v16f32(<16 x float> %x)
345  ret <16 x float> %a
346}
347declare <16 x float> @llvm.roundeven.v16f32(<16 x float>)
348
349define <1 x double> @roundeven_v1f64(<1 x double> %x) {
350; CHECK-LABEL: roundeven_v1f64:
351; CHECK:       # %bb.0:
352; CHECK-NEXT:    lui a0, %hi(.LCPI11_0)
353; CHECK-NEXT:    fld fa5, %lo(.LCPI11_0)(a0)
354; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
355; CHECK-NEXT:    vfabs.v v9, v8
356; CHECK-NEXT:    vmflt.vf v0, v9, fa5
357; CHECK-NEXT:    fsrmi a0, 0
358; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
359; CHECK-NEXT:    fsrm a0
360; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
361; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
362; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
363; CHECK-NEXT:    ret
364  %a = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %x)
365  ret <1 x double> %a
366}
367declare <1 x double> @llvm.roundeven.v1f64(<1 x double>)
368
369define <2 x double> @roundeven_v2f64(<2 x double> %x) {
370; CHECK-LABEL: roundeven_v2f64:
371; CHECK:       # %bb.0:
372; CHECK-NEXT:    lui a0, %hi(.LCPI12_0)
373; CHECK-NEXT:    fld fa5, %lo(.LCPI12_0)(a0)
374; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
375; CHECK-NEXT:    vfabs.v v9, v8
376; CHECK-NEXT:    vmflt.vf v0, v9, fa5
377; CHECK-NEXT:    fsrmi a0, 0
378; CHECK-NEXT:    vfcvt.x.f.v v9, v8, v0.t
379; CHECK-NEXT:    fsrm a0
380; CHECK-NEXT:    vfcvt.f.x.v v9, v9, v0.t
381; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, mu
382; CHECK-NEXT:    vfsgnj.vv v8, v9, v8, v0.t
383; CHECK-NEXT:    ret
384  %a = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %x)
385  ret <2 x double> %a
386}
387declare <2 x double> @llvm.roundeven.v2f64(<2 x double>)
388
389define <4 x double> @roundeven_v4f64(<4 x double> %x) {
390; CHECK-LABEL: roundeven_v4f64:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    lui a0, %hi(.LCPI13_0)
393; CHECK-NEXT:    fld fa5, %lo(.LCPI13_0)(a0)
394; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
395; CHECK-NEXT:    vfabs.v v10, v8
396; CHECK-NEXT:    vmflt.vf v0, v10, fa5
397; CHECK-NEXT:    fsrmi a0, 0
398; CHECK-NEXT:    vfcvt.x.f.v v10, v8, v0.t
399; CHECK-NEXT:    fsrm a0
400; CHECK-NEXT:    vfcvt.f.x.v v10, v10, v0.t
401; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, mu
402; CHECK-NEXT:    vfsgnj.vv v8, v10, v8, v0.t
403; CHECK-NEXT:    ret
404  %a = call <4 x double> @llvm.roundeven.v4f64(<4 x double> %x)
405  ret <4 x double> %a
406}
407declare <4 x double> @llvm.roundeven.v4f64(<4 x double>)
408
409define <8 x double> @roundeven_v8f64(<8 x double> %x) {
410; CHECK-LABEL: roundeven_v8f64:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    lui a0, %hi(.LCPI14_0)
413; CHECK-NEXT:    fld fa5, %lo(.LCPI14_0)(a0)
414; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
415; CHECK-NEXT:    vfabs.v v12, v8
416; CHECK-NEXT:    vmflt.vf v0, v12, fa5
417; CHECK-NEXT:    fsrmi a0, 0
418; CHECK-NEXT:    vfcvt.x.f.v v12, v8, v0.t
419; CHECK-NEXT:    fsrm a0
420; CHECK-NEXT:    vfcvt.f.x.v v12, v12, v0.t
421; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, mu
422; CHECK-NEXT:    vfsgnj.vv v8, v12, v8, v0.t
423; CHECK-NEXT:    ret
424  %a = call <8 x double> @llvm.roundeven.v8f64(<8 x double> %x)
425  ret <8 x double> %a
426}
427declare <8 x double> @llvm.roundeven.v8f64(<8 x double>)
428