1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFH 4; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN,RV64-ZVFHMIN-NOZFHMIN 5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN,RV64_ZVFHMIN-ZFHMIN 6 7define void @splat_v8f16(ptr %x, half %y) { 8; CHECK-RV32-LABEL: splat_v8f16: 9; CHECK-RV32: # %bb.0: 10; CHECK-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma 11; CHECK-RV32-NEXT: vfmv.v.f v8, fa0 12; CHECK-RV32-NEXT: vse16.v v8, (a0) 13; CHECK-RV32-NEXT: ret 14; 15; RV64-ZVFH-LABEL: splat_v8f16: 16; RV64-ZVFH: # %bb.0: 17; RV64-ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma 18; RV64-ZVFH-NEXT: vfmv.v.f v8, fa0 19; RV64-ZVFH-NEXT: vse16.v v8, (a0) 20; RV64-ZVFH-NEXT: ret 21; 22; RV64-ZVFHMIN-NOZFHMIN-LABEL: splat_v8f16: 23; RV64-ZVFHMIN-NOZFHMIN: # %bb.0: 24; RV64-ZVFHMIN-NOZFHMIN-NEXT: fmv.x.w a1, fa0 25; RV64-ZVFHMIN-NOZFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma 26; RV64-ZVFHMIN-NOZFHMIN-NEXT: vmv.v.x v8, a1 27; RV64-ZVFHMIN-NOZFHMIN-NEXT: vse16.v v8, (a0) 28; RV64-ZVFHMIN-NOZFHMIN-NEXT: ret 29; 30; RV64_ZVFHMIN-ZFHMIN-LABEL: splat_v8f16: 31; RV64_ZVFHMIN-ZFHMIN: # %bb.0: 32; RV64_ZVFHMIN-ZFHMIN-NEXT: fmv.x.h a1, fa0 33; RV64_ZVFHMIN-ZFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma 34; RV64_ZVFHMIN-ZFHMIN-NEXT: vmv.v.x v8, a1 35; RV64_ZVFHMIN-ZFHMIN-NEXT: vse16.v v8, (a0) 36; RV64_ZVFHMIN-ZFHMIN-NEXT: ret 37 %a = insertelement <8 x half> poison, half %y, i32 0 38 %b = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> zeroinitializer 39 store <8 x half> %b, ptr %x 40 ret void 41} 42 43define void @splat_v4f32(ptr %x, float %y) { 44; CHECK-LABEL: splat_v4f32: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 47; CHECK-NEXT: vfmv.v.f v8, fa0 48; CHECK-NEXT: vse32.v v8, (a0) 49; CHECK-NEXT: ret 50 %a = insertelement <4 x float> poison, float %y, i32 0 51 %b = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> zeroinitializer 52 store <4 x float> %b, ptr %x 53 ret void 54} 55 56define void @splat_v2f64(ptr %x, double %y) { 57; CHECK-LABEL: splat_v2f64: 58; CHECK: # %bb.0: 59; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 60; CHECK-NEXT: vfmv.v.f v8, fa0 61; CHECK-NEXT: vse64.v v8, (a0) 62; CHECK-NEXT: ret 63 %a = insertelement <2 x double> poison, double %y, i32 0 64 %b = shufflevector <2 x double> %a, <2 x double> poison, <2 x i32> zeroinitializer 65 store <2 x double> %b, ptr %x 66 ret void 67} 68 69define void @splat_16f16(ptr %x, half %y) { 70; CHECK-RV32-LABEL: splat_16f16: 71; CHECK-RV32: # %bb.0: 72; CHECK-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma 73; CHECK-RV32-NEXT: vfmv.v.f v8, fa0 74; CHECK-RV32-NEXT: vse16.v v8, (a0) 75; CHECK-RV32-NEXT: ret 76; 77; RV64-ZVFH-LABEL: splat_16f16: 78; RV64-ZVFH: # %bb.0: 79; RV64-ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma 80; RV64-ZVFH-NEXT: vfmv.v.f v8, fa0 81; RV64-ZVFH-NEXT: vse16.v v8, (a0) 82; RV64-ZVFH-NEXT: ret 83; 84; RV64-ZVFHMIN-NOZFHMIN-LABEL: splat_16f16: 85; RV64-ZVFHMIN-NOZFHMIN: # %bb.0: 86; RV64-ZVFHMIN-NOZFHMIN-NEXT: fmv.x.w a1, fa0 87; RV64-ZVFHMIN-NOZFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma 88; RV64-ZVFHMIN-NOZFHMIN-NEXT: vmv.v.x v8, a1 89; RV64-ZVFHMIN-NOZFHMIN-NEXT: vse16.v v8, (a0) 90; RV64-ZVFHMIN-NOZFHMIN-NEXT: ret 91; 92; RV64_ZVFHMIN-ZFHMIN-LABEL: splat_16f16: 93; RV64_ZVFHMIN-ZFHMIN: # %bb.0: 94; RV64_ZVFHMIN-ZFHMIN-NEXT: fmv.x.h a1, fa0 95; RV64_ZVFHMIN-ZFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma 96; RV64_ZVFHMIN-ZFHMIN-NEXT: vmv.v.x v8, a1 97; RV64_ZVFHMIN-ZFHMIN-NEXT: vse16.v v8, (a0) 98; RV64_ZVFHMIN-ZFHMIN-NEXT: ret 99 %a = insertelement <16 x half> poison, half %y, i32 0 100 %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer 101 store <16 x half> %b, ptr %x 102 ret void 103} 104 105define void @splat_v8f32(ptr %x, float %y) { 106; CHECK-LABEL: splat_v8f32: 107; CHECK: # %bb.0: 108; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 109; CHECK-NEXT: vfmv.v.f v8, fa0 110; CHECK-NEXT: vse32.v v8, (a0) 111; CHECK-NEXT: ret 112 %a = insertelement <8 x float> poison, float %y, i32 0 113 %b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer 114 store <8 x float> %b, ptr %x 115 ret void 116} 117 118define void @splat_v4f64(ptr %x, double %y) { 119; CHECK-LABEL: splat_v4f64: 120; CHECK: # %bb.0: 121; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 122; CHECK-NEXT: vfmv.v.f v8, fa0 123; CHECK-NEXT: vse64.v v8, (a0) 124; CHECK-NEXT: ret 125 %a = insertelement <4 x double> poison, double %y, i32 0 126 %b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer 127 store <4 x double> %b, ptr %x 128 ret void 129} 130 131define void @splat_64f16(ptr %x, half %y) { 132; CHECK-RV32-LABEL: splat_64f16: 133; CHECK-RV32: # %bb.0: 134; CHECK-RV32-NEXT: li a1, 64 135; CHECK-RV32-NEXT: vsetvli zero, a1, e16, m8, ta, ma 136; CHECK-RV32-NEXT: vfmv.v.f v8, fa0 137; CHECK-RV32-NEXT: vse16.v v8, (a0) 138; CHECK-RV32-NEXT: ret 139; 140; RV64-ZVFH-LABEL: splat_64f16: 141; RV64-ZVFH: # %bb.0: 142; RV64-ZVFH-NEXT: li a1, 64 143; RV64-ZVFH-NEXT: vsetvli zero, a1, e16, m8, ta, ma 144; RV64-ZVFH-NEXT: vfmv.v.f v8, fa0 145; RV64-ZVFH-NEXT: vse16.v v8, (a0) 146; RV64-ZVFH-NEXT: ret 147; 148; RV64-ZVFHMIN-NOZFHMIN-LABEL: splat_64f16: 149; RV64-ZVFHMIN-NOZFHMIN: # %bb.0: 150; RV64-ZVFHMIN-NOZFHMIN-NEXT: fmv.x.w a1, fa0 151; RV64-ZVFHMIN-NOZFHMIN-NEXT: li a2, 64 152; RV64-ZVFHMIN-NOZFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma 153; RV64-ZVFHMIN-NOZFHMIN-NEXT: vmv.v.x v8, a1 154; RV64-ZVFHMIN-NOZFHMIN-NEXT: vse16.v v8, (a0) 155; RV64-ZVFHMIN-NOZFHMIN-NEXT: ret 156; 157; RV64_ZVFHMIN-ZFHMIN-LABEL: splat_64f16: 158; RV64_ZVFHMIN-ZFHMIN: # %bb.0: 159; RV64_ZVFHMIN-ZFHMIN-NEXT: fmv.x.h a1, fa0 160; RV64_ZVFHMIN-ZFHMIN-NEXT: li a2, 64 161; RV64_ZVFHMIN-ZFHMIN-NEXT: vsetvli zero, a2, e16, m8, ta, ma 162; RV64_ZVFHMIN-ZFHMIN-NEXT: vmv.v.x v8, a1 163; RV64_ZVFHMIN-ZFHMIN-NEXT: vse16.v v8, (a0) 164; RV64_ZVFHMIN-ZFHMIN-NEXT: ret 165 %a = insertelement <64 x half> poison, half %y, i32 0 166 %b = shufflevector <64 x half> %a, <64 x half> poison, <64 x i32> zeroinitializer 167 store <64 x half> %b, ptr %x 168 ret void 169} 170 171define void @splat_zero_v8f16(ptr %x) { 172; CHECK-LABEL: splat_zero_v8f16: 173; CHECK: # %bb.0: 174; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 175; CHECK-NEXT: vmv.v.i v8, 0 176; CHECK-NEXT: vse16.v v8, (a0) 177; CHECK-NEXT: ret 178 store <8 x half> splat (half 0.0), ptr %x 179 ret void 180} 181 182define void @splat_zero_v4f32(ptr %x) { 183; CHECK-LABEL: splat_zero_v4f32: 184; CHECK: # %bb.0: 185; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 186; CHECK-NEXT: vmv.v.i v8, 0 187; CHECK-NEXT: vse32.v v8, (a0) 188; CHECK-NEXT: ret 189 store <4 x float> splat (float 0.0), ptr %x 190 ret void 191} 192 193define void @splat_zero_v2f64(ptr %x) { 194; CHECK-LABEL: splat_zero_v2f64: 195; CHECK: # %bb.0: 196; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 197; CHECK-NEXT: vmv.v.i v8, 0 198; CHECK-NEXT: vse64.v v8, (a0) 199; CHECK-NEXT: ret 200 store <2 x double> splat (double 0.0), ptr %x 201 ret void 202} 203 204define void @splat_zero_16f16(ptr %x) { 205; CHECK-LABEL: splat_zero_16f16: 206; CHECK: # %bb.0: 207; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 208; CHECK-NEXT: vmv.v.i v8, 0 209; CHECK-NEXT: vse16.v v8, (a0) 210; CHECK-NEXT: ret 211 store <16 x half> splat (half 0.0), ptr %x 212 ret void 213} 214 215define void @splat_zero_v8f32(ptr %x) { 216; CHECK-LABEL: splat_zero_v8f32: 217; CHECK: # %bb.0: 218; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 219; CHECK-NEXT: vmv.v.i v8, 0 220; CHECK-NEXT: vse32.v v8, (a0) 221; CHECK-NEXT: ret 222 store <8 x float> splat (float 0.0), ptr %x 223 ret void 224} 225 226define void @splat_zero_v4f64(ptr %x) { 227; CHECK-LABEL: splat_zero_v4f64: 228; CHECK: # %bb.0: 229; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma 230; CHECK-NEXT: vmv.v.i v8, 0 231; CHECK-NEXT: vse64.v v8, (a0) 232; CHECK-NEXT: ret 233 store <4 x double> splat (double 0.0), ptr %x 234 ret void 235} 236 237define void @splat_negzero_v8f16(ptr %x) { 238; CHECK-LABEL: splat_negzero_v8f16: 239; CHECK: # %bb.0: 240; CHECK-NEXT: lui a1, 1048568 241; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 242; CHECK-NEXT: vmv.v.x v8, a1 243; CHECK-NEXT: vse16.v v8, (a0) 244; CHECK-NEXT: ret 245 store <8 x half> splat (half -0.0), ptr %x 246 ret void 247} 248 249define void @splat_negzero_v4f32(ptr %x) { 250; CHECK-LABEL: splat_negzero_v4f32: 251; CHECK: # %bb.0: 252; CHECK-NEXT: lui a1, 524288 253; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 254; CHECK-NEXT: vmv.v.x v8, a1 255; CHECK-NEXT: vse32.v v8, (a0) 256; CHECK-NEXT: ret 257 store <4 x float> splat (float -0.0), ptr %x 258 ret void 259} 260 261define void @splat_negzero_v2f64(ptr %x) { 262; CHECK-RV32-LABEL: splat_negzero_v2f64: 263; CHECK-RV32: # %bb.0: 264; CHECK-RV32-NEXT: fcvt.d.w fa5, zero 265; CHECK-RV32-NEXT: fneg.d fa5, fa5 266; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 267; CHECK-RV32-NEXT: vfmv.v.f v8, fa5 268; CHECK-RV32-NEXT: vse64.v v8, (a0) 269; CHECK-RV32-NEXT: ret 270; 271; CHECK-RV64-LABEL: splat_negzero_v2f64: 272; CHECK-RV64: # %bb.0: 273; CHECK-RV64-NEXT: li a1, -1 274; CHECK-RV64-NEXT: slli a1, a1, 63 275; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 276; CHECK-RV64-NEXT: vmv.v.x v8, a1 277; CHECK-RV64-NEXT: vse64.v v8, (a0) 278; CHECK-RV64-NEXT: ret 279 store <2 x double> splat (double -0.0), ptr %x 280 ret void 281} 282 283define void @splat_negzero_16f16(ptr %x) { 284; CHECK-LABEL: splat_negzero_16f16: 285; CHECK: # %bb.0: 286; CHECK-NEXT: lui a1, 1048568 287; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma 288; CHECK-NEXT: vmv.v.x v8, a1 289; CHECK-NEXT: vse16.v v8, (a0) 290; CHECK-NEXT: ret 291 store <16 x half> splat (half -0.0), ptr %x 292 ret void 293} 294 295define void @splat_negzero_v8f32(ptr %x) { 296; CHECK-LABEL: splat_negzero_v8f32: 297; CHECK: # %bb.0: 298; CHECK-NEXT: lui a1, 524288 299; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 300; CHECK-NEXT: vmv.v.x v8, a1 301; CHECK-NEXT: vse32.v v8, (a0) 302; CHECK-NEXT: ret 303 store <8 x float> splat (float -0.0), ptr %x 304 ret void 305} 306 307define void @splat_negzero_v4f64(ptr %x) { 308; CHECK-RV32-LABEL: splat_negzero_v4f64: 309; CHECK-RV32: # %bb.0: 310; CHECK-RV32-NEXT: fcvt.d.w fa5, zero 311; CHECK-RV32-NEXT: fneg.d fa5, fa5 312; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma 313; CHECK-RV32-NEXT: vfmv.v.f v8, fa5 314; CHECK-RV32-NEXT: vse64.v v8, (a0) 315; CHECK-RV32-NEXT: ret 316; 317; CHECK-RV64-LABEL: splat_negzero_v4f64: 318; CHECK-RV64: # %bb.0: 319; CHECK-RV64-NEXT: li a1, -1 320; CHECK-RV64-NEXT: slli a1, a1, 63 321; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma 322; CHECK-RV64-NEXT: vmv.v.x v8, a1 323; CHECK-RV64-NEXT: vse64.v v8, (a0) 324; CHECK-RV64-NEXT: ret 325 store <4 x double> splat (double -0.0), ptr %x 326 ret void 327} 328;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 329; RV64-ZVFHMIN: {{.*}} 330