1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2 3; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH 4; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH 5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RV64V 6; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RVA22U64 7; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN,RV32-NO-ZFHMIN 8; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFHMIN,RV64-NO-ZFHMIN 9; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN,RV32-ZFHMIN 10; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFHMIN,RV64-ZFHMIN 11 12; Tests that a floating-point build_vector doesn't try and generate a VID 13; instruction 14define void @buildvec_no_vid_v4f32(ptr %x) { 15; CHECK-LABEL: buildvec_no_vid_v4f32: 16; CHECK: # %bb.0: 17; CHECK-NEXT: lui a1, %hi(.LCPI0_0) 18; CHECK-NEXT: addi a1, a1, %lo(.LCPI0_0) 19; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 20; CHECK-NEXT: vle32.v v8, (a1) 21; CHECK-NEXT: vse32.v v8, (a0) 22; CHECK-NEXT: ret 23 store <4 x float> <float 0.0, float 4.0, float 0.0, float 2.0>, ptr %x 24 ret void 25} 26 27; Not all BUILD_VECTORs are successfully lowered by the backend: some are 28; expanded into scalarized stack stores. However, this may result in an 29; infinite loop in the DAGCombiner which tries to recombine those stores into a 30; BUILD_VECTOR followed by a vector store. The BUILD_VECTOR is then expanded 31; and the loop begins. 32; Until all BUILD_VECTORs are lowered, we disable store-combining after 33; legalization for fixed-length vectors. 34; This test uses a trick with a shufflevector which can't be lowered to a 35; SHUFFLE_VECTOR node; the mask is shorter than the source vectors and the 36; shuffle indices aren't located within the same 4-element subvector, so is 37; expanded to 4 EXTRACT_VECTOR_ELTs and a BUILD_VECTOR. This then triggers the 38; loop when expanded. 39define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, <8 x float> %y) optsize { 40; CHECK-LABEL: hang_when_merging_stores_after_legalization: 41; CHECK: # %bb.0: 42; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma 43; CHECK-NEXT: vmv.v.i v12, -14 44; CHECK-NEXT: vid.v v14 45; CHECK-NEXT: li a0, 7 46; CHECK-NEXT: vmadd.vx v14, a0, v12 47; CHECK-NEXT: li a0, 129 48; CHECK-NEXT: vmv.s.x v15, a0 49; CHECK-NEXT: vmv.v.i v0, 12 50; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu 51; CHECK-NEXT: vcompress.vm v12, v8, v15 52; CHECK-NEXT: vrgatherei16.vv v12, v10, v14, v0.t 53; CHECK-NEXT: vmv1r.v v8, v12 54; CHECK-NEXT: ret 55 %z = shufflevector <8 x float> %x, <8 x float> %y, <4 x i32> <i32 0, i32 7, i32 8, i32 15> 56 ret <4 x float> %z 57} 58 59define void @buildvec_dominant0_v2f32(ptr %x) { 60; CHECK-LABEL: buildvec_dominant0_v2f32: 61; CHECK: # %bb.0: 62; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 63; CHECK-NEXT: vid.v v8 64; CHECK-NEXT: vfcvt.f.x.v v8, v8 65; CHECK-NEXT: vse32.v v8, (a0) 66; CHECK-NEXT: ret 67 store <2 x float> <float 0.0, float 1.0>, ptr %x 68 ret void 69} 70 71; We don't want to lower this to the insertion of two scalar elements as above, 72; as each would require their own load from the constant pool. 73 74define void @buildvec_dominant1_v2f32(ptr %x) { 75; CHECK-LABEL: buildvec_dominant1_v2f32: 76; CHECK: # %bb.0: 77; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 78; CHECK-NEXT: vid.v v8 79; CHECK-NEXT: vadd.vi v8, v8, 1 80; CHECK-NEXT: vfcvt.f.x.v v8, v8 81; CHECK-NEXT: vse32.v v8, (a0) 82; CHECK-NEXT: ret 83 store <2 x float> <float 1.0, float 2.0>, ptr %x 84 ret void 85} 86 87define void @buildvec_dominant0_v4f32(ptr %x) { 88; CHECK-LABEL: buildvec_dominant0_v4f32: 89; CHECK: # %bb.0: 90; CHECK-NEXT: lui a1, 262144 91; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 92; CHECK-NEXT: vmv.v.x v8, a1 93; CHECK-NEXT: vmv.s.x v9, zero 94; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma 95; CHECK-NEXT: vslideup.vi v8, v9, 2 96; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 97; CHECK-NEXT: vse32.v v8, (a0) 98; CHECK-NEXT: ret 99 store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, ptr %x 100 ret void 101} 102 103define void @buildvec_dominant1_v4f32(ptr %x, float %f) { 104; CHECK-LABEL: buildvec_dominant1_v4f32: 105; CHECK: # %bb.0: 106; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 107; CHECK-NEXT: vfmv.v.f v8, fa0 108; CHECK-NEXT: vmv.s.x v9, zero 109; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma 110; CHECK-NEXT: vslideup.vi v8, v9, 1 111; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 112; CHECK-NEXT: vse32.v v8, (a0) 113; CHECK-NEXT: ret 114 %v0 = insertelement <4 x float> poison, float %f, i32 0 115 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1 116 %v2 = insertelement <4 x float> %v1, float %f, i32 2 117 %v3 = insertelement <4 x float> %v2, float %f, i32 3 118 store <4 x float> %v3, ptr %x 119 ret void 120} 121 122define void @buildvec_dominant2_v4f32(ptr %x, float %f) { 123; CHECK-LABEL: buildvec_dominant2_v4f32: 124; CHECK: # %bb.0: 125; CHECK-NEXT: lui a1, 262144 126; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 127; CHECK-NEXT: vmv.s.x v8, a1 128; CHECK-NEXT: vfmv.v.f v9, fa0 129; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma 130; CHECK-NEXT: vslideup.vi v9, v8, 1 131; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 132; CHECK-NEXT: vse32.v v9, (a0) 133; CHECK-NEXT: ret 134 %v0 = insertelement <4 x float> poison, float %f, i32 0 135 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1 136 %v2 = insertelement <4 x float> %v1, float %f, i32 2 137 %v3 = insertelement <4 x float> %v2, float %f, i32 3 138 store <4 x float> %v3, ptr %x 139 ret void 140} 141 142define void @buildvec_merge0_v4f32(ptr %x, float %f) { 143; CHECK-LABEL: buildvec_merge0_v4f32: 144; CHECK: # %bb.0: 145; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 146; CHECK-NEXT: vfmv.v.f v8, fa0 147; CHECK-NEXT: vmv.v.i v0, 6 148; CHECK-NEXT: lui a1, 262144 149; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0 150; CHECK-NEXT: vse32.v v8, (a0) 151; CHECK-NEXT: ret 152 %v0 = insertelement <4 x float> poison, float %f, i32 0 153 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1 154 %v2 = insertelement <4 x float> %v1, float 2.0, i32 2 155 %v3 = insertelement <4 x float> %v2, float %f, i32 3 156 store <4 x float> %v3, ptr %x 157 ret void 158} 159 160define <4 x half> @splat_c3_v4f16(<4 x half> %v) { 161; CHECK-LABEL: splat_c3_v4f16: 162; CHECK: # %bb.0: 163; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 164; CHECK-NEXT: vrgather.vi v9, v8, 3 165; CHECK-NEXT: vmv1r.v v8, v9 166; CHECK-NEXT: ret 167 %x = extractelement <4 x half> %v, i32 3 168 %ins = insertelement <4 x half> poison, half %x, i32 0 169 %splat = shufflevector <4 x half> %ins, <4 x half> poison, <4 x i32> zeroinitializer 170 ret <4 x half> %splat 171} 172 173define <4 x half> @splat_idx_v4f16(<4 x half> %v, i64 %idx) { 174; RV32ZVFH-LABEL: splat_idx_v4f16: 175; RV32ZVFH: # %bb.0: 176; RV32ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 177; RV32ZVFH-NEXT: vrgather.vx v9, v8, a0 178; RV32ZVFH-NEXT: vmv1r.v v8, v9 179; RV32ZVFH-NEXT: ret 180; 181; RV64ZVFH-LABEL: splat_idx_v4f16: 182; RV64ZVFH: # %bb.0: 183; RV64ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 184; RV64ZVFH-NEXT: vrgather.vx v9, v8, a0 185; RV64ZVFH-NEXT: vmv1r.v v8, v9 186; RV64ZVFH-NEXT: ret 187; 188; RV32-NO-ZFHMIN-LABEL: splat_idx_v4f16: 189; RV32-NO-ZFHMIN: # %bb.0: 190; RV32-NO-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 191; RV32-NO-ZFHMIN-NEXT: vrgather.vx v9, v8, a0 192; RV32-NO-ZFHMIN-NEXT: vmv1r.v v8, v9 193; RV32-NO-ZFHMIN-NEXT: ret 194; 195; RV64-NO-ZFHMIN-LABEL: splat_idx_v4f16: 196; RV64-NO-ZFHMIN: # %bb.0: 197; RV64-NO-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 198; RV64-NO-ZFHMIN-NEXT: vrgather.vx v9, v8, a0 199; RV64-NO-ZFHMIN-NEXT: vmv1r.v v8, v9 200; RV64-NO-ZFHMIN-NEXT: ret 201; 202; RV32-ZFHMIN-LABEL: splat_idx_v4f16: 203; RV32-ZFHMIN: # %bb.0: 204; RV32-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 205; RV32-ZFHMIN-NEXT: vslidedown.vx v8, v8, a0 206; RV32-ZFHMIN-NEXT: vmv.x.s a0, v8 207; RV32-ZFHMIN-NEXT: vmv.v.x v8, a0 208; RV32-ZFHMIN-NEXT: ret 209; 210; RV64-ZFHMIN-LABEL: splat_idx_v4f16: 211; RV64-ZFHMIN: # %bb.0: 212; RV64-ZFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 213; RV64-ZFHMIN-NEXT: vslidedown.vx v8, v8, a0 214; RV64-ZFHMIN-NEXT: vmv.x.s a0, v8 215; RV64-ZFHMIN-NEXT: vmv.v.x v8, a0 216; RV64-ZFHMIN-NEXT: ret 217 %x = extractelement <4 x half> %v, i64 %idx 218 %ins = insertelement <4 x half> poison, half %x, i32 0 219 %splat = shufflevector <4 x half> %ins, <4 x half> poison, <4 x i32> zeroinitializer 220 ret <4 x half> %splat 221} 222 223define <8 x float> @splat_c5_v8f32(<8 x float> %v) { 224; CHECK-LABEL: splat_c5_v8f32: 225; CHECK: # %bb.0: 226; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 227; CHECK-NEXT: vrgather.vi v10, v8, 5 228; CHECK-NEXT: vmv.v.v v8, v10 229; CHECK-NEXT: ret 230 %x = extractelement <8 x float> %v, i32 5 231 %ins = insertelement <8 x float> poison, float %x, i32 0 232 %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer 233 ret <8 x float> %splat 234} 235 236define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) { 237; 238; CHECK-LABEL: splat_idx_v8f32: 239; CHECK: # %bb.0: 240; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 241; CHECK-NEXT: vrgather.vx v10, v8, a0 242; CHECK-NEXT: vmv.v.v v8, v10 243; CHECK-NEXT: ret 244 %x = extractelement <8 x float> %v, i64 %idx 245 %ins = insertelement <8 x float> poison, float %x, i32 0 246 %splat = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> zeroinitializer 247 ret <8 x float> %splat 248} 249 250; Test that we pull the vlse of the constant pool out of the loop. 251define dso_local void @splat_load_licm(ptr %0) { 252; RV32-LABEL: splat_load_licm: 253; RV32: # %bb.0: 254; RV32-NEXT: lui a1, 1 255; RV32-NEXT: lui a2, 263168 256; RV32-NEXT: add a1, a0, a1 257; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma 258; RV32-NEXT: vmv.v.x v8, a2 259; RV32-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 260; RV32-NEXT: vse32.v v8, (a0) 261; RV32-NEXT: addi a0, a0, 16 262; RV32-NEXT: bne a0, a1, .LBB12_1 263; RV32-NEXT: # %bb.2: 264; RV32-NEXT: ret 265; 266; RV64V-LABEL: splat_load_licm: 267; RV64V: # %bb.0: 268; RV64V-NEXT: lui a1, 1 269; RV64V-NEXT: lui a2, 263168 270; RV64V-NEXT: add a1, a0, a1 271; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma 272; RV64V-NEXT: vmv.v.x v8, a2 273; RV64V-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 274; RV64V-NEXT: vse32.v v8, (a0) 275; RV64V-NEXT: addi a0, a0, 16 276; RV64V-NEXT: bne a0, a1, .LBB12_1 277; RV64V-NEXT: # %bb.2: 278; RV64V-NEXT: ret 279; 280; RVA22U64-LABEL: splat_load_licm: 281; RVA22U64: # %bb.0: 282; RVA22U64-NEXT: lui a1, 1 283; RVA22U64-NEXT: lui a2, 263168 284; RVA22U64-NEXT: add a1, a1, a0 285; RVA22U64-NEXT: vsetivli zero, 4, e32, m1, ta, ma 286; RVA22U64-NEXT: vmv.v.x v8, a2 287; RVA22U64-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 288; RVA22U64-NEXT: vse32.v v8, (a0) 289; RVA22U64-NEXT: addi a0, a0, 16 290; RVA22U64-NEXT: bne a0, a1, .LBB12_1 291; RVA22U64-NEXT: # %bb.2: 292; RVA22U64-NEXT: ret 293; 294; RV64ZVFHMIN-LABEL: splat_load_licm: 295; RV64ZVFHMIN: # %bb.0: 296; RV64ZVFHMIN-NEXT: lui a1, 1 297; RV64ZVFHMIN-NEXT: lui a2, 263168 298; RV64ZVFHMIN-NEXT: add a1, a0, a1 299; RV64ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma 300; RV64ZVFHMIN-NEXT: vmv.v.x v8, a2 301; RV64ZVFHMIN-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 302; RV64ZVFHMIN-NEXT: vse32.v v8, (a0) 303; RV64ZVFHMIN-NEXT: addi a0, a0, 16 304; RV64ZVFHMIN-NEXT: bne a0, a1, .LBB12_1 305; RV64ZVFHMIN-NEXT: # %bb.2: 306; RV64ZVFHMIN-NEXT: ret 307 br label %2 308 3092: ; preds = %2, %1 310 %3 = phi i32 [ 0, %1 ], [ %6, %2 ] 311 %4 = getelementptr inbounds float, ptr %0, i32 %3 312 %5 = bitcast ptr %4 to ptr 313 store <4 x float> <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>, ptr %5, align 4 314 %6 = add nuw i32 %3, 4 315 %7 = icmp eq i32 %6, 1024 316 br i1 %7, label %8, label %2 317 3188: ; preds = %2 319 ret void 320} 321 322define <2 x half> @buildvec_v2f16(half %a, half %b) { 323; RV32ZVFH-LABEL: buildvec_v2f16: 324; RV32ZVFH: # %bb.0: 325; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 326; RV32ZVFH-NEXT: vfmv.v.f v8, fa0 327; RV32ZVFH-NEXT: vfslide1down.vf v8, v8, fa1 328; RV32ZVFH-NEXT: ret 329; 330; RV64ZVFH-LABEL: buildvec_v2f16: 331; RV64ZVFH: # %bb.0: 332; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 333; RV64ZVFH-NEXT: vfmv.v.f v8, fa0 334; RV64ZVFH-NEXT: vfslide1down.vf v8, v8, fa1 335; RV64ZVFH-NEXT: ret 336; 337; RV32-NO-ZFHMIN-LABEL: buildvec_v2f16: 338; RV32-NO-ZFHMIN: # %bb.0: 339; RV32-NO-ZFHMIN-NEXT: fmv.x.w a0, fa1 340; RV32-NO-ZFHMIN-NEXT: fmv.x.w a1, fa0 341; RV32-NO-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 342; RV32-NO-ZFHMIN-NEXT: vmv.v.x v8, a1 343; RV32-NO-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0 344; RV32-NO-ZFHMIN-NEXT: ret 345; 346; RV64-NO-ZFHMIN-LABEL: buildvec_v2f16: 347; RV64-NO-ZFHMIN: # %bb.0: 348; RV64-NO-ZFHMIN-NEXT: fmv.x.w a0, fa1 349; RV64-NO-ZFHMIN-NEXT: fmv.x.w a1, fa0 350; RV64-NO-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 351; RV64-NO-ZFHMIN-NEXT: vmv.v.x v8, a1 352; RV64-NO-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0 353; RV64-NO-ZFHMIN-NEXT: ret 354; 355; RV32-ZFHMIN-LABEL: buildvec_v2f16: 356; RV32-ZFHMIN: # %bb.0: 357; RV32-ZFHMIN-NEXT: fmv.x.h a0, fa1 358; RV32-ZFHMIN-NEXT: fmv.x.h a1, fa0 359; RV32-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 360; RV32-ZFHMIN-NEXT: vmv.v.x v8, a1 361; RV32-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0 362; RV32-ZFHMIN-NEXT: ret 363; 364; RV64-ZFHMIN-LABEL: buildvec_v2f16: 365; RV64-ZFHMIN: # %bb.0: 366; RV64-ZFHMIN-NEXT: fmv.x.h a0, fa1 367; RV64-ZFHMIN-NEXT: fmv.x.h a1, fa0 368; RV64-ZFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 369; RV64-ZFHMIN-NEXT: vmv.v.x v8, a1 370; RV64-ZFHMIN-NEXT: vslide1down.vx v8, v8, a0 371; RV64-ZFHMIN-NEXT: ret 372 %v1 = insertelement <2 x half> poison, half %a, i64 0 373 %v2 = insertelement <2 x half> %v1, half %b, i64 1 374 ret <2 x half> %v2 375} 376 377define <2 x float> @buildvec_v2f32(float %a, float %b) { 378; CHECK-LABEL: buildvec_v2f32: 379; CHECK: # %bb.0: 380; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 381; CHECK-NEXT: vfmv.v.f v8, fa0 382; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 383; CHECK-NEXT: ret 384 %v1 = insertelement <2 x float> poison, float %a, i64 0 385 %v2 = insertelement <2 x float> %v1, float %b, i64 1 386 ret <2 x float> %v2 387} 388 389define <2 x double> @buildvec_v2f64(double %a, double %b) { 390; CHECK-LABEL: buildvec_v2f64: 391; CHECK: # %bb.0: 392; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 393; CHECK-NEXT: vfmv.v.f v8, fa0 394; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 395; CHECK-NEXT: ret 396 %v1 = insertelement <2 x double> poison, double %a, i64 0 397 %v2 = insertelement <2 x double> %v1, double %b, i64 1 398 ret <2 x double> %v2 399} 400 401define <2 x double> @buildvec_v2f64_b(double %a, double %b) { 402; CHECK-LABEL: buildvec_v2f64_b: 403; CHECK: # %bb.0: 404; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 405; CHECK-NEXT: vfmv.v.f v8, fa0 406; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 407; CHECK-NEXT: ret 408 %v1 = insertelement <2 x double> poison, double %b, i64 1 409 %v2 = insertelement <2 x double> %v1, double %a, i64 0 410 ret <2 x double> %v2 411} 412 413define <4 x float> @buildvec_v4f32(float %a, float %b, float %c, float %d) { 414; CHECK-LABEL: buildvec_v4f32: 415; CHECK: # %bb.0: 416; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma 417; CHECK-NEXT: vfmv.v.f v8, fa0 418; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 419; CHECK-NEXT: vfslide1down.vf v8, v8, fa2 420; CHECK-NEXT: vfslide1down.vf v8, v8, fa3 421; CHECK-NEXT: ret 422 %v1 = insertelement <4 x float> poison, float %a, i64 0 423 %v2 = insertelement <4 x float> %v1, float %b, i64 1 424 %v3 = insertelement <4 x float> %v2, float %c, i64 2 425 %v4 = insertelement <4 x float> %v3, float %d, i64 3 426 ret <4 x float> %v4 427} 428 429define <8 x float> @buildvec_v8f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7) { 430; CHECK-LABEL: buildvec_v8f32: 431; CHECK: # %bb.0: 432; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma 433; CHECK-NEXT: vfmv.v.f v8, fa0 434; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 435; CHECK-NEXT: vfslide1down.vf v8, v8, fa2 436; CHECK-NEXT: vfslide1down.vf v8, v8, fa3 437; CHECK-NEXT: vfslide1down.vf v8, v8, fa4 438; CHECK-NEXT: vfslide1down.vf v8, v8, fa5 439; CHECK-NEXT: vfslide1down.vf v8, v8, fa6 440; CHECK-NEXT: vfslide1down.vf v8, v8, fa7 441; CHECK-NEXT: ret 442 %v0 = insertelement <8 x float> poison, float %e0, i64 0 443 %v1 = insertelement <8 x float> %v0, float %e1, i64 1 444 %v2 = insertelement <8 x float> %v1, float %e2, i64 2 445 %v3 = insertelement <8 x float> %v2, float %e3, i64 3 446 %v4 = insertelement <8 x float> %v3, float %e4, i64 4 447 %v5 = insertelement <8 x float> %v4, float %e5, i64 5 448 %v6 = insertelement <8 x float> %v5, float %e6, i64 6 449 %v7 = insertelement <8 x float> %v6, float %e7, i64 7 450 ret <8 x float> %v7 451} 452 453define <16 x float> @buildvec_v16f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7, float %e8, float %e9, float %e10, float %e11, float %e12, float %e13, float %e14, float %e15) { 454; RV32-LABEL: buildvec_v16f32: 455; RV32: # %bb.0: 456; RV32-NEXT: addi sp, sp, -128 457; RV32-NEXT: .cfi_def_cfa_offset 128 458; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill 459; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill 460; RV32-NEXT: .cfi_offset ra, -4 461; RV32-NEXT: .cfi_offset s0, -8 462; RV32-NEXT: addi s0, sp, 128 463; RV32-NEXT: .cfi_def_cfa s0, 0 464; RV32-NEXT: andi sp, sp, -64 465; RV32-NEXT: sw a4, 48(sp) 466; RV32-NEXT: sw a5, 52(sp) 467; RV32-NEXT: sw a6, 56(sp) 468; RV32-NEXT: sw a7, 60(sp) 469; RV32-NEXT: sw a0, 32(sp) 470; RV32-NEXT: sw a1, 36(sp) 471; RV32-NEXT: sw a2, 40(sp) 472; RV32-NEXT: sw a3, 44(sp) 473; RV32-NEXT: fsw fa4, 16(sp) 474; RV32-NEXT: fsw fa5, 20(sp) 475; RV32-NEXT: fsw fa6, 24(sp) 476; RV32-NEXT: fsw fa7, 28(sp) 477; RV32-NEXT: fsw fa0, 0(sp) 478; RV32-NEXT: fsw fa1, 4(sp) 479; RV32-NEXT: fsw fa2, 8(sp) 480; RV32-NEXT: fsw fa3, 12(sp) 481; RV32-NEXT: mv a0, sp 482; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma 483; RV32-NEXT: vle32.v v8, (a0) 484; RV32-NEXT: addi sp, s0, -128 485; RV32-NEXT: .cfi_def_cfa sp, 128 486; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload 487; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload 488; RV32-NEXT: .cfi_restore ra 489; RV32-NEXT: .cfi_restore s0 490; RV32-NEXT: addi sp, sp, 128 491; RV32-NEXT: .cfi_def_cfa_offset 0 492; RV32-NEXT: ret 493; 494; RV64-LABEL: buildvec_v16f32: 495; RV64: # %bb.0: 496; RV64-NEXT: addi sp, sp, -128 497; RV64-NEXT: .cfi_def_cfa_offset 128 498; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill 499; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill 500; RV64-NEXT: .cfi_offset ra, -8 501; RV64-NEXT: .cfi_offset s0, -16 502; RV64-NEXT: addi s0, sp, 128 503; RV64-NEXT: .cfi_def_cfa s0, 0 504; RV64-NEXT: andi sp, sp, -64 505; RV64-NEXT: fmv.w.x ft0, a0 506; RV64-NEXT: fmv.w.x ft1, a1 507; RV64-NEXT: fmv.w.x ft2, a2 508; RV64-NEXT: fmv.w.x ft3, a3 509; RV64-NEXT: fmv.w.x ft4, a4 510; RV64-NEXT: fmv.w.x ft5, a5 511; RV64-NEXT: fmv.w.x ft6, a6 512; RV64-NEXT: fmv.w.x ft7, a7 513; RV64-NEXT: fsw fa4, 16(sp) 514; RV64-NEXT: fsw fa5, 20(sp) 515; RV64-NEXT: fsw fa6, 24(sp) 516; RV64-NEXT: fsw fa7, 28(sp) 517; RV64-NEXT: fsw fa0, 0(sp) 518; RV64-NEXT: fsw fa1, 4(sp) 519; RV64-NEXT: fsw fa2, 8(sp) 520; RV64-NEXT: fsw fa3, 12(sp) 521; RV64-NEXT: fsw ft4, 48(sp) 522; RV64-NEXT: fsw ft5, 52(sp) 523; RV64-NEXT: fsw ft6, 56(sp) 524; RV64-NEXT: fsw ft7, 60(sp) 525; RV64-NEXT: fsw ft0, 32(sp) 526; RV64-NEXT: fsw ft1, 36(sp) 527; RV64-NEXT: fsw ft2, 40(sp) 528; RV64-NEXT: fsw ft3, 44(sp) 529; RV64-NEXT: mv a0, sp 530; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma 531; RV64-NEXT: vle32.v v8, (a0) 532; RV64-NEXT: addi sp, s0, -128 533; RV64-NEXT: .cfi_def_cfa sp, 128 534; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload 535; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload 536; RV64-NEXT: .cfi_restore ra 537; RV64-NEXT: .cfi_restore s0 538; RV64-NEXT: addi sp, sp, 128 539; RV64-NEXT: .cfi_def_cfa_offset 0 540; RV64-NEXT: ret 541 %v0 = insertelement <16 x float> poison, float %e0, i64 0 542 %v1 = insertelement <16 x float> %v0, float %e1, i64 1 543 %v2 = insertelement <16 x float> %v1, float %e2, i64 2 544 %v3 = insertelement <16 x float> %v2, float %e3, i64 3 545 %v4 = insertelement <16 x float> %v3, float %e4, i64 4 546 %v5 = insertelement <16 x float> %v4, float %e5, i64 5 547 %v6 = insertelement <16 x float> %v5, float %e6, i64 6 548 %v7 = insertelement <16 x float> %v6, float %e7, i64 7 549 %v8 = insertelement <16 x float> %v7, float %e8, i64 8 550 %v9 = insertelement <16 x float> %v8, float %e9, i64 9 551 %v10 = insertelement <16 x float> %v9, float %e10, i64 10 552 %v11 = insertelement <16 x float> %v10, float %e11, i64 11 553 %v12 = insertelement <16 x float> %v11, float %e12, i64 12 554 %v13 = insertelement <16 x float> %v12, float %e13, i64 13 555 %v14 = insertelement <16 x float> %v13, float %e14, i64 14 556 %v15 = insertelement <16 x float> %v14, float %e15, i64 15 557 ret <16 x float> %v15 558} 559 560define <32 x float> @buildvec_v32f32(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7, float %e8, float %e9, float %e10, float %e11, float %e12, float %e13, float %e14, float %e15, float %e16, float %e17, float %e18, float %e19, float %e20, float %e21, float %e22, float %e23, float %e24, float %e25, float %e26, float %e27, float %e28, float %e29, float %e30, float %e31) { 561; RV32-LABEL: buildvec_v32f32: 562; RV32: # %bb.0: 563; RV32-NEXT: addi sp, sp, -256 564; RV32-NEXT: .cfi_def_cfa_offset 256 565; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill 566; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill 567; RV32-NEXT: fsd fs0, 240(sp) # 8-byte Folded Spill 568; RV32-NEXT: fsd fs1, 232(sp) # 8-byte Folded Spill 569; RV32-NEXT: fsd fs2, 224(sp) # 8-byte Folded Spill 570; RV32-NEXT: fsd fs3, 216(sp) # 8-byte Folded Spill 571; RV32-NEXT: .cfi_offset ra, -4 572; RV32-NEXT: .cfi_offset s0, -8 573; RV32-NEXT: .cfi_offset fs0, -16 574; RV32-NEXT: .cfi_offset fs1, -24 575; RV32-NEXT: .cfi_offset fs2, -32 576; RV32-NEXT: .cfi_offset fs3, -40 577; RV32-NEXT: addi s0, sp, 256 578; RV32-NEXT: .cfi_def_cfa s0, 0 579; RV32-NEXT: andi sp, sp, -128 580; RV32-NEXT: flw ft0, 0(s0) 581; RV32-NEXT: flw ft1, 4(s0) 582; RV32-NEXT: flw ft2, 8(s0) 583; RV32-NEXT: flw ft3, 12(s0) 584; RV32-NEXT: flw ft4, 16(s0) 585; RV32-NEXT: flw ft5, 20(s0) 586; RV32-NEXT: flw ft6, 24(s0) 587; RV32-NEXT: flw ft7, 28(s0) 588; RV32-NEXT: flw ft8, 32(s0) 589; RV32-NEXT: flw ft9, 36(s0) 590; RV32-NEXT: flw ft10, 40(s0) 591; RV32-NEXT: flw ft11, 44(s0) 592; RV32-NEXT: flw fs0, 48(s0) 593; RV32-NEXT: flw fs1, 52(s0) 594; RV32-NEXT: flw fs2, 56(s0) 595; RV32-NEXT: flw fs3, 60(s0) 596; RV32-NEXT: sw a4, 48(sp) 597; RV32-NEXT: sw a5, 52(sp) 598; RV32-NEXT: sw a6, 56(sp) 599; RV32-NEXT: sw a7, 60(sp) 600; RV32-NEXT: sw a0, 32(sp) 601; RV32-NEXT: sw a1, 36(sp) 602; RV32-NEXT: sw a2, 40(sp) 603; RV32-NEXT: sw a3, 44(sp) 604; RV32-NEXT: fsw fa4, 16(sp) 605; RV32-NEXT: fsw fa5, 20(sp) 606; RV32-NEXT: fsw fa6, 24(sp) 607; RV32-NEXT: fsw fa7, 28(sp) 608; RV32-NEXT: fsw fa0, 0(sp) 609; RV32-NEXT: fsw fa1, 4(sp) 610; RV32-NEXT: fsw fa2, 8(sp) 611; RV32-NEXT: fsw fa3, 12(sp) 612; RV32-NEXT: li a0, 32 613; RV32-NEXT: fsw fs0, 112(sp) 614; RV32-NEXT: fsw fs1, 116(sp) 615; RV32-NEXT: fsw fs2, 120(sp) 616; RV32-NEXT: fsw fs3, 124(sp) 617; RV32-NEXT: fsw ft8, 96(sp) 618; RV32-NEXT: fsw ft9, 100(sp) 619; RV32-NEXT: fsw ft10, 104(sp) 620; RV32-NEXT: fsw ft11, 108(sp) 621; RV32-NEXT: fsw ft4, 80(sp) 622; RV32-NEXT: fsw ft5, 84(sp) 623; RV32-NEXT: fsw ft6, 88(sp) 624; RV32-NEXT: fsw ft7, 92(sp) 625; RV32-NEXT: fsw ft0, 64(sp) 626; RV32-NEXT: fsw ft1, 68(sp) 627; RV32-NEXT: fsw ft2, 72(sp) 628; RV32-NEXT: fsw ft3, 76(sp) 629; RV32-NEXT: mv a1, sp 630; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma 631; RV32-NEXT: vle32.v v8, (a1) 632; RV32-NEXT: addi sp, s0, -256 633; RV32-NEXT: .cfi_def_cfa sp, 256 634; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload 635; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload 636; RV32-NEXT: fld fs0, 240(sp) # 8-byte Folded Reload 637; RV32-NEXT: fld fs1, 232(sp) # 8-byte Folded Reload 638; RV32-NEXT: fld fs2, 224(sp) # 8-byte Folded Reload 639; RV32-NEXT: fld fs3, 216(sp) # 8-byte Folded Reload 640; RV32-NEXT: .cfi_restore ra 641; RV32-NEXT: .cfi_restore s0 642; RV32-NEXT: .cfi_restore fs0 643; RV32-NEXT: .cfi_restore fs1 644; RV32-NEXT: .cfi_restore fs2 645; RV32-NEXT: .cfi_restore fs3 646; RV32-NEXT: addi sp, sp, 256 647; RV32-NEXT: .cfi_def_cfa_offset 0 648; RV32-NEXT: ret 649; 650; RV64-LABEL: buildvec_v32f32: 651; RV64: # %bb.0: 652; RV64-NEXT: addi sp, sp, -256 653; RV64-NEXT: .cfi_def_cfa_offset 256 654; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill 655; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill 656; RV64-NEXT: fsd fs0, 232(sp) # 8-byte Folded Spill 657; RV64-NEXT: fsd fs1, 224(sp) # 8-byte Folded Spill 658; RV64-NEXT: fsd fs2, 216(sp) # 8-byte Folded Spill 659; RV64-NEXT: fsd fs3, 208(sp) # 8-byte Folded Spill 660; RV64-NEXT: fsd fs4, 200(sp) # 8-byte Folded Spill 661; RV64-NEXT: fsd fs5, 192(sp) # 8-byte Folded Spill 662; RV64-NEXT: fsd fs6, 184(sp) # 8-byte Folded Spill 663; RV64-NEXT: fsd fs7, 176(sp) # 8-byte Folded Spill 664; RV64-NEXT: fsd fs8, 168(sp) # 8-byte Folded Spill 665; RV64-NEXT: fsd fs9, 160(sp) # 8-byte Folded Spill 666; RV64-NEXT: fsd fs10, 152(sp) # 8-byte Folded Spill 667; RV64-NEXT: fsd fs11, 144(sp) # 8-byte Folded Spill 668; RV64-NEXT: .cfi_offset ra, -8 669; RV64-NEXT: .cfi_offset s0, -16 670; RV64-NEXT: .cfi_offset fs0, -24 671; RV64-NEXT: .cfi_offset fs1, -32 672; RV64-NEXT: .cfi_offset fs2, -40 673; RV64-NEXT: .cfi_offset fs3, -48 674; RV64-NEXT: .cfi_offset fs4, -56 675; RV64-NEXT: .cfi_offset fs5, -64 676; RV64-NEXT: .cfi_offset fs6, -72 677; RV64-NEXT: .cfi_offset fs7, -80 678; RV64-NEXT: .cfi_offset fs8, -88 679; RV64-NEXT: .cfi_offset fs9, -96 680; RV64-NEXT: .cfi_offset fs10, -104 681; RV64-NEXT: .cfi_offset fs11, -112 682; RV64-NEXT: addi s0, sp, 256 683; RV64-NEXT: .cfi_def_cfa s0, 0 684; RV64-NEXT: andi sp, sp, -128 685; RV64-NEXT: fmv.w.x ft4, a0 686; RV64-NEXT: fmv.w.x ft5, a1 687; RV64-NEXT: fmv.w.x ft6, a2 688; RV64-NEXT: fmv.w.x ft7, a3 689; RV64-NEXT: fmv.w.x fs0, a4 690; RV64-NEXT: fmv.w.x fs1, a5 691; RV64-NEXT: fmv.w.x fs2, a6 692; RV64-NEXT: fmv.w.x fs3, a7 693; RV64-NEXT: flw ft0, 0(s0) 694; RV64-NEXT: flw ft1, 8(s0) 695; RV64-NEXT: flw ft2, 16(s0) 696; RV64-NEXT: flw ft3, 24(s0) 697; RV64-NEXT: flw ft8, 32(s0) 698; RV64-NEXT: flw ft9, 40(s0) 699; RV64-NEXT: flw ft10, 48(s0) 700; RV64-NEXT: flw ft11, 56(s0) 701; RV64-NEXT: flw fs4, 64(s0) 702; RV64-NEXT: flw fs5, 72(s0) 703; RV64-NEXT: flw fs6, 80(s0) 704; RV64-NEXT: flw fs7, 88(s0) 705; RV64-NEXT: flw fs8, 96(s0) 706; RV64-NEXT: flw fs9, 104(s0) 707; RV64-NEXT: flw fs10, 112(s0) 708; RV64-NEXT: flw fs11, 120(s0) 709; RV64-NEXT: fsw fa4, 16(sp) 710; RV64-NEXT: fsw fa5, 20(sp) 711; RV64-NEXT: fsw fa6, 24(sp) 712; RV64-NEXT: fsw fa7, 28(sp) 713; RV64-NEXT: fsw fa0, 0(sp) 714; RV64-NEXT: fsw fa1, 4(sp) 715; RV64-NEXT: fsw fa2, 8(sp) 716; RV64-NEXT: fsw fa3, 12(sp) 717; RV64-NEXT: li a0, 32 718; RV64-NEXT: fsw fs0, 48(sp) 719; RV64-NEXT: fsw fs1, 52(sp) 720; RV64-NEXT: fsw fs2, 56(sp) 721; RV64-NEXT: fsw fs3, 60(sp) 722; RV64-NEXT: fsw ft4, 32(sp) 723; RV64-NEXT: fsw ft5, 36(sp) 724; RV64-NEXT: fsw ft6, 40(sp) 725; RV64-NEXT: fsw ft7, 44(sp) 726; RV64-NEXT: fsw fs8, 112(sp) 727; RV64-NEXT: fsw fs9, 116(sp) 728; RV64-NEXT: fsw fs10, 120(sp) 729; RV64-NEXT: fsw fs11, 124(sp) 730; RV64-NEXT: fsw fs4, 96(sp) 731; RV64-NEXT: fsw fs5, 100(sp) 732; RV64-NEXT: fsw fs6, 104(sp) 733; RV64-NEXT: fsw fs7, 108(sp) 734; RV64-NEXT: fsw ft8, 80(sp) 735; RV64-NEXT: fsw ft9, 84(sp) 736; RV64-NEXT: fsw ft10, 88(sp) 737; RV64-NEXT: fsw ft11, 92(sp) 738; RV64-NEXT: fsw ft0, 64(sp) 739; RV64-NEXT: fsw ft1, 68(sp) 740; RV64-NEXT: fsw ft2, 72(sp) 741; RV64-NEXT: fsw ft3, 76(sp) 742; RV64-NEXT: mv a1, sp 743; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma 744; RV64-NEXT: vle32.v v8, (a1) 745; RV64-NEXT: addi sp, s0, -256 746; RV64-NEXT: .cfi_def_cfa sp, 256 747; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload 748; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload 749; RV64-NEXT: fld fs0, 232(sp) # 8-byte Folded Reload 750; RV64-NEXT: fld fs1, 224(sp) # 8-byte Folded Reload 751; RV64-NEXT: fld fs2, 216(sp) # 8-byte Folded Reload 752; RV64-NEXT: fld fs3, 208(sp) # 8-byte Folded Reload 753; RV64-NEXT: fld fs4, 200(sp) # 8-byte Folded Reload 754; RV64-NEXT: fld fs5, 192(sp) # 8-byte Folded Reload 755; RV64-NEXT: fld fs6, 184(sp) # 8-byte Folded Reload 756; RV64-NEXT: fld fs7, 176(sp) # 8-byte Folded Reload 757; RV64-NEXT: fld fs8, 168(sp) # 8-byte Folded Reload 758; RV64-NEXT: fld fs9, 160(sp) # 8-byte Folded Reload 759; RV64-NEXT: fld fs10, 152(sp) # 8-byte Folded Reload 760; RV64-NEXT: fld fs11, 144(sp) # 8-byte Folded Reload 761; RV64-NEXT: .cfi_restore ra 762; RV64-NEXT: .cfi_restore s0 763; RV64-NEXT: .cfi_restore fs0 764; RV64-NEXT: .cfi_restore fs1 765; RV64-NEXT: .cfi_restore fs2 766; RV64-NEXT: .cfi_restore fs3 767; RV64-NEXT: .cfi_restore fs4 768; RV64-NEXT: .cfi_restore fs5 769; RV64-NEXT: .cfi_restore fs6 770; RV64-NEXT: .cfi_restore fs7 771; RV64-NEXT: .cfi_restore fs8 772; RV64-NEXT: .cfi_restore fs9 773; RV64-NEXT: .cfi_restore fs10 774; RV64-NEXT: .cfi_restore fs11 775; RV64-NEXT: addi sp, sp, 256 776; RV64-NEXT: .cfi_def_cfa_offset 0 777; RV64-NEXT: ret 778 %v0 = insertelement <32 x float> poison, float %e0, i64 0 779 %v1 = insertelement <32 x float> %v0, float %e1, i64 1 780 %v2 = insertelement <32 x float> %v1, float %e2, i64 2 781 %v3 = insertelement <32 x float> %v2, float %e3, i64 3 782 %v4 = insertelement <32 x float> %v3, float %e4, i64 4 783 %v5 = insertelement <32 x float> %v4, float %e5, i64 5 784 %v6 = insertelement <32 x float> %v5, float %e6, i64 6 785 %v7 = insertelement <32 x float> %v6, float %e7, i64 7 786 %v8 = insertelement <32 x float> %v7, float %e8, i64 8 787 %v9 = insertelement <32 x float> %v8, float %e9, i64 9 788 %v10 = insertelement <32 x float> %v9, float %e10, i64 10 789 %v11 = insertelement <32 x float> %v10, float %e11, i64 11 790 %v12 = insertelement <32 x float> %v11, float %e12, i64 12 791 %v13 = insertelement <32 x float> %v12, float %e13, i64 13 792 %v14 = insertelement <32 x float> %v13, float %e14, i64 14 793 %v15 = insertelement <32 x float> %v14, float %e15, i64 15 794 %v16 = insertelement <32 x float> %v15, float %e16, i64 16 795 %v17 = insertelement <32 x float> %v16, float %e17, i64 17 796 %v18 = insertelement <32 x float> %v17, float %e18, i64 18 797 %v19 = insertelement <32 x float> %v18, float %e19, i64 19 798 %v20 = insertelement <32 x float> %v19, float %e20, i64 20 799 %v21 = insertelement <32 x float> %v20, float %e21, i64 21 800 %v22 = insertelement <32 x float> %v21, float %e22, i64 22 801 %v23 = insertelement <32 x float> %v22, float %e23, i64 23 802 %v24 = insertelement <32 x float> %v23, float %e24, i64 24 803 %v25 = insertelement <32 x float> %v24, float %e25, i64 25 804 %v26 = insertelement <32 x float> %v25, float %e26, i64 26 805 %v27 = insertelement <32 x float> %v26, float %e27, i64 27 806 %v28 = insertelement <32 x float> %v27, float %e28, i64 28 807 %v29 = insertelement <32 x float> %v28, float %e29, i64 29 808 %v30 = insertelement <32 x float> %v29, float %e30, i64 30 809 %v31 = insertelement <32 x float> %v30, float %e31, i64 31 810 ret <32 x float> %v31 811} 812 813define <8 x double> @buildvec_v8f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) { 814; RV32-LABEL: buildvec_v8f64: 815; RV32: # %bb.0: 816; RV32-NEXT: addi sp, sp, -128 817; RV32-NEXT: .cfi_def_cfa_offset 128 818; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill 819; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill 820; RV32-NEXT: .cfi_offset ra, -4 821; RV32-NEXT: .cfi_offset s0, -8 822; RV32-NEXT: addi s0, sp, 128 823; RV32-NEXT: .cfi_def_cfa s0, 0 824; RV32-NEXT: andi sp, sp, -64 825; RV32-NEXT: fsd fa4, 32(sp) 826; RV32-NEXT: fsd fa5, 40(sp) 827; RV32-NEXT: fsd fa6, 48(sp) 828; RV32-NEXT: fsd fa7, 56(sp) 829; RV32-NEXT: fsd fa0, 0(sp) 830; RV32-NEXT: fsd fa1, 8(sp) 831; RV32-NEXT: fsd fa2, 16(sp) 832; RV32-NEXT: fsd fa3, 24(sp) 833; RV32-NEXT: mv a0, sp 834; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma 835; RV32-NEXT: vle64.v v8, (a0) 836; RV32-NEXT: addi sp, s0, -128 837; RV32-NEXT: .cfi_def_cfa sp, 128 838; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload 839; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload 840; RV32-NEXT: .cfi_restore ra 841; RV32-NEXT: .cfi_restore s0 842; RV32-NEXT: addi sp, sp, 128 843; RV32-NEXT: .cfi_def_cfa_offset 0 844; RV32-NEXT: ret 845; 846; RV64-LABEL: buildvec_v8f64: 847; RV64: # %bb.0: 848; RV64-NEXT: addi sp, sp, -128 849; RV64-NEXT: .cfi_def_cfa_offset 128 850; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill 851; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill 852; RV64-NEXT: .cfi_offset ra, -8 853; RV64-NEXT: .cfi_offset s0, -16 854; RV64-NEXT: addi s0, sp, 128 855; RV64-NEXT: .cfi_def_cfa s0, 0 856; RV64-NEXT: andi sp, sp, -64 857; RV64-NEXT: fsd fa4, 32(sp) 858; RV64-NEXT: fsd fa5, 40(sp) 859; RV64-NEXT: fsd fa6, 48(sp) 860; RV64-NEXT: fsd fa7, 56(sp) 861; RV64-NEXT: fsd fa0, 0(sp) 862; RV64-NEXT: fsd fa1, 8(sp) 863; RV64-NEXT: fsd fa2, 16(sp) 864; RV64-NEXT: fsd fa3, 24(sp) 865; RV64-NEXT: mv a0, sp 866; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma 867; RV64-NEXT: vle64.v v8, (a0) 868; RV64-NEXT: addi sp, s0, -128 869; RV64-NEXT: .cfi_def_cfa sp, 128 870; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload 871; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload 872; RV64-NEXT: .cfi_restore ra 873; RV64-NEXT: .cfi_restore s0 874; RV64-NEXT: addi sp, sp, 128 875; RV64-NEXT: .cfi_def_cfa_offset 0 876; RV64-NEXT: ret 877 %v0 = insertelement <8 x double> poison, double %e0, i64 0 878 %v1 = insertelement <8 x double> %v0, double %e1, i64 1 879 %v2 = insertelement <8 x double> %v1, double %e2, i64 2 880 %v3 = insertelement <8 x double> %v2, double %e3, i64 3 881 %v4 = insertelement <8 x double> %v3, double %e4, i64 4 882 %v5 = insertelement <8 x double> %v4, double %e5, i64 5 883 %v6 = insertelement <8 x double> %v5, double %e6, i64 6 884 %v7 = insertelement <8 x double> %v6, double %e7, i64 7 885 ret <8 x double> %v7 886} 887 888define <16 x double> @buildvec_v16f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15) { 889; RV32-LABEL: buildvec_v16f64: 890; RV32: # %bb.0: 891; RV32-NEXT: addi sp, sp, -384 892; RV32-NEXT: .cfi_def_cfa_offset 384 893; RV32-NEXT: sw ra, 380(sp) # 4-byte Folded Spill 894; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill 895; RV32-NEXT: .cfi_offset ra, -4 896; RV32-NEXT: .cfi_offset s0, -8 897; RV32-NEXT: addi s0, sp, 384 898; RV32-NEXT: .cfi_def_cfa s0, 0 899; RV32-NEXT: andi sp, sp, -128 900; RV32-NEXT: sw a0, 120(sp) 901; RV32-NEXT: sw a1, 124(sp) 902; RV32-NEXT: fld ft0, 0(s0) 903; RV32-NEXT: fld ft1, 8(s0) 904; RV32-NEXT: fld ft2, 16(s0) 905; RV32-NEXT: fld ft3, 24(s0) 906; RV32-NEXT: fld ft4, 120(sp) 907; RV32-NEXT: sw a2, 120(sp) 908; RV32-NEXT: sw a3, 124(sp) 909; RV32-NEXT: fld ft5, 120(sp) 910; RV32-NEXT: sw a4, 120(sp) 911; RV32-NEXT: sw a5, 124(sp) 912; RV32-NEXT: fld ft6, 120(sp) 913; RV32-NEXT: sw a6, 120(sp) 914; RV32-NEXT: sw a7, 124(sp) 915; RV32-NEXT: fld ft7, 120(sp) 916; RV32-NEXT: fsd ft0, 224(sp) 917; RV32-NEXT: fsd ft1, 232(sp) 918; RV32-NEXT: fsd ft2, 240(sp) 919; RV32-NEXT: fsd ft3, 248(sp) 920; RV32-NEXT: fsd fa4, 160(sp) 921; RV32-NEXT: fsd fa5, 168(sp) 922; RV32-NEXT: fsd fa6, 176(sp) 923; RV32-NEXT: fsd fa7, 184(sp) 924; RV32-NEXT: fsd fa0, 128(sp) 925; RV32-NEXT: fsd fa1, 136(sp) 926; RV32-NEXT: fsd fa2, 144(sp) 927; RV32-NEXT: fsd fa3, 152(sp) 928; RV32-NEXT: fsd ft4, 192(sp) 929; RV32-NEXT: fsd ft5, 200(sp) 930; RV32-NEXT: fsd ft6, 208(sp) 931; RV32-NEXT: fsd ft7, 216(sp) 932; RV32-NEXT: addi a0, sp, 128 933; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma 934; RV32-NEXT: vle64.v v8, (a0) 935; RV32-NEXT: addi sp, s0, -384 936; RV32-NEXT: .cfi_def_cfa sp, 384 937; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload 938; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload 939; RV32-NEXT: .cfi_restore ra 940; RV32-NEXT: .cfi_restore s0 941; RV32-NEXT: addi sp, sp, 384 942; RV32-NEXT: .cfi_def_cfa_offset 0 943; RV32-NEXT: ret 944; 945; RV64-LABEL: buildvec_v16f64: 946; RV64: # %bb.0: 947; RV64-NEXT: addi sp, sp, -256 948; RV64-NEXT: .cfi_def_cfa_offset 256 949; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill 950; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill 951; RV64-NEXT: .cfi_offset ra, -8 952; RV64-NEXT: .cfi_offset s0, -16 953; RV64-NEXT: addi s0, sp, 256 954; RV64-NEXT: .cfi_def_cfa s0, 0 955; RV64-NEXT: andi sp, sp, -128 956; RV64-NEXT: sd a4, 96(sp) 957; RV64-NEXT: sd a5, 104(sp) 958; RV64-NEXT: sd a6, 112(sp) 959; RV64-NEXT: sd a7, 120(sp) 960; RV64-NEXT: sd a0, 64(sp) 961; RV64-NEXT: sd a1, 72(sp) 962; RV64-NEXT: sd a2, 80(sp) 963; RV64-NEXT: sd a3, 88(sp) 964; RV64-NEXT: fsd fa4, 32(sp) 965; RV64-NEXT: fsd fa5, 40(sp) 966; RV64-NEXT: fsd fa6, 48(sp) 967; RV64-NEXT: fsd fa7, 56(sp) 968; RV64-NEXT: fsd fa0, 0(sp) 969; RV64-NEXT: fsd fa1, 8(sp) 970; RV64-NEXT: fsd fa2, 16(sp) 971; RV64-NEXT: fsd fa3, 24(sp) 972; RV64-NEXT: mv a0, sp 973; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma 974; RV64-NEXT: vle64.v v8, (a0) 975; RV64-NEXT: addi sp, s0, -256 976; RV64-NEXT: .cfi_def_cfa sp, 256 977; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload 978; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload 979; RV64-NEXT: .cfi_restore ra 980; RV64-NEXT: .cfi_restore s0 981; RV64-NEXT: addi sp, sp, 256 982; RV64-NEXT: .cfi_def_cfa_offset 0 983; RV64-NEXT: ret 984 %v0 = insertelement <16 x double> poison, double %e0, i64 0 985 %v1 = insertelement <16 x double> %v0, double %e1, i64 1 986 %v2 = insertelement <16 x double> %v1, double %e2, i64 2 987 %v3 = insertelement <16 x double> %v2, double %e3, i64 3 988 %v4 = insertelement <16 x double> %v3, double %e4, i64 4 989 %v5 = insertelement <16 x double> %v4, double %e5, i64 5 990 %v6 = insertelement <16 x double> %v5, double %e6, i64 6 991 %v7 = insertelement <16 x double> %v6, double %e7, i64 7 992 %v8 = insertelement <16 x double> %v7, double %e8, i64 8 993 %v9 = insertelement <16 x double> %v8, double %e9, i64 9 994 %v10 = insertelement <16 x double> %v9, double %e10, i64 10 995 %v11 = insertelement <16 x double> %v10, double %e11, i64 11 996 %v12 = insertelement <16 x double> %v11, double %e12, i64 12 997 %v13 = insertelement <16 x double> %v12, double %e13, i64 13 998 %v14 = insertelement <16 x double> %v13, double %e14, i64 14 999 %v15 = insertelement <16 x double> %v14, double %e15, i64 15 1000 ret <16 x double> %v15 1001} 1002 1003define <32 x double> @buildvec_v32f64(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15, double %e16, double %e17, double %e18, double %e19, double %e20, double %e21, double %e22, double %e23, double %e24, double %e25, double %e26, double %e27, double %e28, double %e29, double %e30, double %e31) { 1004; RV32-LABEL: buildvec_v32f64: 1005; RV32: # %bb.0: 1006; RV32-NEXT: addi sp, sp, -512 1007; RV32-NEXT: .cfi_def_cfa_offset 512 1008; RV32-NEXT: sw ra, 508(sp) # 4-byte Folded Spill 1009; RV32-NEXT: sw s0, 504(sp) # 4-byte Folded Spill 1010; RV32-NEXT: fsd fs0, 496(sp) # 8-byte Folded Spill 1011; RV32-NEXT: fsd fs1, 488(sp) # 8-byte Folded Spill 1012; RV32-NEXT: fsd fs2, 480(sp) # 8-byte Folded Spill 1013; RV32-NEXT: fsd fs3, 472(sp) # 8-byte Folded Spill 1014; RV32-NEXT: fsd fs4, 464(sp) # 8-byte Folded Spill 1015; RV32-NEXT: fsd fs5, 456(sp) # 8-byte Folded Spill 1016; RV32-NEXT: fsd fs6, 448(sp) # 8-byte Folded Spill 1017; RV32-NEXT: fsd fs7, 440(sp) # 8-byte Folded Spill 1018; RV32-NEXT: fsd fs8, 432(sp) # 8-byte Folded Spill 1019; RV32-NEXT: fsd fs9, 424(sp) # 8-byte Folded Spill 1020; RV32-NEXT: fsd fs10, 416(sp) # 8-byte Folded Spill 1021; RV32-NEXT: fsd fs11, 408(sp) # 8-byte Folded Spill 1022; RV32-NEXT: .cfi_offset ra, -4 1023; RV32-NEXT: .cfi_offset s0, -8 1024; RV32-NEXT: .cfi_offset fs0, -16 1025; RV32-NEXT: .cfi_offset fs1, -24 1026; RV32-NEXT: .cfi_offset fs2, -32 1027; RV32-NEXT: .cfi_offset fs3, -40 1028; RV32-NEXT: .cfi_offset fs4, -48 1029; RV32-NEXT: .cfi_offset fs5, -56 1030; RV32-NEXT: .cfi_offset fs6, -64 1031; RV32-NEXT: .cfi_offset fs7, -72 1032; RV32-NEXT: .cfi_offset fs8, -80 1033; RV32-NEXT: .cfi_offset fs9, -88 1034; RV32-NEXT: .cfi_offset fs10, -96 1035; RV32-NEXT: .cfi_offset fs11, -104 1036; RV32-NEXT: addi s0, sp, 512 1037; RV32-NEXT: .cfi_def_cfa s0, 0 1038; RV32-NEXT: andi sp, sp, -128 1039; RV32-NEXT: sw a0, 120(sp) 1040; RV32-NEXT: sw a1, 124(sp) 1041; RV32-NEXT: fld ft0, 0(s0) 1042; RV32-NEXT: fld ft1, 8(s0) 1043; RV32-NEXT: fld ft2, 16(s0) 1044; RV32-NEXT: fld ft3, 24(s0) 1045; RV32-NEXT: fld ft4, 32(s0) 1046; RV32-NEXT: fld ft5, 40(s0) 1047; RV32-NEXT: fld ft6, 48(s0) 1048; RV32-NEXT: fld ft7, 56(s0) 1049; RV32-NEXT: fld ft8, 64(s0) 1050; RV32-NEXT: fld ft9, 72(s0) 1051; RV32-NEXT: fld ft10, 80(s0) 1052; RV32-NEXT: fld ft11, 88(s0) 1053; RV32-NEXT: fld fs0, 96(s0) 1054; RV32-NEXT: fld fs1, 104(s0) 1055; RV32-NEXT: fld fs2, 112(s0) 1056; RV32-NEXT: fld fs3, 120(s0) 1057; RV32-NEXT: fld fs4, 128(s0) 1058; RV32-NEXT: fld fs5, 136(s0) 1059; RV32-NEXT: fld fs6, 144(s0) 1060; RV32-NEXT: fld fs7, 152(s0) 1061; RV32-NEXT: addi a0, sp, 128 1062; RV32-NEXT: addi a1, sp, 256 1063; RV32-NEXT: fld fs8, 120(sp) 1064; RV32-NEXT: sw a2, 120(sp) 1065; RV32-NEXT: sw a3, 124(sp) 1066; RV32-NEXT: fld fs9, 120(sp) 1067; RV32-NEXT: sw a4, 120(sp) 1068; RV32-NEXT: sw a5, 124(sp) 1069; RV32-NEXT: fld fs10, 120(sp) 1070; RV32-NEXT: sw a6, 120(sp) 1071; RV32-NEXT: sw a7, 124(sp) 1072; RV32-NEXT: fld fs11, 120(sp) 1073; RV32-NEXT: fsd fs4, 224(sp) 1074; RV32-NEXT: fsd fs5, 232(sp) 1075; RV32-NEXT: fsd fs6, 240(sp) 1076; RV32-NEXT: fsd fs7, 248(sp) 1077; RV32-NEXT: fsd fs0, 192(sp) 1078; RV32-NEXT: fsd fs1, 200(sp) 1079; RV32-NEXT: fsd fs2, 208(sp) 1080; RV32-NEXT: fsd fs3, 216(sp) 1081; RV32-NEXT: fsd ft8, 160(sp) 1082; RV32-NEXT: fsd ft9, 168(sp) 1083; RV32-NEXT: fsd ft10, 176(sp) 1084; RV32-NEXT: fsd ft11, 184(sp) 1085; RV32-NEXT: fsd ft4, 128(sp) 1086; RV32-NEXT: fsd ft5, 136(sp) 1087; RV32-NEXT: fsd ft6, 144(sp) 1088; RV32-NEXT: fsd ft7, 152(sp) 1089; RV32-NEXT: fsd ft0, 352(sp) 1090; RV32-NEXT: fsd ft1, 360(sp) 1091; RV32-NEXT: fsd ft2, 368(sp) 1092; RV32-NEXT: fsd ft3, 376(sp) 1093; RV32-NEXT: fsd fa4, 288(sp) 1094; RV32-NEXT: fsd fa5, 296(sp) 1095; RV32-NEXT: fsd fa6, 304(sp) 1096; RV32-NEXT: fsd fa7, 312(sp) 1097; RV32-NEXT: fsd fa0, 256(sp) 1098; RV32-NEXT: fsd fa1, 264(sp) 1099; RV32-NEXT: fsd fa2, 272(sp) 1100; RV32-NEXT: fsd fa3, 280(sp) 1101; RV32-NEXT: fsd fs8, 320(sp) 1102; RV32-NEXT: fsd fs9, 328(sp) 1103; RV32-NEXT: fsd fs10, 336(sp) 1104; RV32-NEXT: fsd fs11, 344(sp) 1105; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma 1106; RV32-NEXT: vle64.v v16, (a0) 1107; RV32-NEXT: vle64.v v8, (a1) 1108; RV32-NEXT: addi sp, s0, -512 1109; RV32-NEXT: .cfi_def_cfa sp, 512 1110; RV32-NEXT: lw ra, 508(sp) # 4-byte Folded Reload 1111; RV32-NEXT: lw s0, 504(sp) # 4-byte Folded Reload 1112; RV32-NEXT: fld fs0, 496(sp) # 8-byte Folded Reload 1113; RV32-NEXT: fld fs1, 488(sp) # 8-byte Folded Reload 1114; RV32-NEXT: fld fs2, 480(sp) # 8-byte Folded Reload 1115; RV32-NEXT: fld fs3, 472(sp) # 8-byte Folded Reload 1116; RV32-NEXT: fld fs4, 464(sp) # 8-byte Folded Reload 1117; RV32-NEXT: fld fs5, 456(sp) # 8-byte Folded Reload 1118; RV32-NEXT: fld fs6, 448(sp) # 8-byte Folded Reload 1119; RV32-NEXT: fld fs7, 440(sp) # 8-byte Folded Reload 1120; RV32-NEXT: fld fs8, 432(sp) # 8-byte Folded Reload 1121; RV32-NEXT: fld fs9, 424(sp) # 8-byte Folded Reload 1122; RV32-NEXT: fld fs10, 416(sp) # 8-byte Folded Reload 1123; RV32-NEXT: fld fs11, 408(sp) # 8-byte Folded Reload 1124; RV32-NEXT: .cfi_restore ra 1125; RV32-NEXT: .cfi_restore s0 1126; RV32-NEXT: .cfi_restore fs0 1127; RV32-NEXT: .cfi_restore fs1 1128; RV32-NEXT: .cfi_restore fs2 1129; RV32-NEXT: .cfi_restore fs3 1130; RV32-NEXT: .cfi_restore fs4 1131; RV32-NEXT: .cfi_restore fs5 1132; RV32-NEXT: .cfi_restore fs6 1133; RV32-NEXT: .cfi_restore fs7 1134; RV32-NEXT: .cfi_restore fs8 1135; RV32-NEXT: .cfi_restore fs9 1136; RV32-NEXT: .cfi_restore fs10 1137; RV32-NEXT: .cfi_restore fs11 1138; RV32-NEXT: addi sp, sp, 512 1139; RV32-NEXT: .cfi_def_cfa_offset 0 1140; RV32-NEXT: ret 1141; 1142; RV64-LABEL: buildvec_v32f64: 1143; RV64: # %bb.0: 1144; RV64-NEXT: addi sp, sp, -384 1145; RV64-NEXT: .cfi_def_cfa_offset 384 1146; RV64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill 1147; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill 1148; RV64-NEXT: fsd fs0, 360(sp) # 8-byte Folded Spill 1149; RV64-NEXT: fsd fs1, 352(sp) # 8-byte Folded Spill 1150; RV64-NEXT: fsd fs2, 344(sp) # 8-byte Folded Spill 1151; RV64-NEXT: fsd fs3, 336(sp) # 8-byte Folded Spill 1152; RV64-NEXT: .cfi_offset ra, -8 1153; RV64-NEXT: .cfi_offset s0, -16 1154; RV64-NEXT: .cfi_offset fs0, -24 1155; RV64-NEXT: .cfi_offset fs1, -32 1156; RV64-NEXT: .cfi_offset fs2, -40 1157; RV64-NEXT: .cfi_offset fs3, -48 1158; RV64-NEXT: addi s0, sp, 384 1159; RV64-NEXT: .cfi_def_cfa s0, 0 1160; RV64-NEXT: andi sp, sp, -128 1161; RV64-NEXT: fld ft0, 0(s0) 1162; RV64-NEXT: fld ft1, 8(s0) 1163; RV64-NEXT: fld ft2, 16(s0) 1164; RV64-NEXT: fld ft3, 24(s0) 1165; RV64-NEXT: fld ft4, 32(s0) 1166; RV64-NEXT: fld ft5, 40(s0) 1167; RV64-NEXT: fld ft6, 48(s0) 1168; RV64-NEXT: fld ft7, 56(s0) 1169; RV64-NEXT: fld ft8, 64(s0) 1170; RV64-NEXT: fld ft9, 72(s0) 1171; RV64-NEXT: fld ft10, 80(s0) 1172; RV64-NEXT: fld ft11, 88(s0) 1173; RV64-NEXT: fld fs0, 96(s0) 1174; RV64-NEXT: fld fs1, 104(s0) 1175; RV64-NEXT: fld fs2, 112(s0) 1176; RV64-NEXT: fld fs3, 120(s0) 1177; RV64-NEXT: sd a4, 224(sp) 1178; RV64-NEXT: sd a5, 232(sp) 1179; RV64-NEXT: sd a6, 240(sp) 1180; RV64-NEXT: sd a7, 248(sp) 1181; RV64-NEXT: sd a0, 192(sp) 1182; RV64-NEXT: sd a1, 200(sp) 1183; RV64-NEXT: sd a2, 208(sp) 1184; RV64-NEXT: sd a3, 216(sp) 1185; RV64-NEXT: fsd fa4, 160(sp) 1186; RV64-NEXT: fsd fa5, 168(sp) 1187; RV64-NEXT: fsd fa6, 176(sp) 1188; RV64-NEXT: fsd fa7, 184(sp) 1189; RV64-NEXT: fsd fa0, 128(sp) 1190; RV64-NEXT: fsd fa1, 136(sp) 1191; RV64-NEXT: fsd fa2, 144(sp) 1192; RV64-NEXT: fsd fa3, 152(sp) 1193; RV64-NEXT: addi a0, sp, 128 1194; RV64-NEXT: mv a1, sp 1195; RV64-NEXT: fsd fs0, 96(sp) 1196; RV64-NEXT: fsd fs1, 104(sp) 1197; RV64-NEXT: fsd fs2, 112(sp) 1198; RV64-NEXT: fsd fs3, 120(sp) 1199; RV64-NEXT: fsd ft8, 64(sp) 1200; RV64-NEXT: fsd ft9, 72(sp) 1201; RV64-NEXT: fsd ft10, 80(sp) 1202; RV64-NEXT: fsd ft11, 88(sp) 1203; RV64-NEXT: fsd ft4, 32(sp) 1204; RV64-NEXT: fsd ft5, 40(sp) 1205; RV64-NEXT: fsd ft6, 48(sp) 1206; RV64-NEXT: fsd ft7, 56(sp) 1207; RV64-NEXT: fsd ft0, 0(sp) 1208; RV64-NEXT: fsd ft1, 8(sp) 1209; RV64-NEXT: fsd ft2, 16(sp) 1210; RV64-NEXT: fsd ft3, 24(sp) 1211; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma 1212; RV64-NEXT: vle64.v v8, (a0) 1213; RV64-NEXT: vle64.v v16, (a1) 1214; RV64-NEXT: addi sp, s0, -384 1215; RV64-NEXT: .cfi_def_cfa sp, 384 1216; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload 1217; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload 1218; RV64-NEXT: fld fs0, 360(sp) # 8-byte Folded Reload 1219; RV64-NEXT: fld fs1, 352(sp) # 8-byte Folded Reload 1220; RV64-NEXT: fld fs2, 344(sp) # 8-byte Folded Reload 1221; RV64-NEXT: fld fs3, 336(sp) # 8-byte Folded Reload 1222; RV64-NEXT: .cfi_restore ra 1223; RV64-NEXT: .cfi_restore s0 1224; RV64-NEXT: .cfi_restore fs0 1225; RV64-NEXT: .cfi_restore fs1 1226; RV64-NEXT: .cfi_restore fs2 1227; RV64-NEXT: .cfi_restore fs3 1228; RV64-NEXT: addi sp, sp, 384 1229; RV64-NEXT: .cfi_def_cfa_offset 0 1230; RV64-NEXT: ret 1231 %v0 = insertelement <32 x double> poison, double %e0, i64 0 1232 %v1 = insertelement <32 x double> %v0, double %e1, i64 1 1233 %v2 = insertelement <32 x double> %v1, double %e2, i64 2 1234 %v3 = insertelement <32 x double> %v2, double %e3, i64 3 1235 %v4 = insertelement <32 x double> %v3, double %e4, i64 4 1236 %v5 = insertelement <32 x double> %v4, double %e5, i64 5 1237 %v6 = insertelement <32 x double> %v5, double %e6, i64 6 1238 %v7 = insertelement <32 x double> %v6, double %e7, i64 7 1239 %v8 = insertelement <32 x double> %v7, double %e8, i64 8 1240 %v9 = insertelement <32 x double> %v8, double %e9, i64 9 1241 %v10 = insertelement <32 x double> %v9, double %e10, i64 10 1242 %v11 = insertelement <32 x double> %v10, double %e11, i64 11 1243 %v12 = insertelement <32 x double> %v11, double %e12, i64 12 1244 %v13 = insertelement <32 x double> %v12, double %e13, i64 13 1245 %v14 = insertelement <32 x double> %v13, double %e14, i64 14 1246 %v15 = insertelement <32 x double> %v14, double %e15, i64 15 1247 %v16 = insertelement <32 x double> %v15, double %e16, i64 16 1248 %v17 = insertelement <32 x double> %v16, double %e17, i64 17 1249 %v18 = insertelement <32 x double> %v17, double %e18, i64 18 1250 %v19 = insertelement <32 x double> %v18, double %e19, i64 19 1251 %v20 = insertelement <32 x double> %v19, double %e20, i64 20 1252 %v21 = insertelement <32 x double> %v20, double %e21, i64 21 1253 %v22 = insertelement <32 x double> %v21, double %e22, i64 22 1254 %v23 = insertelement <32 x double> %v22, double %e23, i64 23 1255 %v24 = insertelement <32 x double> %v23, double %e24, i64 24 1256 %v25 = insertelement <32 x double> %v24, double %e25, i64 25 1257 %v26 = insertelement <32 x double> %v25, double %e26, i64 26 1258 %v27 = insertelement <32 x double> %v26, double %e27, i64 27 1259 %v28 = insertelement <32 x double> %v27, double %e28, i64 28 1260 %v29 = insertelement <32 x double> %v28, double %e29, i64 29 1261 %v30 = insertelement <32 x double> %v29, double %e30, i64 30 1262 %v31 = insertelement <32 x double> %v30, double %e31, i64 31 1263 ret <32 x double> %v31 1264} 1265 1266define <32 x double> @buildvec_v32f64_exact_vlen(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7, double %e8, double %e9, double %e10, double %e11, double %e12, double %e13, double %e14, double %e15, double %e16, double %e17, double %e18, double %e19, double %e20, double %e21, double %e22, double %e23, double %e24, double %e25, double %e26, double %e27, double %e28, double %e29, double %e30, double %e31) vscale_range(2,2) { 1267; RV32-LABEL: buildvec_v32f64_exact_vlen: 1268; RV32: # %bb.0: 1269; RV32-NEXT: addi sp, sp, -96 1270; RV32-NEXT: .cfi_def_cfa_offset 96 1271; RV32-NEXT: fsd fs0, 88(sp) # 8-byte Folded Spill 1272; RV32-NEXT: fsd fs1, 80(sp) # 8-byte Folded Spill 1273; RV32-NEXT: fsd fs2, 72(sp) # 8-byte Folded Spill 1274; RV32-NEXT: fsd fs3, 64(sp) # 8-byte Folded Spill 1275; RV32-NEXT: fsd fs4, 56(sp) # 8-byte Folded Spill 1276; RV32-NEXT: fsd fs5, 48(sp) # 8-byte Folded Spill 1277; RV32-NEXT: fsd fs6, 40(sp) # 8-byte Folded Spill 1278; RV32-NEXT: fsd fs7, 32(sp) # 8-byte Folded Spill 1279; RV32-NEXT: fsd fs8, 24(sp) # 8-byte Folded Spill 1280; RV32-NEXT: fsd fs9, 16(sp) # 8-byte Folded Spill 1281; RV32-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill 1282; RV32-NEXT: .cfi_offset fs0, -8 1283; RV32-NEXT: .cfi_offset fs1, -16 1284; RV32-NEXT: .cfi_offset fs2, -24 1285; RV32-NEXT: .cfi_offset fs3, -32 1286; RV32-NEXT: .cfi_offset fs4, -40 1287; RV32-NEXT: .cfi_offset fs5, -48 1288; RV32-NEXT: .cfi_offset fs6, -56 1289; RV32-NEXT: .cfi_offset fs7, -64 1290; RV32-NEXT: .cfi_offset fs8, -72 1291; RV32-NEXT: .cfi_offset fs9, -80 1292; RV32-NEXT: .cfi_offset fs10, -88 1293; RV32-NEXT: sw a6, 0(sp) 1294; RV32-NEXT: sw a7, 4(sp) 1295; RV32-NEXT: fld ft0, 248(sp) 1296; RV32-NEXT: fld ft1, 240(sp) 1297; RV32-NEXT: fld ft2, 232(sp) 1298; RV32-NEXT: fld ft3, 224(sp) 1299; RV32-NEXT: fld ft6, 216(sp) 1300; RV32-NEXT: fld ft8, 208(sp) 1301; RV32-NEXT: fld ft10, 200(sp) 1302; RV32-NEXT: fld fs1, 192(sp) 1303; RV32-NEXT: fld ft11, 184(sp) 1304; RV32-NEXT: fld fs4, 176(sp) 1305; RV32-NEXT: fld fs2, 168(sp) 1306; RV32-NEXT: fld fs5, 160(sp) 1307; RV32-NEXT: fld fs3, 136(sp) 1308; RV32-NEXT: fld fs6, 128(sp) 1309; RV32-NEXT: fld fs7, 152(sp) 1310; RV32-NEXT: fld fs8, 144(sp) 1311; RV32-NEXT: fld ft4, 120(sp) 1312; RV32-NEXT: fld ft5, 112(sp) 1313; RV32-NEXT: fld ft7, 104(sp) 1314; RV32-NEXT: fld ft9, 96(sp) 1315; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1316; RV32-NEXT: vfmv.v.f v8, fa2 1317; RV32-NEXT: fld fa2, 0(sp) 1318; RV32-NEXT: sw a4, 0(sp) 1319; RV32-NEXT: sw a5, 4(sp) 1320; RV32-NEXT: fld fs0, 0(sp) 1321; RV32-NEXT: sw a2, 0(sp) 1322; RV32-NEXT: sw a3, 4(sp) 1323; RV32-NEXT: fld fs9, 0(sp) 1324; RV32-NEXT: sw a0, 0(sp) 1325; RV32-NEXT: sw a1, 4(sp) 1326; RV32-NEXT: fld fs10, 0(sp) 1327; RV32-NEXT: vfmv.v.f v9, fs8 1328; RV32-NEXT: vfmv.v.f v10, fs6 1329; RV32-NEXT: vfmv.v.f v11, fs5 1330; RV32-NEXT: vfmv.v.f v12, fs4 1331; RV32-NEXT: vfmv.v.f v13, fs1 1332; RV32-NEXT: vfslide1down.vf v17, v9, fs7 1333; RV32-NEXT: vfslide1down.vf v16, v10, fs3 1334; RV32-NEXT: vfslide1down.vf v18, v11, fs2 1335; RV32-NEXT: vfmv.v.f v9, fs10 1336; RV32-NEXT: vfslide1down.vf v19, v12, ft11 1337; RV32-NEXT: vfslide1down.vf v20, v13, ft10 1338; RV32-NEXT: vfslide1down.vf v12, v9, fs9 1339; RV32-NEXT: vfslide1down.vf v9, v8, fa3 1340; RV32-NEXT: vfmv.v.f v8, ft8 1341; RV32-NEXT: vfslide1down.vf v21, v8, ft6 1342; RV32-NEXT: vfmv.v.f v8, fa0 1343; RV32-NEXT: vfslide1down.vf v8, v8, fa1 1344; RV32-NEXT: vfmv.v.f v10, ft3 1345; RV32-NEXT: vfslide1down.vf v22, v10, ft2 1346; RV32-NEXT: vfmv.v.f v10, fa4 1347; RV32-NEXT: vfslide1down.vf v10, v10, fa5 1348; RV32-NEXT: vfmv.v.f v11, fa6 1349; RV32-NEXT: vfslide1down.vf v11, v11, fa7 1350; RV32-NEXT: vfmv.v.f v13, fs0 1351; RV32-NEXT: vfslide1down.vf v13, v13, fa2 1352; RV32-NEXT: vfmv.v.f v14, ft9 1353; RV32-NEXT: vfslide1down.vf v14, v14, ft7 1354; RV32-NEXT: vfmv.v.f v15, ft5 1355; RV32-NEXT: vfslide1down.vf v15, v15, ft4 1356; RV32-NEXT: vfmv.v.f v23, ft1 1357; RV32-NEXT: vfslide1down.vf v23, v23, ft0 1358; RV32-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload 1359; RV32-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload 1360; RV32-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload 1361; RV32-NEXT: fld fs3, 64(sp) # 8-byte Folded Reload 1362; RV32-NEXT: fld fs4, 56(sp) # 8-byte Folded Reload 1363; RV32-NEXT: fld fs5, 48(sp) # 8-byte Folded Reload 1364; RV32-NEXT: fld fs6, 40(sp) # 8-byte Folded Reload 1365; RV32-NEXT: fld fs7, 32(sp) # 8-byte Folded Reload 1366; RV32-NEXT: fld fs8, 24(sp) # 8-byte Folded Reload 1367; RV32-NEXT: fld fs9, 16(sp) # 8-byte Folded Reload 1368; RV32-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload 1369; RV32-NEXT: .cfi_restore fs0 1370; RV32-NEXT: .cfi_restore fs1 1371; RV32-NEXT: .cfi_restore fs2 1372; RV32-NEXT: .cfi_restore fs3 1373; RV32-NEXT: .cfi_restore fs4 1374; RV32-NEXT: .cfi_restore fs5 1375; RV32-NEXT: .cfi_restore fs6 1376; RV32-NEXT: .cfi_restore fs7 1377; RV32-NEXT: .cfi_restore fs8 1378; RV32-NEXT: .cfi_restore fs9 1379; RV32-NEXT: .cfi_restore fs10 1380; RV32-NEXT: addi sp, sp, 96 1381; RV32-NEXT: .cfi_def_cfa_offset 0 1382; RV32-NEXT: ret 1383; 1384; RV64-LABEL: buildvec_v32f64_exact_vlen: 1385; RV64: # %bb.0: 1386; RV64-NEXT: addi sp, sp, -64 1387; RV64-NEXT: .cfi_def_cfa_offset 64 1388; RV64-NEXT: fsd fs0, 56(sp) # 8-byte Folded Spill 1389; RV64-NEXT: fsd fs1, 48(sp) # 8-byte Folded Spill 1390; RV64-NEXT: fsd fs2, 40(sp) # 8-byte Folded Spill 1391; RV64-NEXT: fsd fs3, 32(sp) # 8-byte Folded Spill 1392; RV64-NEXT: fsd fs4, 24(sp) # 8-byte Folded Spill 1393; RV64-NEXT: fsd fs5, 16(sp) # 8-byte Folded Spill 1394; RV64-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill 1395; RV64-NEXT: fsd fs7, 0(sp) # 8-byte Folded Spill 1396; RV64-NEXT: .cfi_offset fs0, -8 1397; RV64-NEXT: .cfi_offset fs1, -16 1398; RV64-NEXT: .cfi_offset fs2, -24 1399; RV64-NEXT: .cfi_offset fs3, -32 1400; RV64-NEXT: .cfi_offset fs4, -40 1401; RV64-NEXT: .cfi_offset fs5, -48 1402; RV64-NEXT: .cfi_offset fs6, -56 1403; RV64-NEXT: .cfi_offset fs7, -64 1404; RV64-NEXT: fmv.d.x ft6, a7 1405; RV64-NEXT: fmv.d.x ft9, a5 1406; RV64-NEXT: fmv.d.x ft10, a3 1407; RV64-NEXT: fmv.d.x ft11, a1 1408; RV64-NEXT: fld ft0, 184(sp) 1409; RV64-NEXT: fld ft1, 176(sp) 1410; RV64-NEXT: fld ft2, 168(sp) 1411; RV64-NEXT: fld ft3, 160(sp) 1412; RV64-NEXT: fld ft4, 152(sp) 1413; RV64-NEXT: fld ft5, 144(sp) 1414; RV64-NEXT: fld ft7, 136(sp) 1415; RV64-NEXT: fld ft8, 128(sp) 1416; RV64-NEXT: fld fs0, 120(sp) 1417; RV64-NEXT: fld fs1, 112(sp) 1418; RV64-NEXT: fld fs2, 104(sp) 1419; RV64-NEXT: fld fs3, 96(sp) 1420; RV64-NEXT: fld fs4, 72(sp) 1421; RV64-NEXT: fld fs5, 64(sp) 1422; RV64-NEXT: fld fs6, 88(sp) 1423; RV64-NEXT: fld fs7, 80(sp) 1424; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1425; RV64-NEXT: vfmv.v.f v8, fa2 1426; RV64-NEXT: vfmv.v.f v10, fa0 1427; RV64-NEXT: vfmv.v.f v11, fa4 1428; RV64-NEXT: vfmv.v.f v12, fa6 1429; RV64-NEXT: vmv.v.x v13, a0 1430; RV64-NEXT: vmv.v.x v14, a2 1431; RV64-NEXT: vfslide1down.vf v9, v8, fa3 1432; RV64-NEXT: vfslide1down.vf v8, v10, fa1 1433; RV64-NEXT: vfslide1down.vf v10, v11, fa5 1434; RV64-NEXT: vfslide1down.vf v11, v12, fa7 1435; RV64-NEXT: vfmv.v.f v15, fs7 1436; RV64-NEXT: vfmv.v.f v16, fs5 1437; RV64-NEXT: vfslide1down.vf v12, v13, ft11 1438; RV64-NEXT: vfslide1down.vf v13, v14, ft10 1439; RV64-NEXT: vfslide1down.vf v17, v15, fs6 1440; RV64-NEXT: vfslide1down.vf v16, v16, fs4 1441; RV64-NEXT: vmv.v.x v14, a4 1442; RV64-NEXT: vfslide1down.vf v14, v14, ft9 1443; RV64-NEXT: vfmv.v.f v15, fs3 1444; RV64-NEXT: vfslide1down.vf v18, v15, fs2 1445; RV64-NEXT: vmv.v.x v15, a6 1446; RV64-NEXT: vfslide1down.vf v15, v15, ft6 1447; RV64-NEXT: vfmv.v.f v19, fs1 1448; RV64-NEXT: vfslide1down.vf v19, v19, fs0 1449; RV64-NEXT: vfmv.v.f v20, ft8 1450; RV64-NEXT: vfslide1down.vf v20, v20, ft7 1451; RV64-NEXT: vfmv.v.f v21, ft5 1452; RV64-NEXT: vfslide1down.vf v21, v21, ft4 1453; RV64-NEXT: vfmv.v.f v22, ft3 1454; RV64-NEXT: vfslide1down.vf v22, v22, ft2 1455; RV64-NEXT: vfmv.v.f v23, ft1 1456; RV64-NEXT: vfslide1down.vf v23, v23, ft0 1457; RV64-NEXT: fld fs0, 56(sp) # 8-byte Folded Reload 1458; RV64-NEXT: fld fs1, 48(sp) # 8-byte Folded Reload 1459; RV64-NEXT: fld fs2, 40(sp) # 8-byte Folded Reload 1460; RV64-NEXT: fld fs3, 32(sp) # 8-byte Folded Reload 1461; RV64-NEXT: fld fs4, 24(sp) # 8-byte Folded Reload 1462; RV64-NEXT: fld fs5, 16(sp) # 8-byte Folded Reload 1463; RV64-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload 1464; RV64-NEXT: fld fs7, 0(sp) # 8-byte Folded Reload 1465; RV64-NEXT: .cfi_restore fs0 1466; RV64-NEXT: .cfi_restore fs1 1467; RV64-NEXT: .cfi_restore fs2 1468; RV64-NEXT: .cfi_restore fs3 1469; RV64-NEXT: .cfi_restore fs4 1470; RV64-NEXT: .cfi_restore fs5 1471; RV64-NEXT: .cfi_restore fs6 1472; RV64-NEXT: .cfi_restore fs7 1473; RV64-NEXT: addi sp, sp, 64 1474; RV64-NEXT: .cfi_def_cfa_offset 0 1475; RV64-NEXT: ret 1476 %v0 = insertelement <32 x double> poison, double %e0, i64 0 1477 %v1 = insertelement <32 x double> %v0, double %e1, i64 1 1478 %v2 = insertelement <32 x double> %v1, double %e2, i64 2 1479 %v3 = insertelement <32 x double> %v2, double %e3, i64 3 1480 %v4 = insertelement <32 x double> %v3, double %e4, i64 4 1481 %v5 = insertelement <32 x double> %v4, double %e5, i64 5 1482 %v6 = insertelement <32 x double> %v5, double %e6, i64 6 1483 %v7 = insertelement <32 x double> %v6, double %e7, i64 7 1484 %v8 = insertelement <32 x double> %v7, double %e8, i64 8 1485 %v9 = insertelement <32 x double> %v8, double %e9, i64 9 1486 %v10 = insertelement <32 x double> %v9, double %e10, i64 10 1487 %v11 = insertelement <32 x double> %v10, double %e11, i64 11 1488 %v12 = insertelement <32 x double> %v11, double %e12, i64 12 1489 %v13 = insertelement <32 x double> %v12, double %e13, i64 13 1490 %v14 = insertelement <32 x double> %v13, double %e14, i64 14 1491 %v15 = insertelement <32 x double> %v14, double %e15, i64 15 1492 %v16 = insertelement <32 x double> %v15, double %e16, i64 16 1493 %v17 = insertelement <32 x double> %v16, double %e17, i64 17 1494 %v18 = insertelement <32 x double> %v17, double %e18, i64 18 1495 %v19 = insertelement <32 x double> %v18, double %e19, i64 19 1496 %v20 = insertelement <32 x double> %v19, double %e20, i64 20 1497 %v21 = insertelement <32 x double> %v20, double %e21, i64 21 1498 %v22 = insertelement <32 x double> %v21, double %e22, i64 22 1499 %v23 = insertelement <32 x double> %v22, double %e23, i64 23 1500 %v24 = insertelement <32 x double> %v23, double %e24, i64 24 1501 %v25 = insertelement <32 x double> %v24, double %e25, i64 25 1502 %v26 = insertelement <32 x double> %v25, double %e26, i64 26 1503 %v27 = insertelement <32 x double> %v26, double %e27, i64 27 1504 %v28 = insertelement <32 x double> %v27, double %e28, i64 28 1505 %v29 = insertelement <32 x double> %v28, double %e29, i64 29 1506 %v30 = insertelement <32 x double> %v29, double %e30, i64 30 1507 %v31 = insertelement <32 x double> %v30, double %e31, i64 31 1508 ret <32 x double> %v31 1509} 1510 1511; FIXME: These constants have enough sign bits that we could use vmv.v.x/i and 1512; vsext, but we don't support this for FP yet. 1513define <2 x float> @signbits() { 1514; CHECK-LABEL: signbits: 1515; CHECK: # %bb.0: # %entry 1516; CHECK-NEXT: lui a0, %hi(.LCPI25_0) 1517; CHECK-NEXT: addi a0, a0, %lo(.LCPI25_0) 1518; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 1519; CHECK-NEXT: vle32.v v8, (a0) 1520; CHECK-NEXT: ret 1521entry: 1522 ret <2 x float> <float 0x36A0000000000000, float 0.000000e+00> 1523} 1524 1525define <2 x half> @vid_v2f16() { 1526; RV32ZVFH-LABEL: vid_v2f16: 1527; RV32ZVFH: # %bb.0: 1528; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1529; RV32ZVFH-NEXT: vid.v v8 1530; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v8 1531; RV32ZVFH-NEXT: ret 1532; 1533; RV64ZVFH-LABEL: vid_v2f16: 1534; RV64ZVFH: # %bb.0: 1535; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1536; RV64ZVFH-NEXT: vid.v v8 1537; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v8 1538; RV64ZVFH-NEXT: ret 1539; 1540; RV32ZVFHMIN-LABEL: vid_v2f16: 1541; RV32ZVFHMIN: # %bb.0: 1542; RV32ZVFHMIN-NEXT: lui a0, 245760 1543; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma 1544; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0 1545; RV32ZVFHMIN-NEXT: ret 1546; 1547; RV64ZVFHMIN-LABEL: vid_v2f16: 1548; RV64ZVFHMIN: # %bb.0: 1549; RV64ZVFHMIN-NEXT: lui a0, 245760 1550; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma 1551; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0 1552; RV64ZVFHMIN-NEXT: ret 1553 ret <2 x half> <half 0.0, half 1.0> 1554} 1555 1556define <2 x half> @vid_addend1_v2f16() { 1557; RV32ZVFH-LABEL: vid_addend1_v2f16: 1558; RV32ZVFH: # %bb.0: 1559; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1560; RV32ZVFH-NEXT: vid.v v8 1561; RV32ZVFH-NEXT: vadd.vi v8, v8, 1 1562; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v8 1563; RV32ZVFH-NEXT: ret 1564; 1565; RV64ZVFH-LABEL: vid_addend1_v2f16: 1566; RV64ZVFH: # %bb.0: 1567; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1568; RV64ZVFH-NEXT: vid.v v8 1569; RV64ZVFH-NEXT: vadd.vi v8, v8, 1 1570; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v8 1571; RV64ZVFH-NEXT: ret 1572; 1573; RV32ZVFHMIN-LABEL: vid_addend1_v2f16: 1574; RV32ZVFHMIN: # %bb.0: 1575; RV32ZVFHMIN-NEXT: lui a0, 262148 1576; RV32ZVFHMIN-NEXT: addi a0, a0, -1024 1577; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma 1578; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0 1579; RV32ZVFHMIN-NEXT: ret 1580; 1581; RV64ZVFHMIN-LABEL: vid_addend1_v2f16: 1582; RV64ZVFHMIN: # %bb.0: 1583; RV64ZVFHMIN-NEXT: lui a0, 262148 1584; RV64ZVFHMIN-NEXT: addi a0, a0, -1024 1585; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma 1586; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0 1587; RV64ZVFHMIN-NEXT: ret 1588 ret <2 x half> <half 1.0, half 2.0> 1589} 1590 1591define <2 x half> @vid_denominator2_v2f16() { 1592; RV32ZVFH-LABEL: vid_denominator2_v2f16: 1593; RV32ZVFH: # %bb.0: 1594; RV32ZVFH-NEXT: lui a0, %hi(.LCPI28_0) 1595; RV32ZVFH-NEXT: addi a0, a0, %lo(.LCPI28_0) 1596; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1597; RV32ZVFH-NEXT: vle16.v v8, (a0) 1598; RV32ZVFH-NEXT: ret 1599; 1600; RV64ZVFH-LABEL: vid_denominator2_v2f16: 1601; RV64ZVFH: # %bb.0: 1602; RV64ZVFH-NEXT: lui a0, %hi(.LCPI28_0) 1603; RV64ZVFH-NEXT: addi a0, a0, %lo(.LCPI28_0) 1604; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1605; RV64ZVFH-NEXT: vle16.v v8, (a0) 1606; RV64ZVFH-NEXT: ret 1607; 1608; RV32ZVFHMIN-LABEL: vid_denominator2_v2f16: 1609; RV32ZVFHMIN: # %bb.0: 1610; RV32ZVFHMIN-NEXT: lui a0, 245764 1611; RV32ZVFHMIN-NEXT: addi a0, a0, -2048 1612; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma 1613; RV32ZVFHMIN-NEXT: vmv.s.x v8, a0 1614; RV32ZVFHMIN-NEXT: ret 1615; 1616; RV64ZVFHMIN-LABEL: vid_denominator2_v2f16: 1617; RV64ZVFHMIN: # %bb.0: 1618; RV64ZVFHMIN-NEXT: lui a0, 245764 1619; RV64ZVFHMIN-NEXT: addi a0, a0, -2048 1620; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e32, m1, ta, ma 1621; RV64ZVFHMIN-NEXT: vmv.s.x v8, a0 1622; RV64ZVFHMIN-NEXT: ret 1623 ret <2 x half> <half 0.5, half 1.0> 1624} 1625 1626define <2 x half> @vid_step2_v2f16() { 1627; RV32ZVFH-LABEL: vid_step2_v2f16: 1628; RV32ZVFH: # %bb.0: 1629; RV32ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1630; RV32ZVFH-NEXT: vid.v v8 1631; RV32ZVFH-NEXT: vadd.vv v8, v8, v8 1632; RV32ZVFH-NEXT: vfcvt.f.x.v v8, v8 1633; RV32ZVFH-NEXT: ret 1634; 1635; RV64ZVFH-LABEL: vid_step2_v2f16: 1636; RV64ZVFH: # %bb.0: 1637; RV64ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1638; RV64ZVFH-NEXT: vid.v v8 1639; RV64ZVFH-NEXT: vadd.vv v8, v8, v8 1640; RV64ZVFH-NEXT: vfcvt.f.x.v v8, v8 1641; RV64ZVFH-NEXT: ret 1642; 1643; RV32ZVFHMIN-LABEL: vid_step2_v2f16: 1644; RV32ZVFHMIN: # %bb.0: 1645; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1646; RV32ZVFHMIN-NEXT: vid.v v8 1647; RV32ZVFHMIN-NEXT: vsll.vi v8, v8, 14 1648; RV32ZVFHMIN-NEXT: ret 1649; 1650; RV64ZVFHMIN-LABEL: vid_step2_v2f16: 1651; RV64ZVFHMIN: # %bb.0: 1652; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 1653; RV64ZVFHMIN-NEXT: vid.v v8 1654; RV64ZVFHMIN-NEXT: vsll.vi v8, v8, 14 1655; RV64ZVFHMIN-NEXT: ret 1656 ret <2 x half> <half 0.0, half 2.0> 1657} 1658 1659define <2 x float> @vid_v2f32() { 1660; CHECK-LABEL: vid_v2f32: 1661; CHECK: # %bb.0: 1662; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 1663; CHECK-NEXT: vid.v v8 1664; CHECK-NEXT: vfcvt.f.x.v v8, v8 1665; CHECK-NEXT: ret 1666 ret <2 x float> <float 0.0, float 1.0> 1667} 1668 1669define <2 x float> @vid_addend1_v2f32() { 1670; CHECK-LABEL: vid_addend1_v2f32: 1671; CHECK: # %bb.0: 1672; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 1673; CHECK-NEXT: vid.v v8 1674; CHECK-NEXT: vadd.vi v8, v8, 1 1675; CHECK-NEXT: vfcvt.f.x.v v8, v8 1676; CHECK-NEXT: ret 1677 ret <2 x float> <float 1.0, float 2.0> 1678} 1679 1680define <2 x float> @vid_denominator2_v2f32() { 1681; CHECK-LABEL: vid_denominator2_v2f32: 1682; CHECK: # %bb.0: 1683; CHECK-NEXT: lui a0, %hi(.LCPI32_0) 1684; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0) 1685; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 1686; CHECK-NEXT: vle32.v v8, (a0) 1687; CHECK-NEXT: ret 1688 ret <2 x float> <float 0.5, float 1.0> 1689} 1690 1691define <2 x float> @vid_step2_v2f32() { 1692; CHECK-LABEL: vid_step2_v2f32: 1693; CHECK: # %bb.0: 1694; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma 1695; CHECK-NEXT: vid.v v8 1696; CHECK-NEXT: vadd.vv v8, v8, v8 1697; CHECK-NEXT: vfcvt.f.x.v v8, v8 1698; CHECK-NEXT: ret 1699 ret <2 x float> <float 0.0, float 2.0> 1700} 1701 1702define <2 x double> @vid_v2f64() { 1703; CHECK-LABEL: vid_v2f64: 1704; CHECK: # %bb.0: 1705; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1706; CHECK-NEXT: vid.v v8 1707; CHECK-NEXT: vfcvt.f.x.v v8, v8 1708; CHECK-NEXT: ret 1709 ret <2 x double> <double 0.0, double 1.0> 1710} 1711 1712define <2 x double> @vid_addend1_v2f64() { 1713; CHECK-LABEL: vid_addend1_v2f64: 1714; CHECK: # %bb.0: 1715; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1716; CHECK-NEXT: vid.v v8 1717; CHECK-NEXT: vadd.vi v8, v8, 1 1718; CHECK-NEXT: vfcvt.f.x.v v8, v8 1719; CHECK-NEXT: ret 1720 ret <2 x double> <double 1.0, double 2.0> 1721} 1722 1723define <2 x double> @vid_denominator2_v2f64() { 1724; CHECK-LABEL: vid_denominator2_v2f64: 1725; CHECK: # %bb.0: 1726; CHECK-NEXT: lui a0, %hi(.LCPI36_0) 1727; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0) 1728; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1729; CHECK-NEXT: vle64.v v8, (a0) 1730; CHECK-NEXT: ret 1731 ret <2 x double> <double 0.5, double 1.0> 1732} 1733 1734define <2 x double> @vid_step2_v2f64() { 1735; CHECK-LABEL: vid_step2_v2f64: 1736; CHECK: # %bb.0: 1737; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma 1738; CHECK-NEXT: vid.v v8 1739; CHECK-NEXT: vadd.vv v8, v8, v8 1740; CHECK-NEXT: vfcvt.f.x.v v8, v8 1741; CHECK-NEXT: ret 1742 ret <2 x double> <double 0.0, double 2.0> 1743} 1744 1745 1746define <8 x float> @buildvec_v8f32_zvl256(float %e0, float %e1, float %e2, float %e3, float %e4, float %e5, float %e6, float %e7) vscale_range(4, 128) { 1747; CHECK-LABEL: buildvec_v8f32_zvl256: 1748; CHECK: # %bb.0: 1749; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, mu 1750; CHECK-NEXT: vfmv.v.f v8, fa0 1751; CHECK-NEXT: vfmv.v.f v9, fa4 1752; CHECK-NEXT: vmv.v.i v0, 15 1753; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 1754; CHECK-NEXT: vfslide1down.vf v9, v9, fa5 1755; CHECK-NEXT: vfslide1down.vf v8, v8, fa2 1756; CHECK-NEXT: vfslide1down.vf v9, v9, fa6 1757; CHECK-NEXT: vfslide1down.vf v10, v8, fa3 1758; CHECK-NEXT: vfslide1down.vf v8, v9, fa7 1759; CHECK-NEXT: vslidedown.vi v8, v10, 4, v0.t 1760; CHECK-NEXT: ret 1761 %v0 = insertelement <8 x float> poison, float %e0, i64 0 1762 %v1 = insertelement <8 x float> %v0, float %e1, i64 1 1763 %v2 = insertelement <8 x float> %v1, float %e2, i64 2 1764 %v3 = insertelement <8 x float> %v2, float %e3, i64 3 1765 %v4 = insertelement <8 x float> %v3, float %e4, i64 4 1766 %v5 = insertelement <8 x float> %v4, float %e5, i64 5 1767 %v6 = insertelement <8 x float> %v5, float %e6, i64 6 1768 %v7 = insertelement <8 x float> %v6, float %e7, i64 7 1769 ret <8 x float> %v7 1770} 1771 1772 1773define <8 x double> @buildvec_v8f64_zvl256(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) vscale_range(4, 128) { 1774; CHECK-LABEL: buildvec_v8f64_zvl256: 1775; CHECK: # %bb.0: 1776; CHECK-NEXT: vsetivli zero, 8, e64, m2, ta, ma 1777; CHECK-NEXT: vfmv.v.f v8, fa0 1778; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 1779; CHECK-NEXT: vfslide1down.vf v8, v8, fa2 1780; CHECK-NEXT: vfslide1down.vf v8, v8, fa3 1781; CHECK-NEXT: vfslide1down.vf v8, v8, fa4 1782; CHECK-NEXT: vfslide1down.vf v8, v8, fa5 1783; CHECK-NEXT: vfslide1down.vf v8, v8, fa6 1784; CHECK-NEXT: vfslide1down.vf v8, v8, fa7 1785; CHECK-NEXT: ret 1786 %v0 = insertelement <8 x double> poison, double %e0, i64 0 1787 %v1 = insertelement <8 x double> %v0, double %e1, i64 1 1788 %v2 = insertelement <8 x double> %v1, double %e2, i64 2 1789 %v3 = insertelement <8 x double> %v2, double %e3, i64 3 1790 %v4 = insertelement <8 x double> %v3, double %e4, i64 4 1791 %v5 = insertelement <8 x double> %v4, double %e5, i64 5 1792 %v6 = insertelement <8 x double> %v5, double %e6, i64 6 1793 %v7 = insertelement <8 x double> %v6, double %e7, i64 7 1794 ret <8 x double> %v7 1795} 1796 1797define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, double %e3, double %e4, double %e5, double %e6, double %e7) vscale_range(8, 128) { 1798; CHECK-LABEL: buildvec_v8f64_zvl512: 1799; CHECK: # %bb.0: 1800; CHECK-NEXT: vsetivli zero, 8, e64, m1, ta, mu 1801; CHECK-NEXT: vfmv.v.f v8, fa0 1802; CHECK-NEXT: vfmv.v.f v9, fa4 1803; CHECK-NEXT: vmv.v.i v0, 15 1804; CHECK-NEXT: vfslide1down.vf v8, v8, fa1 1805; CHECK-NEXT: vfslide1down.vf v9, v9, fa5 1806; CHECK-NEXT: vfslide1down.vf v8, v8, fa2 1807; CHECK-NEXT: vfslide1down.vf v9, v9, fa6 1808; CHECK-NEXT: vfslide1down.vf v10, v8, fa3 1809; CHECK-NEXT: vfslide1down.vf v8, v9, fa7 1810; CHECK-NEXT: vslidedown.vi v8, v10, 4, v0.t 1811; CHECK-NEXT: ret 1812 %v0 = insertelement <8 x double> poison, double %e0, i64 0 1813 %v1 = insertelement <8 x double> %v0, double %e1, i64 1 1814 %v2 = insertelement <8 x double> %v1, double %e2, i64 2 1815 %v3 = insertelement <8 x double> %v2, double %e3, i64 3 1816 %v4 = insertelement <8 x double> %v3, double %e4, i64 4 1817 %v5 = insertelement <8 x double> %v4, double %e5, i64 5 1818 %v6 = insertelement <8 x double> %v5, double %e6, i64 6 1819 %v7 = insertelement <8 x double> %v6, double %e7, i64 7 1820 ret <8 x double> %v7 1821} 1822