1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-NO-ZFBFMIN 3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-NO-ZFBFMIN 4; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFBFMIN,RV32-ZFBFMIN 5; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfbfmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFBFMIN,RV64-ZFBFMIN 6 7define <4 x bfloat> @splat_idx_v4bf16(<4 x bfloat> %v, i64 %idx) { 8; RV32-NO-ZFBFMIN-LABEL: splat_idx_v4bf16: 9; RV32-NO-ZFBFMIN: # %bb.0: 10; RV32-NO-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 11; RV32-NO-ZFBFMIN-NEXT: vrgather.vx v9, v8, a0 12; RV32-NO-ZFBFMIN-NEXT: vmv1r.v v8, v9 13; RV32-NO-ZFBFMIN-NEXT: ret 14; 15; RV64-NO-ZFBFMIN-LABEL: splat_idx_v4bf16: 16; RV64-NO-ZFBFMIN: # %bb.0: 17; RV64-NO-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 18; RV64-NO-ZFBFMIN-NEXT: vrgather.vx v9, v8, a0 19; RV64-NO-ZFBFMIN-NEXT: vmv1r.v v8, v9 20; RV64-NO-ZFBFMIN-NEXT: ret 21; 22; RV32-ZFBFMIN-LABEL: splat_idx_v4bf16: 23; RV32-ZFBFMIN: # %bb.0: 24; RV32-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 25; RV32-ZFBFMIN-NEXT: vslidedown.vx v8, v8, a0 26; RV32-ZFBFMIN-NEXT: vmv.x.s a0, v8 27; RV32-ZFBFMIN-NEXT: vmv.v.x v8, a0 28; RV32-ZFBFMIN-NEXT: ret 29; 30; RV64-ZFBFMIN-LABEL: splat_idx_v4bf16: 31; RV64-ZFBFMIN: # %bb.0: 32; RV64-ZFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 33; RV64-ZFBFMIN-NEXT: vslidedown.vx v8, v8, a0 34; RV64-ZFBFMIN-NEXT: vmv.x.s a0, v8 35; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a0 36; RV64-ZFBFMIN-NEXT: ret 37 %x = extractelement <4 x bfloat> %v, i64 %idx 38 %ins = insertelement <4 x bfloat> poison, bfloat %x, i32 0 39 %splat = shufflevector <4 x bfloat> %ins, <4 x bfloat> poison, <4 x i32> zeroinitializer 40 ret <4 x bfloat> %splat 41} 42 43define <2 x bfloat> @buildvec_v2bf16(bfloat %a, bfloat %b) { 44; RV32-NO-ZFBFMIN-LABEL: buildvec_v2bf16: 45; RV32-NO-ZFBFMIN: # %bb.0: 46; RV32-NO-ZFBFMIN-NEXT: fmv.x.w a0, fa1 47; RV32-NO-ZFBFMIN-NEXT: fmv.x.w a1, fa0 48; RV32-NO-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 49; RV32-NO-ZFBFMIN-NEXT: vmv.v.x v8, a1 50; RV32-NO-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0 51; RV32-NO-ZFBFMIN-NEXT: ret 52; 53; RV64-NO-ZFBFMIN-LABEL: buildvec_v2bf16: 54; RV64-NO-ZFBFMIN: # %bb.0: 55; RV64-NO-ZFBFMIN-NEXT: fmv.x.w a0, fa1 56; RV64-NO-ZFBFMIN-NEXT: fmv.x.w a1, fa0 57; RV64-NO-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 58; RV64-NO-ZFBFMIN-NEXT: vmv.v.x v8, a1 59; RV64-NO-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0 60; RV64-NO-ZFBFMIN-NEXT: ret 61; 62; RV32-ZFBFMIN-LABEL: buildvec_v2bf16: 63; RV32-ZFBFMIN: # %bb.0: 64; RV32-ZFBFMIN-NEXT: fmv.x.h a0, fa1 65; RV32-ZFBFMIN-NEXT: fmv.x.h a1, fa0 66; RV32-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 67; RV32-ZFBFMIN-NEXT: vmv.v.x v8, a1 68; RV32-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0 69; RV32-ZFBFMIN-NEXT: ret 70; 71; RV64-ZFBFMIN-LABEL: buildvec_v2bf16: 72; RV64-ZFBFMIN: # %bb.0: 73; RV64-ZFBFMIN-NEXT: fmv.x.h a0, fa1 74; RV64-ZFBFMIN-NEXT: fmv.x.h a1, fa0 75; RV64-ZFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 76; RV64-ZFBFMIN-NEXT: vmv.v.x v8, a1 77; RV64-ZFBFMIN-NEXT: vslide1down.vx v8, v8, a0 78; RV64-ZFBFMIN-NEXT: ret 79 %v1 = insertelement <2 x bfloat> poison, bfloat %a, i64 0 80 %v2 = insertelement <2 x bfloat> %v1, bfloat %b, i64 1 81 ret <2 x bfloat> %v2 82} 83 84define <2 x bfloat> @vid_v2bf16() { 85; CHECK-LABEL: vid_v2bf16: 86; CHECK: # %bb.0: 87; CHECK-NEXT: lui a0, 260096 88; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma 89; CHECK-NEXT: vmv.s.x v8, a0 90; CHECK-NEXT: ret 91 ret <2 x bfloat> <bfloat 0.0, bfloat 1.0> 92} 93 94define <2 x bfloat> @vid_addend1_v2bf16() { 95; CHECK-LABEL: vid_addend1_v2bf16: 96; CHECK: # %bb.0: 97; CHECK-NEXT: lui a0, 262148 98; CHECK-NEXT: addi a0, a0, -128 99; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma 100; CHECK-NEXT: vmv.s.x v8, a0 101; CHECK-NEXT: ret 102 ret <2 x bfloat> <bfloat 1.0, bfloat 2.0> 103} 104 105define <2 x bfloat> @vid_denominator2_v2bf16() { 106; CHECK-LABEL: vid_denominator2_v2bf16: 107; CHECK: # %bb.0: 108; CHECK-NEXT: lui a0, 260100 109; CHECK-NEXT: addi a0, a0, -256 110; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma 111; CHECK-NEXT: vmv.s.x v8, a0 112; CHECK-NEXT: ret 113 ret <2 x bfloat> <bfloat 0.5, bfloat 1.0> 114} 115 116define <2 x bfloat> @vid_step2_v2bf16() { 117; CHECK-LABEL: vid_step2_v2bf16: 118; CHECK: # %bb.0: 119; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma 120; CHECK-NEXT: vid.v v8 121; CHECK-NEXT: vsll.vi v8, v8, 14 122; CHECK-NEXT: ret 123 ret <2 x bfloat> <bfloat 0.0, bfloat 2.0> 124} 125;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 126; RV32: {{.*}} 127; RV32ZVFBFMIN: {{.*}} 128; RV64: {{.*}} 129; RV64ZVFBFMIN: {{.*}} 130