xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
6
7; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
8; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
9; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
10; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,VLA
11
12; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
13; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
14; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
15; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK,VLS %s
16
17define void @extract_v2i8_v4i8_0(ptr %x, ptr %y) {
18; CHECK-LABEL: extract_v2i8_v4i8_0:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
21; CHECK-NEXT:    vle8.v v8, (a0)
22; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
23; CHECK-NEXT:    vse8.v v8, (a1)
24; CHECK-NEXT:    ret
25  %a = load <4 x i8>, ptr %x
26  %c = call <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 0)
27  store <2 x i8> %c, ptr %y
28  ret void
29}
30
31define void @extract_v2i8_v4i8_2(ptr %x, ptr %y) {
32; CHECK-LABEL: extract_v2i8_v4i8_2:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
35; CHECK-NEXT:    vle8.v v8, (a0)
36; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
37; CHECK-NEXT:    vslidedown.vi v8, v8, 2
38; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
39; CHECK-NEXT:    vse8.v v8, (a1)
40; CHECK-NEXT:    ret
41  %a = load <4 x i8>, ptr %x
42  %c = call <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %a, i64 2)
43  store <2 x i8> %c, ptr %y
44  ret void
45}
46
47define void @extract_v2i8_v8i8_0(ptr %x, ptr %y) {
48; CHECK-LABEL: extract_v2i8_v8i8_0:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
51; CHECK-NEXT:    vle8.v v8, (a0)
52; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
53; CHECK-NEXT:    vse8.v v8, (a1)
54; CHECK-NEXT:    ret
55  %a = load <8 x i8>, ptr %x
56  %c = call <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 0)
57  store <2 x i8> %c, ptr %y
58  ret void
59}
60
61define void @extract_v2i8_v8i8_6(ptr %x, ptr %y) {
62; CHECK-LABEL: extract_v2i8_v8i8_6:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
65; CHECK-NEXT:    vle8.v v8, (a0)
66; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, ta, ma
67; CHECK-NEXT:    vslidedown.vi v8, v8, 6
68; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
69; CHECK-NEXT:    vse8.v v8, (a1)
70; CHECK-NEXT:    ret
71  %a = load <8 x i8>, ptr %x
72  %c = call <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %a, i64 6)
73  store <2 x i8> %c, ptr %y
74  ret void
75}
76
77define void @extract_v1i32_v8i32_4(ptr %x, ptr %y) {
78; VLA-LABEL: extract_v1i32_v8i32_4:
79; VLA:       # %bb.0:
80; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
81; VLA-NEXT:    vle32.v v8, (a0)
82; VLA-NEXT:    vslidedown.vi v8, v8, 4
83; VLA-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
84; VLA-NEXT:    vse32.v v8, (a1)
85; VLA-NEXT:    ret
86;
87; VLS-LABEL: extract_v1i32_v8i32_4:
88; VLS:       # %bb.0:
89; VLS-NEXT:    vl2re32.v v8, (a0)
90; VLS-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
91; VLS-NEXT:    vse32.v v9, (a1)
92; VLS-NEXT:    ret
93  %a = load <8 x i32>, ptr %x
94  %c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 4)
95  store <1 x i32> %c, ptr %y
96  ret void
97}
98
99define void @extract_v1i32_v8i32_5(ptr %x, ptr %y) {
100; VLA-LABEL: extract_v1i32_v8i32_5:
101; VLA:       # %bb.0:
102; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
103; VLA-NEXT:    vle32.v v8, (a0)
104; VLA-NEXT:    vslidedown.vi v8, v8, 5
105; VLA-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
106; VLA-NEXT:    vse32.v v8, (a1)
107; VLA-NEXT:    ret
108;
109; VLS-LABEL: extract_v1i32_v8i32_5:
110; VLS:       # %bb.0:
111; VLS-NEXT:    vl2re32.v v8, (a0)
112; VLS-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
113; VLS-NEXT:    vslidedown.vi v8, v9, 1
114; VLS-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
115; VLS-NEXT:    vse32.v v8, (a1)
116; VLS-NEXT:    ret
117  %a = load <8 x i32>, ptr %x
118  %c = call <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %a, i64 5)
119  store <1 x i32> %c, ptr %y
120  ret void
121}
122
123define void @extract_v2i32_v8i32_0(ptr %x, ptr %y) {
124; VLA-LABEL: extract_v2i32_v8i32_0:
125; VLA:       # %bb.0:
126; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
127; VLA-NEXT:    vle32.v v8, (a0)
128; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
129; VLA-NEXT:    vse32.v v8, (a1)
130; VLA-NEXT:    ret
131;
132; VLS-LABEL: extract_v2i32_v8i32_0:
133; VLS:       # %bb.0:
134; VLS-NEXT:    vl2re32.v v8, (a0)
135; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
136; VLS-NEXT:    vse32.v v8, (a1)
137; VLS-NEXT:    ret
138  %a = load <8 x i32>, ptr %x
139  %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 0)
140  store <2 x i32> %c, ptr %y
141  ret void
142}
143
144define void @extract_v2i32_v8i32_2(ptr %x, ptr %y) {
145; VLA-LABEL: extract_v2i32_v8i32_2:
146; VLA:       # %bb.0:
147; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
148; VLA-NEXT:    vle32.v v8, (a0)
149; VLA-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
150; VLA-NEXT:    vslidedown.vi v8, v8, 2
151; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
152; VLA-NEXT:    vse32.v v8, (a1)
153; VLA-NEXT:    ret
154;
155; VLS-LABEL: extract_v2i32_v8i32_2:
156; VLS:       # %bb.0:
157; VLS-NEXT:    vl2re32.v v8, (a0)
158; VLS-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
159; VLS-NEXT:    vslidedown.vi v8, v8, 2
160; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
161; VLS-NEXT:    vse32.v v8, (a1)
162; VLS-NEXT:    ret
163  %a = load <8 x i32>, ptr %x
164  %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 2)
165  store <2 x i32> %c, ptr %y
166  ret void
167}
168
169define void @extract_v2i32_v8i32_4(ptr %x, ptr %y) {
170; VLA-LABEL: extract_v2i32_v8i32_4:
171; VLA:       # %bb.0:
172; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
173; VLA-NEXT:    vle32.v v8, (a0)
174; VLA-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
175; VLA-NEXT:    vslidedown.vi v8, v8, 4
176; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
177; VLA-NEXT:    vse32.v v8, (a1)
178; VLA-NEXT:    ret
179;
180; VLS-LABEL: extract_v2i32_v8i32_4:
181; VLS:       # %bb.0:
182; VLS-NEXT:    vl2re32.v v8, (a0)
183; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
184; VLS-NEXT:    vse32.v v9, (a1)
185; VLS-NEXT:    ret
186  %a = load <8 x i32>, ptr %x
187  %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 4)
188  store <2 x i32> %c, ptr %y
189  ret void
190}
191
192define void @extract_v2i32_v8i32_6(ptr %x, ptr %y) {
193; VLA-LABEL: extract_v2i32_v8i32_6:
194; VLA:       # %bb.0:
195; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
196; VLA-NEXT:    vle32.v v8, (a0)
197; VLA-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
198; VLA-NEXT:    vslidedown.vi v8, v8, 6
199; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
200; VLA-NEXT:    vse32.v v8, (a1)
201; VLA-NEXT:    ret
202;
203; VLS-LABEL: extract_v2i32_v8i32_6:
204; VLS:       # %bb.0:
205; VLS-NEXT:    vl2re32.v v8, (a0)
206; VLS-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
207; VLS-NEXT:    vslidedown.vi v8, v9, 2
208; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
209; VLS-NEXT:    vse32.v v8, (a1)
210; VLS-NEXT:    ret
211  %a = load <8 x i32>, ptr %x
212  %c = call <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %a, i64 6)
213  store <2 x i32> %c, ptr %y
214  ret void
215}
216
217define void @extract_v2i32_nxv16i32_0(<vscale x 16 x i32> %x, ptr %y) {
218; CHECK-LABEL: extract_v2i32_nxv16i32_0:
219; CHECK:       # %bb.0:
220; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
221; CHECK-NEXT:    vse32.v v8, (a0)
222; CHECK-NEXT:    ret
223  %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 0)
224  store <2 x i32> %c, ptr %y
225  ret void
226}
227
228
229define void @extract_v2i32_nxv16i32_2(<vscale x 16 x i32> %x, ptr %y) {
230; CHECK-LABEL: extract_v2i32_nxv16i32_2:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
233; CHECK-NEXT:    vslidedown.vi v8, v8, 2
234; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
235; CHECK-NEXT:    vse32.v v8, (a0)
236; CHECK-NEXT:    ret
237  %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 2)
238  store <2 x i32> %c, ptr %y
239  ret void
240}
241
242define void @extract_v2i32_nxv16i32_4(<vscale x 16 x i32> %x, ptr %y) {
243; VLA-LABEL: extract_v2i32_nxv16i32_4:
244; VLA:       # %bb.0:
245; VLA-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
246; VLA-NEXT:    vslidedown.vi v8, v8, 4
247; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
248; VLA-NEXT:    vse32.v v8, (a0)
249; VLA-NEXT:    ret
250;
251; VLS-LABEL: extract_v2i32_nxv16i32_4:
252; VLS:       # %bb.0:
253; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
254; VLS-NEXT:    vse32.v v9, (a0)
255; VLS-NEXT:    ret
256  %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 4)
257  store <2 x i32> %c, ptr %y
258  ret void
259}
260
261define void @extract_v2i32_nxv16i32_6(<vscale x 16 x i32> %x, ptr %y) {
262; VLA-LABEL: extract_v2i32_nxv16i32_6:
263; VLA:       # %bb.0:
264; VLA-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
265; VLA-NEXT:    vslidedown.vi v8, v8, 6
266; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
267; VLA-NEXT:    vse32.v v8, (a0)
268; VLA-NEXT:    ret
269;
270; VLS-LABEL: extract_v2i32_nxv16i32_6:
271; VLS:       # %bb.0:
272; VLS-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
273; VLS-NEXT:    vslidedown.vi v8, v9, 2
274; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
275; VLS-NEXT:    vse32.v v8, (a0)
276; VLS-NEXT:    ret
277  %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 6)
278  store <2 x i32> %c, ptr %y
279  ret void
280}
281
282define void @extract_v2i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {
283; VLA-LABEL: extract_v2i32_nxv16i32_8:
284; VLA:       # %bb.0:
285; VLA-NEXT:    vsetivli zero, 2, e32, m4, ta, ma
286; VLA-NEXT:    vslidedown.vi v8, v8, 8
287; VLA-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
288; VLA-NEXT:    vse32.v v8, (a0)
289; VLA-NEXT:    ret
290;
291; VLS-LABEL: extract_v2i32_nxv16i32_8:
292; VLS:       # %bb.0:
293; VLS-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
294; VLS-NEXT:    vse32.v v10, (a0)
295; VLS-NEXT:    ret
296  %c = call <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)
297  store <2 x i32> %c, ptr %y
298  ret void
299}
300
301define void @extract_v2i8_nxv2i8_0(<vscale x 2 x i8> %x, ptr %y) {
302; CHECK-LABEL: extract_v2i8_nxv2i8_0:
303; CHECK:       # %bb.0:
304; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
305; CHECK-NEXT:    vse8.v v8, (a0)
306; CHECK-NEXT:    ret
307  %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 0)
308  store <2 x i8> %c, ptr %y
309  ret void
310}
311
312define void @extract_v2i8_nxv2i8_2(<vscale x 2 x i8> %x, ptr %y) {
313; CHECK-LABEL: extract_v2i8_nxv2i8_2:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
316; CHECK-NEXT:    vslidedown.vi v8, v8, 2
317; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
318; CHECK-NEXT:    vse8.v v8, (a0)
319; CHECK-NEXT:    ret
320  %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 2)
321  store <2 x i8> %c, ptr %y
322  ret void
323}
324
325define void @extract_v2i8_nxv2i8_4(<vscale x 2 x i8> %x, ptr %y) {
326; CHECK-LABEL: extract_v2i8_nxv2i8_4:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
329; CHECK-NEXT:    vslidedown.vi v8, v8, 4
330; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
331; CHECK-NEXT:    vse8.v v8, (a0)
332; CHECK-NEXT:    ret
333  %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 4)
334  store <2 x i8> %c, ptr %y
335  ret void
336}
337
338define void @extract_v2i8_nxv2i8_6(<vscale x 2 x i8> %x, ptr %y) {
339; CHECK-LABEL: extract_v2i8_nxv2i8_6:
340; CHECK:       # %bb.0:
341; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
342; CHECK-NEXT:    vslidedown.vi v8, v8, 6
343; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
344; CHECK-NEXT:    vse8.v v8, (a0)
345; CHECK-NEXT:    ret
346  %c = call <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %x, i64 6)
347  store <2 x i8> %c, ptr %y
348  ret void
349}
350
351define void @extract_v8i32_nxv16i32_8(<vscale x 16 x i32> %x, ptr %y) {
352; VLA-LABEL: extract_v8i32_nxv16i32_8:
353; VLA:       # %bb.0:
354; VLA-NEXT:    vsetivli zero, 8, e32, m4, ta, ma
355; VLA-NEXT:    vslidedown.vi v8, v8, 8
356; VLA-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
357; VLA-NEXT:    vse32.v v8, (a0)
358; VLA-NEXT:    ret
359;
360; VLS-LABEL: extract_v8i32_nxv16i32_8:
361; VLS:       # %bb.0:
362; VLS-NEXT:    vs2r.v v10, (a0)
363; VLS-NEXT:    ret
364  %c = call <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %x, i64 8)
365  store <8 x i32> %c, ptr %y
366  ret void
367}
368
369define void @extract_v8i1_v64i1_0(ptr %x, ptr %y) {
370; VLA-LABEL: extract_v8i1_v64i1_0:
371; VLA:       # %bb.0:
372; VLA-NEXT:    li a2, 64
373; VLA-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
374; VLA-NEXT:    vlm.v v8, (a0)
375; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
376; VLA-NEXT:    vsm.v v8, (a1)
377; VLA-NEXT:    ret
378;
379; VLS-LABEL: extract_v8i1_v64i1_0:
380; VLS:       # %bb.0:
381; VLS-NEXT:    vsetvli a2, zero, e8, m4, ta, ma
382; VLS-NEXT:    vlm.v v8, (a0)
383; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
384; VLS-NEXT:    vsm.v v8, (a1)
385; VLS-NEXT:    ret
386  %a = load <64 x i1>, ptr %x
387  %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
388  store <8 x i1> %c, ptr %y
389  ret void
390}
391
392define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {
393; VLA-LABEL: extract_v8i1_v64i1_8:
394; VLA:       # %bb.0:
395; VLA-NEXT:    li a2, 64
396; VLA-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
397; VLA-NEXT:    vlm.v v8, (a0)
398; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
399; VLA-NEXT:    vslidedown.vi v8, v8, 1
400; VLA-NEXT:    vsm.v v8, (a1)
401; VLA-NEXT:    ret
402;
403; VLS-LABEL: extract_v8i1_v64i1_8:
404; VLS:       # %bb.0:
405; VLS-NEXT:    vsetvli a2, zero, e8, m4, ta, ma
406; VLS-NEXT:    vlm.v v8, (a0)
407; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
408; VLS-NEXT:    vslidedown.vi v8, v8, 1
409; VLS-NEXT:    vsm.v v8, (a1)
410; VLS-NEXT:    ret
411  %a = load <64 x i1>, ptr %x
412  %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
413  store <8 x i1> %c, ptr %y
414  ret void
415}
416
417define void @extract_v8i1_v64i1_48(ptr %x, ptr %y) {
418; VLA-LABEL: extract_v8i1_v64i1_48:
419; VLA:       # %bb.0:
420; VLA-NEXT:    li a2, 64
421; VLA-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
422; VLA-NEXT:    vlm.v v8, (a0)
423; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
424; VLA-NEXT:    vslidedown.vi v8, v8, 6
425; VLA-NEXT:    vsm.v v8, (a1)
426; VLA-NEXT:    ret
427;
428; VLS-LABEL: extract_v8i1_v64i1_48:
429; VLS:       # %bb.0:
430; VLS-NEXT:    vsetvli a2, zero, e8, m4, ta, ma
431; VLS-NEXT:    vlm.v v8, (a0)
432; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
433; VLS-NEXT:    vslidedown.vi v8, v8, 6
434; VLS-NEXT:    vsm.v v8, (a1)
435; VLS-NEXT:    ret
436  %a = load <64 x i1>, ptr %x
437  %c = call <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
438  store <8 x i1> %c, ptr %y
439  ret void
440}
441
442define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, ptr %y) {
443; CHECK-LABEL: extract_v8i1_nxv2i1_0:
444; CHECK:       # %bb.0:
445; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
446; CHECK-NEXT:    vsm.v v0, (a0)
447; CHECK-NEXT:    ret
448  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
449  store <8 x i1> %c, ptr %y
450  ret void
451}
452
453define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, ptr %y) {
454; CHECK-LABEL: extract_v8i1_nxv64i1_0:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
457; CHECK-NEXT:    vsm.v v0, (a0)
458; CHECK-NEXT:    ret
459  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
460  store <8 x i1> %c, ptr %y
461  ret void
462}
463
464define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, ptr %y) {
465; CHECK-LABEL: extract_v8i1_nxv64i1_8:
466; CHECK:       # %bb.0:
467; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
468; CHECK-NEXT:    vslidedown.vi v8, v0, 1
469; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
470; CHECK-NEXT:    vsm.v v8, (a0)
471; CHECK-NEXT:    ret
472  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)
473  store <8 x i1> %c, ptr %y
474  ret void
475}
476
477define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, ptr %y) {
478; CHECK-LABEL: extract_v8i1_nxv64i1_48:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
481; CHECK-NEXT:    vslidedown.vi v8, v0, 6
482; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
483; CHECK-NEXT:    vsm.v v8, (a0)
484; CHECK-NEXT:    ret
485  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)
486  store <8 x i1> %c, ptr %y
487  ret void
488}
489
490define void @extract_v8i1_nxv64i1_128(<vscale x 64 x i1> %x, ptr %y) {
491; CHECK-LABEL: extract_v8i1_nxv64i1_128:
492; CHECK:       # %bb.0:
493; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
494; CHECK-NEXT:    vslidedown.vi v8, v0, 16
495; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
496; CHECK-NEXT:    vsm.v v8, (a0)
497; CHECK-NEXT:    ret
498  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 128)
499  store <8 x i1> %c, ptr %y
500  ret void
501}
502
503define void @extract_v8i1_nxv64i1_192(<vscale x 64 x i1> %x, ptr %y) {
504; CHECK-LABEL: extract_v8i1_nxv64i1_192:
505; CHECK:       # %bb.0:
506; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
507; CHECK-NEXT:    vslidedown.vi v8, v0, 24
508; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
509; CHECK-NEXT:    vsm.v v8, (a0)
510; CHECK-NEXT:    ret
511  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 192)
512  store <8 x i1> %c, ptr %y
513  ret void
514}
515
516define void @extract_v2i1_v64i1_0(ptr %x, ptr %y) {
517; VLA-LABEL: extract_v2i1_v64i1_0:
518; VLA:       # %bb.0:
519; VLA-NEXT:    li a2, 64
520; VLA-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
521; VLA-NEXT:    vlm.v v0, (a0)
522; VLA-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
523; VLA-NEXT:    vmv.v.i v8, 0
524; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
525; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
526; VLA-NEXT:    vmv.v.i v9, 0
527; VLA-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
528; VLA-NEXT:    vmv.v.v v9, v8
529; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
530; VLA-NEXT:    vmsne.vi v8, v9, 0
531; VLA-NEXT:    vsm.v v8, (a1)
532; VLA-NEXT:    ret
533;
534; VLS-LABEL: extract_v2i1_v64i1_0:
535; VLS:       # %bb.0:
536; VLS-NEXT:    vsetvli a2, zero, e8, m4, ta, ma
537; VLS-NEXT:    vlm.v v0, (a0)
538; VLS-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
539; VLS-NEXT:    vmv.v.i v8, 0
540; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
541; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
542; VLS-NEXT:    vmv.v.i v9, 0
543; VLS-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
544; VLS-NEXT:    vmv.v.v v9, v8
545; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
546; VLS-NEXT:    vmsne.vi v8, v9, 0
547; VLS-NEXT:    vsm.v v8, (a1)
548; VLS-NEXT:    ret
549  %a = load <64 x i1>, ptr %x
550  %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
551  store <2 x i1> %c, ptr %y
552  ret void
553}
554
555define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
556; VLA-LABEL: extract_v2i1_v64i1_2:
557; VLA:       # %bb.0:
558; VLA-NEXT:    li a2, 64
559; VLA-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
560; VLA-NEXT:    vlm.v v0, (a0)
561; VLA-NEXT:    vmv.v.i v8, 0
562; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
563; VLA-NEXT:    vsetivli zero, 2, e8, m1, ta, ma
564; VLA-NEXT:    vslidedown.vi v8, v8, 2
565; VLA-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
566; VLA-NEXT:    vmsne.vi v0, v8, 0
567; VLA-NEXT:    vmv.v.i v8, 0
568; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
569; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
570; VLA-NEXT:    vmv.v.i v9, 0
571; VLA-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
572; VLA-NEXT:    vmv.v.v v9, v8
573; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
574; VLA-NEXT:    vmsne.vi v8, v9, 0
575; VLA-NEXT:    vsm.v v8, (a1)
576; VLA-NEXT:    ret
577;
578; VLS-LABEL: extract_v2i1_v64i1_2:
579; VLS:       # %bb.0:
580; VLS-NEXT:    vsetvli a2, zero, e8, m4, ta, ma
581; VLS-NEXT:    vlm.v v0, (a0)
582; VLS-NEXT:    vmv.v.i v8, 0
583; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
584; VLS-NEXT:    vsetivli zero, 2, e8, m1, ta, ma
585; VLS-NEXT:    vslidedown.vi v8, v8, 2
586; VLS-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
587; VLS-NEXT:    vmsne.vi v0, v8, 0
588; VLS-NEXT:    vmv.v.i v8, 0
589; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
590; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
591; VLS-NEXT:    vmv.v.i v9, 0
592; VLS-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
593; VLS-NEXT:    vmv.v.v v9, v8
594; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
595; VLS-NEXT:    vmsne.vi v8, v9, 0
596; VLS-NEXT:    vsm.v v8, (a1)
597; VLS-NEXT:    ret
598  %a = load <64 x i1>, ptr %x
599  %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
600  store <2 x i1> %c, ptr %y
601  ret void
602}
603
604define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
605; VLA-LABEL: extract_v2i1_v64i1_42:
606; VLA:       # %bb.0:
607; VLA-NEXT:    li a2, 64
608; VLA-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
609; VLA-NEXT:    vlm.v v0, (a0)
610; VLA-NEXT:    li a0, 42
611; VLA-NEXT:    vmv.v.i v8, 0
612; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
613; VLA-NEXT:    vsetivli zero, 2, e8, m4, ta, ma
614; VLA-NEXT:    vslidedown.vx v8, v8, a0
615; VLA-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
616; VLA-NEXT:    vmsne.vi v0, v8, 0
617; VLA-NEXT:    vmv.v.i v8, 0
618; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
619; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
620; VLA-NEXT:    vmv.v.i v9, 0
621; VLA-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
622; VLA-NEXT:    vmv.v.v v9, v8
623; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
624; VLA-NEXT:    vmsne.vi v8, v9, 0
625; VLA-NEXT:    vsm.v v8, (a1)
626; VLA-NEXT:    ret
627;
628; VLS-LABEL: extract_v2i1_v64i1_42:
629; VLS:       # %bb.0:
630; VLS-NEXT:    vsetvli a2, zero, e8, m4, ta, ma
631; VLS-NEXT:    vlm.v v0, (a0)
632; VLS-NEXT:    vmv.v.i v8, 0
633; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
634; VLS-NEXT:    vsetivli zero, 2, e8, m1, ta, ma
635; VLS-NEXT:    vslidedown.vi v8, v10, 10
636; VLS-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
637; VLS-NEXT:    vmsne.vi v0, v8, 0
638; VLS-NEXT:    vmv.v.i v8, 0
639; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
640; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
641; VLS-NEXT:    vmv.v.i v9, 0
642; VLS-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
643; VLS-NEXT:    vmv.v.v v9, v8
644; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
645; VLS-NEXT:    vmsne.vi v8, v9, 0
646; VLS-NEXT:    vsm.v v8, (a1)
647; VLS-NEXT:    ret
648  %a = load <64 x i1>, ptr %x
649  %c = call <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
650  store <2 x i1> %c, ptr %y
651  ret void
652}
653
654define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, ptr %y) {
655; CHECK-LABEL: extract_v2i1_nxv2i1_0:
656; CHECK:       # %bb.0:
657; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
658; CHECK-NEXT:    vmv.v.i v8, 0
659; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
660; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
661; CHECK-NEXT:    vmv.v.i v9, 0
662; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
663; CHECK-NEXT:    vmv.v.v v9, v8
664; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
665; CHECK-NEXT:    vmsne.vi v8, v9, 0
666; CHECK-NEXT:    vsm.v v8, (a0)
667; CHECK-NEXT:    ret
668  %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
669  store <2 x i1> %c, ptr %y
670  ret void
671}
672
673define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, ptr %y) {
674; VLA-LABEL: extract_v2i1_nxv2i1_2:
675; VLA:       # %bb.0:
676; VLA-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
677; VLA-NEXT:    vmv.v.i v8, 0
678; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
679; VLA-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
680; VLA-NEXT:    vslidedown.vi v8, v8, 2
681; VLA-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
682; VLA-NEXT:    vmsne.vi v0, v8, 0
683; VLA-NEXT:    vmv.v.i v8, 0
684; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
685; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
686; VLA-NEXT:    vmv.v.i v9, 0
687; VLA-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
688; VLA-NEXT:    vmv.v.v v9, v8
689; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
690; VLA-NEXT:    vmsne.vi v8, v9, 0
691; VLA-NEXT:    vsm.v v8, (a0)
692; VLA-NEXT:    ret
693;
694; VLS-LABEL: extract_v2i1_nxv2i1_2:
695; VLS:       # %bb.0:
696; VLS-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
697; VLS-NEXT:    vmv.v.i v8, 0
698; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
699; VLS-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
700; VLS-NEXT:    vslidedown.vi v8, v8, 2
701; VLS-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
702; VLS-NEXT:    vmsne.vi v0, v8, 0
703; VLS-NEXT:    vmv.v.i v8, 0
704; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
705; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
706; VLS-NEXT:    vmv.v.i v9, 0
707; VLS-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
708; VLS-NEXT:    vmv.v.v v9, v8
709; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
710; VLS-NEXT:    vmsne.vi v8, v9, 0
711; VLS-NEXT:    vsm.v v8, (a0)
712; VLS-NEXT:    ret
713  %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
714  store <2 x i1> %c, ptr %y
715  ret void
716}
717
718define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, ptr %y) {
719; CHECK-LABEL: extract_v2i1_nxv64i1_0:
720; CHECK:       # %bb.0:
721; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
722; CHECK-NEXT:    vmv.v.i v8, 0
723; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
724; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
725; CHECK-NEXT:    vmv.v.i v9, 0
726; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
727; CHECK-NEXT:    vmv.v.v v9, v8
728; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
729; CHECK-NEXT:    vmsne.vi v8, v9, 0
730; CHECK-NEXT:    vsm.v v8, (a0)
731; CHECK-NEXT:    ret
732  %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
733  store <2 x i1> %c, ptr %y
734  ret void
735}
736
737define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, ptr %y) {
738; CHECK-LABEL: extract_v2i1_nxv64i1_2:
739; CHECK:       # %bb.0:
740; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
741; CHECK-NEXT:    vmv.v.i v8, 0
742; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
743; CHECK-NEXT:    vsetivli zero, 2, e8, m1, ta, ma
744; CHECK-NEXT:    vslidedown.vi v8, v8, 2
745; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
746; CHECK-NEXT:    vmsne.vi v0, v8, 0
747; CHECK-NEXT:    vmv.v.i v8, 0
748; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
749; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
750; CHECK-NEXT:    vmv.v.i v9, 0
751; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
752; CHECK-NEXT:    vmv.v.v v9, v8
753; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
754; CHECK-NEXT:    vmsne.vi v8, v9, 0
755; CHECK-NEXT:    vsm.v v8, (a0)
756; CHECK-NEXT:    ret
757  %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
758  store <2 x i1> %c, ptr %y
759  ret void
760}
761
762define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, ptr %y) {
763; VLA-LABEL: extract_v2i1_nxv64i1_42:
764; VLA:       # %bb.0:
765; VLA-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
766; VLA-NEXT:    vmv.v.i v8, 0
767; VLA-NEXT:    li a1, 42
768; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
769; VLA-NEXT:    vsetivli zero, 2, e8, m4, ta, ma
770; VLA-NEXT:    vslidedown.vx v8, v8, a1
771; VLA-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
772; VLA-NEXT:    vmsne.vi v0, v8, 0
773; VLA-NEXT:    vmv.v.i v8, 0
774; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
775; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
776; VLA-NEXT:    vmv.v.i v9, 0
777; VLA-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
778; VLA-NEXT:    vmv.v.v v9, v8
779; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
780; VLA-NEXT:    vmsne.vi v8, v9, 0
781; VLA-NEXT:    vsm.v v8, (a0)
782; VLA-NEXT:    ret
783;
784; VLS-LABEL: extract_v2i1_nxv64i1_42:
785; VLS:       # %bb.0:
786; VLS-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
787; VLS-NEXT:    vmv.v.i v8, 0
788; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
789; VLS-NEXT:    vsetivli zero, 2, e8, m1, ta, ma
790; VLS-NEXT:    vslidedown.vi v8, v10, 10
791; VLS-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
792; VLS-NEXT:    vmsne.vi v0, v8, 0
793; VLS-NEXT:    vmv.v.i v8, 0
794; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
795; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
796; VLS-NEXT:    vmv.v.i v9, 0
797; VLS-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
798; VLS-NEXT:    vmv.v.v v9, v8
799; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
800; VLS-NEXT:    vmsne.vi v8, v9, 0
801; VLS-NEXT:    vsm.v v8, (a0)
802; VLS-NEXT:    ret
803  %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
804  store <2 x i1> %c, ptr %y
805  ret void
806}
807
808define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, ptr %y) {
809; VLA-LABEL: extract_v2i1_nxv32i1_26:
810; VLA:       # %bb.0:
811; VLA-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
812; VLA-NEXT:    vmv.v.i v8, 0
813; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
814; VLA-NEXT:    vsetivli zero, 2, e8, m2, ta, ma
815; VLA-NEXT:    vslidedown.vi v8, v8, 26
816; VLA-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
817; VLA-NEXT:    vmsne.vi v0, v8, 0
818; VLA-NEXT:    vmv.v.i v8, 0
819; VLA-NEXT:    vmerge.vim v8, v8, 1, v0
820; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
821; VLA-NEXT:    vmv.v.i v9, 0
822; VLA-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
823; VLA-NEXT:    vmv.v.v v9, v8
824; VLA-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
825; VLA-NEXT:    vmsne.vi v8, v9, 0
826; VLA-NEXT:    vsm.v v8, (a0)
827; VLA-NEXT:    ret
828;
829; VLS-LABEL: extract_v2i1_nxv32i1_26:
830; VLS:       # %bb.0:
831; VLS-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
832; VLS-NEXT:    vmv.v.i v8, 0
833; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
834; VLS-NEXT:    vsetivli zero, 2, e8, m1, ta, ma
835; VLS-NEXT:    vslidedown.vi v8, v9, 10
836; VLS-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
837; VLS-NEXT:    vmsne.vi v0, v8, 0
838; VLS-NEXT:    vmv.v.i v8, 0
839; VLS-NEXT:    vmerge.vim v8, v8, 1, v0
840; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
841; VLS-NEXT:    vmv.v.i v9, 0
842; VLS-NEXT:    vsetivli zero, 2, e8, mf2, tu, ma
843; VLS-NEXT:    vmv.v.v v9, v8
844; VLS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
845; VLS-NEXT:    vmsne.vi v8, v9, 0
846; VLS-NEXT:    vsm.v v8, (a0)
847; VLS-NEXT:    ret
848  %c = call <2 x i1> @llvm.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
849  store <2 x i1> %c, ptr %y
850  ret void
851}
852
853define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, ptr %y) {
854; CHECK-LABEL: extract_v8i1_nxv32i1_16:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
857; CHECK-NEXT:    vslidedown.vi v8, v0, 2
858; CHECK-NEXT:    vsm.v v8, (a0)
859; CHECK-NEXT:    ret
860  %c = call <8 x i1> @llvm.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)
861  store <8 x i1> %c, ptr %y
862  ret void
863}
864
865define <1 x i64> @extract_v1i64_v2i64_1(<2 x i64> %x) {
866; CHECK-LABEL: extract_v1i64_v2i64_1:
867; CHECK:       # %bb.0:
868; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
869; CHECK-NEXT:    vslidedown.vi v8, v8, 1
870; CHECK-NEXT:    ret
871  %v = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %x, i64 1)
872  ret <1 x i64> %v
873}
874
875define void @extract_v2bf16_v4bf16_0(ptr %x, ptr %y) {
876; CHECK-LABEL: extract_v2bf16_v4bf16_0:
877; CHECK:       # %bb.0:
878; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
879; CHECK-NEXT:    vle16.v v8, (a0)
880; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
881; CHECK-NEXT:    vse16.v v8, (a1)
882; CHECK-NEXT:    ret
883  %a = load <4 x bfloat>, ptr %x
884  %c = call <2 x bfloat> @llvm.vector.extract.v2bf16.v4bf16(<4 x bfloat> %a, i64 0)
885  store <2 x bfloat> %c, ptr %y
886  ret void
887}
888
889define void @extract_v2bf16_v4bf16_2(ptr %x, ptr %y) {
890; CHECK-LABEL: extract_v2bf16_v4bf16_2:
891; CHECK:       # %bb.0:
892; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
893; CHECK-NEXT:    vle16.v v8, (a0)
894; CHECK-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma
895; CHECK-NEXT:    vslidedown.vi v8, v8, 2
896; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
897; CHECK-NEXT:    vse16.v v8, (a1)
898; CHECK-NEXT:    ret
899  %a = load <4 x bfloat>, ptr %x
900  %c = call <2 x bfloat> @llvm.vector.extract.v2bf16.v4bf16(<4 x bfloat> %a, i64 2)
901  store <2 x bfloat> %c, ptr %y
902  ret void
903}
904
905define void @extract_v2f16_v4f16_0(ptr %x, ptr %y) {
906; CHECK-LABEL: extract_v2f16_v4f16_0:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
909; CHECK-NEXT:    vle16.v v8, (a0)
910; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
911; CHECK-NEXT:    vse16.v v8, (a1)
912; CHECK-NEXT:    ret
913  %a = load <4 x half>, ptr %x
914  %c = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %a, i64 0)
915  store <2 x half> %c, ptr %y
916  ret void
917}
918
919define void @extract_v2f16_v4f16_2(ptr %x, ptr %y) {
920; CHECK-LABEL: extract_v2f16_v4f16_2:
921; CHECK:       # %bb.0:
922; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
923; CHECK-NEXT:    vle16.v v8, (a0)
924; CHECK-NEXT:    vsetivli zero, 2, e16, mf2, ta, ma
925; CHECK-NEXT:    vslidedown.vi v8, v8, 2
926; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
927; CHECK-NEXT:    vse16.v v8, (a1)
928; CHECK-NEXT:    ret
929  %a = load <4 x half>, ptr %x
930  %c = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %a, i64 2)
931  store <2 x half> %c, ptr %y
932  ret void
933}
934
935declare <2 x i1> @llvm.vector.extract.v2i1.v64i1(<64 x i1> %vec, i64 %idx)
936declare <8 x i1> @llvm.vector.extract.v8i1.v64i1(<64 x i1> %vec, i64 %idx)
937
938declare <2 x i1> @llvm.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %vec, i64 %idx)
939declare <8 x i1> @llvm.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %vec, i64 %idx)
940
941declare <2 x i1> @llvm.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %vec, i64 %idx)
942declare <8 x i1> @llvm.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %vec, i64 %idx)
943
944declare <2 x i1> @llvm.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %vec, i64 %idx)
945declare <8 x i1> @llvm.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %vec, i64 %idx)
946
947declare <2 x i8> @llvm.vector.extract.v2i8.v4i8(<4 x i8> %vec, i64 %idx)
948declare <2 x i8> @llvm.vector.extract.v2i8.v8i8(<8 x i8> %vec, i64 %idx)
949
950declare <1 x i32> @llvm.vector.extract.v1i32.v8i32(<8 x i32> %vec, i64 %idx)
951declare <2 x i32> @llvm.vector.extract.v2i32.v8i32(<8 x i32> %vec, i64 %idx)
952
953declare <2 x i8> @llvm.vector.extract.v2i8.nxv2i8(<vscale x 2 x i8> %vec, i64 %idx)
954
955declare <2 x i32> @llvm.vector.extract.v2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
956declare <8 x i32> @llvm.vector.extract.v8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
957