xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32ZBS
6; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zbs -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64ZBS
7
8define i1 @extractelt_v1i1(ptr %x, i64 %idx) nounwind {
9; CHECK-LABEL: extractelt_v1i1:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
12; CHECK-NEXT:    vle8.v v8, (a0)
13; CHECK-NEXT:    vmseq.vi v0, v8, 0
14; CHECK-NEXT:    vmv.s.x v8, zero
15; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
16; CHECK-NEXT:    vslidedown.vx v8, v8, a1
17; CHECK-NEXT:    vmv.x.s a0, v8
18; CHECK-NEXT:    ret
19  %a = load <1 x i8>, ptr %x
20  %b = icmp eq <1 x i8> %a, zeroinitializer
21  %c = extractelement <1 x i1> %b, i64 %idx
22  ret i1 %c
23}
24
25define i1 @extractelt_v2i1(ptr %x, i64 %idx) nounwind {
26; CHECK-LABEL: extractelt_v2i1:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
29; CHECK-NEXT:    vle8.v v8, (a0)
30; CHECK-NEXT:    vmseq.vi v0, v8, 0
31; CHECK-NEXT:    vmv.v.i v8, 0
32; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
33; CHECK-NEXT:    vslidedown.vx v8, v8, a1
34; CHECK-NEXT:    vmv.x.s a0, v8
35; CHECK-NEXT:    ret
36  %a = load <2 x i8>, ptr %x
37  %b = icmp eq <2 x i8> %a, zeroinitializer
38  %c = extractelement <2 x i1> %b, i64 %idx
39  ret i1 %c
40}
41
42define i1 @extractelt_v4i1(ptr %x, i64 %idx) nounwind {
43; CHECK-LABEL: extractelt_v4i1:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
46; CHECK-NEXT:    vle8.v v8, (a0)
47; CHECK-NEXT:    vmseq.vi v0, v8, 0
48; CHECK-NEXT:    vmv.v.i v8, 0
49; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
50; CHECK-NEXT:    vslidedown.vx v8, v8, a1
51; CHECK-NEXT:    vmv.x.s a0, v8
52; CHECK-NEXT:    ret
53  %a = load <4 x i8>, ptr %x
54  %b = icmp eq <4 x i8> %a, zeroinitializer
55  %c = extractelement <4 x i1> %b, i64 %idx
56  ret i1 %c
57}
58
59define i1 @extractelt_v8i1(ptr %x, i64 %idx) nounwind {
60; RV32-LABEL: extractelt_v8i1:
61; RV32:       # %bb.0:
62; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
63; RV32-NEXT:    vle8.v v8, (a0)
64; RV32-NEXT:    vmseq.vi v8, v8, 0
65; RV32-NEXT:    vmv.x.s a0, v8
66; RV32-NEXT:    srl a0, a0, a1
67; RV32-NEXT:    andi a0, a0, 1
68; RV32-NEXT:    ret
69;
70; RV64-LABEL: extractelt_v8i1:
71; RV64:       # %bb.0:
72; RV64-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
73; RV64-NEXT:    vle8.v v8, (a0)
74; RV64-NEXT:    vmseq.vi v8, v8, 0
75; RV64-NEXT:    vmv.x.s a0, v8
76; RV64-NEXT:    srl a0, a0, a1
77; RV64-NEXT:    andi a0, a0, 1
78; RV64-NEXT:    ret
79;
80; RV32ZBS-LABEL: extractelt_v8i1:
81; RV32ZBS:       # %bb.0:
82; RV32ZBS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
83; RV32ZBS-NEXT:    vle8.v v8, (a0)
84; RV32ZBS-NEXT:    vmseq.vi v8, v8, 0
85; RV32ZBS-NEXT:    vmv.x.s a0, v8
86; RV32ZBS-NEXT:    bext a0, a0, a1
87; RV32ZBS-NEXT:    ret
88;
89; RV64ZBS-LABEL: extractelt_v8i1:
90; RV64ZBS:       # %bb.0:
91; RV64ZBS-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
92; RV64ZBS-NEXT:    vle8.v v8, (a0)
93; RV64ZBS-NEXT:    vmseq.vi v8, v8, 0
94; RV64ZBS-NEXT:    vmv.x.s a0, v8
95; RV64ZBS-NEXT:    bext a0, a0, a1
96; RV64ZBS-NEXT:    ret
97  %a = load <8 x i8>, ptr %x
98  %b = icmp eq <8 x i8> %a, zeroinitializer
99  %c = extractelement <8 x i1> %b, i64 %idx
100  ret i1 %c
101}
102
103define i1 @extractelt_v16i1(ptr %x, i64 %idx) nounwind {
104; RV32-LABEL: extractelt_v16i1:
105; RV32:       # %bb.0:
106; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
107; RV32-NEXT:    vle8.v v8, (a0)
108; RV32-NEXT:    vmseq.vi v8, v8, 0
109; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
110; RV32-NEXT:    vmv.x.s a0, v8
111; RV32-NEXT:    srl a0, a0, a1
112; RV32-NEXT:    andi a0, a0, 1
113; RV32-NEXT:    ret
114;
115; RV64-LABEL: extractelt_v16i1:
116; RV64:       # %bb.0:
117; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
118; RV64-NEXT:    vle8.v v8, (a0)
119; RV64-NEXT:    vmseq.vi v8, v8, 0
120; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
121; RV64-NEXT:    vmv.x.s a0, v8
122; RV64-NEXT:    srl a0, a0, a1
123; RV64-NEXT:    andi a0, a0, 1
124; RV64-NEXT:    ret
125;
126; RV32ZBS-LABEL: extractelt_v16i1:
127; RV32ZBS:       # %bb.0:
128; RV32ZBS-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
129; RV32ZBS-NEXT:    vle8.v v8, (a0)
130; RV32ZBS-NEXT:    vmseq.vi v8, v8, 0
131; RV32ZBS-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
132; RV32ZBS-NEXT:    vmv.x.s a0, v8
133; RV32ZBS-NEXT:    bext a0, a0, a1
134; RV32ZBS-NEXT:    ret
135;
136; RV64ZBS-LABEL: extractelt_v16i1:
137; RV64ZBS:       # %bb.0:
138; RV64ZBS-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
139; RV64ZBS-NEXT:    vle8.v v8, (a0)
140; RV64ZBS-NEXT:    vmseq.vi v8, v8, 0
141; RV64ZBS-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
142; RV64ZBS-NEXT:    vmv.x.s a0, v8
143; RV64ZBS-NEXT:    bext a0, a0, a1
144; RV64ZBS-NEXT:    ret
145  %a = load <16 x i8>, ptr %x
146  %b = icmp eq <16 x i8> %a, zeroinitializer
147  %c = extractelement <16 x i1> %b, i64 %idx
148  ret i1 %c
149}
150
151define i1 @extractelt_v32i1(ptr %x, i64 %idx) nounwind {
152; RV32-LABEL: extractelt_v32i1:
153; RV32:       # %bb.0:
154; RV32-NEXT:    li a2, 32
155; RV32-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
156; RV32-NEXT:    vle8.v v8, (a0)
157; RV32-NEXT:    vmseq.vi v10, v8, 0
158; RV32-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
159; RV32-NEXT:    vmv.x.s a0, v10
160; RV32-NEXT:    srl a0, a0, a1
161; RV32-NEXT:    andi a0, a0, 1
162; RV32-NEXT:    ret
163;
164; RV64-LABEL: extractelt_v32i1:
165; RV64:       # %bb.0:
166; RV64-NEXT:    li a2, 32
167; RV64-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
168; RV64-NEXT:    vle8.v v8, (a0)
169; RV64-NEXT:    vmseq.vi v10, v8, 0
170; RV64-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
171; RV64-NEXT:    vmv.x.s a0, v10
172; RV64-NEXT:    srl a0, a0, a1
173; RV64-NEXT:    andi a0, a0, 1
174; RV64-NEXT:    ret
175;
176; RV32ZBS-LABEL: extractelt_v32i1:
177; RV32ZBS:       # %bb.0:
178; RV32ZBS-NEXT:    li a2, 32
179; RV32ZBS-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
180; RV32ZBS-NEXT:    vle8.v v8, (a0)
181; RV32ZBS-NEXT:    vmseq.vi v10, v8, 0
182; RV32ZBS-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
183; RV32ZBS-NEXT:    vmv.x.s a0, v10
184; RV32ZBS-NEXT:    bext a0, a0, a1
185; RV32ZBS-NEXT:    ret
186;
187; RV64ZBS-LABEL: extractelt_v32i1:
188; RV64ZBS:       # %bb.0:
189; RV64ZBS-NEXT:    li a2, 32
190; RV64ZBS-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
191; RV64ZBS-NEXT:    vle8.v v8, (a0)
192; RV64ZBS-NEXT:    vmseq.vi v10, v8, 0
193; RV64ZBS-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
194; RV64ZBS-NEXT:    vmv.x.s a0, v10
195; RV64ZBS-NEXT:    bext a0, a0, a1
196; RV64ZBS-NEXT:    ret
197  %a = load <32 x i8>, ptr %x
198  %b = icmp eq <32 x i8> %a, zeroinitializer
199  %c = extractelement <32 x i1> %b, i64 %idx
200  ret i1 %c
201}
202
203define i1 @extractelt_v64i1(ptr %x, i64 %idx) nounwind {
204; RV32-LABEL: extractelt_v64i1:
205; RV32:       # %bb.0:
206; RV32-NEXT:    li a2, 64
207; RV32-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
208; RV32-NEXT:    vle8.v v8, (a0)
209; RV32-NEXT:    vmseq.vi v12, v8, 0
210; RV32-NEXT:    srli a0, a1, 5
211; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
212; RV32-NEXT:    vslidedown.vx v8, v12, a0
213; RV32-NEXT:    vmv.x.s a0, v8
214; RV32-NEXT:    srl a0, a0, a1
215; RV32-NEXT:    andi a0, a0, 1
216; RV32-NEXT:    ret
217;
218; RV64-LABEL: extractelt_v64i1:
219; RV64:       # %bb.0:
220; RV64-NEXT:    li a2, 64
221; RV64-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
222; RV64-NEXT:    vle8.v v8, (a0)
223; RV64-NEXT:    vmseq.vi v12, v8, 0
224; RV64-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
225; RV64-NEXT:    vmv.x.s a0, v12
226; RV64-NEXT:    srl a0, a0, a1
227; RV64-NEXT:    andi a0, a0, 1
228; RV64-NEXT:    ret
229;
230; RV32ZBS-LABEL: extractelt_v64i1:
231; RV32ZBS:       # %bb.0:
232; RV32ZBS-NEXT:    li a2, 64
233; RV32ZBS-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
234; RV32ZBS-NEXT:    vle8.v v8, (a0)
235; RV32ZBS-NEXT:    vmseq.vi v12, v8, 0
236; RV32ZBS-NEXT:    srli a0, a1, 5
237; RV32ZBS-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
238; RV32ZBS-NEXT:    vslidedown.vx v8, v12, a0
239; RV32ZBS-NEXT:    vmv.x.s a0, v8
240; RV32ZBS-NEXT:    bext a0, a0, a1
241; RV32ZBS-NEXT:    ret
242;
243; RV64ZBS-LABEL: extractelt_v64i1:
244; RV64ZBS:       # %bb.0:
245; RV64ZBS-NEXT:    li a2, 64
246; RV64ZBS-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
247; RV64ZBS-NEXT:    vle8.v v8, (a0)
248; RV64ZBS-NEXT:    vmseq.vi v12, v8, 0
249; RV64ZBS-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
250; RV64ZBS-NEXT:    vmv.x.s a0, v12
251; RV64ZBS-NEXT:    bext a0, a0, a1
252; RV64ZBS-NEXT:    ret
253  %a = load <64 x i8>, ptr %x
254  %b = icmp eq <64 x i8> %a, zeroinitializer
255  %c = extractelement <64 x i1> %b, i64 %idx
256  ret i1 %c
257}
258
259define i1 @extractelt_v128i1(ptr %x, i64 %idx) nounwind {
260; RV32-LABEL: extractelt_v128i1:
261; RV32:       # %bb.0:
262; RV32-NEXT:    li a2, 128
263; RV32-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
264; RV32-NEXT:    vle8.v v8, (a0)
265; RV32-NEXT:    vmseq.vi v16, v8, 0
266; RV32-NEXT:    srli a0, a1, 5
267; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
268; RV32-NEXT:    vslidedown.vx v8, v16, a0
269; RV32-NEXT:    vmv.x.s a0, v8
270; RV32-NEXT:    srl a0, a0, a1
271; RV32-NEXT:    andi a0, a0, 1
272; RV32-NEXT:    ret
273;
274; RV64-LABEL: extractelt_v128i1:
275; RV64:       # %bb.0:
276; RV64-NEXT:    li a2, 128
277; RV64-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
278; RV64-NEXT:    vle8.v v8, (a0)
279; RV64-NEXT:    vmseq.vi v16, v8, 0
280; RV64-NEXT:    srli a0, a1, 6
281; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
282; RV64-NEXT:    vslidedown.vx v8, v16, a0
283; RV64-NEXT:    vmv.x.s a0, v8
284; RV64-NEXT:    srl a0, a0, a1
285; RV64-NEXT:    andi a0, a0, 1
286; RV64-NEXT:    ret
287;
288; RV32ZBS-LABEL: extractelt_v128i1:
289; RV32ZBS:       # %bb.0:
290; RV32ZBS-NEXT:    li a2, 128
291; RV32ZBS-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
292; RV32ZBS-NEXT:    vle8.v v8, (a0)
293; RV32ZBS-NEXT:    vmseq.vi v16, v8, 0
294; RV32ZBS-NEXT:    srli a0, a1, 5
295; RV32ZBS-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
296; RV32ZBS-NEXT:    vslidedown.vx v8, v16, a0
297; RV32ZBS-NEXT:    vmv.x.s a0, v8
298; RV32ZBS-NEXT:    bext a0, a0, a1
299; RV32ZBS-NEXT:    ret
300;
301; RV64ZBS-LABEL: extractelt_v128i1:
302; RV64ZBS:       # %bb.0:
303; RV64ZBS-NEXT:    li a2, 128
304; RV64ZBS-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
305; RV64ZBS-NEXT:    vle8.v v8, (a0)
306; RV64ZBS-NEXT:    vmseq.vi v16, v8, 0
307; RV64ZBS-NEXT:    srli a0, a1, 6
308; RV64ZBS-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
309; RV64ZBS-NEXT:    vslidedown.vx v8, v16, a0
310; RV64ZBS-NEXT:    vmv.x.s a0, v8
311; RV64ZBS-NEXT:    bext a0, a0, a1
312; RV64ZBS-NEXT:    ret
313  %a = load <128 x i8>, ptr %x
314  %b = icmp eq <128 x i8> %a, zeroinitializer
315  %c = extractelement <128 x i1> %b, i64 %idx
316  ret i1 %c
317}
318
319define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
320; RV32-LABEL: extractelt_v256i1:
321; RV32:       # %bb.0:
322; RV32-NEXT:    addi sp, sp, -384
323; RV32-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
324; RV32-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
325; RV32-NEXT:    addi s0, sp, 384
326; RV32-NEXT:    andi sp, sp, -128
327; RV32-NEXT:    andi a1, a1, 255
328; RV32-NEXT:    mv a2, sp
329; RV32-NEXT:    li a3, 128
330; RV32-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
331; RV32-NEXT:    vle8.v v8, (a0)
332; RV32-NEXT:    addi a0, a0, 128
333; RV32-NEXT:    vle8.v v16, (a0)
334; RV32-NEXT:    add a1, a2, a1
335; RV32-NEXT:    vmseq.vi v0, v8, 0
336; RV32-NEXT:    vmv.v.i v24, 0
337; RV32-NEXT:    vmseq.vi v8, v16, 0
338; RV32-NEXT:    vmerge.vim v16, v24, 1, v0
339; RV32-NEXT:    vse8.v v16, (a2)
340; RV32-NEXT:    vmv1r.v v0, v8
341; RV32-NEXT:    vmerge.vim v8, v24, 1, v0
342; RV32-NEXT:    addi a0, sp, 128
343; RV32-NEXT:    vse8.v v8, (a0)
344; RV32-NEXT:    lbu a0, 0(a1)
345; RV32-NEXT:    addi sp, s0, -384
346; RV32-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
347; RV32-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
348; RV32-NEXT:    addi sp, sp, 384
349; RV32-NEXT:    ret
350;
351; RV64-LABEL: extractelt_v256i1:
352; RV64:       # %bb.0:
353; RV64-NEXT:    addi sp, sp, -384
354; RV64-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
355; RV64-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
356; RV64-NEXT:    addi s0, sp, 384
357; RV64-NEXT:    andi sp, sp, -128
358; RV64-NEXT:    andi a1, a1, 255
359; RV64-NEXT:    mv a2, sp
360; RV64-NEXT:    li a3, 128
361; RV64-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
362; RV64-NEXT:    vle8.v v8, (a0)
363; RV64-NEXT:    addi a0, a0, 128
364; RV64-NEXT:    vle8.v v16, (a0)
365; RV64-NEXT:    add a1, a2, a1
366; RV64-NEXT:    vmseq.vi v0, v8, 0
367; RV64-NEXT:    vmv.v.i v24, 0
368; RV64-NEXT:    vmseq.vi v8, v16, 0
369; RV64-NEXT:    vmerge.vim v16, v24, 1, v0
370; RV64-NEXT:    vse8.v v16, (a2)
371; RV64-NEXT:    vmv1r.v v0, v8
372; RV64-NEXT:    vmerge.vim v8, v24, 1, v0
373; RV64-NEXT:    addi a0, sp, 128
374; RV64-NEXT:    vse8.v v8, (a0)
375; RV64-NEXT:    lbu a0, 0(a1)
376; RV64-NEXT:    addi sp, s0, -384
377; RV64-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
378; RV64-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
379; RV64-NEXT:    addi sp, sp, 384
380; RV64-NEXT:    ret
381;
382; RV32ZBS-LABEL: extractelt_v256i1:
383; RV32ZBS:       # %bb.0:
384; RV32ZBS-NEXT:    addi sp, sp, -384
385; RV32ZBS-NEXT:    sw ra, 380(sp) # 4-byte Folded Spill
386; RV32ZBS-NEXT:    sw s0, 376(sp) # 4-byte Folded Spill
387; RV32ZBS-NEXT:    addi s0, sp, 384
388; RV32ZBS-NEXT:    andi sp, sp, -128
389; RV32ZBS-NEXT:    andi a1, a1, 255
390; RV32ZBS-NEXT:    mv a2, sp
391; RV32ZBS-NEXT:    li a3, 128
392; RV32ZBS-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
393; RV32ZBS-NEXT:    vle8.v v8, (a0)
394; RV32ZBS-NEXT:    addi a0, a0, 128
395; RV32ZBS-NEXT:    vle8.v v16, (a0)
396; RV32ZBS-NEXT:    add a1, a2, a1
397; RV32ZBS-NEXT:    vmseq.vi v0, v8, 0
398; RV32ZBS-NEXT:    vmv.v.i v24, 0
399; RV32ZBS-NEXT:    vmseq.vi v8, v16, 0
400; RV32ZBS-NEXT:    vmerge.vim v16, v24, 1, v0
401; RV32ZBS-NEXT:    vse8.v v16, (a2)
402; RV32ZBS-NEXT:    vmv1r.v v0, v8
403; RV32ZBS-NEXT:    vmerge.vim v8, v24, 1, v0
404; RV32ZBS-NEXT:    addi a0, sp, 128
405; RV32ZBS-NEXT:    vse8.v v8, (a0)
406; RV32ZBS-NEXT:    lbu a0, 0(a1)
407; RV32ZBS-NEXT:    addi sp, s0, -384
408; RV32ZBS-NEXT:    lw ra, 380(sp) # 4-byte Folded Reload
409; RV32ZBS-NEXT:    lw s0, 376(sp) # 4-byte Folded Reload
410; RV32ZBS-NEXT:    addi sp, sp, 384
411; RV32ZBS-NEXT:    ret
412;
413; RV64ZBS-LABEL: extractelt_v256i1:
414; RV64ZBS:       # %bb.0:
415; RV64ZBS-NEXT:    addi sp, sp, -384
416; RV64ZBS-NEXT:    sd ra, 376(sp) # 8-byte Folded Spill
417; RV64ZBS-NEXT:    sd s0, 368(sp) # 8-byte Folded Spill
418; RV64ZBS-NEXT:    addi s0, sp, 384
419; RV64ZBS-NEXT:    andi sp, sp, -128
420; RV64ZBS-NEXT:    andi a1, a1, 255
421; RV64ZBS-NEXT:    mv a2, sp
422; RV64ZBS-NEXT:    li a3, 128
423; RV64ZBS-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
424; RV64ZBS-NEXT:    vle8.v v8, (a0)
425; RV64ZBS-NEXT:    addi a0, a0, 128
426; RV64ZBS-NEXT:    vle8.v v16, (a0)
427; RV64ZBS-NEXT:    add a1, a2, a1
428; RV64ZBS-NEXT:    vmseq.vi v0, v8, 0
429; RV64ZBS-NEXT:    vmv.v.i v24, 0
430; RV64ZBS-NEXT:    vmseq.vi v8, v16, 0
431; RV64ZBS-NEXT:    vmerge.vim v16, v24, 1, v0
432; RV64ZBS-NEXT:    vse8.v v16, (a2)
433; RV64ZBS-NEXT:    vmv1r.v v0, v8
434; RV64ZBS-NEXT:    vmerge.vim v8, v24, 1, v0
435; RV64ZBS-NEXT:    addi a0, sp, 128
436; RV64ZBS-NEXT:    vse8.v v8, (a0)
437; RV64ZBS-NEXT:    lbu a0, 0(a1)
438; RV64ZBS-NEXT:    addi sp, s0, -384
439; RV64ZBS-NEXT:    ld ra, 376(sp) # 8-byte Folded Reload
440; RV64ZBS-NEXT:    ld s0, 368(sp) # 8-byte Folded Reload
441; RV64ZBS-NEXT:    addi sp, sp, 384
442; RV64ZBS-NEXT:    ret
443  %a = load <256 x i8>, ptr %x
444  %b = icmp eq <256 x i8> %a, zeroinitializer
445  %c = extractelement <256 x i1> %b, i64 %idx
446  ret i1 %c
447}
448
449define i1 @extractelt_v1i1_idx0(ptr %x) nounwind {
450; CHECK-LABEL: extractelt_v1i1_idx0:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
453; CHECK-NEXT:    vle8.v v8, (a0)
454; CHECK-NEXT:    vmseq.vi v8, v8, 0
455; CHECK-NEXT:    vfirst.m a0, v8
456; CHECK-NEXT:    seqz a0, a0
457; CHECK-NEXT:    ret
458  %a = load <1 x i8>, ptr %x
459  %b = icmp eq <1 x i8> %a, zeroinitializer
460  %c = extractelement <1 x i1> %b, i64 0
461  ret i1 %c
462}
463
464define i1 @extractelt_v2i1_idx0(ptr %x) nounwind {
465; CHECK-LABEL: extractelt_v2i1_idx0:
466; CHECK:       # %bb.0:
467; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
468; CHECK-NEXT:    vle8.v v8, (a0)
469; CHECK-NEXT:    vmseq.vi v8, v8, 0
470; CHECK-NEXT:    vfirst.m a0, v8
471; CHECK-NEXT:    seqz a0, a0
472; CHECK-NEXT:    ret
473  %a = load <2 x i8>, ptr %x
474  %b = icmp eq <2 x i8> %a, zeroinitializer
475  %c = extractelement <2 x i1> %b, i64 0
476  ret i1 %c
477}
478
479define i1 @extractelt_v4i1_idx0(ptr %x) nounwind {
480; CHECK-LABEL: extractelt_v4i1_idx0:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
483; CHECK-NEXT:    vle8.v v8, (a0)
484; CHECK-NEXT:    vmseq.vi v8, v8, 0
485; CHECK-NEXT:    vfirst.m a0, v8
486; CHECK-NEXT:    seqz a0, a0
487; CHECK-NEXT:    ret
488  %a = load <4 x i8>, ptr %x
489  %b = icmp eq <4 x i8> %a, zeroinitializer
490  %c = extractelement <4 x i1> %b, i64 0
491  ret i1 %c
492}
493
494define i1 @extractelt_v8i1_idx0(ptr %x) nounwind {
495; CHECK-LABEL: extractelt_v8i1_idx0:
496; CHECK:       # %bb.0:
497; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
498; CHECK-NEXT:    vle8.v v8, (a0)
499; CHECK-NEXT:    vmseq.vi v8, v8, 0
500; CHECK-NEXT:    vfirst.m a0, v8
501; CHECK-NEXT:    seqz a0, a0
502; CHECK-NEXT:    ret
503  %a = load <8 x i8>, ptr %x
504  %b = icmp eq <8 x i8> %a, zeroinitializer
505  %c = extractelement <8 x i1> %b, i64 0
506  ret i1 %c
507}
508
509define i1 @extractelt_v16i1_idx0(ptr %x) nounwind {
510; CHECK-LABEL: extractelt_v16i1_idx0:
511; CHECK:       # %bb.0:
512; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
513; CHECK-NEXT:    vle8.v v8, (a0)
514; CHECK-NEXT:    vmseq.vi v8, v8, 0
515; CHECK-NEXT:    vfirst.m a0, v8
516; CHECK-NEXT:    seqz a0, a0
517; CHECK-NEXT:    ret
518  %a = load <16 x i8>, ptr %x
519  %b = icmp eq <16 x i8> %a, zeroinitializer
520  %c = extractelement <16 x i1> %b, i64 0
521  ret i1 %c
522}
523
524define i1 @extractelt_v32i1_idx0(ptr %x) nounwind {
525; CHECK-LABEL: extractelt_v32i1_idx0:
526; CHECK:       # %bb.0:
527; CHECK-NEXT:    li a1, 32
528; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
529; CHECK-NEXT:    vle8.v v8, (a0)
530; CHECK-NEXT:    vmseq.vi v10, v8, 0
531; CHECK-NEXT:    vfirst.m a0, v10
532; CHECK-NEXT:    seqz a0, a0
533; CHECK-NEXT:    ret
534  %a = load <32 x i8>, ptr %x
535  %b = icmp eq <32 x i8> %a, zeroinitializer
536  %c = extractelement <32 x i1> %b, i64 0
537  ret i1 %c
538}
539
540define i1 @extractelt_v64i1_idx0(ptr %x) nounwind {
541; CHECK-LABEL: extractelt_v64i1_idx0:
542; CHECK:       # %bb.0:
543; CHECK-NEXT:    li a1, 64
544; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma
545; CHECK-NEXT:    vle8.v v8, (a0)
546; CHECK-NEXT:    vmseq.vi v12, v8, 0
547; CHECK-NEXT:    vfirst.m a0, v12
548; CHECK-NEXT:    seqz a0, a0
549; CHECK-NEXT:    ret
550  %a = load <64 x i8>, ptr %x
551  %b = icmp eq <64 x i8> %a, zeroinitializer
552  %c = extractelement <64 x i1> %b, i64 0
553  ret i1 %c
554}
555
556define i1 @extractelt_v128i1_idx0(ptr %x) nounwind {
557; CHECK-LABEL: extractelt_v128i1_idx0:
558; CHECK:       # %bb.0:
559; CHECK-NEXT:    li a1, 128
560; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
561; CHECK-NEXT:    vle8.v v8, (a0)
562; CHECK-NEXT:    vmseq.vi v16, v8, 0
563; CHECK-NEXT:    vfirst.m a0, v16
564; CHECK-NEXT:    seqz a0, a0
565; CHECK-NEXT:    ret
566  %a = load <128 x i8>, ptr %x
567  %b = icmp eq <128 x i8> %a, zeroinitializer
568  %c = extractelement <128 x i1> %b, i64 0
569  ret i1 %c
570}
571
572define i1 @extractelt_v256i1_idx0(ptr %x) nounwind {
573; CHECK-LABEL: extractelt_v256i1_idx0:
574; CHECK:       # %bb.0:
575; CHECK-NEXT:    li a1, 128
576; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
577; CHECK-NEXT:    vle8.v v8, (a0)
578; CHECK-NEXT:    vmseq.vi v16, v8, 0
579; CHECK-NEXT:    vfirst.m a0, v16
580; CHECK-NEXT:    seqz a0, a0
581; CHECK-NEXT:    ret
582  %a = load <256 x i8>, ptr %x
583  %b = icmp eq <256 x i8> %a, zeroinitializer
584  %c = extractelement <256 x i1> %b, i64 0
585  ret i1 %c
586}
587