xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll (revision 18f0f709345cc7e611c4f944832edb71284caacb) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs -mtriple=riscv32 -mattr=+m,+v %s -o - \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-RV32
4; RUN: llc -verify-machineinstrs -mtriple=riscv64 -mattr=+m,+v %s -o - \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,CHECK-RV64
6
7declare <1 x i8> @llvm.masked.expandload.v1i8(ptr, <1 x i1>, <1 x i8>)
8define <1 x i8> @expandload_v1i8(ptr %base, <1 x i8> %src0, <1 x i1> %mask) {
9; CHECK-LABEL: expandload_v1i8:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
12; CHECK-NEXT:    vcpop.m a1, v0
13; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
14; CHECK-NEXT:    vle8.v v9, (a0)
15; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
16; CHECK-NEXT:    viota.m v10, v0
17; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
18; CHECK-NEXT:    ret
19  %res = call <1 x i8> @llvm.masked.expandload.v1i8(ptr %base, <1 x i1> %mask, <1 x i8> %src0)
20  ret <1 x i8>%res
21}
22
23declare <2 x i8> @llvm.masked.expandload.v2i8(ptr, <2 x i1>, <2 x i8>)
24define <2 x i8> @expandload_v2i8(ptr %base, <2 x i8> %src0, <2 x i1> %mask) {
25; CHECK-LABEL: expandload_v2i8:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
28; CHECK-NEXT:    vcpop.m a1, v0
29; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
30; CHECK-NEXT:    vle8.v v9, (a0)
31; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, mu
32; CHECK-NEXT:    viota.m v10, v0
33; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
34; CHECK-NEXT:    ret
35  %res = call <2 x i8> @llvm.masked.expandload.v2i8(ptr %base, <2 x i1> %mask, <2 x i8> %src0)
36  ret <2 x i8>%res
37}
38
39declare <4 x i8> @llvm.masked.expandload.v4i8(ptr, <4 x i1>, <4 x i8>)
40define <4 x i8> @expandload_v4i8(ptr %base, <4 x i8> %src0, <4 x i1> %mask) {
41; CHECK-LABEL: expandload_v4i8:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
44; CHECK-NEXT:    vcpop.m a1, v0
45; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
46; CHECK-NEXT:    vle8.v v9, (a0)
47; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
48; CHECK-NEXT:    viota.m v10, v0
49; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
50; CHECK-NEXT:    ret
51  %res = call <4 x i8> @llvm.masked.expandload.v4i8(ptr %base, <4 x i1> %mask, <4 x i8> %src0)
52  ret <4 x i8>%res
53}
54
55declare <8 x i8> @llvm.masked.expandload.v8i8(ptr, <8 x i1>, <8 x i8>)
56define <8 x i8> @expandload_v8i8(ptr %base, <8 x i8> %src0, <8 x i1> %mask) {
57; CHECK-LABEL: expandload_v8i8:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
60; CHECK-NEXT:    vcpop.m a1, v0
61; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
62; CHECK-NEXT:    vle8.v v9, (a0)
63; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
64; CHECK-NEXT:    viota.m v10, v0
65; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
66; CHECK-NEXT:    ret
67  %res = call <8 x i8> @llvm.masked.expandload.v8i8(ptr %base, <8 x i1> %mask, <8 x i8> %src0)
68  ret <8 x i8>%res
69}
70
71declare <1 x i16> @llvm.masked.expandload.v1i16(ptr, <1 x i1>, <1 x i16>)
72define <1 x i16> @expandload_v1i16(ptr %base, <1 x i16> %src0, <1 x i1> %mask) {
73; CHECK-LABEL: expandload_v1i16:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
76; CHECK-NEXT:    vcpop.m a1, v0
77; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
78; CHECK-NEXT:    vle16.v v9, (a0)
79; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, mu
80; CHECK-NEXT:    viota.m v10, v0
81; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
82; CHECK-NEXT:    ret
83  %res = call <1 x i16> @llvm.masked.expandload.v1i16(ptr align 2 %base, <1 x i1> %mask, <1 x i16> %src0)
84  ret <1 x i16>%res
85}
86
87declare <2 x i16> @llvm.masked.expandload.v2i16(ptr, <2 x i1>, <2 x i16>)
88define <2 x i16> @expandload_v2i16(ptr %base, <2 x i16> %src0, <2 x i1> %mask) {
89; CHECK-LABEL: expandload_v2i16:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
92; CHECK-NEXT:    vcpop.m a1, v0
93; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
94; CHECK-NEXT:    vle16.v v9, (a0)
95; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, mu
96; CHECK-NEXT:    viota.m v10, v0
97; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
98; CHECK-NEXT:    ret
99  %res = call <2 x i16> @llvm.masked.expandload.v2i16(ptr align 2 %base, <2 x i1> %mask, <2 x i16> %src0)
100  ret <2 x i16>%res
101}
102
103declare <4 x i16> @llvm.masked.expandload.v4i16(ptr, <4 x i1>, <4 x i16>)
104define <4 x i16> @expandload_v4i16(ptr %base, <4 x i16> %src0, <4 x i1> %mask) {
105; CHECK-LABEL: expandload_v4i16:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
108; CHECK-NEXT:    vcpop.m a1, v0
109; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
110; CHECK-NEXT:    vle16.v v9, (a0)
111; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
112; CHECK-NEXT:    viota.m v10, v0
113; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
114; CHECK-NEXT:    ret
115  %res = call <4 x i16> @llvm.masked.expandload.v4i16(ptr align 2 %base, <4 x i1> %mask, <4 x i16> %src0)
116  ret <4 x i16>%res
117}
118
119declare <8 x i16> @llvm.masked.expandload.v8i16(ptr, <8 x i1>, <8 x i16>)
120define <8 x i16> @expandload_v8i16(ptr %base, <8 x i16> %src0, <8 x i1> %mask) {
121; CHECK-LABEL: expandload_v8i16:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
124; CHECK-NEXT:    vcpop.m a1, v0
125; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
126; CHECK-NEXT:    vle16.v v9, (a0)
127; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
128; CHECK-NEXT:    viota.m v10, v0
129; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
130; CHECK-NEXT:    ret
131  %res = call <8 x i16> @llvm.masked.expandload.v8i16(ptr align 2 %base, <8 x i1> %mask, <8 x i16> %src0)
132  ret <8 x i16>%res
133}
134
135declare <1 x i32> @llvm.masked.expandload.v1i32(ptr, <1 x i1>, <1 x i32>)
136define <1 x i32> @expandload_v1i32(ptr %base, <1 x i32> %src0, <1 x i1> %mask) {
137; CHECK-LABEL: expandload_v1i32:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
140; CHECK-NEXT:    vcpop.m a1, v0
141; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
142; CHECK-NEXT:    vle32.v v9, (a0)
143; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, mu
144; CHECK-NEXT:    viota.m v10, v0
145; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
146; CHECK-NEXT:    ret
147  %res = call <1 x i32> @llvm.masked.expandload.v1i32(ptr align 4 %base, <1 x i1> %mask, <1 x i32> %src0)
148  ret <1 x i32>%res
149}
150
151declare <2 x i32> @llvm.masked.expandload.v2i32(ptr, <2 x i1>, <2 x i32>)
152define <2 x i32> @expandload_v2i32(ptr %base, <2 x i32> %src0, <2 x i1> %mask) {
153; CHECK-LABEL: expandload_v2i32:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
156; CHECK-NEXT:    vcpop.m a1, v0
157; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
158; CHECK-NEXT:    vle32.v v9, (a0)
159; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
160; CHECK-NEXT:    viota.m v10, v0
161; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
162; CHECK-NEXT:    ret
163  %res = call <2 x i32> @llvm.masked.expandload.v2i32(ptr align 4 %base, <2 x i1> %mask, <2 x i32> %src0)
164  ret <2 x i32>%res
165}
166
167declare <4 x i32> @llvm.masked.expandload.v4i32(ptr, <4 x i1>, <4 x i32>)
168define <4 x i32> @expandload_v4i32(ptr %base, <4 x i32> %src0, <4 x i1> %mask) {
169; CHECK-LABEL: expandload_v4i32:
170; CHECK:       # %bb.0:
171; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
172; CHECK-NEXT:    vcpop.m a1, v0
173; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
174; CHECK-NEXT:    vle32.v v9, (a0)
175; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
176; CHECK-NEXT:    viota.m v10, v0
177; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
178; CHECK-NEXT:    ret
179  %res = call <4 x i32> @llvm.masked.expandload.v4i32(ptr align 4 %base, <4 x i1> %mask, <4 x i32> %src0)
180  ret <4 x i32>%res
181}
182
183declare <8 x i32> @llvm.masked.expandload.v8i32(ptr, <8 x i1>, <8 x i32>)
184define <8 x i32> @expandload_v8i32(ptr %base, <8 x i32> %src0, <8 x i1> %mask) {
185; CHECK-LABEL: expandload_v8i32:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
188; CHECK-NEXT:    vcpop.m a1, v0
189; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
190; CHECK-NEXT:    vle32.v v10, (a0)
191; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
192; CHECK-NEXT:    viota.m v12, v0
193; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t
194; CHECK-NEXT:    ret
195  %res = call <8 x i32> @llvm.masked.expandload.v8i32(ptr align 4 %base, <8 x i1> %mask, <8 x i32> %src0)
196  ret <8 x i32>%res
197}
198
199declare <1 x i64> @llvm.masked.expandload.v1i64(ptr, <1 x i1>, <1 x i64>)
200define <1 x i64> @expandload_v1i64(ptr %base, <1 x i64> %src0, <1 x i1> %mask) {
201; CHECK-LABEL: expandload_v1i64:
202; CHECK:       # %bb.0:
203; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
204; CHECK-NEXT:    vcpop.m a1, v0
205; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
206; CHECK-NEXT:    vle64.v v9, (a0)
207; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
208; CHECK-NEXT:    viota.m v10, v0
209; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
210; CHECK-NEXT:    ret
211  %res = call <1 x i64> @llvm.masked.expandload.v1i64(ptr align 8 %base, <1 x i1> %mask, <1 x i64> %src0)
212  ret <1 x i64>%res
213}
214
215declare <2 x i64> @llvm.masked.expandload.v2i64(ptr, <2 x i1>, <2 x i64>)
216define <2 x i64> @expandload_v2i64(ptr %base, <2 x i64> %src0, <2 x i1> %mask) {
217; CHECK-LABEL: expandload_v2i64:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
220; CHECK-NEXT:    vcpop.m a1, v0
221; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
222; CHECK-NEXT:    vle64.v v9, (a0)
223; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
224; CHECK-NEXT:    viota.m v10, v0
225; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t
226; CHECK-NEXT:    ret
227  %res = call <2 x i64> @llvm.masked.expandload.v2i64(ptr align 8 %base, <2 x i1> %mask, <2 x i64> %src0)
228  ret <2 x i64>%res
229}
230
231declare <4 x i64> @llvm.masked.expandload.v4i64(ptr, <4 x i1>, <4 x i64>)
232define <4 x i64> @expandload_v4i64(ptr %base, <4 x i64> %src0, <4 x i1> %mask) {
233; CHECK-LABEL: expandload_v4i64:
234; CHECK:       # %bb.0:
235; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
236; CHECK-NEXT:    vcpop.m a1, v0
237; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
238; CHECK-NEXT:    vle64.v v10, (a0)
239; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
240; CHECK-NEXT:    viota.m v12, v0
241; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t
242; CHECK-NEXT:    ret
243  %res = call <4 x i64> @llvm.masked.expandload.v4i64(ptr align 8 %base, <4 x i1> %mask, <4 x i64> %src0)
244  ret <4 x i64>%res
245}
246
247declare <8 x i64> @llvm.masked.expandload.v8i64(ptr, <8 x i1>, <8 x i64>)
248define <8 x i64> @expandload_v8i64(ptr %base, <8 x i64> %src0, <8 x i1> %mask) {
249; CHECK-LABEL: expandload_v8i64:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
252; CHECK-NEXT:    vcpop.m a1, v0
253; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
254; CHECK-NEXT:    vle64.v v12, (a0)
255; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
256; CHECK-NEXT:    viota.m v16, v0
257; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t
258; CHECK-NEXT:    ret
259  %res = call <8 x i64> @llvm.masked.expandload.v8i64(ptr align 8 %base, <8 x i1> %mask, <8 x i64> %src0)
260  ret <8 x i64>%res
261}
262;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
263; CHECK-RV32: {{.*}}
264; CHECK-RV64: {{.*}}
265