xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
4
5declare void @llvm.masked.compressstore.v1f16(<1 x half>, ptr, <1 x i1>)
6define void @compressstore_v1f16(ptr %base, <1 x half> %v, <1 x i1> %mask) {
7; RV32-LABEL: compressstore_v1f16:
8; RV32:       # %bb.0:
9; RV32-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
10; RV32-NEXT:    vcompress.vm v9, v8, v0
11; RV32-NEXT:    vcpop.m a1, v0
12; RV32-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
13; RV32-NEXT:    vse16.v v9, (a0)
14; RV32-NEXT:    ret
15;
16; RV64-LABEL: compressstore_v1f16:
17; RV64:       # %bb.0:
18; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
19; RV64-NEXT:    vcompress.vm v9, v8, v0
20; RV64-NEXT:    vcpop.m a1, v0
21; RV64-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
22; RV64-NEXT:    vse16.v v9, (a0)
23; RV64-NEXT:    ret
24  call void @llvm.masked.compressstore.v1f16(<1 x half> %v, ptr align 2 %base, <1 x i1> %mask)
25  ret void
26}
27
28declare void @llvm.masked.compressstore.v2f16(<2 x half>, ptr, <2 x i1>)
29define void @compressstore_v2f16(ptr %base, <2 x half> %v, <2 x i1> %mask) {
30; RV32-LABEL: compressstore_v2f16:
31; RV32:       # %bb.0:
32; RV32-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
33; RV32-NEXT:    vcompress.vm v9, v8, v0
34; RV32-NEXT:    vcpop.m a1, v0
35; RV32-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
36; RV32-NEXT:    vse16.v v9, (a0)
37; RV32-NEXT:    ret
38;
39; RV64-LABEL: compressstore_v2f16:
40; RV64:       # %bb.0:
41; RV64-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
42; RV64-NEXT:    vcompress.vm v9, v8, v0
43; RV64-NEXT:    vcpop.m a1, v0
44; RV64-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
45; RV64-NEXT:    vse16.v v9, (a0)
46; RV64-NEXT:    ret
47  call void @llvm.masked.compressstore.v2f16(<2 x half> %v, ptr align 2 %base, <2 x i1> %mask)
48  ret void
49}
50
51declare void @llvm.masked.compressstore.v4f16(<4 x half>, ptr, <4 x i1>)
52define void @compressstore_v4f16(ptr %base, <4 x half> %v, <4 x i1> %mask) {
53; RV32-LABEL: compressstore_v4f16:
54; RV32:       # %bb.0:
55; RV32-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
56; RV32-NEXT:    vcompress.vm v9, v8, v0
57; RV32-NEXT:    vcpop.m a1, v0
58; RV32-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
59; RV32-NEXT:    vse16.v v9, (a0)
60; RV32-NEXT:    ret
61;
62; RV64-LABEL: compressstore_v4f16:
63; RV64:       # %bb.0:
64; RV64-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
65; RV64-NEXT:    vcompress.vm v9, v8, v0
66; RV64-NEXT:    vcpop.m a1, v0
67; RV64-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
68; RV64-NEXT:    vse16.v v9, (a0)
69; RV64-NEXT:    ret
70  call void @llvm.masked.compressstore.v4f16(<4 x half> %v, ptr align 2 %base, <4 x i1> %mask)
71  ret void
72}
73
74declare void @llvm.masked.compressstore.v8f16(<8 x half>, ptr, <8 x i1>)
75define void @compressstore_v8f16(ptr %base, <8 x half> %v, <8 x i1> %mask) {
76; RV32-LABEL: compressstore_v8f16:
77; RV32:       # %bb.0:
78; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
79; RV32-NEXT:    vcompress.vm v9, v8, v0
80; RV32-NEXT:    vcpop.m a1, v0
81; RV32-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
82; RV32-NEXT:    vse16.v v9, (a0)
83; RV32-NEXT:    ret
84;
85; RV64-LABEL: compressstore_v8f16:
86; RV64:       # %bb.0:
87; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
88; RV64-NEXT:    vcompress.vm v9, v8, v0
89; RV64-NEXT:    vcpop.m a1, v0
90; RV64-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
91; RV64-NEXT:    vse16.v v9, (a0)
92; RV64-NEXT:    ret
93  call void @llvm.masked.compressstore.v8f16(<8 x half> %v, ptr align 2 %base, <8 x i1> %mask)
94  ret void
95}
96
97declare void @llvm.masked.compressstore.v1f32(<1 x float>, ptr, <1 x i1>)
98define void @compressstore_v1f32(ptr %base, <1 x float> %v, <1 x i1> %mask) {
99; RV32-LABEL: compressstore_v1f32:
100; RV32:       # %bb.0:
101; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
102; RV32-NEXT:    vcompress.vm v9, v8, v0
103; RV32-NEXT:    vcpop.m a1, v0
104; RV32-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
105; RV32-NEXT:    vse32.v v9, (a0)
106; RV32-NEXT:    ret
107;
108; RV64-LABEL: compressstore_v1f32:
109; RV64:       # %bb.0:
110; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
111; RV64-NEXT:    vcompress.vm v9, v8, v0
112; RV64-NEXT:    vcpop.m a1, v0
113; RV64-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
114; RV64-NEXT:    vse32.v v9, (a0)
115; RV64-NEXT:    ret
116  call void @llvm.masked.compressstore.v1f32(<1 x float> %v, ptr align 4 %base, <1 x i1> %mask)
117  ret void
118}
119
120declare void @llvm.masked.compressstore.v2f32(<2 x float>, ptr, <2 x i1>)
121define void @compressstore_v2f32(ptr %base, <2 x float> %v, <2 x i1> %mask) {
122; RV32-LABEL: compressstore_v2f32:
123; RV32:       # %bb.0:
124; RV32-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
125; RV32-NEXT:    vcompress.vm v9, v8, v0
126; RV32-NEXT:    vcpop.m a1, v0
127; RV32-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
128; RV32-NEXT:    vse32.v v9, (a0)
129; RV32-NEXT:    ret
130;
131; RV64-LABEL: compressstore_v2f32:
132; RV64:       # %bb.0:
133; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
134; RV64-NEXT:    vcompress.vm v9, v8, v0
135; RV64-NEXT:    vcpop.m a1, v0
136; RV64-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
137; RV64-NEXT:    vse32.v v9, (a0)
138; RV64-NEXT:    ret
139  call void @llvm.masked.compressstore.v2f32(<2 x float> %v, ptr align 4 %base, <2 x i1> %mask)
140  ret void
141}
142
143declare void @llvm.masked.compressstore.v4f32(<4 x float>, ptr, <4 x i1>)
144define void @compressstore_v4f32(ptr %base, <4 x float> %v, <4 x i1> %mask) {
145; RV32-LABEL: compressstore_v4f32:
146; RV32:       # %bb.0:
147; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
148; RV32-NEXT:    vcompress.vm v9, v8, v0
149; RV32-NEXT:    vcpop.m a1, v0
150; RV32-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
151; RV32-NEXT:    vse32.v v9, (a0)
152; RV32-NEXT:    ret
153;
154; RV64-LABEL: compressstore_v4f32:
155; RV64:       # %bb.0:
156; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
157; RV64-NEXT:    vcompress.vm v9, v8, v0
158; RV64-NEXT:    vcpop.m a1, v0
159; RV64-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
160; RV64-NEXT:    vse32.v v9, (a0)
161; RV64-NEXT:    ret
162  call void @llvm.masked.compressstore.v4f32(<4 x float> %v, ptr align 4 %base, <4 x i1> %mask)
163  ret void
164}
165
166declare void @llvm.masked.compressstore.v8f32(<8 x float>, ptr, <8 x i1>)
167define void @compressstore_v8f32(ptr %base, <8 x float> %v, <8 x i1> %mask) {
168; RV32-LABEL: compressstore_v8f32:
169; RV32:       # %bb.0:
170; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
171; RV32-NEXT:    vcompress.vm v10, v8, v0
172; RV32-NEXT:    vcpop.m a1, v0
173; RV32-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
174; RV32-NEXT:    vse32.v v10, (a0)
175; RV32-NEXT:    ret
176;
177; RV64-LABEL: compressstore_v8f32:
178; RV64:       # %bb.0:
179; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
180; RV64-NEXT:    vcompress.vm v10, v8, v0
181; RV64-NEXT:    vcpop.m a1, v0
182; RV64-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
183; RV64-NEXT:    vse32.v v10, (a0)
184; RV64-NEXT:    ret
185  call void @llvm.masked.compressstore.v8f32(<8 x float> %v, ptr align 4 %base, <8 x i1> %mask)
186  ret void
187}
188
189declare void @llvm.masked.compressstore.v1f64(<1 x double>, ptr, <1 x i1>)
190define void @compressstore_v1f64(ptr %base, <1 x double> %v, <1 x i1> %mask) {
191; RV32-LABEL: compressstore_v1f64:
192; RV32:       # %bb.0:
193; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
194; RV32-NEXT:    vcompress.vm v9, v8, v0
195; RV32-NEXT:    vcpop.m a1, v0
196; RV32-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
197; RV32-NEXT:    vse64.v v9, (a0)
198; RV32-NEXT:    ret
199;
200; RV64-LABEL: compressstore_v1f64:
201; RV64:       # %bb.0:
202; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
203; RV64-NEXT:    vcompress.vm v9, v8, v0
204; RV64-NEXT:    vcpop.m a1, v0
205; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
206; RV64-NEXT:    vse64.v v9, (a0)
207; RV64-NEXT:    ret
208  call void @llvm.masked.compressstore.v1f64(<1 x double> %v, ptr align 8 %base, <1 x i1> %mask)
209  ret void
210}
211
212declare void @llvm.masked.compressstore.v2f64(<2 x double>, ptr, <2 x i1>)
213define void @compressstore_v2f64(ptr %base, <2 x double> %v, <2 x i1> %mask) {
214; RV32-LABEL: compressstore_v2f64:
215; RV32:       # %bb.0:
216; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
217; RV32-NEXT:    vcompress.vm v9, v8, v0
218; RV32-NEXT:    vcpop.m a1, v0
219; RV32-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
220; RV32-NEXT:    vse64.v v9, (a0)
221; RV32-NEXT:    ret
222;
223; RV64-LABEL: compressstore_v2f64:
224; RV64:       # %bb.0:
225; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
226; RV64-NEXT:    vcompress.vm v9, v8, v0
227; RV64-NEXT:    vcpop.m a1, v0
228; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
229; RV64-NEXT:    vse64.v v9, (a0)
230; RV64-NEXT:    ret
231  call void @llvm.masked.compressstore.v2f64(<2 x double> %v, ptr align 8 %base, <2 x i1> %mask)
232  ret void
233}
234
235declare void @llvm.masked.compressstore.v4f64(<4 x double>, ptr, <4 x i1>)
236define void @compressstore_v4f64(ptr %base, <4 x double> %v, <4 x i1> %mask) {
237; RV32-LABEL: compressstore_v4f64:
238; RV32:       # %bb.0:
239; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
240; RV32-NEXT:    vcompress.vm v10, v8, v0
241; RV32-NEXT:    vcpop.m a1, v0
242; RV32-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
243; RV32-NEXT:    vse64.v v10, (a0)
244; RV32-NEXT:    ret
245;
246; RV64-LABEL: compressstore_v4f64:
247; RV64:       # %bb.0:
248; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
249; RV64-NEXT:    vcompress.vm v10, v8, v0
250; RV64-NEXT:    vcpop.m a1, v0
251; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
252; RV64-NEXT:    vse64.v v10, (a0)
253; RV64-NEXT:    ret
254  call void @llvm.masked.compressstore.v4f64(<4 x double> %v, ptr align 8 %base, <4 x i1> %mask)
255  ret void
256}
257
258declare void @llvm.masked.compressstore.v8f64(<8 x double>, ptr, <8 x i1>)
259define void @compressstore_v8f64(ptr %base, <8 x double> %v, <8 x i1> %mask) {
260; RV32-LABEL: compressstore_v8f64:
261; RV32:       # %bb.0:
262; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
263; RV32-NEXT:    vcompress.vm v12, v8, v0
264; RV32-NEXT:    vcpop.m a1, v0
265; RV32-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
266; RV32-NEXT:    vse64.v v12, (a0)
267; RV32-NEXT:    ret
268;
269; RV64-LABEL: compressstore_v8f64:
270; RV64:       # %bb.0:
271; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
272; RV64-NEXT:    vcompress.vm v12, v8, v0
273; RV64-NEXT:    vcpop.m a1, v0
274; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
275; RV64-NEXT:    vse64.v v12, (a0)
276; RV64-NEXT:    ret
277  call void @llvm.masked.compressstore.v8f64(<8 x double> %v, ptr align 8 %base, <8 x i1> %mask)
278  ret void
279}
280