xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compress-int.ll (revision b799cc3418f5fda0dd1bbd80a9e7e97cca5f40c2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
4
5define <1 x i8> @vector_compress_v1i8(<1 x i8> %v, <1 x i1> %mask) {
6; CHECK-LABEL: vector_compress_v1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
9; CHECK-NEXT:    vcompress.vm v9, v8, v0
10; CHECK-NEXT:    vmv1r.v v8, v9
11; CHECK-NEXT:    ret
12  %ret = call <1 x i8> @llvm.experimental.vector.compress.v1i8(<1 x i8> %v, <1 x i1> %mask, <1 x i8> undef)
13  ret <1 x i8> %ret
14}
15
16define <1 x i8> @vector_compress_v1i8_passthru(<1 x i8> %passthru, <1 x i8> %v, <1 x i1> %mask) {
17; CHECK-LABEL: vector_compress_v1i8_passthru:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, tu, ma
20; CHECK-NEXT:    vcompress.vm v8, v9, v0
21; CHECK-NEXT:    ret
22  %ret = call <1 x i8> @llvm.experimental.vector.compress.v1i8(<1 x i8> %v, <1 x i1> %mask, <1 x i8> %passthru)
23  ret <1 x i8> %ret
24}
25
26define <2 x i8> @vector_compress_v2i8(<2 x i8> %v, <2 x i1> %mask) {
27; CHECK-LABEL: vector_compress_v2i8:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
30; CHECK-NEXT:    vcompress.vm v9, v8, v0
31; CHECK-NEXT:    vmv1r.v v8, v9
32; CHECK-NEXT:    ret
33  %ret = call <2 x i8> @llvm.experimental.vector.compress.v2i8(<2 x i8> %v, <2 x i1> %mask, <2 x i8> undef)
34  ret <2 x i8> %ret
35}
36
37define <2 x i8> @vector_compress_v2i8_passthru(<2 x i8> %passthru, <2 x i8> %v, <2 x i1> %mask) {
38; CHECK-LABEL: vector_compress_v2i8_passthru:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, tu, ma
41; CHECK-NEXT:    vcompress.vm v8, v9, v0
42; CHECK-NEXT:    ret
43  %ret = call <2 x i8> @llvm.experimental.vector.compress.v2i8(<2 x i8> %v, <2 x i1> %mask, <2 x i8> %passthru)
44  ret <2 x i8> %ret
45}
46
47define <4 x i8> @vector_compress_v4i8(<4 x i8> %v, <4 x i1> %mask) {
48; CHECK-LABEL: vector_compress_v4i8:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
51; CHECK-NEXT:    vcompress.vm v9, v8, v0
52; CHECK-NEXT:    vmv1r.v v8, v9
53; CHECK-NEXT:    ret
54  %ret = call <4 x i8> @llvm.experimental.vector.compress.v4i8(<4 x i8> %v, <4 x i1> %mask, <4 x i8> undef)
55  ret <4 x i8> %ret
56}
57
58define <4 x i8> @vector_compress_v4i8_passthru(<4 x i8> %passthru, <4 x i8> %v, <4 x i1> %mask) {
59; CHECK-LABEL: vector_compress_v4i8_passthru:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, tu, ma
62; CHECK-NEXT:    vcompress.vm v8, v9, v0
63; CHECK-NEXT:    ret
64  %ret = call <4 x i8> @llvm.experimental.vector.compress.v4i8(<4 x i8> %v, <4 x i1> %mask, <4 x i8> %passthru)
65  ret <4 x i8> %ret
66}
67
68define <8 x i8> @vector_compress_v8i8(<8 x i8> %v, <8 x i1> %mask) {
69; CHECK-LABEL: vector_compress_v8i8:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
72; CHECK-NEXT:    vcompress.vm v9, v8, v0
73; CHECK-NEXT:    vmv1r.v v8, v9
74; CHECK-NEXT:    ret
75  %ret = call <8 x i8> @llvm.experimental.vector.compress.v8i8(<8 x i8> %v, <8 x i1> %mask, <8 x i8> undef)
76  ret <8 x i8> %ret
77}
78
79define <8 x i8> @vector_compress_v8i8_passthru(<8 x i8> %passthru, <8 x i8> %v, <8 x i1> %mask) {
80; CHECK-LABEL: vector_compress_v8i8_passthru:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, tu, ma
83; CHECK-NEXT:    vcompress.vm v8, v9, v0
84; CHECK-NEXT:    ret
85  %ret = call <8 x i8> @llvm.experimental.vector.compress.v8i8(<8 x i8> %v, <8 x i1> %mask, <8 x i8> %passthru)
86  ret <8 x i8> %ret
87}
88
89define <1 x i16> @vector_compress_v1i16(<1 x i16> %v, <1 x i1> %mask) {
90; CHECK-LABEL: vector_compress_v1i16:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
93; CHECK-NEXT:    vcompress.vm v9, v8, v0
94; CHECK-NEXT:    vmv1r.v v8, v9
95; CHECK-NEXT:    ret
96  %ret = call <1 x i16> @llvm.experimental.vector.compress.v1i16(<1 x i16> %v, <1 x i1> %mask, <1 x i16> undef)
97  ret <1 x i16> %ret
98}
99
100define <1 x i16> @vector_compress_v1i16_passthru(<1 x i16> %passthru, <1 x i16> %v, <1 x i1> %mask) {
101; CHECK-LABEL: vector_compress_v1i16_passthru:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, tu, ma
104; CHECK-NEXT:    vcompress.vm v8, v9, v0
105; CHECK-NEXT:    ret
106  %ret = call <1 x i16> @llvm.experimental.vector.compress.v1i16(<1 x i16> %v, <1 x i1> %mask, <1 x i16> %passthru)
107  ret <1 x i16> %ret
108}
109
110define <2 x i16> @vector_compress_v2i16(<2 x i16> %v, <2 x i1> %mask) {
111; CHECK-LABEL: vector_compress_v2i16:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
114; CHECK-NEXT:    vcompress.vm v9, v8, v0
115; CHECK-NEXT:    vmv1r.v v8, v9
116; CHECK-NEXT:    ret
117  %ret = call <2 x i16> @llvm.experimental.vector.compress.v2i16(<2 x i16> %v, <2 x i1> %mask, <2 x i16> undef)
118  ret <2 x i16> %ret
119}
120
121define <2 x i16> @vector_compress_v2i16_passthru(<2 x i16> %passthru, <2 x i16> %v, <2 x i1> %mask) {
122; CHECK-LABEL: vector_compress_v2i16_passthru:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, tu, ma
125; CHECK-NEXT:    vcompress.vm v8, v9, v0
126; CHECK-NEXT:    ret
127  %ret = call <2 x i16> @llvm.experimental.vector.compress.v2i16(<2 x i16> %v, <2 x i1> %mask, <2 x i16> %passthru)
128  ret <2 x i16> %ret
129}
130
131define <4 x i16> @vector_compress_v4i16(<4 x i16> %v, <4 x i1> %mask) {
132; CHECK-LABEL: vector_compress_v4i16:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
135; CHECK-NEXT:    vcompress.vm v9, v8, v0
136; CHECK-NEXT:    vmv1r.v v8, v9
137; CHECK-NEXT:    ret
138  %ret = call <4 x i16> @llvm.experimental.vector.compress.v4i16(<4 x i16> %v, <4 x i1> %mask, <4 x i16> undef)
139  ret <4 x i16> %ret
140}
141
142define <4 x i16> @vector_compress_v4i16_passthru(<4 x i16> %passthru, <4 x i16> %v, <4 x i1> %mask) {
143; CHECK-LABEL: vector_compress_v4i16_passthru:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, tu, ma
146; CHECK-NEXT:    vcompress.vm v8, v9, v0
147; CHECK-NEXT:    ret
148  %ret = call <4 x i16> @llvm.experimental.vector.compress.v4i16(<4 x i16> %v, <4 x i1> %mask, <4 x i16> %passthru)
149  ret <4 x i16> %ret
150}
151
152define <8 x i16> @vector_compress_v8i16(<8 x i16> %v, <8 x i1> %mask) {
153; CHECK-LABEL: vector_compress_v8i16:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
156; CHECK-NEXT:    vcompress.vm v9, v8, v0
157; CHECK-NEXT:    vmv.v.v v8, v9
158; CHECK-NEXT:    ret
159  %ret = call <8 x i16> @llvm.experimental.vector.compress.v8i16(<8 x i16> %v, <8 x i1> %mask, <8 x i16> undef)
160  ret <8 x i16> %ret
161}
162
163define <8 x i16> @vector_compress_v8i16_passthru(<8 x i16> %passthru, <8 x i16> %v, <8 x i1> %mask) {
164; CHECK-LABEL: vector_compress_v8i16_passthru:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetivli zero, 8, e16, m1, tu, ma
167; CHECK-NEXT:    vcompress.vm v8, v9, v0
168; CHECK-NEXT:    ret
169  %ret = call <8 x i16> @llvm.experimental.vector.compress.v8i16(<8 x i16> %v, <8 x i1> %mask, <8 x i16> %passthru)
170  ret <8 x i16> %ret
171}
172
173define <1 x i32> @vector_compress_v1i32(<1 x i32> %v, <1 x i1> %mask) {
174; CHECK-LABEL: vector_compress_v1i32:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
177; CHECK-NEXT:    vcompress.vm v9, v8, v0
178; CHECK-NEXT:    vmv1r.v v8, v9
179; CHECK-NEXT:    ret
180  %ret = call <1 x i32> @llvm.experimental.vector.compress.v1i32(<1 x i32> %v, <1 x i1> %mask, <1 x i32> undef)
181  ret <1 x i32> %ret
182}
183
184define <1 x i32> @vector_compress_v1i32_passthru(<1 x i32> %passthru, <1 x i32> %v, <1 x i1> %mask) {
185; CHECK-LABEL: vector_compress_v1i32_passthru:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, tu, ma
188; CHECK-NEXT:    vcompress.vm v8, v9, v0
189; CHECK-NEXT:    ret
190  %ret = call <1 x i32> @llvm.experimental.vector.compress.v1i32(<1 x i32> %v, <1 x i1> %mask, <1 x i32> %passthru)
191  ret <1 x i32> %ret
192}
193
194define <2 x i32> @vector_compress_v2i32(<2 x i32> %v, <2 x i1> %mask) {
195; CHECK-LABEL: vector_compress_v2i32:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
198; CHECK-NEXT:    vcompress.vm v9, v8, v0
199; CHECK-NEXT:    vmv1r.v v8, v9
200; CHECK-NEXT:    ret
201  %ret = call <2 x i32> @llvm.experimental.vector.compress.v2i32(<2 x i32> %v, <2 x i1> %mask, <2 x i32> undef)
202  ret <2 x i32> %ret
203}
204
205define <2 x i32> @vector_compress_v2i32_passthru(<2 x i32> %passthru, <2 x i32> %v, <2 x i1> %mask) {
206; CHECK-LABEL: vector_compress_v2i32_passthru:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
209; CHECK-NEXT:    vcompress.vm v8, v9, v0
210; CHECK-NEXT:    ret
211  %ret = call <2 x i32> @llvm.experimental.vector.compress.v2i32(<2 x i32> %v, <2 x i1> %mask, <2 x i32> %passthru)
212  ret <2 x i32> %ret
213}
214
215define <4 x i32> @vector_compress_v4i32(<4 x i32> %v, <4 x i1> %mask) {
216; CHECK-LABEL: vector_compress_v4i32:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
219; CHECK-NEXT:    vcompress.vm v9, v8, v0
220; CHECK-NEXT:    vmv.v.v v8, v9
221; CHECK-NEXT:    ret
222  %ret = call <4 x i32> @llvm.experimental.vector.compress.v4i32(<4 x i32> %v, <4 x i1> %mask, <4 x i32> undef)
223  ret <4 x i32> %ret
224}
225
226define <4 x i32> @vector_compress_v4i32_passthru(<4 x i32> %passthru, <4 x i32> %v, <4 x i1> %mask) {
227; CHECK-LABEL: vector_compress_v4i32_passthru:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    vsetivli zero, 4, e32, m1, tu, ma
230; CHECK-NEXT:    vcompress.vm v8, v9, v0
231; CHECK-NEXT:    ret
232  %ret = call <4 x i32> @llvm.experimental.vector.compress.v4i32(<4 x i32> %v, <4 x i1> %mask, <4 x i32> %passthru)
233  ret <4 x i32> %ret
234}
235
236define <8 x i32> @vector_compress_v8i32(<8 x i32> %v, <8 x i1> %mask) {
237; CHECK-LABEL: vector_compress_v8i32:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
240; CHECK-NEXT:    vcompress.vm v10, v8, v0
241; CHECK-NEXT:    vmv.v.v v8, v10
242; CHECK-NEXT:    ret
243  %ret = call <8 x i32> @llvm.experimental.vector.compress.v8i32(<8 x i32> %v, <8 x i1> %mask, <8 x i32> undef)
244  ret <8 x i32> %ret
245}
246
247define <8 x i32> @vector_compress_v8i32_passthru(<8 x i32> %passthru, <8 x i32> %v, <8 x i1> %mask) {
248; CHECK-LABEL: vector_compress_v8i32_passthru:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    vsetivli zero, 8, e32, m2, tu, ma
251; CHECK-NEXT:    vcompress.vm v8, v10, v0
252; CHECK-NEXT:    ret
253  %ret = call <8 x i32> @llvm.experimental.vector.compress.v8i32(<8 x i32> %v, <8 x i1> %mask, <8 x i32> %passthru)
254  ret <8 x i32> %ret
255}
256
257define <1 x i64> @vector_compress_v1i64(<1 x i64> %v, <1 x i1> %mask) {
258; CHECK-LABEL: vector_compress_v1i64:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
261; CHECK-NEXT:    vcompress.vm v9, v8, v0
262; CHECK-NEXT:    vmv.v.v v8, v9
263; CHECK-NEXT:    ret
264  %ret = call <1 x i64> @llvm.experimental.vector.compress.v1i64(<1 x i64> %v, <1 x i1> %mask, <1 x i64> undef)
265  ret <1 x i64> %ret
266}
267
268define <1 x i64> @vector_compress_v1i64_passthru(<1 x i64> %passthru, <1 x i64> %v, <1 x i1> %mask) {
269; CHECK-LABEL: vector_compress_v1i64_passthru:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetivli zero, 1, e64, m1, tu, ma
272; CHECK-NEXT:    vcompress.vm v8, v9, v0
273; CHECK-NEXT:    ret
274  %ret = call <1 x i64> @llvm.experimental.vector.compress.v1i64(<1 x i64> %v, <1 x i1> %mask, <1 x i64> %passthru)
275  ret <1 x i64> %ret
276}
277
278define <2 x i64> @vector_compress_v2i64(<2 x i64> %v, <2 x i1> %mask) {
279; CHECK-LABEL: vector_compress_v2i64:
280; CHECK:       # %bb.0:
281; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
282; CHECK-NEXT:    vcompress.vm v9, v8, v0
283; CHECK-NEXT:    vmv.v.v v8, v9
284; CHECK-NEXT:    ret
285  %ret = call <2 x i64> @llvm.experimental.vector.compress.v2i64(<2 x i64> %v, <2 x i1> %mask, <2 x i64> undef)
286  ret <2 x i64> %ret
287}
288
289define <2 x i64> @vector_compress_v2i64_passthru(<2 x i64> %passthru, <2 x i64> %v, <2 x i1> %mask) {
290; CHECK-LABEL: vector_compress_v2i64_passthru:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    vsetivli zero, 2, e64, m1, tu, ma
293; CHECK-NEXT:    vcompress.vm v8, v9, v0
294; CHECK-NEXT:    ret
295  %ret = call <2 x i64> @llvm.experimental.vector.compress.v2i64(<2 x i64> %v, <2 x i1> %mask, <2 x i64> %passthru)
296  ret <2 x i64> %ret
297}
298
299define <4 x i64> @vector_compress_v4i64(<4 x i64> %v, <4 x i1> %mask) {
300; CHECK-LABEL: vector_compress_v4i64:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
303; CHECK-NEXT:    vcompress.vm v10, v8, v0
304; CHECK-NEXT:    vmv.v.v v8, v10
305; CHECK-NEXT:    ret
306  %ret = call <4 x i64> @llvm.experimental.vector.compress.v4i64(<4 x i64> %v, <4 x i1> %mask, <4 x i64> undef)
307  ret <4 x i64> %ret
308}
309
310define <4 x i64> @vector_compress_v4i64_passthru(<4 x i64> %passthru, <4 x i64> %v, <4 x i1> %mask) {
311; CHECK-LABEL: vector_compress_v4i64_passthru:
312; CHECK:       # %bb.0:
313; CHECK-NEXT:    vsetivli zero, 4, e64, m2, tu, ma
314; CHECK-NEXT:    vcompress.vm v8, v10, v0
315; CHECK-NEXT:    ret
316  %ret = call <4 x i64> @llvm.experimental.vector.compress.v4i64(<4 x i64> %v, <4 x i1> %mask, <4 x i64> %passthru)
317  ret <4 x i64> %ret
318}
319
320define <8 x i64> @vector_compress_v8i64(<8 x i64> %v, <8 x i1> %mask) {
321; CHECK-LABEL: vector_compress_v8i64:
322; CHECK:       # %bb.0:
323; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
324; CHECK-NEXT:    vcompress.vm v12, v8, v0
325; CHECK-NEXT:    vmv.v.v v8, v12
326; CHECK-NEXT:    ret
327  %ret = call <8 x i64> @llvm.experimental.vector.compress.v8i64(<8 x i64> %v, <8 x i1> %mask, <8 x i64> undef)
328  ret <8 x i64> %ret
329}
330
331define <8 x i64> @vector_compress_v8i64_passthru(<8 x i64> %passthru, <8 x i64> %v, <8 x i1> %mask) {
332; CHECK-LABEL: vector_compress_v8i64_passthru:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    vsetivli zero, 8, e64, m4, tu, ma
335; CHECK-NEXT:    vcompress.vm v8, v12, v0
336; CHECK-NEXT:    ret
337  %ret = call <8 x i64> @llvm.experimental.vector.compress.v8i64(<8 x i64> %v, <8 x i1> %mask, <8 x i64> %passthru)
338  ret <8 x i64> %ret
339}
340