xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-neg-abs.ll (revision 2291d0aba927b885cf39150e59fde466a2524bb5)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3
4define <2 x i64> @expanded_fixed_neg_abs64(<2 x i64> %x) {
5; CHECK-LABEL: expanded_fixed_neg_abs64:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
8; CHECK-NEXT:    vrsub.vi v9, v8, 0
9; CHECK-NEXT:    vmin.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %t = sub <2 x i64> <i64 0, i64 0>, %x
12  %t1 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %t, <2 x i64> %x)
13  %t2 = sub <2 x i64> <i64 0, i64 0>, %t1
14  ret <2 x i64> %t2
15}
16
17define <2 x i64> @expanded_fixed_neg_abs64_unsigned(<2 x i64> %x) {
18; CHECK-LABEL: expanded_fixed_neg_abs64_unsigned:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
21; CHECK-NEXT:    vrsub.vi v9, v8, 0
22; CHECK-NEXT:    vminu.vv v8, v8, v9
23; CHECK-NEXT:    ret
24  %t = sub <2 x i64> <i64 0, i64 0>, %x
25  %t1 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> %t, <2 x i64> %x)
26  %t2 = sub <2 x i64> <i64 0, i64 0>, %t1
27  ret <2 x i64> %t2
28}
29
30define <2 x i64> @expanded_fixed_neg_inv_abs64(<2 x i64> %x) {
31; CHECK-LABEL: expanded_fixed_neg_inv_abs64:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
34; CHECK-NEXT:    vrsub.vi v9, v8, 0
35; CHECK-NEXT:    vmax.vv v8, v8, v9
36; CHECK-NEXT:    ret
37  %t = sub <2 x i64> <i64 0, i64 0>, %x
38  %t1 = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %t, <2 x i64> %x)
39  %t2 = sub <2 x i64> <i64 0, i64 0>, %t1
40  ret <2 x i64> %t2
41}
42
43define <2 x i64> @expanded_fixed_neg_inv_abs64_unsigned(<2 x i64> %x) {
44; CHECK-LABEL: expanded_fixed_neg_inv_abs64_unsigned:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
47; CHECK-NEXT:    vrsub.vi v9, v8, 0
48; CHECK-NEXT:    vmaxu.vv v8, v8, v9
49; CHECK-NEXT:    ret
50  %t = sub <2 x i64> <i64 0, i64 0>, %x
51  %t1 = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %t, <2 x i64> %x)
52  %t2 = sub <2 x i64> <i64 0, i64 0>, %t1
53  ret <2 x i64> %t2
54}
55