xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
4
5define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) {
6; CHECK-LABEL: extract_nxv8i32_nxv4i32_0:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    ret
9  %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
10  ret <vscale x 4 x i32> %c
11}
12
13define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) {
14; CHECK-LABEL: extract_nxv8i32_nxv4i32_4:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
17; CHECK-NEXT:    vmv2r.v v8, v10
18; CHECK-NEXT:    ret
19  %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
20  ret <vscale x 4 x i32> %c
21}
22
23define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) {
24; CHECK-LABEL: extract_nxv8i32_nxv2i32_0:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    ret
27  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
28  ret <vscale x 2 x i32> %c
29}
30
31define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) {
32; CHECK-LABEL: extract_nxv8i32_nxv2i32_2:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
35; CHECK-NEXT:    vmv1r.v v8, v9
36; CHECK-NEXT:    ret
37  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2)
38  ret <vscale x 2 x i32> %c
39}
40
41define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) {
42; CHECK-LABEL: extract_nxv8i32_nxv2i32_4:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
45; CHECK-NEXT:    vmv1r.v v8, v10
46; CHECK-NEXT:    ret
47  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4)
48  ret <vscale x 2 x i32> %c
49}
50
51define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) {
52; CHECK-LABEL: extract_nxv8i32_nxv2i32_6:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
55; CHECK-NEXT:    vmv1r.v v8, v11
56; CHECK-NEXT:    ret
57  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6)
58  ret <vscale x 2 x i32> %c
59}
60
61define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) {
62; CHECK-LABEL: extract_nxv16i32_nxv8i32_0:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    ret
65  %c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
66  ret <vscale x 8 x i32> %c
67}
68
69define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) {
70; CHECK-LABEL: extract_nxv16i32_nxv8i32_8:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
73; CHECK-NEXT:    vmv4r.v v8, v12
74; CHECK-NEXT:    ret
75  %c = call <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
76  ret <vscale x 8 x i32> %c
77}
78
79define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) {
80; CHECK-LABEL: extract_nxv16i32_nxv4i32_0:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    ret
83  %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
84  ret <vscale x 4 x i32> %c
85}
86
87define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) {
88; CHECK-LABEL: extract_nxv16i32_nxv4i32_4:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
91; CHECK-NEXT:    vmv2r.v v8, v10
92; CHECK-NEXT:    ret
93  %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
94  ret <vscale x 4 x i32> %c
95}
96
97define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) {
98; CHECK-LABEL: extract_nxv16i32_nxv4i32_8:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
101; CHECK-NEXT:    vmv2r.v v8, v12
102; CHECK-NEXT:    ret
103  %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
104  ret <vscale x 4 x i32> %c
105}
106
107define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) {
108; CHECK-LABEL: extract_nxv16i32_nxv4i32_12:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
111; CHECK-NEXT:    vmv2r.v v8, v14
112; CHECK-NEXT:    ret
113  %c = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
114  ret <vscale x 4 x i32> %c
115}
116
117define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) {
118; CHECK-LABEL: extract_nxv16i32_nxv2i32_0:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    ret
121  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
122  ret <vscale x 2 x i32> %c
123}
124
125define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) {
126; CHECK-LABEL: extract_nxv16i32_nxv2i32_2:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
129; CHECK-NEXT:    vmv1r.v v8, v9
130; CHECK-NEXT:    ret
131  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
132  ret <vscale x 2 x i32> %c
133}
134
135define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) {
136; CHECK-LABEL: extract_nxv16i32_nxv2i32_4:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
139; CHECK-NEXT:    vmv1r.v v8, v10
140; CHECK-NEXT:    ret
141  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4)
142  ret <vscale x 2 x i32> %c
143}
144
145define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) {
146; CHECK-LABEL: extract_nxv16i32_nxv2i32_6:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
149; CHECK-NEXT:    vmv1r.v v8, v11
150; CHECK-NEXT:    ret
151  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6)
152  ret <vscale x 2 x i32> %c
153}
154
155define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) {
156; CHECK-LABEL: extract_nxv16i32_nxv2i32_8:
157; CHECK:       # %bb.0:
158; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
159; CHECK-NEXT:    vmv1r.v v8, v12
160; CHECK-NEXT:    ret
161  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8)
162  ret <vscale x 2 x i32> %c
163}
164
165define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) {
166; CHECK-LABEL: extract_nxv16i32_nxv2i32_10:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
169; CHECK-NEXT:    vmv1r.v v8, v13
170; CHECK-NEXT:    ret
171  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10)
172  ret <vscale x 2 x i32> %c
173}
174
175define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) {
176; CHECK-LABEL: extract_nxv16i32_nxv2i32_12:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
179; CHECK-NEXT:    vmv1r.v v8, v14
180; CHECK-NEXT:    ret
181  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12)
182  ret <vscale x 2 x i32> %c
183}
184
185define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) {
186; CHECK-LABEL: extract_nxv16i32_nxv2i32_14:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
189; CHECK-NEXT:    vmv1r.v v8, v15
190; CHECK-NEXT:    ret
191  %c = call <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14)
192  ret <vscale x 2 x i32> %c
193}
194
195define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) {
196; CHECK-LABEL: extract_nxv16i32_nxv1i32_0:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    ret
199  %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0)
200  ret <vscale x 1 x i32> %c
201}
202
203define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) {
204; CHECK-LABEL: extract_nxv16i32_nxv1i32_1:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    csrr a0, vlenb
207; CHECK-NEXT:    srli a0, a0, 3
208; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
209; CHECK-NEXT:    vslidedown.vx v8, v8, a0
210; CHECK-NEXT:    ret
211  %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1)
212  ret <vscale x 1 x i32> %c
213}
214
215define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_3(<vscale x 16 x i32> %vec) {
216; CHECK-LABEL: extract_nxv16i32_nxv1i32_3:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    csrr a0, vlenb
219; CHECK-NEXT:    srli a0, a0, 3
220; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
221; CHECK-NEXT:    vslidedown.vx v8, v9, a0
222; CHECK-NEXT:    ret
223  %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 3)
224  ret <vscale x 1 x i32> %c
225}
226
227define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_15(<vscale x 16 x i32> %vec) {
228; CHECK-LABEL: extract_nxv16i32_nxv1i32_15:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    csrr a0, vlenb
231; CHECK-NEXT:    srli a0, a0, 3
232; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
233; CHECK-NEXT:    vslidedown.vx v8, v15, a0
234; CHECK-NEXT:    ret
235  %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 15)
236  ret <vscale x 1 x i32> %c
237}
238
239define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) {
240; CHECK-LABEL: extract_nxv16i32_nxv1i32_2:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
243; CHECK-NEXT:    vmv1r.v v8, v9
244; CHECK-NEXT:    ret
245  %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2)
246  ret <vscale x 1 x i32> %c
247}
248
249define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) {
250; CHECK-LABEL: extract_nxv2i32_nxv1i32_0:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    ret
253  %c = call <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0)
254  ret <vscale x 1 x i32> %c
255}
256
257define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_0(<vscale x 32 x i8> %vec) {
258; CHECK-LABEL: extract_nxv32i8_nxv2i8_0:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    ret
261  %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 0)
262  ret <vscale x 2 x i8> %c
263}
264
265define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_2(<vscale x 32 x i8> %vec) {
266; CHECK-LABEL: extract_nxv32i8_nxv2i8_2:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    csrr a0, vlenb
269; CHECK-NEXT:    srli a0, a0, 2
270; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
271; CHECK-NEXT:    vslidedown.vx v8, v8, a0
272; CHECK-NEXT:    ret
273  %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 2)
274  ret <vscale x 2 x i8> %c
275}
276
277define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_4(<vscale x 32 x i8> %vec) {
278; CHECK-LABEL: extract_nxv32i8_nxv2i8_4:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    csrr a0, vlenb
281; CHECK-NEXT:    srli a0, a0, 1
282; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
283; CHECK-NEXT:    vslidedown.vx v8, v8, a0
284; CHECK-NEXT:    ret
285  %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 4)
286  ret <vscale x 2 x i8> %c
287}
288
289define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
290; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:
291; CHECK:       # %bb.0:
292; CHECK-NEXT:    csrr a0, vlenb
293; CHECK-NEXT:    srli a1, a0, 3
294; CHECK-NEXT:    slli a1, a1, 1
295; CHECK-NEXT:    sub a0, a0, a1
296; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
297; CHECK-NEXT:    vslidedown.vx v8, v8, a0
298; CHECK-NEXT:    ret
299  %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 6)
300  ret <vscale x 2 x i8> %c
301}
302
303define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_8(<vscale x 32 x i8> %vec) {
304; CHECK-LABEL: extract_nxv32i8_nxv2i8_8:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
307; CHECK-NEXT:    vmv1r.v v8, v9
308; CHECK-NEXT:    ret
309  %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 8)
310  ret <vscale x 2 x i8> %c
311}
312
313define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
314; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    csrr a0, vlenb
317; CHECK-NEXT:    srli a1, a0, 3
318; CHECK-NEXT:    slli a1, a1, 1
319; CHECK-NEXT:    sub a0, a0, a1
320; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
321; CHECK-NEXT:    vslidedown.vx v8, v10, a0
322; CHECK-NEXT:    ret
323  %c = call <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 22)
324  ret <vscale x 2 x i8> %c
325}
326
327define <vscale x 1 x i8> @extract_nxv8i8_nxv1i8_7(<vscale x 8 x i8> %vec) {
328; CHECK-LABEL: extract_nxv8i8_nxv1i8_7:
329; CHECK:       # %bb.0:
330; CHECK-NEXT:    csrr a0, vlenb
331; CHECK-NEXT:    srli a1, a0, 3
332; CHECK-NEXT:    sub a0, a0, a1
333; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
334; CHECK-NEXT:    vslidedown.vx v8, v8, a0
335; CHECK-NEXT:    ret
336  %c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 7)
337  ret <vscale x 1 x i8> %c
338}
339
340define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {
341; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:
342; CHECK:       # %bb.0:
343; CHECK-NEXT:    csrr a0, vlenb
344; CHECK-NEXT:    srli a0, a0, 3
345; CHECK-NEXT:    slli a1, a0, 1
346; CHECK-NEXT:    add a0, a1, a0
347; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
348; CHECK-NEXT:    vslidedown.vx v8, v8, a0
349; CHECK-NEXT:    ret
350  %c = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 3)
351  ret <vscale x 1 x i8> %c
352}
353
354define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_0(<vscale x 16 x half> %vec) {
355; CHECK-LABEL: extract_nxv2f16_nxv16f16_0:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    ret
358  %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 0)
359  ret <vscale x 2 x half> %c
360}
361
362define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_2(<vscale x 16 x half> %vec) {
363; CHECK-LABEL: extract_nxv2f16_nxv16f16_2:
364; CHECK:       # %bb.0:
365; CHECK-NEXT:    csrr a0, vlenb
366; CHECK-NEXT:    srli a0, a0, 2
367; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
368; CHECK-NEXT:    vslidedown.vx v8, v8, a0
369; CHECK-NEXT:    ret
370  %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 2)
371  ret <vscale x 2 x half> %c
372}
373
374define <vscale x 2 x half> @extract_nxv2f16_nxv16f16_4(<vscale x 16 x half> %vec) {
375; CHECK-LABEL: extract_nxv2f16_nxv16f16_4:
376; CHECK:       # %bb.0:
377; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
378; CHECK-NEXT:    vmv1r.v v8, v9
379; CHECK-NEXT:    ret
380  %c = call <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 4)
381  ret <vscale x 2 x half> %c
382}
383
384define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_0(<vscale x 64 x i1> %mask) {
385; CHECK-LABEL: extract_nxv64i1_nxv8i1_0:
386; CHECK:       # %bb.0:
387; CHECK-NEXT:    ret
388  %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 0)
389  ret <vscale x 8 x i1> %c
390}
391
392define <vscale x 8 x i1> @extract_nxv64i1_nxv8i1_8(<vscale x 64 x i1> %mask) {
393; CHECK-LABEL: extract_nxv64i1_nxv8i1_8:
394; CHECK:       # %bb.0:
395; CHECK-NEXT:    csrr a0, vlenb
396; CHECK-NEXT:    srli a0, a0, 3
397; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
398; CHECK-NEXT:    vslidedown.vx v0, v0, a0
399; CHECK-NEXT:    ret
400  %c = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %mask, i64 8)
401  ret <vscale x 8 x i1> %c
402}
403
404define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_0(<vscale x 64 x i1> %mask) {
405; CHECK-LABEL: extract_nxv64i1_nxv2i1_0:
406; CHECK:       # %bb.0:
407; CHECK-NEXT:    ret
408  %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 0)
409  ret <vscale x 2 x i1> %c
410}
411
412define <vscale x 2 x i1> @extract_nxv64i1_nxv2i1_2(<vscale x 64 x i1> %mask) {
413; CHECK-LABEL: extract_nxv64i1_nxv2i1_2:
414; CHECK:       # %bb.0:
415; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
416; CHECK-NEXT:    vmv.v.i v8, 0
417; CHECK-NEXT:    csrr a0, vlenb
418; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
419; CHECK-NEXT:    srli a0, a0, 2
420; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
421; CHECK-NEXT:    vslidedown.vx v8, v8, a0
422; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
423; CHECK-NEXT:    vmsne.vi v0, v8, 0
424; CHECK-NEXT:    ret
425  %c = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %mask, i64 2)
426  ret <vscale x 2 x i1> %c
427}
428
429define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_0(<vscale x 32 x i1> %x) {
430; CHECK-LABEL: extract_nxv4i1_nxv32i1_0:
431; CHECK:       # %bb.0:
432; CHECK-NEXT:    ret
433  %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 0)
434  ret <vscale x 4 x i1> %c
435}
436
437define <vscale x 4 x i1> @extract_nxv4i1_nxv32i1_4(<vscale x 32 x i1> %x) {
438; CHECK-LABEL: extract_nxv4i1_nxv32i1_4:
439; CHECK:       # %bb.0:
440; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
441; CHECK-NEXT:    vmv.v.i v8, 0
442; CHECK-NEXT:    csrr a0, vlenb
443; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
444; CHECK-NEXT:    srli a0, a0, 1
445; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
446; CHECK-NEXT:    vslidedown.vx v8, v8, a0
447; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
448; CHECK-NEXT:    vmsne.vi v0, v8, 0
449; CHECK-NEXT:    ret
450  %c = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %x, i64 4)
451  ret <vscale x 4 x i1> %c
452}
453
454define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_0(<vscale x 32 x i1> %x) {
455; CHECK-LABEL: extract_nxv16i1_nxv32i1_0:
456; CHECK:       # %bb.0:
457; CHECK-NEXT:    ret
458  %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 0)
459  ret <vscale x 16 x i1> %c
460}
461
462define <vscale x 16 x i1> @extract_nxv16i1_nxv32i1_16(<vscale x 32 x i1> %x) {
463; CHECK-LABEL: extract_nxv16i1_nxv32i1_16:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    csrr a0, vlenb
466; CHECK-NEXT:    srli a0, a0, 2
467; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
468; CHECK-NEXT:    vslidedown.vx v0, v0, a0
469; CHECK-NEXT:    ret
470  %c = call <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %x, i64 16)
471  ret <vscale x 16 x i1> %c
472}
473
474;
475; Extract f16 vector that needs widening from one that needs widening.
476;
477define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_0(<vscale x 12 x half> %in) {
478; CHECK-LABEL: extract_nxv6f16_nxv12f16_0:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    ret
481  %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 0)
482  ret <vscale x 6 x half> %res
483}
484
485define <vscale x 6 x half> @extract_nxv6f16_nxv12f16_6(<vscale x 12 x half> %in) {
486; CHECK-LABEL: extract_nxv6f16_nxv12f16_6:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    csrr a0, vlenb
489; CHECK-NEXT:    srli a0, a0, 2
490; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
491; CHECK-NEXT:    vslidedown.vx v13, v10, a0
492; CHECK-NEXT:    vslidedown.vx v12, v9, a0
493; CHECK-NEXT:    add a1, a0, a0
494; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
495; CHECK-NEXT:    vslideup.vx v12, v10, a0
496; CHECK-NEXT:    vmv2r.v v8, v12
497; CHECK-NEXT:    ret
498  %res = call <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half> %in, i64 6)
499  ret <vscale x 6 x half> %res
500}
501
502define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv16bf16_0(<vscale x 16 x bfloat> %vec) {
503; CHECK-LABEL: extract_nxv2bf16_nxv16bf16_0:
504; CHECK:       # %bb.0:
505; CHECK-NEXT:    ret
506  %c = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %vec, i64 0)
507  ret <vscale x 2 x bfloat> %c
508}
509
510define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv16bf16_2(<vscale x 16 x bfloat> %vec) {
511; CHECK-LABEL: extract_nxv2bf16_nxv16bf16_2:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    csrr a0, vlenb
514; CHECK-NEXT:    srli a0, a0, 2
515; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
516; CHECK-NEXT:    vslidedown.vx v8, v8, a0
517; CHECK-NEXT:    ret
518  %c = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %vec, i64 2)
519  ret <vscale x 2 x bfloat> %c
520}
521
522define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv16bf16_4(<vscale x 16 x bfloat> %vec) {
523; CHECK-LABEL: extract_nxv2bf16_nxv16bf16_4:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
526; CHECK-NEXT:    vmv1r.v v8, v9
527; CHECK-NEXT:    ret
528  %c = call <vscale x 2 x bfloat> @llvm.vector.extract.nxv2bf16.nxv16bf16(<vscale x 16 x bfloat> %vec, i64 4)
529  ret <vscale x 2 x bfloat> %c
530}
531
532define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_0(<vscale x 12 x bfloat> %in) {
533; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_0:
534; CHECK:       # %bb.0:
535; CHECK-NEXT:    ret
536  %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 0)
537  ret <vscale x 6 x bfloat> %res
538}
539
540define <vscale x 6 x bfloat> @extract_nxv6bf16_nxv12bf16_6(<vscale x 12 x bfloat> %in) {
541; CHECK-LABEL: extract_nxv6bf16_nxv12bf16_6:
542; CHECK:       # %bb.0:
543; CHECK-NEXT:    csrr a0, vlenb
544; CHECK-NEXT:    srli a0, a0, 2
545; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
546; CHECK-NEXT:    vslidedown.vx v13, v10, a0
547; CHECK-NEXT:    vslidedown.vx v12, v9, a0
548; CHECK-NEXT:    add a1, a0, a0
549; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
550; CHECK-NEXT:    vslideup.vx v12, v10, a0
551; CHECK-NEXT:    vmv2r.v v8, v12
552; CHECK-NEXT:    ret
553  %res = call <vscale x 6 x bfloat> @llvm.vector.extract.nxv6bf16.nxv12bf16(<vscale x 12 x bfloat> %in, i64 6)
554  ret <vscale x 6 x bfloat> %res
555}
556
557declare <vscale x 6 x half> @llvm.vector.extract.nxv6f16.nxv12f16(<vscale x 12 x half>, i64)
558
559declare <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, i64 %idx)
560declare <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv8i8(<vscale x 8 x i8> %vec, i64 %idx)
561
562declare <vscale x 2 x i8> @llvm.vector.extract.nxv2i8.nxv32i8(<vscale x 32 x i8> %vec, i64 %idx)
563
564declare <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 %idx)
565
566declare <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
567declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx)
568
569declare <vscale x 1 x i32> @llvm.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
570declare <vscale x 2 x i32> @llvm.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
571declare <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
572declare <vscale x 8 x i32> @llvm.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx)
573
574declare <vscale x 2 x half> @llvm.vector.extract.nxv2f16.nxv16f16(<vscale x 16 x half> %vec, i64 %idx)
575
576declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1(<vscale x 32 x i1> %vec, i64 %idx)
577declare <vscale x 16 x i1> @llvm.vector.extract.nxv16i1(<vscale x 32 x i1> %vec, i64 %idx)
578
579declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1(<vscale x 64 x i1> %vec, i64 %idx)
580declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1(<vscale x 64 x i1> %vec, i64 %idx)
581