1fe4c99d1SPhilip Reames; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2fe4c99d1SPhilip Reames; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s 3fe4c99d1SPhilip Reames 4*a63bd7e9SPhilip Reames; The case below demonstrates cross block CSE of vector instructions with 5*a63bd7e9SPhilip Reames; undefined passthru operands. 6fe4c99d1SPhilip Reamesdefine void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 7fe4c99d1SPhilip Reames; CHECK-LABEL: foo: 8fe4c99d1SPhilip Reames; CHECK: # %bb.0: 9fe4c99d1SPhilip Reames; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma 10*a63bd7e9SPhilip Reames; CHECK-NEXT: vadd.vv v8, v8, v9 11*a63bd7e9SPhilip Reames; CHECK-NEXT: vs1r.v v8, (a0) 12fe4c99d1SPhilip Reames; CHECK-NEXT: bnez a2, .LBB0_2 13fe4c99d1SPhilip Reames; CHECK-NEXT: # %bb.1: # %falsebb 14fe4c99d1SPhilip Reames; CHECK-NEXT: vs1r.v v8, (a1) 15fe4c99d1SPhilip Reames; CHECK-NEXT: .LBB0_2: # %mergebb 16fe4c99d1SPhilip Reames; CHECK-NEXT: ret 17fe4c99d1SPhilip Reames %a = add <vscale x 2 x i32> %x, %y 18fe4c99d1SPhilip Reames store <vscale x 2 x i32> %a, ptr %p1 19fe4c99d1SPhilip Reames br i1 %cond, label %mergebb, label %falsebb 20fe4c99d1SPhilip Reames 21fe4c99d1SPhilip Reamesfalsebb: 22fe4c99d1SPhilip Reames %b = add <vscale x 2 x i32> %x, %y 23fe4c99d1SPhilip Reames store <vscale x 2 x i32> %b, ptr %p2 24fe4c99d1SPhilip Reames br label %mergebb 25fe4c99d1SPhilip Reames 26fe4c99d1SPhilip Reamesmergebb: 27fe4c99d1SPhilip Reames ret void 28fe4c99d1SPhilip Reames} 29